2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t cb_shader_mask
;
62 uint32_t db_alpha_to_mask
;
64 uint32_t commutative_4bit
;
66 bool single_cb_enable
;
67 bool mrt0_is_dual_src
;
70 struct radv_dsa_order_invariance
{
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
83 struct radv_tessellation_state
{
84 uint32_t ls_hs_config
;
90 static const VkPipelineMultisampleStateCreateInfo
*
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
93 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
94 return pCreateInfo
->pMultisampleState
;
98 static const VkPipelineTessellationStateCreateInfo
*
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
101 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
102 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
103 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
104 return pCreateInfo
->pTessellationState
;
110 static const VkPipelineDepthStencilStateCreateInfo
*
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
113 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
114 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
116 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
117 subpass
->depth_stencil_attachment
)
118 return pCreateInfo
->pDepthStencilState
;
122 static const VkPipelineColorBlendStateCreateInfo
*
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
125 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
126 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
128 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
129 subpass
->has_color_att
)
130 return pCreateInfo
->pColorBlendState
;
134 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
136 struct radv_shader_variant
*variant
= NULL
;
137 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
138 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
139 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
140 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
141 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
142 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
145 return variant
->info
.is_ngg
;
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
150 assert(radv_pipeline_has_ngg(pipeline
));
152 struct radv_shader_variant
*variant
= NULL
;
153 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
154 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
155 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
156 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
157 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
158 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
161 return variant
->info
.is_ngg_passthrough
;
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
166 if (!radv_pipeline_has_gs(pipeline
))
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
173 if (radv_pipeline_has_ngg(pipeline
))
176 assert(pipeline
->gs_copy_shader
);
181 radv_pipeline_destroy(struct radv_device
*device
,
182 struct radv_pipeline
*pipeline
,
183 const VkAllocationCallbacks
* allocator
)
185 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
186 if (pipeline
->shaders
[i
])
187 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
189 if (pipeline
->gs_copy_shader
)
190 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
193 free(pipeline
->cs
.buf
);
195 vk_object_base_finish(&pipeline
->base
);
196 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
199 void radv_DestroyPipeline(
201 VkPipeline _pipeline
,
202 const VkAllocationCallbacks
* pAllocator
)
204 RADV_FROM_HANDLE(radv_device
, device
, _device
);
205 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
210 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
213 static uint32_t get_hash_flags(struct radv_device
*device
)
215 uint32_t hash_flags
= 0;
217 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
218 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
219 if (device
->physical_device
->cs_wave_size
== 32)
220 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
221 if (device
->physical_device
->ps_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
223 if (device
->physical_device
->ge_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
225 if (device
->physical_device
->use_llvm
)
226 hash_flags
|= RADV_HASH_SHADER_LLVM
;
231 radv_pipeline_scratch_init(struct radv_device
*device
,
232 struct radv_pipeline
*pipeline
)
234 unsigned scratch_bytes_per_wave
= 0;
235 unsigned max_waves
= 0;
236 unsigned min_waves
= 1;
238 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
239 if (pipeline
->shaders
[i
] &&
240 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
241 unsigned max_stage_waves
= device
->scratch_waves
;
243 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
244 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
246 max_stage_waves
= MIN2(max_stage_waves
,
247 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
248 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
249 max_waves
= MAX2(max_waves
, max_stage_waves
);
253 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
254 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
255 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
256 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
257 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
260 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
261 pipeline
->max_waves
= max_waves
;
265 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
268 case VK_LOGIC_OP_CLEAR
:
269 return V_028808_ROP3_CLEAR
;
270 case VK_LOGIC_OP_AND
:
271 return V_028808_ROP3_AND
;
272 case VK_LOGIC_OP_AND_REVERSE
:
273 return V_028808_ROP3_AND_REVERSE
;
274 case VK_LOGIC_OP_COPY
:
275 return V_028808_ROP3_COPY
;
276 case VK_LOGIC_OP_AND_INVERTED
:
277 return V_028808_ROP3_AND_INVERTED
;
278 case VK_LOGIC_OP_NO_OP
:
279 return V_028808_ROP3_NO_OP
;
280 case VK_LOGIC_OP_XOR
:
281 return V_028808_ROP3_XOR
;
283 return V_028808_ROP3_OR
;
284 case VK_LOGIC_OP_NOR
:
285 return V_028808_ROP3_NOR
;
286 case VK_LOGIC_OP_EQUIVALENT
:
287 return V_028808_ROP3_EQUIVALENT
;
288 case VK_LOGIC_OP_INVERT
:
289 return V_028808_ROP3_INVERT
;
290 case VK_LOGIC_OP_OR_REVERSE
:
291 return V_028808_ROP3_OR_REVERSE
;
292 case VK_LOGIC_OP_COPY_INVERTED
:
293 return V_028808_ROP3_COPY_INVERTED
;
294 case VK_LOGIC_OP_OR_INVERTED
:
295 return V_028808_ROP3_OR_INVERTED
;
296 case VK_LOGIC_OP_NAND
:
297 return V_028808_ROP3_NAND
;
298 case VK_LOGIC_OP_SET
:
299 return V_028808_ROP3_SET
;
301 unreachable("Unhandled logic op");
306 static uint32_t si_translate_blend_function(VkBlendOp op
)
309 case VK_BLEND_OP_ADD
:
310 return V_028780_COMB_DST_PLUS_SRC
;
311 case VK_BLEND_OP_SUBTRACT
:
312 return V_028780_COMB_SRC_MINUS_DST
;
313 case VK_BLEND_OP_REVERSE_SUBTRACT
:
314 return V_028780_COMB_DST_MINUS_SRC
;
315 case VK_BLEND_OP_MIN
:
316 return V_028780_COMB_MIN_DST_SRC
;
317 case VK_BLEND_OP_MAX
:
318 return V_028780_COMB_MAX_DST_SRC
;
324 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
327 case VK_BLEND_FACTOR_ZERO
:
328 return V_028780_BLEND_ZERO
;
329 case VK_BLEND_FACTOR_ONE
:
330 return V_028780_BLEND_ONE
;
331 case VK_BLEND_FACTOR_SRC_COLOR
:
332 return V_028780_BLEND_SRC_COLOR
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
335 case VK_BLEND_FACTOR_DST_COLOR
:
336 return V_028780_BLEND_DST_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
339 case VK_BLEND_FACTOR_SRC_ALPHA
:
340 return V_028780_BLEND_SRC_ALPHA
;
341 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
342 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_DST_ALPHA
:
344 return V_028780_BLEND_DST_ALPHA
;
345 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
346 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
347 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
348 return V_028780_BLEND_CONSTANT_COLOR
;
349 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
350 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
352 return V_028780_BLEND_CONSTANT_ALPHA
;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
356 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
357 case VK_BLEND_FACTOR_SRC1_COLOR
:
358 return V_028780_BLEND_SRC1_COLOR
;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
360 return V_028780_BLEND_INV_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_SRC1_ALPHA
:
362 return V_028780_BLEND_SRC1_ALPHA
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
364 return V_028780_BLEND_INV_SRC1_ALPHA
;
370 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
373 case VK_BLEND_OP_ADD
:
374 return V_028760_OPT_COMB_ADD
;
375 case VK_BLEND_OP_SUBTRACT
:
376 return V_028760_OPT_COMB_SUBTRACT
;
377 case VK_BLEND_OP_REVERSE_SUBTRACT
:
378 return V_028760_OPT_COMB_REVSUBTRACT
;
379 case VK_BLEND_OP_MIN
:
380 return V_028760_OPT_COMB_MIN
;
381 case VK_BLEND_OP_MAX
:
382 return V_028760_OPT_COMB_MAX
;
384 return V_028760_OPT_COMB_BLEND_DISABLED
;
388 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
391 case VK_BLEND_FACTOR_ZERO
:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
393 case VK_BLEND_FACTOR_ONE
:
394 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
395 case VK_BLEND_FACTOR_SRC_COLOR
:
396 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
397 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
399 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
400 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
401 case VK_BLEND_FACTOR_SRC_ALPHA
:
402 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
403 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
405 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
406 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
407 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
409 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
414 * Get rid of DST in the blend factors by commuting the operands:
415 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
418 unsigned *dst_factor
, unsigned expected_dst
,
419 unsigned replacement_src
)
421 if (*src_factor
== expected_dst
&&
422 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
423 *src_factor
= VK_BLEND_FACTOR_ZERO
;
424 *dst_factor
= replacement_src
;
426 /* Commuting the operands requires reversing subtractions. */
427 if (*func
== VK_BLEND_OP_SUBTRACT
)
428 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
429 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
430 *func
= VK_BLEND_OP_SUBTRACT
;
434 static bool si_blend_factor_uses_dst(unsigned factor
)
436 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
437 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
438 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
439 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
443 static bool is_dual_src(VkBlendFactor factor
)
446 case VK_BLEND_FACTOR_SRC1_COLOR
:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
448 case VK_BLEND_FACTOR_SRC1_ALPHA
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
456 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
458 bool blend_need_alpha
)
460 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
461 struct ac_spi_color_formats formats
= {};
462 unsigned format
, ntype
, swap
;
464 format
= radv_translate_colorformat(vk_format
);
465 ntype
= radv_translate_color_numformat(vk_format
, desc
,
466 vk_format_get_first_non_void_channel(vk_format
));
467 swap
= radv_translate_colorswap(vk_format
, false);
469 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
471 if (blend_enable
&& blend_need_alpha
)
472 return formats
.blend_alpha
;
473 else if(blend_need_alpha
)
474 return formats
.alpha
;
475 else if(blend_enable
)
476 return formats
.blend
;
478 return formats
.normal
;
482 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
483 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
484 struct radv_blend_state
*blend
)
486 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
487 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
488 unsigned col_format
= 0;
489 unsigned num_targets
;
491 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
494 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
495 cf
= V_028714_SPI_SHADER_ZERO
;
497 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
499 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
501 cf
= radv_choose_spi_color_format(attachment
->format
,
503 blend
->need_src_alpha
& (1 << i
));
506 col_format
|= cf
<< (4 * i
);
509 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
510 /* When a subpass doesn't have any color attachments, write the
511 * alpha channel of MRT0 when alpha coverage is enabled because
512 * the depth attachment needs it.
514 col_format
|= V_028714_SPI_SHADER_32_AR
;
517 /* If the i-th target format is set, all previous target formats must
518 * be non-zero to avoid hangs.
520 num_targets
= (util_last_bit(col_format
) + 3) / 4;
521 for (unsigned i
= 0; i
< num_targets
; i
++) {
522 if (!(col_format
& (0xf << (i
* 4)))) {
523 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
527 /* The output for dual source blending should have the same format as
530 if (blend
->mrt0_is_dual_src
)
531 col_format
|= (col_format
& 0xf) << 4;
533 blend
->spi_shader_col_format
= col_format
;
537 format_is_int8(VkFormat format
)
539 const struct vk_format_description
*desc
= vk_format_description(format
);
540 int channel
= vk_format_get_first_non_void_channel(format
);
542 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
543 desc
->channel
[channel
].size
== 8;
547 format_is_int10(VkFormat format
)
549 const struct vk_format_description
*desc
= vk_format_description(format
);
551 if (desc
->nr_channels
!= 4)
553 for (unsigned i
= 0; i
< 4; i
++) {
554 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
561 * Ordered so that for each i,
562 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
564 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
565 VK_FORMAT_R32_SFLOAT
,
566 VK_FORMAT_R32G32_SFLOAT
,
567 VK_FORMAT_R8G8B8A8_UNORM
,
568 VK_FORMAT_R16G16B16A16_UNORM
,
569 VK_FORMAT_R16G16B16A16_SNORM
,
570 VK_FORMAT_R16G16B16A16_UINT
,
571 VK_FORMAT_R16G16B16A16_SINT
,
572 VK_FORMAT_R32G32B32A32_SFLOAT
,
573 VK_FORMAT_R8G8B8A8_UINT
,
574 VK_FORMAT_R8G8B8A8_SINT
,
575 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
576 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
579 unsigned radv_format_meta_fs_key(VkFormat format
)
581 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
583 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
584 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
585 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
587 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
588 bool is_int8
= format_is_int8(format
);
589 bool is_int10
= format_is_int10(format
);
591 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
595 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
596 unsigned *is_int8
, unsigned *is_int10
)
598 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
599 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
603 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
604 struct radv_render_pass_attachment
*attachment
;
606 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
609 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
611 if (format_is_int8(attachment
->format
))
613 if (format_is_int10(attachment
->format
))
619 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
620 VkBlendOp op
, VkBlendFactor src
,
621 VkBlendFactor dst
, unsigned chanmask
)
623 /* Src factor is allowed when it does not depend on Dst. */
624 static const uint32_t src_allowed
=
625 (1u << VK_BLEND_FACTOR_ONE
) |
626 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
627 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
628 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
629 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
630 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
631 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
632 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
633 (1u << VK_BLEND_FACTOR_ZERO
) |
634 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
635 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
636 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
637 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
638 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
639 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
641 if (dst
== VK_BLEND_FACTOR_ONE
&&
642 (src_allowed
& (1u << src
))) {
643 /* Addition is commutative, but floating point addition isn't
644 * associative: subtle changes can be introduced via different
645 * rounding. Be conservative, only enable for min and max.
647 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
648 blend
->commutative_4bit
|= chanmask
;
652 static struct radv_blend_state
653 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
654 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
655 const struct radv_graphics_pipeline_create_info
*extra
)
657 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
658 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
659 struct radv_blend_state blend
= {0};
660 unsigned mode
= V_028808_CB_NORMAL
;
663 if (extra
&& extra
->custom_blend_mode
) {
664 blend
.single_cb_enable
= true;
665 mode
= extra
->custom_blend_mode
;
668 blend
.cb_color_control
= 0;
670 if (vkblend
->logicOpEnable
)
671 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
673 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
676 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
677 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
678 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
679 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
680 S_028B70_OFFSET_ROUND(1);
682 if (vkms
&& vkms
->alphaToCoverageEnable
) {
683 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
684 blend
.need_src_alpha
|= 0x1;
687 blend
.cb_target_mask
= 0;
689 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
690 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
691 unsigned blend_cntl
= 0;
692 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
693 VkBlendOp eqRGB
= att
->colorBlendOp
;
694 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
695 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
696 VkBlendOp eqA
= att
->alphaBlendOp
;
697 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
698 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
700 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
702 if (!att
->colorWriteMask
)
705 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
706 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
707 if (!att
->blendEnable
) {
708 blend
.cb_blend_control
[i
] = blend_cntl
;
712 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
714 blend
.mrt0_is_dual_src
= true;
716 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
717 srcRGB
= VK_BLEND_FACTOR_ONE
;
718 dstRGB
= VK_BLEND_FACTOR_ONE
;
720 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
721 srcA
= VK_BLEND_FACTOR_ONE
;
722 dstA
= VK_BLEND_FACTOR_ONE
;
725 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
727 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
730 /* Blending optimizations for RB+.
731 * These transformations don't change the behavior.
733 * First, get rid of DST in the blend factors:
734 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
736 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
737 VK_BLEND_FACTOR_DST_COLOR
,
738 VK_BLEND_FACTOR_SRC_COLOR
);
740 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
741 VK_BLEND_FACTOR_DST_COLOR
,
742 VK_BLEND_FACTOR_SRC_COLOR
);
744 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
745 VK_BLEND_FACTOR_DST_ALPHA
,
746 VK_BLEND_FACTOR_SRC_ALPHA
);
748 /* Look up the ideal settings from tables. */
749 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
750 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
751 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
752 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
754 /* Handle interdependencies. */
755 if (si_blend_factor_uses_dst(srcRGB
))
756 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
757 if (si_blend_factor_uses_dst(srcA
))
758 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
760 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
761 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
762 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
763 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
764 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
766 /* Set the final value. */
767 blend
.sx_mrt_blend_opt
[i
] =
768 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
769 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
770 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
771 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
772 S_028760_ALPHA_DST_OPT(dstA_opt
) |
773 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
774 blend_cntl
|= S_028780_ENABLE(1);
776 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
777 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
778 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
779 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
780 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
781 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
782 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
783 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
785 blend
.cb_blend_control
[i
] = blend_cntl
;
787 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
789 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
790 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
791 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
792 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
793 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
794 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
795 blend
.need_src_alpha
|= 1 << i
;
797 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
798 blend
.cb_blend_control
[i
] = 0;
799 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
803 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
804 /* Disable RB+ blend optimizations for dual source blending. */
805 if (blend
.mrt0_is_dual_src
) {
806 for (i
= 0; i
< 8; i
++) {
807 blend
.sx_mrt_blend_opt
[i
] =
808 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
809 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
813 /* RB+ doesn't work with dual source blending, logic op and
816 if (blend
.mrt0_is_dual_src
||
817 (vkblend
&& vkblend
->logicOpEnable
) ||
818 mode
== V_028808_CB_RESOLVE
)
819 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
822 if (blend
.cb_target_mask
)
823 blend
.cb_color_control
|= S_028808_MODE(mode
);
825 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
827 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
831 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
834 case VK_STENCIL_OP_KEEP
:
835 return V_02842C_STENCIL_KEEP
;
836 case VK_STENCIL_OP_ZERO
:
837 return V_02842C_STENCIL_ZERO
;
838 case VK_STENCIL_OP_REPLACE
:
839 return V_02842C_STENCIL_REPLACE_TEST
;
840 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
841 return V_02842C_STENCIL_ADD_CLAMP
;
842 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
843 return V_02842C_STENCIL_SUB_CLAMP
;
844 case VK_STENCIL_OP_INVERT
:
845 return V_02842C_STENCIL_INVERT
;
846 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
847 return V_02842C_STENCIL_ADD_WRAP
;
848 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
849 return V_02842C_STENCIL_SUB_WRAP
;
855 static uint32_t si_translate_fill(VkPolygonMode func
)
858 case VK_POLYGON_MODE_FILL
:
859 return V_028814_X_DRAW_TRIANGLES
;
860 case VK_POLYGON_MODE_LINE
:
861 return V_028814_X_DRAW_LINES
;
862 case VK_POLYGON_MODE_POINT
:
863 return V_028814_X_DRAW_POINTS
;
866 return V_028814_X_DRAW_POINTS
;
870 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
872 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
873 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
874 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
875 uint32_t ps_iter_samples
= 1;
876 uint32_t num_samples
;
878 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
880 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
881 * subpass uses color attachments, totalSamples is the number of
882 * samples of the color attachments. Otherwise, totalSamples is the
883 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
884 * specified at pipeline creation time."
886 if (subpass
->has_color_att
) {
887 num_samples
= subpass
->color_sample_count
;
889 num_samples
= vkms
->rasterizationSamples
;
892 if (vkms
->sampleShadingEnable
) {
893 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
894 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
896 return ps_iter_samples
;
900 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
902 return pCreateInfo
->depthTestEnable
&&
903 pCreateInfo
->depthWriteEnable
&&
904 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
908 radv_writes_stencil(const VkStencilOpState
*state
)
910 return state
->writeMask
&&
911 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
912 state
->passOp
!= VK_STENCIL_OP_KEEP
||
913 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
917 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
919 return pCreateInfo
->stencilTestEnable
&&
920 (radv_writes_stencil(&pCreateInfo
->front
) ||
921 radv_writes_stencil(&pCreateInfo
->back
));
925 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
927 return radv_is_depth_write_enabled(pCreateInfo
) ||
928 radv_is_stencil_write_enabled(pCreateInfo
);
932 radv_order_invariant_stencil_op(VkStencilOp op
)
934 /* REPLACE is normally order invariant, except when the stencil
935 * reference value is written by the fragment shader. Tracking this
936 * interaction does not seem worth the effort, so be conservative.
938 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
939 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
940 op
!= VK_STENCIL_OP_REPLACE
;
944 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
946 /* Compute whether, assuming Z writes are disabled, this stencil state
947 * is order invariant in the sense that the set of passing fragments as
948 * well as the final stencil buffer result does not depend on the order
951 return !state
->writeMask
||
952 /* The following assumes that Z writes are disabled. */
953 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
954 radv_order_invariant_stencil_op(state
->passOp
) &&
955 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
956 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
957 radv_order_invariant_stencil_op(state
->failOp
));
961 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
962 struct radv_blend_state
*blend
,
963 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
965 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
966 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
967 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
968 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
969 unsigned colormask
= blend
->cb_target_enabled_4bit
;
971 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
974 /* Be conservative if a logic operation is enabled with color buffers. */
975 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
978 /* Default depth/stencil invariance when no attachment is bound. */
979 struct radv_dsa_order_invariance dsa_order_invariant
= {
980 .zs
= true, .pass_set
= true
984 struct radv_render_pass_attachment
*attachment
=
985 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
986 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
987 struct radv_dsa_order_invariance order_invariance
[2];
988 struct radv_shader_variant
*ps
=
989 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
991 /* Compute depth/stencil order invariance in order to know if
992 * it's safe to enable out-of-order.
994 bool zfunc_is_ordered
=
995 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
996 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
997 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
998 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
999 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1001 bool nozwrite_and_order_invariant_stencil
=
1002 !radv_is_ds_write_enabled(vkds
) ||
1003 (!radv_is_depth_write_enabled(vkds
) &&
1004 radv_order_invariant_stencil_state(&vkds
->front
) &&
1005 radv_order_invariant_stencil_state(&vkds
->back
));
1007 order_invariance
[1].zs
=
1008 nozwrite_and_order_invariant_stencil
||
1009 (!radv_is_stencil_write_enabled(vkds
) &&
1011 order_invariance
[0].zs
=
1012 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1014 order_invariance
[1].pass_set
=
1015 nozwrite_and_order_invariant_stencil
||
1016 (!radv_is_stencil_write_enabled(vkds
) &&
1017 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1018 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1019 order_invariance
[0].pass_set
=
1020 !radv_is_depth_write_enabled(vkds
) ||
1021 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1022 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1024 dsa_order_invariant
= order_invariance
[has_stencil
];
1025 if (!dsa_order_invariant
.zs
)
1028 /* The set of PS invocations is always order invariant,
1029 * except when early Z/S tests are requested.
1032 ps
->info
.ps
.writes_memory
&&
1033 ps
->info
.ps
.early_fragment_test
&&
1034 !dsa_order_invariant
.pass_set
)
1037 /* Determine if out-of-order rasterization should be disabled
1038 * when occlusion queries are used.
1040 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1041 !dsa_order_invariant
.pass_set
;
1044 /* No color buffers are enabled for writing. */
1048 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1051 /* Only commutative blending. */
1052 if (blendmask
& ~blend
->commutative_4bit
)
1055 if (!dsa_order_invariant
.pass_set
)
1059 if (colormask
& ~blendmask
)
1066 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1067 struct radv_blend_state
*blend
,
1068 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1070 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1071 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1072 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1073 bool out_of_order_rast
= false;
1074 int ps_iter_samples
= 1;
1075 uint32_t mask
= 0xffff;
1078 ms
->num_samples
= vkms
->rasterizationSamples
;
1080 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1082 * "Sample shading is enabled for a graphics pipeline:
1084 * - If the interface of the fragment shader entry point of the
1085 * graphics pipeline includes an input variable decorated
1086 * with SampleId or SamplePosition. In this case
1087 * minSampleShadingFactor takes the value 1.0.
1088 * - Else if the sampleShadingEnable member of the
1089 * VkPipelineMultisampleStateCreateInfo structure specified
1090 * when creating the graphics pipeline is set to VK_TRUE. In
1091 * this case minSampleShadingFactor takes the value of
1092 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1094 * Otherwise, sample shading is considered disabled."
1096 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1097 ps_iter_samples
= ms
->num_samples
;
1099 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1102 ms
->num_samples
= 1;
1105 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1106 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1107 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1108 /* Out-of-order rasterization is explicitly enabled by the
1111 out_of_order_rast
= true;
1113 /* Determine if the driver can enable out-of-order
1114 * rasterization internally.
1117 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1120 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1121 ms
->pa_sc_aa_config
= 0;
1122 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1123 S_028804_INCOHERENT_EQAA_READS(1) |
1124 S_028804_INTERPOLATE_COMP_Z(1) |
1125 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1126 ms
->pa_sc_mode_cntl_1
=
1127 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1128 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1129 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1130 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1132 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1133 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1134 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1135 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1136 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1137 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1138 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1139 S_028A48_VPORT_SCISSOR_ENABLE(1);
1141 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1142 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1143 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1145 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1146 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1147 /* From the Vulkan spec 1.1.129:
1149 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1150 * are being rasterized, sample locations may all be
1151 * treated as being at the pixel center (this may
1152 * affect attribute and depth interpolation)."
1154 ms
->num_samples
= 1;
1158 if (ms
->num_samples
> 1) {
1159 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1160 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1161 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1162 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1163 unsigned log_z_samples
= util_logbase2(z_samples
);
1164 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1165 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1166 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1167 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1168 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1169 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1170 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1171 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1172 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1173 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1174 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1175 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1176 if (ps_iter_samples
> 1)
1177 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1180 if (vkms
&& vkms
->pSampleMask
) {
1181 mask
= vkms
->pSampleMask
[0] & 0xffff;
1184 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1185 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1189 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1192 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1193 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1194 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1198 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1199 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1203 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1206 unreachable("unhandled primitive type");
1211 si_translate_prim(enum VkPrimitiveTopology topology
)
1214 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1215 return V_008958_DI_PT_POINTLIST
;
1216 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1217 return V_008958_DI_PT_LINELIST
;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1219 return V_008958_DI_PT_LINESTRIP
;
1220 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1221 return V_008958_DI_PT_TRILIST
;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1223 return V_008958_DI_PT_TRISTRIP
;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1225 return V_008958_DI_PT_TRIFAN
;
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1227 return V_008958_DI_PT_LINELIST_ADJ
;
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1229 return V_008958_DI_PT_LINESTRIP_ADJ
;
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1231 return V_008958_DI_PT_TRILIST_ADJ
;
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1233 return V_008958_DI_PT_TRISTRIP_ADJ
;
1234 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1235 return V_008958_DI_PT_PATCH
;
1243 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1246 case 0: /* GL_POINTS */
1247 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1248 case 1: /* GL_LINES */
1249 case 3: /* GL_LINE_STRIP */
1250 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1251 case 0x8E7A: /* GL_ISOLINES */
1252 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1254 case 4: /* GL_TRIANGLES */
1255 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1256 case 5: /* GL_TRIANGLE_STRIP */
1257 case 7: /* GL_QUADS */
1258 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1266 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1269 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1270 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1271 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1272 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1273 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1276 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1277 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1278 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1282 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1289 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1292 case VK_DYNAMIC_STATE_VIEWPORT
:
1293 return RADV_DYNAMIC_VIEWPORT
;
1294 case VK_DYNAMIC_STATE_SCISSOR
:
1295 return RADV_DYNAMIC_SCISSOR
;
1296 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1297 return RADV_DYNAMIC_LINE_WIDTH
;
1298 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1299 return RADV_DYNAMIC_DEPTH_BIAS
;
1300 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1301 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1302 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1303 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1304 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1305 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1306 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1307 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1308 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1309 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1310 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1311 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1312 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1313 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1314 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1315 return RADV_DYNAMIC_LINE_STIPPLE
;
1317 unreachable("Unhandled dynamic state");
1321 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1323 uint32_t states
= RADV_DYNAMIC_ALL
;
1325 /* If rasterization is disabled we do not care about any of the dynamic states,
1326 * since they are all rasterization related only. */
1327 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1330 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1331 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1333 if (!pCreateInfo
->pDepthStencilState
||
1334 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1335 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1337 if (!pCreateInfo
->pDepthStencilState
||
1338 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1339 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1340 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1341 RADV_DYNAMIC_STENCIL_REFERENCE
);
1343 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1344 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1346 if (!pCreateInfo
->pMultisampleState
||
1347 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1348 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1349 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1351 if (!pCreateInfo
->pRasterizationState
||
1352 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1353 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1354 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1356 /* TODO: blend constants & line width. */
1363 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1364 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1366 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1367 uint32_t states
= needed_states
;
1368 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1369 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1371 pipeline
->dynamic_state
= default_dynamic_state
;
1372 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1374 if (pCreateInfo
->pDynamicState
) {
1375 /* Remove all of the states that are marked as dynamic */
1376 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1377 for (uint32_t s
= 0; s
< count
; s
++)
1378 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1381 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1383 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1384 assert(pCreateInfo
->pViewportState
);
1386 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1387 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1388 typed_memcpy(dynamic
->viewport
.viewports
,
1389 pCreateInfo
->pViewportState
->pViewports
,
1390 pCreateInfo
->pViewportState
->viewportCount
);
1394 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1395 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1396 if (states
& RADV_DYNAMIC_SCISSOR
) {
1397 typed_memcpy(dynamic
->scissor
.scissors
,
1398 pCreateInfo
->pViewportState
->pScissors
,
1399 pCreateInfo
->pViewportState
->scissorCount
);
1403 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1404 assert(pCreateInfo
->pRasterizationState
);
1405 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1408 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1409 assert(pCreateInfo
->pRasterizationState
);
1410 dynamic
->depth_bias
.bias
=
1411 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1412 dynamic
->depth_bias
.clamp
=
1413 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1414 dynamic
->depth_bias
.slope
=
1415 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1418 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1420 * pColorBlendState is [...] NULL if the pipeline has rasterization
1421 * disabled or if the subpass of the render pass the pipeline is
1422 * created against does not use any color attachments.
1424 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1425 assert(pCreateInfo
->pColorBlendState
);
1426 typed_memcpy(dynamic
->blend_constants
,
1427 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1430 /* If there is no depthstencil attachment, then don't read
1431 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1432 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1433 * no need to override the depthstencil defaults in
1434 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1436 * Section 9.2 of the Vulkan 1.0.15 spec says:
1438 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1439 * disabled or if the subpass of the render pass the pipeline is created
1440 * against does not use a depth/stencil attachment.
1442 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1443 assert(pCreateInfo
->pDepthStencilState
);
1445 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1446 dynamic
->depth_bounds
.min
=
1447 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1448 dynamic
->depth_bounds
.max
=
1449 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1452 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1453 dynamic
->stencil_compare_mask
.front
=
1454 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1455 dynamic
->stencil_compare_mask
.back
=
1456 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1459 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1460 dynamic
->stencil_write_mask
.front
=
1461 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1462 dynamic
->stencil_write_mask
.back
=
1463 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1466 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1467 dynamic
->stencil_reference
.front
=
1468 pCreateInfo
->pDepthStencilState
->front
.reference
;
1469 dynamic
->stencil_reference
.back
=
1470 pCreateInfo
->pDepthStencilState
->back
.reference
;
1474 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1475 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1476 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1477 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1478 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1479 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1480 discard_rectangle_info
->pDiscardRectangles
,
1481 discard_rectangle_info
->discardRectangleCount
);
1485 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1486 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1487 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1488 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1489 /* If sampleLocationsEnable is VK_FALSE, the default sample
1490 * locations are used and the values specified in
1491 * sampleLocationsInfo are ignored.
1493 if (sample_location_info
->sampleLocationsEnable
) {
1494 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1495 &sample_location_info
->sampleLocationsInfo
;
1497 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1499 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1500 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1501 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1502 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1503 pSampleLocationsInfo
->pSampleLocations
,
1504 pSampleLocationsInfo
->sampleLocationsCount
);
1508 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1509 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1510 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1511 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1512 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1513 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1516 pipeline
->dynamic_state
.mask
= states
;
1520 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1521 const struct radv_pipeline
*pipeline
,
1523 struct radv_shader_info
*infos
,
1524 struct gfx9_gs_info
*out
)
1526 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1527 struct radv_es_output_info
*es_info
;
1528 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1529 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1531 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1532 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1533 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1535 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1536 bool uses_adjacency
;
1537 switch(key
->topology
) {
1538 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1539 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1540 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1541 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1542 uses_adjacency
= true;
1545 uses_adjacency
= false;
1549 /* All these are in dwords: */
1550 /* We can't allow using the whole LDS, because GS waves compete with
1551 * other shader stages for LDS space. */
1552 const unsigned max_lds_size
= 8 * 1024;
1553 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1554 unsigned esgs_lds_size
;
1556 /* All these are per subgroup: */
1557 const unsigned max_out_prims
= 32 * 1024;
1558 const unsigned max_es_verts
= 255;
1559 const unsigned ideal_gs_prims
= 64;
1560 unsigned max_gs_prims
, gs_prims
;
1561 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1563 if (uses_adjacency
|| gs_num_invocations
> 1)
1564 max_gs_prims
= 127 / gs_num_invocations
;
1568 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1569 * Make sure we don't go over the maximum value.
1571 if (gs_info
->gs
.vertices_out
> 0) {
1572 max_gs_prims
= MIN2(max_gs_prims
,
1574 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1576 assert(max_gs_prims
> 0);
1578 /* If the primitive has adjacency, halve the number of vertices
1579 * that will be reused in multiple primitives.
1581 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1583 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1584 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1586 /* Compute ESGS LDS size based on the worst case number of ES vertices
1587 * needed to create the target number of GS prims per subgroup.
1589 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1591 /* If total LDS usage is too big, refactor partitions based on ratio
1592 * of ESGS item sizes.
1594 if (esgs_lds_size
> max_lds_size
) {
1595 /* Our target GS Prims Per Subgroup was too large. Calculate
1596 * the maximum number of GS Prims Per Subgroup that will fit
1597 * into LDS, capped by the maximum that the hardware can support.
1599 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1601 assert(gs_prims
> 0);
1602 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1605 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1606 assert(esgs_lds_size
<= max_lds_size
);
1609 /* Now calculate remaining ESGS information. */
1611 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1613 es_verts
= max_es_verts
;
1615 /* Vertices for adjacency primitives are not always reused, so restore
1616 * it for ES_VERTS_PER_SUBGRP.
1618 min_es_verts
= gs_info
->gs
.vertices_in
;
1620 /* For normal primitives, the VGT only checks if they are past the ES
1621 * verts per subgroup after allocating a full GS primitive and if they
1622 * are, kick off a new subgroup. But if those additional ES verts are
1623 * unique (e.g. not reused) we need to make sure there is enough LDS
1624 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1626 es_verts
-= min_es_verts
- 1;
1628 uint32_t es_verts_per_subgroup
= es_verts
;
1629 uint32_t gs_prims_per_subgroup
= gs_prims
;
1630 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1631 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1632 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1633 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1634 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1635 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1636 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1637 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1638 assert(max_prims_per_subgroup
<= max_out_prims
);
1641 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1642 unsigned min_verts_per_prim
, bool use_adjacency
)
1644 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1647 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1651 radv_get_num_input_vertices(nir_shader
**nir
)
1653 if (nir
[MESA_SHADER_GEOMETRY
]) {
1654 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1656 return gs
->info
.gs
.vertices_in
;
1659 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1660 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1662 if (tes
->info
.tess
.point_mode
)
1664 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1673 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1674 struct radv_pipeline
*pipeline
,
1676 struct radv_shader_info
*infos
,
1677 struct gfx10_ngg_info
*ngg
)
1679 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1680 struct radv_es_output_info
*es_info
=
1681 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1682 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1683 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1684 unsigned min_verts_per_prim
=
1685 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1686 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1687 bool uses_adjacency
;
1688 switch(key
->topology
) {
1689 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1690 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1691 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1692 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1693 uses_adjacency
= true;
1696 uses_adjacency
= false;
1700 /* All these are in dwords: */
1701 /* We can't allow using the whole LDS, because GS waves compete with
1702 * other shader stages for LDS space.
1704 * TODO: We should really take the shader's internal LDS use into
1705 * account. The linker will fail if the size is greater than
1708 const unsigned max_lds_size
= 8 * 1024 - 768;
1709 const unsigned target_lds_size
= max_lds_size
;
1710 unsigned esvert_lds_size
= 0;
1711 unsigned gsprim_lds_size
= 0;
1713 /* All these are per subgroup: */
1714 bool max_vert_out_per_gs_instance
= false;
1715 unsigned max_esverts_base
= 256;
1716 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1718 /* Hardware has the following non-natural restrictions on the value
1719 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1721 * - at most 252 for any line input primitive type
1722 * - at most 251 for any quad input primitive type
1723 * - at most 251 for triangle strips with adjacency (this happens to
1724 * be the natural limit for triangle *lists* with adjacency)
1726 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1728 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1729 unsigned max_out_verts_per_gsprim
=
1730 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1732 if (max_out_verts_per_gsprim
<= 256) {
1733 if (max_out_verts_per_gsprim
) {
1734 max_gsprims_base
= MIN2(max_gsprims_base
,
1735 256 / max_out_verts_per_gsprim
);
1738 /* Use special multi-cycling mode in which each GS
1739 * instance gets its own subgroup. Does not work with
1741 max_vert_out_per_gs_instance
= true;
1742 max_gsprims_base
= 1;
1743 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1746 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1747 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1750 /* LDS size for passing data from GS to ES. */
1751 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1752 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1753 : &infos
[MESA_SHADER_VERTEX
].so
;
1755 if (so_info
->num_outputs
)
1756 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1758 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1759 * corresponding to the ES thread of the provoking vertex. All
1760 * ES threads load and export PrimitiveID for their thread.
1762 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1763 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1764 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1767 unsigned max_gsprims
= max_gsprims_base
;
1768 unsigned max_esverts
= max_esverts_base
;
1770 if (esvert_lds_size
)
1771 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1772 if (gsprim_lds_size
)
1773 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1775 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1776 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1777 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1779 if (esvert_lds_size
|| gsprim_lds_size
) {
1780 /* Now that we have a rough proportionality between esverts
1781 * and gsprims based on the primitive type, scale both of them
1782 * down simultaneously based on required LDS space.
1784 * We could be smarter about this if we knew how much vertex
1787 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1788 max_gsprims
* gsprim_lds_size
;
1789 if (lds_total
> target_lds_size
) {
1790 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1791 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1793 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1794 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1795 min_verts_per_prim
, uses_adjacency
);
1796 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1800 /* Round up towards full wave sizes for better ALU utilization. */
1801 if (!max_vert_out_per_gs_instance
) {
1802 unsigned orig_max_esverts
;
1803 unsigned orig_max_gsprims
;
1806 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1807 wavesize
= gs_info
->wave_size
;
1809 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1810 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1811 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1815 orig_max_esverts
= max_esverts
;
1816 orig_max_gsprims
= max_gsprims
;
1818 max_esverts
= align(max_esverts
, wavesize
);
1819 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1820 if (esvert_lds_size
)
1821 max_esverts
= MIN2(max_esverts
,
1822 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1824 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1826 max_gsprims
= align(max_gsprims
, wavesize
);
1827 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1828 if (gsprim_lds_size
)
1829 max_gsprims
= MIN2(max_gsprims
,
1830 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1832 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1833 min_verts_per_prim
, uses_adjacency
);
1834 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1835 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1838 /* Hardware restriction: minimum value of max_esverts */
1839 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1841 unsigned max_out_vertices
=
1842 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1843 gs_type
== MESA_SHADER_GEOMETRY
?
1844 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1846 assert(max_out_vertices
<= 256);
1848 unsigned prim_amp_factor
= 1;
1849 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1850 /* Number of output primitives per GS input primitive after
1852 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1855 /* The GE only checks against the maximum number of ES verts after
1856 * allocating a full GS primitive. So we need to ensure that whenever
1857 * this check passes, there is enough space for a full primitive without
1860 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1861 ngg
->max_gsprims
= max_gsprims
;
1862 ngg
->max_out_verts
= max_out_vertices
;
1863 ngg
->prim_amp_factor
= prim_amp_factor
;
1864 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1865 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1866 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1868 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1869 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1871 ngg
->vgt_esgs_ring_itemsize
= 1;
1874 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1876 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1880 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1881 const struct gfx9_gs_info
*gs
)
1883 struct radv_device
*device
= pipeline
->device
;
1884 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1885 unsigned wave_size
= 64;
1886 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1887 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1888 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1890 unsigned gs_vertex_reuse
=
1891 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1892 unsigned alignment
= 256 * num_se
;
1893 /* The maximum size is 63.999 MB per SE. */
1894 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1895 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1897 /* Calculate the minimum size. */
1898 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1899 wave_size
, alignment
);
1900 /* These are recommended sizes, not minimum sizes. */
1901 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1902 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1903 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1904 gs_info
->gs
.max_gsvs_emit_size
;
1906 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1907 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1908 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1910 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1911 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1913 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1916 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1919 /* If tessellation is all offchip and on-chip GS isn't used, this
1920 * workaround is not needed.
1924 /* SPI barrier management bug:
1925 * Make sure we have at least 4k of LDS in use to avoid the bug.
1926 * It applies to workgroup sizes of more than one wavefront.
1928 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1929 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1930 *lds_size
= MAX2(*lds_size
, 8);
1933 struct radv_shader_variant
*
1934 radv_get_shader(struct radv_pipeline
*pipeline
,
1935 gl_shader_stage stage
)
1937 if (stage
== MESA_SHADER_VERTEX
) {
1938 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1939 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1940 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1941 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1942 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1943 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1944 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1945 if (!radv_pipeline_has_tess(pipeline
))
1947 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1948 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1949 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1950 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1952 return pipeline
->shaders
[stage
];
1955 static struct radv_tessellation_state
1956 calculate_tess_state(struct radv_pipeline
*pipeline
,
1957 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1959 unsigned num_tcs_input_cp
;
1960 unsigned num_tcs_output_cp
;
1962 unsigned num_patches
;
1963 struct radv_tessellation_state tess
= {0};
1965 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1966 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1967 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1969 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1971 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1972 assert(lds_size
<= 65536);
1973 lds_size
= align(lds_size
, 512) / 512;
1975 assert(lds_size
<= 32768);
1976 lds_size
= align(lds_size
, 256) / 256;
1978 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1980 tess
.lds_size
= lds_size
;
1982 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1983 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1984 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1985 tess
.num_patches
= num_patches
;
1987 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1988 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1990 switch (tes
->info
.tes
.primitive_mode
) {
1992 type
= V_028B6C_TESS_TRIANGLE
;
1995 type
= V_028B6C_TESS_QUAD
;
1998 type
= V_028B6C_TESS_ISOLINE
;
2002 switch (tes
->info
.tes
.spacing
) {
2003 case TESS_SPACING_EQUAL
:
2004 partitioning
= V_028B6C_PART_INTEGER
;
2006 case TESS_SPACING_FRACTIONAL_ODD
:
2007 partitioning
= V_028B6C_PART_FRAC_ODD
;
2009 case TESS_SPACING_FRACTIONAL_EVEN
:
2010 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2016 bool ccw
= tes
->info
.tes
.ccw
;
2017 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2018 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2019 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2021 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2024 if (tes
->info
.tes
.point_mode
)
2025 topology
= V_028B6C_OUTPUT_POINT
;
2026 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2027 topology
= V_028B6C_OUTPUT_LINE
;
2029 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2031 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2033 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2034 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2035 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2036 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2038 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2040 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2042 tess
.tf_param
= S_028B6C_TYPE(type
) |
2043 S_028B6C_PARTITIONING(partitioning
) |
2044 S_028B6C_TOPOLOGY(topology
) |
2045 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2050 static const struct radv_prim_vertex_count prim_size_table
[] = {
2051 [V_008958_DI_PT_NONE
] = {0, 0},
2052 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2053 [V_008958_DI_PT_LINELIST
] = {2, 2},
2054 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2055 [V_008958_DI_PT_TRILIST
] = {3, 3},
2056 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2057 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2058 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2059 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2060 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2061 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2062 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2063 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2064 [V_008958_DI_PT_POLYGON
] = {3, 1},
2065 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2068 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2070 if (radv_pipeline_has_gs(pipeline
))
2071 if (radv_pipeline_has_ngg(pipeline
))
2072 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2074 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2075 else if (radv_pipeline_has_tess(pipeline
))
2076 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2078 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2082 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2084 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2085 int shader_count
= 0;
2087 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2088 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2090 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2091 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2093 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2094 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2096 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2097 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2099 if(shaders
[MESA_SHADER_VERTEX
]) {
2100 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2103 if (shader_count
> 1) {
2104 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2105 unsigned last
= ordered_shaders
[0]->info
.stage
;
2107 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2108 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2109 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2111 for (int i
= 0; i
< shader_count
; ++i
) {
2112 nir_variable_mode mask
= 0;
2114 if (ordered_shaders
[i
]->info
.stage
!= first
)
2115 mask
= mask
| nir_var_shader_in
;
2117 if (ordered_shaders
[i
]->info
.stage
!= last
)
2118 mask
= mask
| nir_var_shader_out
;
2120 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2121 radv_optimize_nir(ordered_shaders
[i
], false, false);
2125 for (int i
= 1; i
< shader_count
; ++i
) {
2126 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2127 ordered_shaders
[i
- 1]);
2129 if (nir_link_opt_varyings(ordered_shaders
[i
],
2130 ordered_shaders
[i
- 1]))
2131 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2133 nir_remove_dead_variables(ordered_shaders
[i
],
2134 nir_var_shader_out
, NULL
);
2135 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2136 nir_var_shader_in
, NULL
);
2138 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2139 ordered_shaders
[i
- 1]);
2141 nir_compact_varyings(ordered_shaders
[i
],
2142 ordered_shaders
[i
- 1], true);
2145 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2146 ac_lower_indirect_derefs(ordered_shaders
[i
],
2147 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2149 radv_optimize_nir(ordered_shaders
[i
], false, false);
2151 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2152 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2153 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2155 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2161 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2162 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2164 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2165 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2167 if (!has_tess
&& !has_gs
)
2170 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2171 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2173 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2174 /* These are merged into the next stage */
2175 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2176 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2180 nir_linked_io_var_info vs2tcs
=
2181 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2182 nir_linked_io_var_info tcs2tes
=
2183 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2185 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2186 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2187 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2188 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2189 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2190 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2193 nir_linked_io_var_info tes2gs
=
2194 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2196 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2197 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2199 } else if (has_gs
) {
2200 nir_linked_io_var_info vs2gs
=
2201 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2203 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2204 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2209 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2210 uint32_t attrib_binding
)
2212 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2213 const VkVertexInputBindingDescription
*input_binding
=
2214 &input_state
->pVertexBindingDescriptions
[i
];
2216 if (input_binding
->binding
== attrib_binding
)
2217 return input_binding
->stride
;
2223 static struct radv_pipeline_key
2224 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2225 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2226 const struct radv_blend_state
*blend
,
2227 bool has_view_index
)
2229 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2230 pCreateInfo
->pVertexInputState
;
2231 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2232 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2234 struct radv_pipeline_key key
;
2235 memset(&key
, 0, sizeof(key
));
2237 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2238 key
.optimisations_disabled
= 1;
2240 key
.has_multiview_view_index
= has_view_index
;
2242 uint32_t binding_input_rate
= 0;
2243 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2244 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2245 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2246 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2247 binding_input_rate
|= 1u << binding
;
2248 instance_rate_divisors
[binding
] = 1;
2251 if (divisor_state
) {
2252 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2253 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2254 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2258 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2259 const VkVertexInputAttributeDescription
*desc
=
2260 &input_state
->pVertexAttributeDescriptions
[i
];
2261 const struct vk_format_description
*format_desc
;
2262 unsigned location
= desc
->location
;
2263 unsigned binding
= desc
->binding
;
2264 unsigned num_format
, data_format
;
2267 if (binding_input_rate
& (1u << binding
)) {
2268 key
.instance_rate_inputs
|= 1u << location
;
2269 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2272 format_desc
= vk_format_description(desc
->format
);
2273 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2275 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2276 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2278 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2279 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2280 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2281 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2283 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2284 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2285 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2288 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2289 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2290 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2292 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2293 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2294 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2296 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2297 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2298 adjust
= RADV_ALPHA_ADJUST_SINT
;
2304 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2307 switch (desc
->format
) {
2308 case VK_FORMAT_B8G8R8A8_UNORM
:
2309 case VK_FORMAT_B8G8R8A8_SNORM
:
2310 case VK_FORMAT_B8G8R8A8_USCALED
:
2311 case VK_FORMAT_B8G8R8A8_SSCALED
:
2312 case VK_FORMAT_B8G8R8A8_UINT
:
2313 case VK_FORMAT_B8G8R8A8_SINT
:
2314 case VK_FORMAT_B8G8R8A8_SRGB
:
2315 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2316 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2317 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2318 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2319 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2320 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2321 key
.vertex_post_shuffle
|= 1 << location
;
2328 const VkPipelineTessellationStateCreateInfo
*tess
=
2329 radv_pipeline_get_tessellation_state(pCreateInfo
);
2331 key
.tess_input_vertices
= tess
->patchControlPoints
;
2333 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2334 radv_pipeline_get_multisample_state(pCreateInfo
);
2335 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2336 uint32_t num_samples
= vkms
->rasterizationSamples
;
2337 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2338 key
.num_samples
= num_samples
;
2339 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2342 key
.col_format
= blend
->spi_shader_col_format
;
2343 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2344 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2346 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2347 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2353 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2355 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2356 bool uses_xfb
= !!xfb
;
2363 radv_fill_shader_keys(struct radv_device
*device
,
2364 struct radv_shader_variant_key
*keys
,
2365 const struct radv_pipeline_key
*key
,
2368 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2369 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2370 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2371 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2372 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2373 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2374 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2375 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2376 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2378 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2380 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2381 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2382 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2383 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2384 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2386 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2389 if (nir
[MESA_SHADER_GEOMETRY
]) {
2390 if (nir
[MESA_SHADER_TESS_CTRL
])
2391 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2393 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2396 if (device
->physical_device
->use_ngg
) {
2397 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2398 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2400 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2403 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2404 nir
[MESA_SHADER_GEOMETRY
] &&
2405 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2406 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2407 /* Fallback to the legacy path if tessellation is
2408 * enabled with extreme geometry because
2409 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2412 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2415 if (!device
->physical_device
->use_ngg_gs
) {
2416 if (nir
[MESA_SHADER_GEOMETRY
]) {
2417 if (nir
[MESA_SHADER_TESS_CTRL
])
2418 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2420 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2424 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2426 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2431 bool uses_xfb
= nir
[last_xfb_stage
] &&
2432 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2434 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2435 if (nir
[MESA_SHADER_TESS_CTRL
])
2436 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2438 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2441 /* Determine if the pipeline is eligible for the NGG passthrough
2442 * mode. It can't be enabled for geometry shaders, for NGG
2443 * streamout or for vertex shaders that export the primitive ID
2444 * (this is checked later because we don't have the info here.)
2446 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2447 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2448 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2449 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2450 } else if (nir
[MESA_SHADER_VERTEX
] &&
2451 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2452 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2457 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2458 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2460 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2461 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2462 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2463 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2464 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2466 if (nir
[MESA_SHADER_COMPUTE
]) {
2467 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2472 radv_get_wave_size(struct radv_device
*device
,
2473 const VkPipelineShaderStageCreateInfo
*pStage
,
2474 gl_shader_stage stage
,
2475 const struct radv_shader_variant_key
*key
)
2477 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2479 else if (stage
== MESA_SHADER_COMPUTE
) {
2480 if (key
->cs
.subgroup_size
) {
2481 /* Return the required subgroup size if specified. */
2482 return key
->cs
.subgroup_size
;
2484 return device
->physical_device
->cs_wave_size
;
2486 else if (stage
== MESA_SHADER_FRAGMENT
)
2487 return device
->physical_device
->ps_wave_size
;
2489 return device
->physical_device
->ge_wave_size
;
2493 radv_get_ballot_bit_size(struct radv_device
*device
,
2494 const VkPipelineShaderStageCreateInfo
*pStage
,
2495 gl_shader_stage stage
,
2496 const struct radv_shader_variant_key
*key
)
2498 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2499 return key
->cs
.subgroup_size
;
2504 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2505 const VkPipelineShaderStageCreateInfo
**pStages
,
2506 struct radv_shader_variant_key
*keys
,
2507 struct radv_shader_info
*infos
,
2510 unsigned active_stages
= 0;
2511 unsigned filled_stages
= 0;
2513 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2515 active_stages
|= (1 << i
);
2518 if (nir
[MESA_SHADER_FRAGMENT
]) {
2519 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2520 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2522 &keys
[MESA_SHADER_FRAGMENT
],
2523 &infos
[MESA_SHADER_FRAGMENT
],
2524 pipeline
->device
->physical_device
->use_llvm
);
2526 /* TODO: These are no longer used as keys we should refactor this */
2527 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2528 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2529 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2530 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2531 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2532 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2533 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2534 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2535 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2536 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2537 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2538 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2539 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2540 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2541 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2542 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2544 /* NGG passthrough mode can't be enabled for vertex shaders
2545 * that export the primitive ID.
2547 * TODO: I should really refactor the keys logic.
2549 if (nir
[MESA_SHADER_VERTEX
] &&
2550 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2551 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2554 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2557 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2558 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2559 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2560 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2561 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2564 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2565 nir
[MESA_SHADER_TESS_CTRL
]) {
2566 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2567 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2568 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2570 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2572 for (int i
= 0; i
< 2; i
++) {
2573 radv_nir_shader_info_pass(combined_nir
[i
],
2574 pipeline
->layout
, &key
,
2575 &infos
[MESA_SHADER_TESS_CTRL
],
2576 pipeline
->device
->physical_device
->use_llvm
);
2579 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2580 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2581 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2582 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2584 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2585 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2588 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2589 nir
[MESA_SHADER_GEOMETRY
]) {
2590 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2591 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2593 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2595 for (int i
= 0; i
< 2; i
++) {
2596 radv_nir_shader_info_pass(combined_nir
[i
],
2599 &infos
[MESA_SHADER_GEOMETRY
],
2600 pipeline
->device
->physical_device
->use_llvm
);
2603 filled_stages
|= (1 << pre_stage
);
2604 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2607 active_stages
^= filled_stages
;
2608 while (active_stages
) {
2609 int i
= u_bit_scan(&active_stages
);
2611 if (i
== MESA_SHADER_TESS_CTRL
) {
2612 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2613 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2616 if (i
== MESA_SHADER_TESS_EVAL
) {
2617 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2618 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2619 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2620 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2623 radv_nir_shader_info_init(&infos
[i
]);
2624 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2625 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2628 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2630 infos
[i
].wave_size
=
2631 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2633 infos
[i
].ballot_bit_size
=
2634 radv_get_ballot_bit_size(pipeline
->device
,
2642 merge_tess_info(struct shader_info
*tes_info
,
2643 const struct shader_info
*tcs_info
)
2645 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2647 * "PointMode. Controls generation of points rather than triangles
2648 * or lines. This functionality defaults to disabled, and is
2649 * enabled if either shader stage includes the execution mode.
2651 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2652 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2653 * and OutputVertices, it says:
2655 * "One mode must be set in at least one of the tessellation
2658 * So, the fields can be set in either the TCS or TES, but they must
2659 * agree if set in both. Our backend looks at TES, so bitwise-or in
2660 * the values from the TCS.
2662 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2663 tes_info
->tess
.tcs_vertices_out
== 0 ||
2664 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2665 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2667 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2668 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2669 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2670 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2672 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2673 tes_info
->tess
.primitive_mode
== 0 ||
2674 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2675 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2676 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2677 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2681 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2686 if (ext
->pPipelineCreationFeedback
) {
2687 ext
->pPipelineCreationFeedback
->flags
= 0;
2688 ext
->pPipelineCreationFeedback
->duration
= 0;
2691 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2692 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2693 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2698 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2703 feedback
->duration
-= radv_get_current_time();
2704 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2708 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2713 feedback
->duration
+= radv_get_current_time();
2714 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2715 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2718 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2719 struct radv_device
*device
,
2720 struct radv_pipeline_cache
*cache
,
2721 const struct radv_pipeline_key
*key
,
2722 const VkPipelineShaderStageCreateInfo
**pStages
,
2723 const VkPipelineCreateFlags flags
,
2724 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2725 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2727 struct radv_shader_module fs_m
= {0};
2728 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2729 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2730 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2731 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2732 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2733 unsigned char hash
[20], gs_copy_hash
[20];
2734 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2735 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2736 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2737 device
->keep_shader_info
;
2739 radv_start_feedback(pipeline_feedback
);
2741 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2743 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2744 if (modules
[i
]->nir
)
2745 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2746 strlen(modules
[i
]->nir
->info
.name
),
2749 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2753 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2754 memcpy(gs_copy_hash
, hash
, 20);
2755 gs_copy_hash
[0] ^= 1;
2757 bool found_in_application_cache
= true;
2758 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2759 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2760 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2761 &found_in_application_cache
);
2762 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2765 if (!keep_executable_info
&& !keep_statistic_info
&&
2766 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2767 &found_in_application_cache
) &&
2768 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2769 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2773 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2774 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2775 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2778 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2780 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2781 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2782 fs_m
.nir
= fs_b
.shader
;
2783 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2786 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2787 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2788 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2793 radv_start_feedback(stage_feedbacks
[i
]);
2795 if (key
->compute_subgroup_size
) {
2796 /* Only compute shaders currently support requiring a
2797 * specific subgroup size.
2799 assert(i
== MESA_SHADER_COMPUTE
);
2800 subgroup_size
= key
->compute_subgroup_size
;
2801 ballot_bit_size
= key
->compute_subgroup_size
;
2804 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2805 stage
? stage
->pName
: "main", i
,
2806 stage
? stage
->pSpecializationInfo
: NULL
,
2807 flags
, pipeline
->layout
,
2808 subgroup_size
, ballot_bit_size
);
2810 /* We don't want to alter meta shaders IR directly so clone it
2813 if (nir
[i
]->info
.name
) {
2814 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2817 radv_stop_feedback(stage_feedbacks
[i
], false);
2820 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2821 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2822 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2825 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2826 radv_link_shaders(pipeline
, nir
);
2828 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2830 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2832 /* do this again since information such as outputs_read can be out-of-date */
2833 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2835 if (device
->physical_device
->use_llvm
) {
2836 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2838 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2839 nir_lower_non_uniform_ubo_access
|
2840 nir_lower_non_uniform_ssbo_access
|
2841 nir_lower_non_uniform_texture_access
|
2842 nir_lower_non_uniform_image_access
);
2847 if (nir
[MESA_SHADER_FRAGMENT
])
2848 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2850 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2851 if (radv_can_dump_shader(device
, modules
[i
], false))
2852 nir_print_shader(nir
[i
], stderr
);
2855 radv_fill_shader_keys(device
, keys
, key
, nir
);
2857 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2859 if ((nir
[MESA_SHADER_VERTEX
] &&
2860 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2861 (nir
[MESA_SHADER_TESS_EVAL
] &&
2862 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2863 struct gfx10_ngg_info
*ngg_info
;
2865 if (nir
[MESA_SHADER_GEOMETRY
])
2866 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2867 else if (nir
[MESA_SHADER_TESS_CTRL
])
2868 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2870 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2872 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2873 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2874 struct gfx9_gs_info
*gs_info
=
2875 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2877 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2880 if(modules
[MESA_SHADER_GEOMETRY
]) {
2881 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2882 if (!pipeline
->gs_copy_shader
&&
2883 !radv_pipeline_has_ngg(pipeline
)) {
2884 struct radv_shader_info info
= {};
2885 struct radv_shader_variant_key key
= {};
2887 key
.has_multiview_view_index
=
2888 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2890 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2891 pipeline
->layout
, &key
,
2892 &info
, pipeline
->device
->physical_device
->use_llvm
);
2893 info
.wave_size
= 64; /* Wave32 not supported. */
2894 info
.ballot_bit_size
= 64;
2896 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2897 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2898 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2899 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2902 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2903 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2904 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2906 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2907 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2909 radv_pipeline_cache_insert_shaders(device
, cache
,
2914 free(gs_copy_binary
);
2917 if (nir
[MESA_SHADER_FRAGMENT
]) {
2918 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2919 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2921 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2922 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2923 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2924 infos
+ MESA_SHADER_FRAGMENT
,
2925 keep_executable_info
, keep_statistic_info
,
2926 &binaries
[MESA_SHADER_FRAGMENT
]);
2928 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2932 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2933 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2934 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2935 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2936 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2938 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2940 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2942 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2943 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2945 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2947 modules
[MESA_SHADER_VERTEX
] = NULL
;
2948 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2949 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2952 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2953 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2954 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2955 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2957 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2959 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2961 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2962 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2964 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2966 modules
[pre_stage
] = NULL
;
2969 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2970 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2971 if (i
== MESA_SHADER_TESS_CTRL
) {
2972 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2974 if (i
== MESA_SHADER_TESS_EVAL
) {
2975 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2976 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2979 radv_start_feedback(stage_feedbacks
[i
]);
2981 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2983 keys
+ i
, infos
+ i
, keep_executable_info
,
2984 keep_statistic_info
, &binaries
[i
]);
2986 radv_stop_feedback(stage_feedbacks
[i
], false);
2990 if (!keep_executable_info
&& !keep_statistic_info
) {
2991 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2995 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2998 ralloc_free(nir
[i
]);
3000 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3001 radv_shader_dump_stats(device
,
3002 pipeline
->shaders
[i
],
3008 ralloc_free(fs_m
.nir
);
3010 radv_stop_feedback(pipeline_feedback
, false);
3015 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3016 gl_shader_stage stage
, enum chip_class chip_class
)
3018 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3019 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3020 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3023 case MESA_SHADER_FRAGMENT
:
3024 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3025 case MESA_SHADER_VERTEX
:
3027 if (chip_class
>= GFX10
) {
3028 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3029 } else if (chip_class
== GFX9
) {
3030 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3032 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3038 if (chip_class
>= GFX10
) {
3039 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3041 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3046 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3048 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3049 case MESA_SHADER_GEOMETRY
:
3050 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3051 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3052 case MESA_SHADER_COMPUTE
:
3053 return R_00B900_COMPUTE_USER_DATA_0
;
3054 case MESA_SHADER_TESS_CTRL
:
3055 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3056 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3057 case MESA_SHADER_TESS_EVAL
:
3059 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3060 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3061 } else if (has_ngg
) {
3062 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3064 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3067 unreachable("unknown shader");
3071 struct radv_bin_size_entry
{
3077 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3079 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3083 /* One shader engine */
3089 { UINT_MAX
, { 0, 0}},
3092 /* Two shader engines */
3098 { UINT_MAX
, { 0, 0}},
3101 /* Four shader engines */
3106 { UINT_MAX
, { 0, 0}},
3112 /* One shader engine */
3118 { UINT_MAX
, { 0, 0}},
3121 /* Two shader engines */
3127 { UINT_MAX
, { 0, 0}},
3130 /* Four shader engines */
3137 { UINT_MAX
, { 0, 0}},
3143 /* One shader engine */
3150 { UINT_MAX
, { 0, 0}},
3153 /* Two shader engines */
3161 { UINT_MAX
, { 0, 0}},
3164 /* Four shader engines */
3172 { UINT_MAX
, { 0, 0}},
3176 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3180 // One shader engine
3187 { UINT_MAX
, { 0, 0}},
3190 // Two shader engines
3198 { UINT_MAX
, { 0, 0}},
3201 // Four shader engines
3209 { UINT_MAX
, { 0, 0}},
3215 // One shader engine
3223 { UINT_MAX
, { 0, 0}},
3226 // Two shader engines
3235 { UINT_MAX
, { 0, 0}},
3238 // Four shader engines
3247 { UINT_MAX
, { 0, 0}},
3253 // One shader engine
3261 { UINT_MAX
, { 0, 0}},
3264 // Two shader engines
3273 { UINT_MAX
, { 0, 0}},
3276 // Four shader engines
3284 { UINT_MAX
, { 0, 0}},
3289 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3290 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3291 VkExtent2D extent
= {512, 512};
3293 unsigned log_num_rb_per_se
=
3294 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3295 pipeline
->device
->physical_device
->rad_info
.max_se
);
3296 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3298 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3299 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3300 unsigned effective_samples
= total_samples
;
3301 unsigned color_bytes_per_pixel
= 0;
3303 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3304 radv_pipeline_get_color_blend_state(pCreateInfo
);
3306 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3307 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3310 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3313 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3314 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3317 /* MSAA images typically don't use all samples all the time. */
3318 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3319 effective_samples
= 2;
3320 color_bytes_per_pixel
*= effective_samples
;
3323 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3324 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3327 extent
= color_entry
->extent
;
3329 if (subpass
->depth_stencil_attachment
) {
3330 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3332 /* Coefficients taken from AMDVLK */
3333 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3334 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3335 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3337 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3338 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3341 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3342 extent
= ds_entry
->extent
;
3349 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3351 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3352 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3353 VkExtent2D extent
= {512, 512};
3355 const unsigned db_tag_size
= 64;
3356 const unsigned db_tag_count
= 312;
3357 const unsigned color_tag_size
= 1024;
3358 const unsigned color_tag_count
= 31;
3359 const unsigned fmask_tag_size
= 256;
3360 const unsigned fmask_tag_count
= 44;
3362 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3363 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3365 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3366 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3367 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3369 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3370 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3372 unsigned color_bytes_per_pixel
= 0;
3373 unsigned fmask_bytes_per_pixel
= 0;
3375 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3376 radv_pipeline_get_color_blend_state(pCreateInfo
);
3378 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3379 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3382 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3385 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3386 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3388 if (total_samples
> 1) {
3389 assert(samples_log
<= 3);
3390 const unsigned fmask_array
[] = {0, 1, 1, 4};
3391 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3395 color_bytes_per_pixel
*= total_samples
;
3397 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3399 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3400 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3401 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3403 if (fmask_bytes_per_pixel
) {
3404 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3406 const VkExtent2D fmask_extent
= (VkExtent2D
){
3407 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3408 .height
= 1ull << (color_pixel_count_log
/ 2)
3411 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3412 extent
= fmask_extent
;
3415 if (subpass
->depth_stencil_attachment
) {
3416 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3418 /* Coefficients taken from AMDVLK */
3419 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3420 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3421 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3423 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3425 const VkExtent2D db_extent
= (VkExtent2D
){
3426 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3427 .height
= 1ull << (color_pixel_count_log
/ 2)
3430 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3434 extent
.width
= MAX2(extent
.width
, 128);
3435 extent
.height
= MAX2(extent
.width
, 64);
3441 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3442 struct radv_pipeline
*pipeline
,
3443 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3445 uint32_t pa_sc_binner_cntl_0
=
3446 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3447 S_028C44_DISABLE_START_OF_PRIM(1);
3448 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3450 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3451 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3452 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3453 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3454 radv_pipeline_get_color_blend_state(pCreateInfo
);
3455 unsigned min_bytes_per_pixel
= 0;
3458 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3459 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3462 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3465 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3466 unsigned bytes
= vk_format_get_blocksize(format
);
3467 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3468 min_bytes_per_pixel
= bytes
;
3472 pa_sc_binner_cntl_0
=
3473 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3474 S_028C44_BIN_SIZE_X(0) |
3475 S_028C44_BIN_SIZE_Y(0) |
3476 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3477 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3478 S_028C44_DISABLE_START_OF_PRIM(1);
3481 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3482 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3485 struct radv_binning_settings
3486 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3488 struct radv_binning_settings settings
;
3489 if (pdev
->rad_info
.has_dedicated_vram
) {
3490 if (pdev
->rad_info
.num_render_backends
> 4) {
3491 settings
.context_states_per_bin
= 1;
3492 settings
.persistent_states_per_bin
= 1;
3494 settings
.context_states_per_bin
= 3;
3495 settings
.persistent_states_per_bin
= 8;
3497 settings
.fpovs_per_batch
= 63;
3499 /* The context states are affected by the scissor bug. */
3500 settings
.context_states_per_bin
= 6;
3501 /* 32 causes hangs for RAVEN. */
3502 settings
.persistent_states_per_bin
= 16;
3503 settings
.fpovs_per_batch
= 63;
3506 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3507 settings
.context_states_per_bin
= 1;
3513 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3514 struct radv_pipeline
*pipeline
,
3515 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3516 const struct radv_blend_state
*blend
)
3518 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3521 VkExtent2D bin_size
;
3522 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3523 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3524 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3525 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3527 unreachable("Unhandled generation for binning bin size calculation");
3529 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3530 struct radv_binning_settings settings
=
3531 radv_get_binning_settings(pipeline
->device
->physical_device
);
3533 bool disable_start_of_prim
= true;
3534 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3536 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3538 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3539 !ps
->info
.ps
.can_discard
&&
3540 !ps
->info
.ps
.writes_memory
&&
3541 blend
->cb_target_enabled_4bit
) {
3542 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3543 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3546 const uint32_t pa_sc_binner_cntl_0
=
3547 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3548 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3549 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3550 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3551 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3552 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3553 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3554 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3555 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3556 S_028C44_OPTIMAL_BIN_SELECTION(1);
3558 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3559 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3561 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3566 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3567 struct radv_pipeline
*pipeline
,
3568 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3569 const struct radv_graphics_pipeline_create_info
*extra
)
3571 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3572 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3573 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3574 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3575 struct radv_render_pass_attachment
*attachment
= NULL
;
3576 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3577 uint32_t db_render_control
= 0, db_render_override2
= 0;
3578 uint32_t db_render_override
= 0;
3580 if (subpass
->depth_stencil_attachment
)
3581 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3583 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3584 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3586 if (vkds
&& has_depth_attachment
) {
3587 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3588 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3589 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3590 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3592 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3593 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3595 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3596 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3599 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3600 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3601 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3602 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3603 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3604 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3606 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3607 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3608 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3609 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3612 if (attachment
&& extra
) {
3613 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3614 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3616 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3617 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3618 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3619 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3620 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3623 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3624 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3626 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3627 ps
->info
.ps
.writes_z
) {
3628 /* From VK_EXT_depth_range_unrestricted spec:
3630 * "The behavior described in Primitive Clipping still applies.
3631 * If depth clamping is disabled the depth values are still
3632 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3633 * depth clamping is enabled the above equation is ignored and
3634 * the depth values are instead clamped to the VkViewport
3635 * minDepth and maxDepth values, which in the case of this
3636 * extension can be outside of the 0.0 to 1.0 range."
3638 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3641 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3642 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3644 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3645 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3646 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3650 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3651 struct radv_pipeline
*pipeline
,
3652 const struct radv_blend_state
*blend
)
3654 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3655 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3657 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3658 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3660 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3662 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3663 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3666 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3668 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3669 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3671 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3672 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3675 static const VkConservativeRasterizationModeEXT
3676 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3678 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3679 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3681 if (!conservative_raster
)
3682 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3683 return conservative_raster
->conservativeRasterizationMode
;
3687 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3688 struct radv_pipeline
*pipeline
,
3689 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3691 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3692 const VkConservativeRasterizationModeEXT mode
=
3693 radv_get_conservative_raster_mode(vkraster
);
3694 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3695 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3697 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3698 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3699 if (depth_clip_state
) {
3700 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3703 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3704 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3705 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3706 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3707 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3708 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3710 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3711 S_0286D4_FLAT_SHADE_ENA(1) |
3712 S_0286D4_PNT_SPRITE_ENA(1) |
3713 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3714 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3715 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3716 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3717 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3719 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3720 S_028BE4_PIX_CENTER(1) | // TODO verify
3721 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3722 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3724 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3725 S_028814_FACE(vkraster
->frontFace
) |
3726 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3727 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3728 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3729 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3730 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3731 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3732 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3733 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3735 /* Conservative rasterization. */
3736 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3737 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3739 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3740 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3741 S_028804_OVERRASTERIZATION_AMOUNT(4);
3743 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3744 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3745 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3747 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3748 pa_sc_conservative_rast
|=
3749 S_028C4C_OVER_RAST_ENABLE(1) |
3750 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3751 S_028C4C_UNDER_RAST_ENABLE(0) |
3752 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3753 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3755 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3756 pa_sc_conservative_rast
|=
3757 S_028C4C_OVER_RAST_ENABLE(0) |
3758 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3759 S_028C4C_UNDER_RAST_ENABLE(1) |
3760 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3761 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3765 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3766 pa_sc_conservative_rast
);
3771 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3772 struct radv_pipeline
*pipeline
)
3774 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3776 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3777 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3778 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3780 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3781 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3782 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3783 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3784 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3786 /* The exclusion bits can be set to improve rasterization efficiency
3787 * if no sample lies on the pixel boundary (-8 sample offset). It's
3788 * currently always TRUE because the driver doesn't support 16 samples.
3790 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3791 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3792 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3793 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3795 /* GFX9: Flush DFSM when the AA mode changes. */
3796 if (pipeline
->device
->dfsm_allowed
) {
3797 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3798 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3803 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3804 struct radv_pipeline
*pipeline
)
3806 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3807 const struct radv_shader_variant
*vs
=
3808 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3809 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3810 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3811 unsigned vgt_primitiveid_en
= 0;
3812 uint32_t vgt_gs_mode
= 0;
3814 if (radv_pipeline_has_ngg(pipeline
))
3817 if (radv_pipeline_has_gs(pipeline
)) {
3818 const struct radv_shader_variant
*gs
=
3819 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3821 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3822 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3823 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3824 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3825 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3828 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3829 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3833 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3834 struct radeon_cmdbuf
*cs
,
3835 struct radv_pipeline
*pipeline
,
3836 struct radv_shader_variant
*shader
)
3838 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3840 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3841 radeon_emit(cs
, va
>> 8);
3842 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3843 radeon_emit(cs
, shader
->config
.rsrc1
);
3844 radeon_emit(cs
, shader
->config
.rsrc2
);
3846 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3847 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3848 clip_dist_mask
= outinfo
->clip_dist_mask
;
3849 cull_dist_mask
= outinfo
->cull_dist_mask
;
3850 total_mask
= clip_dist_mask
| cull_dist_mask
;
3851 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3852 outinfo
->writes_layer
||
3853 outinfo
->writes_viewport_index
;
3854 unsigned spi_vs_out_config
, nparams
;
3856 /* VS is required to export at least one param. */
3857 nparams
= MAX2(outinfo
->param_exports
, 1);
3858 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3860 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3861 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3864 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3866 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3867 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3868 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3869 V_02870C_SPI_SHADER_4COMP
:
3870 V_02870C_SPI_SHADER_NONE
) |
3871 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3872 V_02870C_SPI_SHADER_4COMP
:
3873 V_02870C_SPI_SHADER_NONE
) |
3874 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3875 V_02870C_SPI_SHADER_4COMP
:
3876 V_02870C_SPI_SHADER_NONE
));
3878 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3879 S_028818_VTX_W0_FMT(1) |
3880 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3881 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3882 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3884 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3885 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3886 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3887 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3888 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3889 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3890 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3891 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3892 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3893 cull_dist_mask
<< 8 |
3896 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3897 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3898 outinfo
->writes_viewport_index
);
3902 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3903 struct radv_pipeline
*pipeline
,
3904 struct radv_shader_variant
*shader
)
3906 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3908 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3909 radeon_emit(cs
, va
>> 8);
3910 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3911 radeon_emit(cs
, shader
->config
.rsrc1
);
3912 radeon_emit(cs
, shader
->config
.rsrc2
);
3916 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3917 struct radv_pipeline
*pipeline
,
3918 struct radv_shader_variant
*shader
,
3919 const struct radv_tessellation_state
*tess
)
3921 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3922 uint32_t rsrc2
= shader
->config
.rsrc2
;
3924 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3925 radeon_emit(cs
, va
>> 8);
3926 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3928 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3929 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3930 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3931 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3933 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3934 radeon_emit(cs
, shader
->config
.rsrc1
);
3935 radeon_emit(cs
, rsrc2
);
3939 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3940 struct radeon_cmdbuf
*cs
,
3941 struct radv_pipeline
*pipeline
,
3942 struct radv_shader_variant
*shader
)
3944 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3945 gl_shader_stage es_type
=
3946 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3947 struct radv_shader_variant
*es
=
3948 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3949 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3951 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3952 radeon_emit(cs
, va
>> 8);
3953 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3954 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3955 radeon_emit(cs
, shader
->config
.rsrc1
);
3956 radeon_emit(cs
, shader
->config
.rsrc2
);
3958 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3959 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3960 clip_dist_mask
= outinfo
->clip_dist_mask
;
3961 cull_dist_mask
= outinfo
->cull_dist_mask
;
3962 total_mask
= clip_dist_mask
| cull_dist_mask
;
3963 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3964 outinfo
->writes_layer
||
3965 outinfo
->writes_viewport_index
;
3966 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3967 (es
&& es
->info
.uses_prim_id
);
3968 bool break_wave_at_eoi
= false;
3972 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3973 struct radv_shader_variant
*gs
=
3974 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3976 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3977 break_wave_at_eoi
= true;
3980 nparams
= MAX2(outinfo
->param_exports
, 1);
3981 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3982 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3983 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3985 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3986 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3987 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3988 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3989 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3990 V_02870C_SPI_SHADER_4COMP
:
3991 V_02870C_SPI_SHADER_NONE
) |
3992 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3993 V_02870C_SPI_SHADER_4COMP
:
3994 V_02870C_SPI_SHADER_NONE
) |
3995 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3996 V_02870C_SPI_SHADER_4COMP
:
3997 V_02870C_SPI_SHADER_NONE
));
3999 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
4000 S_028818_VTX_W0_FMT(1) |
4001 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4002 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4003 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4004 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4005 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4006 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4007 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4008 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4009 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4010 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4011 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4012 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
4013 cull_dist_mask
<< 8 |
4016 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4017 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4018 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4020 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4021 ngg_state
->vgt_esgs_ring_itemsize
);
4023 /* NGG specific registers. */
4024 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4025 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4027 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4028 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4029 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4030 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4031 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4032 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4033 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4034 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4035 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4036 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4037 S_028B90_CNT(gs_num_invocations
) |
4038 S_028B90_ENABLE(gs_num_invocations
> 1) |
4039 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4041 /* User edge flags are set by the pos exports. If user edge flags are
4042 * not used, we must use hw-generated edge flags and pass them via
4043 * the prim export to prevent drawing lines on internal edges of
4044 * decomposed primitives (such as quads) with polygon mode = lines.
4046 * TODO: We should combine hw-generated edge flags with user edge
4047 * flags in the shader.
4049 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4050 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4051 !radv_pipeline_has_gs(pipeline
)) |
4052 /* Reuse for NGG. */
4053 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4055 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4056 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4057 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4059 /* Bug workaround for a possible hang with non-tessellation cases.
4060 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4062 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4064 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4065 !radv_pipeline_has_tess(pipeline
) &&
4066 ngg_state
->hw_max_esverts
!= 256) {
4067 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4069 if (ngg_state
->hw_max_esverts
> 5) {
4070 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4074 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4078 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4079 struct radv_pipeline
*pipeline
,
4080 struct radv_shader_variant
*shader
,
4081 const struct radv_tessellation_state
*tess
)
4083 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4085 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4086 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4088 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4089 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4091 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4094 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4095 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4096 radeon_emit(cs
, va
>> 8);
4097 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4099 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4100 radeon_emit(cs
, va
>> 8);
4101 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4104 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4105 radeon_emit(cs
, shader
->config
.rsrc1
);
4106 radeon_emit(cs
, hs_rsrc2
);
4108 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4109 radeon_emit(cs
, va
>> 8);
4110 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4111 radeon_emit(cs
, shader
->config
.rsrc1
);
4112 radeon_emit(cs
, shader
->config
.rsrc2
);
4117 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4118 struct radeon_cmdbuf
*cs
,
4119 struct radv_pipeline
*pipeline
,
4120 const struct radv_tessellation_state
*tess
)
4122 struct radv_shader_variant
*vs
;
4124 /* Skip shaders merged into HS/GS */
4125 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4129 if (vs
->info
.vs
.as_ls
)
4130 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4131 else if (vs
->info
.vs
.as_es
)
4132 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4133 else if (vs
->info
.is_ngg
)
4134 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4136 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4140 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4141 struct radeon_cmdbuf
*cs
,
4142 struct radv_pipeline
*pipeline
,
4143 const struct radv_tessellation_state
*tess
)
4145 if (!radv_pipeline_has_tess(pipeline
))
4148 struct radv_shader_variant
*tes
, *tcs
;
4150 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4151 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4154 if (tes
->info
.is_ngg
) {
4155 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4156 } else if (tes
->info
.tes
.as_es
)
4157 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4159 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4162 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4164 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4167 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4168 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4169 tess
->ls_hs_config
);
4171 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4172 tess
->ls_hs_config
);
4174 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4175 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4176 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4177 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4178 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4179 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4184 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4185 struct radeon_cmdbuf
*cs
,
4186 struct radv_pipeline
*pipeline
,
4187 struct radv_shader_variant
*gs
)
4189 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4190 unsigned gs_max_out_vertices
;
4191 uint8_t *num_components
;
4196 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4197 max_stream
= gs
->info
.gs
.max_stream
;
4198 num_components
= gs
->info
.gs
.num_stream_output_components
;
4200 offset
= num_components
[0] * gs_max_out_vertices
;
4202 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4203 radeon_emit(ctx_cs
, offset
);
4204 if (max_stream
>= 1)
4205 offset
+= num_components
[1] * gs_max_out_vertices
;
4206 radeon_emit(ctx_cs
, offset
);
4207 if (max_stream
>= 2)
4208 offset
+= num_components
[2] * gs_max_out_vertices
;
4209 radeon_emit(ctx_cs
, offset
);
4210 if (max_stream
>= 3)
4211 offset
+= num_components
[3] * gs_max_out_vertices
;
4212 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4214 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4215 radeon_emit(ctx_cs
, num_components
[0]);
4216 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4217 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4218 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4220 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4221 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4222 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4223 S_028B90_ENABLE(gs_num_invocations
> 0));
4225 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4226 gs_state
->vgt_esgs_ring_itemsize
);
4228 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4230 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4231 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4232 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4233 radeon_emit(cs
, va
>> 8);
4234 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4236 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4237 radeon_emit(cs
, va
>> 8);
4238 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4241 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4242 radeon_emit(cs
, gs
->config
.rsrc1
);
4243 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4245 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4246 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4248 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4249 radeon_emit(cs
, va
>> 8);
4250 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4251 radeon_emit(cs
, gs
->config
.rsrc1
);
4252 radeon_emit(cs
, gs
->config
.rsrc2
);
4255 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4259 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4260 struct radeon_cmdbuf
*cs
,
4261 struct radv_pipeline
*pipeline
)
4263 struct radv_shader_variant
*gs
;
4265 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4269 if (gs
->info
.is_ngg
)
4270 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4272 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4274 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4275 gs
->info
.gs
.vertices_out
);
4278 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4279 bool explicit, bool float16
)
4281 uint32_t ps_input_cntl
;
4282 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4283 ps_input_cntl
= S_028644_OFFSET(offset
);
4284 if (flat_shade
|| explicit)
4285 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4287 /* Force parameter cache to be read in passthrough
4290 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4293 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4294 S_028644_ATTR0_VALID(1);
4297 /* The input is a DEFAULT_VAL constant. */
4298 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4299 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4300 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4301 ps_input_cntl
= S_028644_OFFSET(0x20) |
4302 S_028644_DEFAULT_VAL(offset
);
4304 return ps_input_cntl
;
4308 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4309 struct radv_pipeline
*pipeline
)
4311 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4312 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4313 uint32_t ps_input_cntl
[32];
4315 unsigned ps_offset
= 0;
4317 if (ps
->info
.ps
.prim_id_input
) {
4318 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4319 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4320 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4325 if (ps
->info
.ps
.layer_input
||
4326 ps
->info
.needs_multiview_view_index
) {
4327 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4328 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4329 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4331 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4335 if (ps
->info
.ps
.viewport_index_input
) {
4336 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4337 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4338 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4340 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4344 if (ps
->info
.ps
.has_pcoord
) {
4346 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4347 ps_input_cntl
[ps_offset
] = val
;
4351 if (ps
->info
.ps
.num_input_clips_culls
) {
4354 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4355 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4356 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4360 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4361 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4362 ps
->info
.ps
.num_input_clips_culls
> 4) {
4363 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4368 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4373 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4376 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4377 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4378 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4383 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4384 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4385 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4387 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4392 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4393 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4394 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4400 radv_compute_db_shader_control(const struct radv_device
*device
,
4401 const struct radv_pipeline
*pipeline
,
4402 const struct radv_shader_variant
*ps
)
4404 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4406 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4407 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4409 z_order
= V_02880C_LATE_Z
;
4411 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4412 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4413 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4414 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4416 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4417 !device
->physical_device
->rad_info
.rbplus_allowed
;
4419 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4420 * but this appears to break Project Cars (DXVK). See
4421 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4423 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4425 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4426 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4427 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4428 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4429 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4430 S_02880C_Z_ORDER(z_order
) |
4431 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4432 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4433 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4434 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4435 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4439 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4440 struct radeon_cmdbuf
*cs
,
4441 struct radv_pipeline
*pipeline
)
4443 struct radv_shader_variant
*ps
;
4445 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4447 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4448 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4450 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4451 radeon_emit(cs
, va
>> 8);
4452 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4453 radeon_emit(cs
, ps
->config
.rsrc1
);
4454 radeon_emit(cs
, ps
->config
.rsrc2
);
4456 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4457 radv_compute_db_shader_control(pipeline
->device
,
4460 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4461 ps
->config
.spi_ps_input_ena
);
4463 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4464 ps
->config
.spi_ps_input_addr
);
4466 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4467 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4468 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4470 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4472 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4473 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4474 ps
->info
.ps
.writes_stencil
,
4475 ps
->info
.ps
.writes_sample_mask
));
4477 if (pipeline
->device
->dfsm_allowed
) {
4478 /* optimise this? */
4479 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4480 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4485 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4486 struct radv_pipeline
*pipeline
)
4488 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4489 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4492 unsigned vtx_reuse_depth
= 30;
4493 if (radv_pipeline_has_tess(pipeline
) &&
4494 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4495 vtx_reuse_depth
= 14;
4497 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4498 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4502 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4504 uint32_t stages
= 0;
4505 if (radv_pipeline_has_tess(pipeline
)) {
4506 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4507 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4509 if (radv_pipeline_has_gs(pipeline
))
4510 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4512 else if (radv_pipeline_has_ngg(pipeline
))
4513 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4515 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4516 } else if (radv_pipeline_has_gs(pipeline
)) {
4517 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4519 } else if (radv_pipeline_has_ngg(pipeline
)) {
4520 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4523 if (radv_pipeline_has_ngg(pipeline
)) {
4524 stages
|= S_028B54_PRIMGEN_EN(1);
4525 if (pipeline
->streamout_shader
)
4526 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4527 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4528 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4529 } else if (radv_pipeline_has_gs(pipeline
)) {
4530 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4533 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4534 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4536 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4537 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4539 if (radv_pipeline_has_tess(pipeline
))
4540 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4542 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4543 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4544 if (pipeline
->gs_copy_shader
)
4545 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4546 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4547 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4548 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4549 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4551 if (radv_pipeline_has_ngg(pipeline
))
4554 /* legacy GS only supports Wave64 */
4555 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4556 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4557 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4564 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4566 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4567 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4569 if (!discard_rectangle_info
)
4574 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4575 /* Interpret i as a bitmask, and then set the bit in the mask if
4576 * that combination of rectangles in which the pixel is contained
4577 * should pass the cliprect test. */
4578 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4580 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4584 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4595 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4596 struct radv_pipeline
*pipeline
,
4597 const struct radv_tessellation_state
*tess
)
4599 bool break_wave_at_eoi
= false;
4600 unsigned primgroup_size
;
4601 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4603 if (radv_pipeline_has_tess(pipeline
)) {
4604 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4605 } else if (radv_pipeline_has_gs(pipeline
)) {
4606 const struct gfx9_gs_info
*gs_state
=
4607 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4608 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4609 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4611 primgroup_size
= 128; /* recommended without a GS and tess */
4614 if (radv_pipeline_has_tess(pipeline
)) {
4615 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4616 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4617 break_wave_at_eoi
= true;
4620 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4621 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4622 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4623 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4624 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4628 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4629 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4630 const struct radv_graphics_pipeline_create_info
*extra
,
4631 const struct radv_blend_state
*blend
,
4632 const struct radv_tessellation_state
*tess
,
4633 unsigned prim
, unsigned gs_out
)
4635 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4636 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4639 ctx_cs
->max_dw
= 256;
4640 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4641 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4643 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4644 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4645 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4646 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4647 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4648 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4649 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4650 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4651 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4652 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4653 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4654 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4656 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4657 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4659 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4661 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4662 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4663 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4665 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4667 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4669 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4671 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4673 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4674 assert(cs
->cdw
<= cs
->max_dw
);
4677 static struct radv_ia_multi_vgt_param_helpers
4678 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4679 const struct radv_tessellation_state
*tess
,
4682 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4683 const struct radv_device
*device
= pipeline
->device
;
4685 if (radv_pipeline_has_tess(pipeline
))
4686 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4687 else if (radv_pipeline_has_gs(pipeline
))
4688 ia_multi_vgt_param
.primgroup_size
= 64;
4690 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4692 /* GS requirement. */
4693 ia_multi_vgt_param
.partial_es_wave
= false;
4694 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4695 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4696 ia_multi_vgt_param
.partial_es_wave
= true;
4698 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4699 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4700 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4701 * 4 shader engines. Set 1 to pass the assertion below.
4702 * The other cases are hardware requirements. */
4703 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4704 prim
== V_008958_DI_PT_POLYGON
||
4705 prim
== V_008958_DI_PT_LINELOOP
||
4706 prim
== V_008958_DI_PT_TRIFAN
||
4707 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4708 (pipeline
->graphics
.prim_restart_enable
&&
4709 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4710 (prim
!= V_008958_DI_PT_POINTLIST
&&
4711 prim
!= V_008958_DI_PT_LINESTRIP
))))
4712 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4715 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4716 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4717 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4718 if (radv_pipeline_has_gs(pipeline
) &&
4719 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4720 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4721 if (radv_pipeline_has_tess(pipeline
)) {
4722 /* SWITCH_ON_EOI must be set if PrimID is used. */
4723 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4724 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4725 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4728 ia_multi_vgt_param
.partial_vs_wave
= false;
4729 if (radv_pipeline_has_tess(pipeline
)) {
4730 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4731 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4732 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4733 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4734 radv_pipeline_has_gs(pipeline
))
4735 ia_multi_vgt_param
.partial_vs_wave
= true;
4736 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4737 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4738 if (radv_pipeline_has_gs(pipeline
)) {
4739 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4740 ia_multi_vgt_param
.partial_es_wave
= true;
4742 ia_multi_vgt_param
.partial_vs_wave
= true;
4747 /* Workaround for a VGT hang when strip primitive types are used with
4748 * primitive restart.
4750 if (pipeline
->graphics
.prim_restart_enable
&&
4751 (prim
== V_008958_DI_PT_LINESTRIP
||
4752 prim
== V_008958_DI_PT_TRISTRIP
||
4753 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4754 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4755 ia_multi_vgt_param
.partial_vs_wave
= true;
4758 if (radv_pipeline_has_gs(pipeline
)) {
4759 /* On these chips there is the possibility of a hang if the
4760 * pipeline uses a GS and partial_vs_wave is not set.
4762 * This mostly does not hit 4-SE chips, as those typically set
4763 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4764 * with GS due to another workaround.
4766 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4768 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4769 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4770 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4771 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4772 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4773 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4774 ia_multi_vgt_param
.partial_vs_wave
= true;
4778 ia_multi_vgt_param
.base
=
4779 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4780 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4781 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4782 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4783 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4785 return ia_multi_vgt_param
;
4790 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4791 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4793 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4794 pCreateInfo
->pVertexInputState
;
4795 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4797 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4798 const VkVertexInputAttributeDescription
*desc
=
4799 &vi_info
->pVertexAttributeDescriptions
[i
];
4800 unsigned loc
= desc
->location
;
4801 const struct vk_format_description
*format_desc
;
4803 format_desc
= vk_format_description(desc
->format
);
4805 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4808 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4809 const VkVertexInputBindingDescription
*desc
=
4810 &vi_info
->pVertexBindingDescriptions
[i
];
4812 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4813 pipeline
->num_vertex_bindings
=
4814 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4818 static struct radv_shader_variant
*
4819 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4823 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4824 struct radv_shader_variant
*shader
=
4825 radv_get_shader(pipeline
, i
);
4827 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4835 radv_secure_compile(struct radv_pipeline
*pipeline
,
4836 struct radv_device
*device
,
4837 const struct radv_pipeline_key
*key
,
4838 const VkPipelineShaderStageCreateInfo
**pStages
,
4839 const VkPipelineCreateFlags flags
,
4840 unsigned num_stages
)
4842 uint8_t allowed_pipeline_hashes
[2][20];
4843 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4844 pipeline
->layout
, key
, get_hash_flags(device
));
4846 /* Generate the GC copy hash */
4847 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4848 allowed_pipeline_hashes
[1][0] ^= 1;
4850 uint8_t allowed_hashes
[2][20];
4851 for (unsigned i
= 0; i
< 2; ++i
) {
4852 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4853 allowed_pipeline_hashes
[i
], 20,
4857 /* Do an early exit if all cache entries are already there. */
4858 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4859 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4860 void *copy_entry
= NULL
;
4861 if (may_need_copy_shader
)
4862 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4864 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4868 if(has_all_cache_entries
)
4871 unsigned process
= 0;
4872 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4874 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4875 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4876 device
->sc_state
->secure_compile_thread_counter
++;
4877 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4878 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4879 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4884 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4887 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4890 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4891 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4893 /* Fork a copy of the slim untainted secure compile process */
4894 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4895 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4897 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4898 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4899 return VK_ERROR_DEVICE_LOST
;
4901 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4902 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4904 /* Write pipeline / shader module out to secure process via pipe */
4905 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4906 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4908 /* Write pipeline layout out to secure process */
4909 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4910 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4911 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4912 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4913 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4914 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4917 /* Write pipeline key out to secure process */
4918 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4920 /* Write pipeline create flags out to secure process */
4921 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4923 /* Write stage and shader information out to secure process */
4924 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4925 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4929 /* Write stage out to secure process */
4930 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4931 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4933 /* Write entry point name out to secure process */
4934 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4935 write(fd_secure_input
, &name_size
, sizeof(size_t));
4936 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4938 /* Write shader module out to secure process */
4939 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4940 assert(!module
->nir
);
4941 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4942 write(fd_secure_input
, &module_size
, sizeof(size_t));
4943 write(fd_secure_input
, module
, module_size
);
4945 /* Write specialization info out to secure process */
4946 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4947 bool has_spec_info
= specInfo
? true : false;
4948 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4950 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4951 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4953 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4954 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4955 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4959 /* Read the data returned from the secure process */
4960 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4961 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4962 return VK_ERROR_DEVICE_LOST
;
4964 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4965 assert(device
->physical_device
->disk_cache
);
4967 uint8_t disk_sha1
[20];
4968 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4969 return VK_ERROR_DEVICE_LOST
;
4971 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4972 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4973 return VK_ERROR_DEVICE_LOST
;
4975 uint32_t entry_size
;
4976 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4977 return VK_ERROR_DEVICE_LOST
;
4979 struct cache_entry
*entry
= malloc(entry_size
);
4980 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4981 return VK_ERROR_DEVICE_LOST
;
4983 disk_cache_put(device
->physical_device
->disk_cache
,
4984 disk_sha1
, entry
, entry_size
,
4988 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4989 uint8_t disk_sha1
[20];
4990 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4991 return VK_ERROR_DEVICE_LOST
;
4993 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4994 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4995 return VK_ERROR_DEVICE_LOST
;
4998 struct cache_entry
*entry
= (struct cache_entry
*)
4999 disk_cache_get(device
->physical_device
->disk_cache
,
5002 uint8_t found
= entry
? 1 : 0;
5003 write(fd_secure_input
, &found
, sizeof(uint8_t));
5006 write(fd_secure_input
, &size
, sizeof(size_t));
5007 write(fd_secure_input
, entry
, size
);
5014 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
5015 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
5017 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
5018 device
->sc_state
->secure_compile_thread_counter
--;
5019 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5020 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5026 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5027 struct radv_device
*device
,
5028 struct radv_pipeline_cache
*cache
,
5029 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5030 const struct radv_graphics_pipeline_create_info
*extra
)
5033 bool has_view_index
= false;
5035 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5036 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5037 if (subpass
->view_mask
)
5038 has_view_index
= true;
5040 pipeline
->device
= device
;
5041 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5042 assert(pipeline
->layout
);
5044 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5046 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5047 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5048 radv_init_feedback(creation_feedback
);
5050 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5052 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5053 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5054 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5055 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5056 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5057 if(creation_feedback
)
5058 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5061 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5062 if (radv_device_use_secure_compile(device
->instance
)) {
5063 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5065 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5066 pCreateInfo
->flags
, pipeline_feedback
,
5068 if (result
!= VK_SUCCESS
)
5072 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5073 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5075 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5077 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5078 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5080 if (radv_pipeline_has_gs(pipeline
)) {
5081 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5082 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5083 } else if (radv_pipeline_has_tess(pipeline
)) {
5084 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5085 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5087 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5088 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5090 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5092 if (extra
&& extra
->use_rectlist
) {
5093 prim
= V_008958_DI_PT_RECTLIST
;
5094 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5095 pipeline
->graphics
.can_use_guardband
= true;
5096 if (radv_pipeline_has_ngg(pipeline
))
5097 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5099 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5100 /* prim vertex count will need TESS changes */
5101 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5103 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5105 /* Ensure that some export memory is always allocated, for two reasons:
5107 * 1) Correctness: The hardware ignores the EXEC mask if no export
5108 * memory is allocated, so KILL and alpha test do not work correctly
5110 * 2) Performance: Every shader needs at least a NULL export, even when
5111 * it writes no color/depth output. The NULL export instruction
5112 * stalls without this setting.
5114 * Don't add this to CB_SHADER_MASK.
5116 * GFX10 supports pixel shaders without exports by setting both the
5117 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5118 * instructions if any are present.
5120 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5121 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5122 ps
->info
.ps
.can_discard
) &&
5123 !blend
.spi_shader_col_format
) {
5124 if (!ps
->info
.ps
.writes_z
&&
5125 !ps
->info
.ps
.writes_stencil
&&
5126 !ps
->info
.ps
.writes_sample_mask
)
5127 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5130 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
5131 if (blend
.mrt0_is_dual_src
) {
5132 blend
.cb_shader_mask
|= (blend
.cb_shader_mask
& 0xf) << 4;
5136 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
5137 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
5138 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
5139 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
5140 /* According to the CB spec states, CB_SHADER_MASK should be
5141 * set to enable writes to all four channels of MRT0.
5143 blend
.cb_shader_mask
= 0xf;
5146 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5147 if (pipeline
->shaders
[i
]) {
5148 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5152 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5153 struct radv_shader_variant
*gs
=
5154 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5156 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5159 struct radv_tessellation_state tess
= {0};
5160 if (radv_pipeline_has_tess(pipeline
)) {
5161 if (prim
== V_008958_DI_PT_PATCH
) {
5162 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5163 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5165 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5168 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5170 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5172 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5173 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5175 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5176 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5177 if (loc
->sgpr_idx
!= -1) {
5178 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5179 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5180 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5181 pipeline
->graphics
.vtx_emit_num
= 3;
5183 pipeline
->graphics
.vtx_emit_num
= 2;
5186 /* Find the last vertex shader stage that eventually uses streamout. */
5187 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5189 result
= radv_pipeline_scratch_init(device
, pipeline
);
5190 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5196 radv_graphics_pipeline_create(
5198 VkPipelineCache _cache
,
5199 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5200 const struct radv_graphics_pipeline_create_info
*extra
,
5201 const VkAllocationCallbacks
*pAllocator
,
5202 VkPipeline
*pPipeline
)
5204 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5205 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5206 struct radv_pipeline
*pipeline
;
5209 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5210 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5211 if (pipeline
== NULL
)
5212 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5214 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5215 VK_OBJECT_TYPE_PIPELINE
);
5217 result
= radv_pipeline_init(pipeline
, device
, cache
,
5218 pCreateInfo
, extra
);
5219 if (result
!= VK_SUCCESS
) {
5220 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5224 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5229 VkResult
radv_CreateGraphicsPipelines(
5231 VkPipelineCache pipelineCache
,
5233 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5234 const VkAllocationCallbacks
* pAllocator
,
5235 VkPipeline
* pPipelines
)
5237 VkResult result
= VK_SUCCESS
;
5240 for (; i
< count
; i
++) {
5242 r
= radv_graphics_pipeline_create(_device
,
5245 NULL
, pAllocator
, &pPipelines
[i
]);
5246 if (r
!= VK_SUCCESS
) {
5248 pPipelines
[i
] = VK_NULL_HANDLE
;
5250 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5255 for (; i
< count
; ++i
)
5256 pPipelines
[i
] = VK_NULL_HANDLE
;
5263 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5265 struct radv_shader_variant
*compute_shader
;
5266 struct radv_device
*device
= pipeline
->device
;
5267 unsigned threads_per_threadgroup
;
5268 unsigned threadgroups_per_cu
= 1;
5269 unsigned waves_per_threadgroup
;
5270 unsigned max_waves_per_sh
= 0;
5273 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5274 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5276 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5277 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5279 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5280 radeon_emit(&pipeline
->cs
, va
>> 8);
5281 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5283 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5284 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5285 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5286 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5287 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5290 /* Calculate best compute resource limits. */
5291 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5292 compute_shader
->info
.cs
.block_size
[1] *
5293 compute_shader
->info
.cs
.block_size
[2];
5294 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5295 compute_shader
->info
.wave_size
);
5297 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5298 waves_per_threadgroup
== 1)
5299 threadgroups_per_cu
= 2;
5301 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5302 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5303 waves_per_threadgroup
,
5305 threadgroups_per_cu
));
5307 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5308 radeon_emit(&pipeline
->cs
,
5309 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5310 radeon_emit(&pipeline
->cs
,
5311 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5312 radeon_emit(&pipeline
->cs
,
5313 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5315 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5318 static struct radv_pipeline_key
5319 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5320 const VkComputePipelineCreateInfo
*pCreateInfo
)
5322 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5323 struct radv_pipeline_key key
;
5324 memset(&key
, 0, sizeof(key
));
5326 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5327 key
.optimisations_disabled
= 1;
5329 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5330 vk_find_struct_const(stage
->pNext
,
5331 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5333 if (subgroup_size
) {
5334 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5335 subgroup_size
->requiredSubgroupSize
== 64);
5336 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5342 static VkResult
radv_compute_pipeline_create(
5344 VkPipelineCache _cache
,
5345 const VkComputePipelineCreateInfo
* pCreateInfo
,
5346 const VkAllocationCallbacks
* pAllocator
,
5347 VkPipeline
* pPipeline
)
5349 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5350 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5351 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5352 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5353 struct radv_pipeline
*pipeline
;
5356 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5357 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5358 if (pipeline
== NULL
)
5359 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5361 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5362 VK_OBJECT_TYPE_PIPELINE
);
5364 pipeline
->device
= device
;
5365 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5366 assert(pipeline
->layout
);
5368 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5369 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5370 radv_init_feedback(creation_feedback
);
5372 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5373 if (creation_feedback
)
5374 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5376 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5378 struct radv_pipeline_key key
=
5379 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5381 if (radv_device_use_secure_compile(device
->instance
)) {
5382 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5383 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5387 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5388 pCreateInfo
->flags
, pipeline_feedback
,
5390 if (result
!= VK_SUCCESS
) {
5391 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5396 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5397 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5398 result
= radv_pipeline_scratch_init(device
, pipeline
);
5399 if (result
!= VK_SUCCESS
) {
5400 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5404 radv_compute_generate_pm4(pipeline
);
5406 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5411 VkResult
radv_CreateComputePipelines(
5413 VkPipelineCache pipelineCache
,
5415 const VkComputePipelineCreateInfo
* pCreateInfos
,
5416 const VkAllocationCallbacks
* pAllocator
,
5417 VkPipeline
* pPipelines
)
5419 VkResult result
= VK_SUCCESS
;
5422 for (; i
< count
; i
++) {
5424 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5426 pAllocator
, &pPipelines
[i
]);
5427 if (r
!= VK_SUCCESS
) {
5429 pPipelines
[i
] = VK_NULL_HANDLE
;
5431 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5436 for (; i
< count
; ++i
)
5437 pPipelines
[i
] = VK_NULL_HANDLE
;
5443 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5446 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5447 if (!pipeline
->shaders
[i
])
5450 if (i
== MESA_SHADER_GEOMETRY
&&
5451 !radv_pipeline_has_ngg(pipeline
)) {
5461 static struct radv_shader_variant
*
5462 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5464 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5465 if (!pipeline
->shaders
[i
])
5469 return pipeline
->shaders
[i
];
5474 if (i
== MESA_SHADER_GEOMETRY
&&
5475 !radv_pipeline_has_ngg(pipeline
)) {
5478 return pipeline
->gs_copy_shader
;
5488 /* Basically strlcpy (which does not exist on linux) specialized for
5490 static void desc_copy(char *desc
, const char *src
) {
5491 int len
= strlen(src
);
5492 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5493 memcpy(desc
, src
, len
);
5494 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5497 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5499 const VkPipelineInfoKHR
* pPipelineInfo
,
5500 uint32_t* pExecutableCount
,
5501 VkPipelineExecutablePropertiesKHR
* pProperties
)
5503 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5504 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5507 *pExecutableCount
= total_count
;
5511 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5512 for (unsigned i
= 0, executable_idx
= 0;
5513 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5514 if (!pipeline
->shaders
[i
])
5516 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5517 const char *name
= NULL
;
5518 const char *description
= NULL
;
5520 case MESA_SHADER_VERTEX
:
5521 name
= "Vertex Shader";
5522 description
= "Vulkan Vertex Shader";
5524 case MESA_SHADER_TESS_CTRL
:
5525 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5526 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5527 name
= "Vertex + Tessellation Control Shaders";
5528 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5530 name
= "Tessellation Control Shader";
5531 description
= "Vulkan Tessellation Control Shader";
5534 case MESA_SHADER_TESS_EVAL
:
5535 name
= "Tessellation Evaluation Shader";
5536 description
= "Vulkan Tessellation Evaluation Shader";
5538 case MESA_SHADER_GEOMETRY
:
5539 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5540 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5541 name
= "Tessellation Evaluation + Geometry Shaders";
5542 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5543 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5544 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5545 name
= "Vertex + Geometry Shader";
5546 description
= "Combined Vulkan Vertex and Geometry Shaders";
5548 name
= "Geometry Shader";
5549 description
= "Vulkan Geometry Shader";
5552 case MESA_SHADER_FRAGMENT
:
5553 name
= "Fragment Shader";
5554 description
= "Vulkan Fragment Shader";
5556 case MESA_SHADER_COMPUTE
:
5557 name
= "Compute Shader";
5558 description
= "Vulkan Compute Shader";
5562 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5563 desc_copy(pProperties
[executable_idx
].name
, name
);
5564 desc_copy(pProperties
[executable_idx
].description
, description
);
5567 if (i
== MESA_SHADER_GEOMETRY
&&
5568 !radv_pipeline_has_ngg(pipeline
)) {
5569 assert(pipeline
->gs_copy_shader
);
5570 if (executable_idx
>= count
)
5573 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5574 pProperties
[executable_idx
].subgroupSize
= 64;
5575 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5576 desc_copy(pProperties
[executable_idx
].description
,
5577 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5583 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5584 *pExecutableCount
= count
;
5588 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5590 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5591 uint32_t* pStatisticCount
,
5592 VkPipelineExecutableStatisticKHR
* pStatistics
)
5594 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5595 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5596 gl_shader_stage stage
;
5597 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5599 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5600 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5601 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5603 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5604 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5605 VkResult result
= VK_SUCCESS
;
5608 desc_copy(s
->name
, "SGPRs");
5609 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5610 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5611 s
->value
.u64
= shader
->config
.num_sgprs
;
5616 desc_copy(s
->name
, "VGPRs");
5617 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5618 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5619 s
->value
.u64
= shader
->config
.num_vgprs
;
5624 desc_copy(s
->name
, "Spilled SGPRs");
5625 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5626 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5627 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5632 desc_copy(s
->name
, "Spilled VGPRs");
5633 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5634 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5635 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5640 desc_copy(s
->name
, "PrivMem VGPRs");
5641 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5642 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5643 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5648 desc_copy(s
->name
, "Code size");
5649 desc_copy(s
->description
, "Code size in bytes");
5650 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5651 s
->value
.u64
= shader
->exec_size
;
5656 desc_copy(s
->name
, "LDS size");
5657 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5658 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5659 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5664 desc_copy(s
->name
, "Scratch size");
5665 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5666 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5667 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5672 desc_copy(s
->name
, "Subgroups per SIMD");
5673 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5674 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5675 s
->value
.u64
= max_waves
;
5679 if (shader
->statistics
) {
5680 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5681 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5682 uint32_t value
= shader
->statistics
->values
[i
];
5684 desc_copy(s
->name
, info
->name
);
5685 desc_copy(s
->description
, info
->desc
);
5686 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5687 s
->value
.u64
= value
;
5694 *pStatisticCount
= s
- pStatistics
;
5696 *pStatisticCount
= end
- pStatistics
;
5697 result
= VK_INCOMPLETE
;
5699 *pStatisticCount
= s
- pStatistics
;
5705 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5707 size_t total_size
= strlen(src
) + 1;
5710 *data_size
= total_size
;
5714 size_t size
= MIN2(total_size
, *data_size
);
5716 memcpy(data
, src
, size
);
5718 *((char*)data
+ size
- 1) = 0;
5719 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5722 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5724 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5725 uint32_t* pInternalRepresentationCount
,
5726 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5728 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5729 gl_shader_stage stage
;
5730 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5732 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5733 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5734 VkResult result
= VK_SUCCESS
;
5738 desc_copy(p
->name
, "NIR Shader(s)");
5739 desc_copy(p
->description
, "The optimized NIR shader(s)");
5740 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5741 result
= VK_INCOMPLETE
;
5748 if (pipeline
->device
->physical_device
->use_llvm
) {
5749 desc_copy(p
->name
, "LLVM IR");
5750 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5752 desc_copy(p
->name
, "ACO IR");
5753 desc_copy(p
->description
, "The ACO IR after some optimizations");
5755 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5756 result
= VK_INCOMPLETE
;
5763 desc_copy(p
->name
, "Assembly");
5764 desc_copy(p
->description
, "Final Assembly");
5765 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5766 result
= VK_INCOMPLETE
;
5770 if (!pInternalRepresentations
)
5771 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5773 result
= VK_INCOMPLETE
;
5774 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5776 *pInternalRepresentationCount
= p
- pInternalRepresentations
;