2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 static const VkPipelineMultisampleStateCreateInfo
*
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
88 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
89 return pCreateInfo
->pMultisampleState
;
93 static const VkPipelineTessellationStateCreateInfo
*
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
96 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
97 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
98 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
99 return pCreateInfo
->pTessellationState
;
105 static const VkPipelineDepthStencilStateCreateInfo
*
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
108 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
109 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
111 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
112 subpass
->depth_stencil_attachment
)
113 return pCreateInfo
->pDepthStencilState
;
117 static const VkPipelineColorBlendStateCreateInfo
*
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
120 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
121 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
123 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
124 subpass
->has_color_att
)
125 return pCreateInfo
->pColorBlendState
;
129 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
131 struct radv_shader_variant
*variant
= NULL
;
132 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
133 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
134 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
135 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
136 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
137 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
140 return variant
->info
.is_ngg
;
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
145 assert(radv_pipeline_has_ngg(pipeline
));
147 struct radv_shader_variant
*variant
= NULL
;
148 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
149 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
150 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
151 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
152 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
153 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
156 return variant
->info
.is_ngg_passthrough
;
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
161 if (!radv_pipeline_has_gs(pipeline
))
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
168 if (radv_pipeline_has_ngg(pipeline
))
171 assert(pipeline
->gs_copy_shader
);
176 radv_pipeline_destroy(struct radv_device
*device
,
177 struct radv_pipeline
*pipeline
,
178 const VkAllocationCallbacks
* allocator
)
180 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
181 if (pipeline
->shaders
[i
])
182 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
184 if (pipeline
->gs_copy_shader
)
185 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
188 free(pipeline
->cs
.buf
);
190 vk_object_base_finish(&pipeline
->base
);
191 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
194 void radv_DestroyPipeline(
196 VkPipeline _pipeline
,
197 const VkAllocationCallbacks
* pAllocator
)
199 RADV_FROM_HANDLE(radv_device
, device
, _device
);
200 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
205 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
208 static uint32_t get_hash_flags(struct radv_device
*device
)
210 uint32_t hash_flags
= 0;
212 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
213 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
214 if (device
->physical_device
->cs_wave_size
== 32)
215 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
216 if (device
->physical_device
->ps_wave_size
== 32)
217 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
218 if (device
->physical_device
->ge_wave_size
== 32)
219 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
220 if (device
->physical_device
->use_llvm
)
221 hash_flags
|= RADV_HASH_SHADER_LLVM
;
226 radv_pipeline_scratch_init(struct radv_device
*device
,
227 struct radv_pipeline
*pipeline
)
229 unsigned scratch_bytes_per_wave
= 0;
230 unsigned max_waves
= 0;
231 unsigned min_waves
= 1;
233 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
234 if (pipeline
->shaders
[i
] &&
235 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
236 unsigned max_stage_waves
= device
->scratch_waves
;
238 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
239 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
241 max_stage_waves
= MIN2(max_stage_waves
,
242 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
243 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
244 max_waves
= MAX2(max_waves
, max_stage_waves
);
248 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
249 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
250 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
251 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
252 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
255 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
256 pipeline
->max_waves
= max_waves
;
260 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
263 case VK_LOGIC_OP_CLEAR
:
264 return V_028808_ROP3_CLEAR
;
265 case VK_LOGIC_OP_AND
:
266 return V_028808_ROP3_AND
;
267 case VK_LOGIC_OP_AND_REVERSE
:
268 return V_028808_ROP3_AND_REVERSE
;
269 case VK_LOGIC_OP_COPY
:
270 return V_028808_ROP3_COPY
;
271 case VK_LOGIC_OP_AND_INVERTED
:
272 return V_028808_ROP3_AND_INVERTED
;
273 case VK_LOGIC_OP_NO_OP
:
274 return V_028808_ROP3_NO_OP
;
275 case VK_LOGIC_OP_XOR
:
276 return V_028808_ROP3_XOR
;
278 return V_028808_ROP3_OR
;
279 case VK_LOGIC_OP_NOR
:
280 return V_028808_ROP3_NOR
;
281 case VK_LOGIC_OP_EQUIVALENT
:
282 return V_028808_ROP3_EQUIVALENT
;
283 case VK_LOGIC_OP_INVERT
:
284 return V_028808_ROP3_INVERT
;
285 case VK_LOGIC_OP_OR_REVERSE
:
286 return V_028808_ROP3_OR_REVERSE
;
287 case VK_LOGIC_OP_COPY_INVERTED
:
288 return V_028808_ROP3_COPY_INVERTED
;
289 case VK_LOGIC_OP_OR_INVERTED
:
290 return V_028808_ROP3_OR_INVERTED
;
291 case VK_LOGIC_OP_NAND
:
292 return V_028808_ROP3_NAND
;
293 case VK_LOGIC_OP_SET
:
294 return V_028808_ROP3_SET
;
296 unreachable("Unhandled logic op");
301 static uint32_t si_translate_blend_function(VkBlendOp op
)
304 case VK_BLEND_OP_ADD
:
305 return V_028780_COMB_DST_PLUS_SRC
;
306 case VK_BLEND_OP_SUBTRACT
:
307 return V_028780_COMB_SRC_MINUS_DST
;
308 case VK_BLEND_OP_REVERSE_SUBTRACT
:
309 return V_028780_COMB_DST_MINUS_SRC
;
310 case VK_BLEND_OP_MIN
:
311 return V_028780_COMB_MIN_DST_SRC
;
312 case VK_BLEND_OP_MAX
:
313 return V_028780_COMB_MAX_DST_SRC
;
319 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
322 case VK_BLEND_FACTOR_ZERO
:
323 return V_028780_BLEND_ZERO
;
324 case VK_BLEND_FACTOR_ONE
:
325 return V_028780_BLEND_ONE
;
326 case VK_BLEND_FACTOR_SRC_COLOR
:
327 return V_028780_BLEND_SRC_COLOR
;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
330 case VK_BLEND_FACTOR_DST_COLOR
:
331 return V_028780_BLEND_DST_COLOR
;
332 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
333 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
334 case VK_BLEND_FACTOR_SRC_ALPHA
:
335 return V_028780_BLEND_SRC_ALPHA
;
336 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
337 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
338 case VK_BLEND_FACTOR_DST_ALPHA
:
339 return V_028780_BLEND_DST_ALPHA
;
340 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
341 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
342 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
343 return V_028780_BLEND_CONSTANT_COLOR
;
344 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
345 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
346 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
347 return V_028780_BLEND_CONSTANT_ALPHA
;
348 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
349 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
350 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
351 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
352 case VK_BLEND_FACTOR_SRC1_COLOR
:
353 return V_028780_BLEND_SRC1_COLOR
;
354 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
355 return V_028780_BLEND_INV_SRC1_COLOR
;
356 case VK_BLEND_FACTOR_SRC1_ALPHA
:
357 return V_028780_BLEND_SRC1_ALPHA
;
358 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
359 return V_028780_BLEND_INV_SRC1_ALPHA
;
365 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
368 case VK_BLEND_OP_ADD
:
369 return V_028760_OPT_COMB_ADD
;
370 case VK_BLEND_OP_SUBTRACT
:
371 return V_028760_OPT_COMB_SUBTRACT
;
372 case VK_BLEND_OP_REVERSE_SUBTRACT
:
373 return V_028760_OPT_COMB_REVSUBTRACT
;
374 case VK_BLEND_OP_MIN
:
375 return V_028760_OPT_COMB_MIN
;
376 case VK_BLEND_OP_MAX
:
377 return V_028760_OPT_COMB_MAX
;
379 return V_028760_OPT_COMB_BLEND_DISABLED
;
383 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
386 case VK_BLEND_FACTOR_ZERO
:
387 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
388 case VK_BLEND_FACTOR_ONE
:
389 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
390 case VK_BLEND_FACTOR_SRC_COLOR
:
391 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
392 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
394 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
395 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
396 case VK_BLEND_FACTOR_SRC_ALPHA
:
397 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
399 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
400 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
402 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
404 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
409 * Get rid of DST in the blend factors by commuting the operands:
410 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
412 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
413 unsigned *dst_factor
, unsigned expected_dst
,
414 unsigned replacement_src
)
416 if (*src_factor
== expected_dst
&&
417 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
418 *src_factor
= VK_BLEND_FACTOR_ZERO
;
419 *dst_factor
= replacement_src
;
421 /* Commuting the operands requires reversing subtractions. */
422 if (*func
== VK_BLEND_OP_SUBTRACT
)
423 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
424 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
425 *func
= VK_BLEND_OP_SUBTRACT
;
429 static bool si_blend_factor_uses_dst(unsigned factor
)
431 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
432 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
433 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
434 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
435 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
438 static bool is_dual_src(VkBlendFactor factor
)
441 case VK_BLEND_FACTOR_SRC1_COLOR
:
442 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
443 case VK_BLEND_FACTOR_SRC1_ALPHA
:
444 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
451 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
453 bool blend_need_alpha
)
455 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
456 struct ac_spi_color_formats formats
= {};
457 unsigned format
, ntype
, swap
;
459 format
= radv_translate_colorformat(vk_format
);
460 ntype
= radv_translate_color_numformat(vk_format
, desc
,
461 vk_format_get_first_non_void_channel(vk_format
));
462 swap
= radv_translate_colorswap(vk_format
, false);
464 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
466 if (blend_enable
&& blend_need_alpha
)
467 return formats
.blend_alpha
;
468 else if(blend_need_alpha
)
469 return formats
.alpha
;
470 else if(blend_enable
)
471 return formats
.blend
;
473 return formats
.normal
;
477 format_is_int8(VkFormat format
)
479 const struct vk_format_description
*desc
= vk_format_description(format
);
480 int channel
= vk_format_get_first_non_void_channel(format
);
482 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
483 desc
->channel
[channel
].size
== 8;
487 format_is_int10(VkFormat format
)
489 const struct vk_format_description
*desc
= vk_format_description(format
);
491 if (desc
->nr_channels
!= 4)
493 for (unsigned i
= 0; i
< 4; i
++) {
494 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
501 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
502 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
503 struct radv_blend_state
*blend
)
505 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
506 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
507 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
508 unsigned num_targets
;
510 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
513 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
514 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
515 cf
= V_028714_SPI_SHADER_ZERO
;
517 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
519 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
521 cf
= radv_choose_spi_color_format(attachment
->format
,
523 blend
->need_src_alpha
& (1 << i
));
525 if (format_is_int8(attachment
->format
))
527 if (format_is_int10(attachment
->format
))
531 col_format
|= cf
<< (4 * i
);
534 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
535 /* When a subpass doesn't have any color attachments, write the
536 * alpha channel of MRT0 when alpha coverage is enabled because
537 * the depth attachment needs it.
539 col_format
|= V_028714_SPI_SHADER_32_AR
;
542 /* If the i-th target format is set, all previous target formats must
543 * be non-zero to avoid hangs.
545 num_targets
= (util_last_bit(col_format
) + 3) / 4;
546 for (unsigned i
= 0; i
< num_targets
; i
++) {
547 if (!(col_format
& (0xf << (i
* 4)))) {
548 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
552 /* The output for dual source blending should have the same format as
555 if (blend
->mrt0_is_dual_src
)
556 col_format
|= (col_format
& 0xf) << 4;
558 blend
->spi_shader_col_format
= col_format
;
559 blend
->col_format_is_int8
= is_int8
;
560 blend
->col_format_is_int10
= is_int10
;
564 * Ordered so that for each i,
565 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
567 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
568 VK_FORMAT_R32_SFLOAT
,
569 VK_FORMAT_R32G32_SFLOAT
,
570 VK_FORMAT_R8G8B8A8_UNORM
,
571 VK_FORMAT_R16G16B16A16_UNORM
,
572 VK_FORMAT_R16G16B16A16_SNORM
,
573 VK_FORMAT_R16G16B16A16_UINT
,
574 VK_FORMAT_R16G16B16A16_SINT
,
575 VK_FORMAT_R32G32B32A32_SFLOAT
,
576 VK_FORMAT_R8G8B8A8_UINT
,
577 VK_FORMAT_R8G8B8A8_SINT
,
578 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
579 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
582 unsigned radv_format_meta_fs_key(VkFormat format
)
584 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
586 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
587 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
588 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
590 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
591 bool is_int8
= format_is_int8(format
);
592 bool is_int10
= format_is_int10(format
);
594 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
598 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
599 VkBlendOp op
, VkBlendFactor src
,
600 VkBlendFactor dst
, unsigned chanmask
)
602 /* Src factor is allowed when it does not depend on Dst. */
603 static const uint32_t src_allowed
=
604 (1u << VK_BLEND_FACTOR_ONE
) |
605 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
607 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
609 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
610 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
611 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
612 (1u << VK_BLEND_FACTOR_ZERO
) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
620 if (dst
== VK_BLEND_FACTOR_ONE
&&
621 (src_allowed
& (1u << src
))) {
622 /* Addition is commutative, but floating point addition isn't
623 * associative: subtle changes can be introduced via different
624 * rounding. Be conservative, only enable for min and max.
626 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
627 blend
->commutative_4bit
|= chanmask
;
631 static struct radv_blend_state
632 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
633 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
634 const struct radv_graphics_pipeline_create_info
*extra
)
636 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
637 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
638 struct radv_blend_state blend
= {0};
639 unsigned mode
= V_028808_CB_NORMAL
;
642 if (extra
&& extra
->custom_blend_mode
) {
643 blend
.single_cb_enable
= true;
644 mode
= extra
->custom_blend_mode
;
647 blend
.cb_color_control
= 0;
649 if (vkblend
->logicOpEnable
)
650 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
652 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
655 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
656 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
657 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
658 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
659 S_028B70_OFFSET_ROUND(1);
661 if (vkms
&& vkms
->alphaToCoverageEnable
) {
662 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
663 blend
.need_src_alpha
|= 0x1;
666 blend
.cb_target_mask
= 0;
668 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
669 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
670 unsigned blend_cntl
= 0;
671 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
672 VkBlendOp eqRGB
= att
->colorBlendOp
;
673 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
674 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
675 VkBlendOp eqA
= att
->alphaBlendOp
;
676 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
677 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
679 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
681 if (!att
->colorWriteMask
)
684 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
685 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
686 if (!att
->blendEnable
) {
687 blend
.cb_blend_control
[i
] = blend_cntl
;
691 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
693 blend
.mrt0_is_dual_src
= true;
695 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
696 srcRGB
= VK_BLEND_FACTOR_ONE
;
697 dstRGB
= VK_BLEND_FACTOR_ONE
;
699 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
700 srcA
= VK_BLEND_FACTOR_ONE
;
701 dstA
= VK_BLEND_FACTOR_ONE
;
704 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
706 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
709 /* Blending optimizations for RB+.
710 * These transformations don't change the behavior.
712 * First, get rid of DST in the blend factors:
713 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
715 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
716 VK_BLEND_FACTOR_DST_COLOR
,
717 VK_BLEND_FACTOR_SRC_COLOR
);
719 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
720 VK_BLEND_FACTOR_DST_COLOR
,
721 VK_BLEND_FACTOR_SRC_COLOR
);
723 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
724 VK_BLEND_FACTOR_DST_ALPHA
,
725 VK_BLEND_FACTOR_SRC_ALPHA
);
727 /* Look up the ideal settings from tables. */
728 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
729 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
730 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
731 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
733 /* Handle interdependencies. */
734 if (si_blend_factor_uses_dst(srcRGB
))
735 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
736 if (si_blend_factor_uses_dst(srcA
))
737 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
739 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
740 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
741 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
742 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
743 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
745 /* Set the final value. */
746 blend
.sx_mrt_blend_opt
[i
] =
747 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
748 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
749 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
750 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
751 S_028760_ALPHA_DST_OPT(dstA_opt
) |
752 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
753 blend_cntl
|= S_028780_ENABLE(1);
755 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
756 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
757 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
758 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
759 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
760 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
761 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
762 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
764 blend
.cb_blend_control
[i
] = blend_cntl
;
766 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
768 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
769 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
770 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
771 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
772 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
773 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
774 blend
.need_src_alpha
|= 1 << i
;
776 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
777 blend
.cb_blend_control
[i
] = 0;
778 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
782 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
783 /* Disable RB+ blend optimizations for dual source blending. */
784 if (blend
.mrt0_is_dual_src
) {
785 for (i
= 0; i
< 8; i
++) {
786 blend
.sx_mrt_blend_opt
[i
] =
787 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
788 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
792 /* RB+ doesn't work with dual source blending, logic op and
795 if (blend
.mrt0_is_dual_src
||
796 (vkblend
&& vkblend
->logicOpEnable
) ||
797 mode
== V_028808_CB_RESOLVE
)
798 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
801 if (blend
.cb_target_mask
)
802 blend
.cb_color_control
|= S_028808_MODE(mode
);
804 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
806 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
810 static uint32_t si_translate_fill(VkPolygonMode func
)
813 case VK_POLYGON_MODE_FILL
:
814 return V_028814_X_DRAW_TRIANGLES
;
815 case VK_POLYGON_MODE_LINE
:
816 return V_028814_X_DRAW_LINES
;
817 case VK_POLYGON_MODE_POINT
:
818 return V_028814_X_DRAW_POINTS
;
821 return V_028814_X_DRAW_POINTS
;
825 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
827 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
828 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
829 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
830 uint32_t ps_iter_samples
= 1;
831 uint32_t num_samples
;
833 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
835 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
836 * subpass uses color attachments, totalSamples is the number of
837 * samples of the color attachments. Otherwise, totalSamples is the
838 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
839 * specified at pipeline creation time."
841 if (subpass
->has_color_att
) {
842 num_samples
= subpass
->color_sample_count
;
844 num_samples
= vkms
->rasterizationSamples
;
847 if (vkms
->sampleShadingEnable
) {
848 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
849 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
851 return ps_iter_samples
;
855 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
857 return pCreateInfo
->depthTestEnable
&&
858 pCreateInfo
->depthWriteEnable
&&
859 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
863 radv_writes_stencil(const VkStencilOpState
*state
)
865 return state
->writeMask
&&
866 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
867 state
->passOp
!= VK_STENCIL_OP_KEEP
||
868 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
872 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
874 return pCreateInfo
->stencilTestEnable
&&
875 (radv_writes_stencil(&pCreateInfo
->front
) ||
876 radv_writes_stencil(&pCreateInfo
->back
));
880 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
882 return radv_is_depth_write_enabled(pCreateInfo
) ||
883 radv_is_stencil_write_enabled(pCreateInfo
);
887 radv_order_invariant_stencil_op(VkStencilOp op
)
889 /* REPLACE is normally order invariant, except when the stencil
890 * reference value is written by the fragment shader. Tracking this
891 * interaction does not seem worth the effort, so be conservative.
893 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
894 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
895 op
!= VK_STENCIL_OP_REPLACE
;
899 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
901 /* Compute whether, assuming Z writes are disabled, this stencil state
902 * is order invariant in the sense that the set of passing fragments as
903 * well as the final stencil buffer result does not depend on the order
906 return !state
->writeMask
||
907 /* The following assumes that Z writes are disabled. */
908 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
909 radv_order_invariant_stencil_op(state
->passOp
) &&
910 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
911 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
912 radv_order_invariant_stencil_op(state
->failOp
));
916 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
918 VkDynamicState ds_states
[] = {
919 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
,
920 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
,
921 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
,
922 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
,
923 VK_DYNAMIC_STATE_STENCIL_OP_EXT
,
926 if (pCreateInfo
->pDynamicState
) {
927 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
928 for (uint32_t i
= 0; i
< count
; i
++) {
929 for (uint32_t j
= 0; j
< ARRAY_SIZE(ds_states
); j
++) {
930 if (pCreateInfo
->pDynamicState
->pDynamicStates
[i
] == ds_states
[j
])
940 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
941 struct radv_blend_state
*blend
,
942 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
944 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
945 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
946 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
947 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
948 unsigned colormask
= blend
->cb_target_enabled_4bit
;
950 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
953 /* Be conservative if a logic operation is enabled with color buffers. */
954 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
957 /* Be conservative if an extended dynamic depth/stencil state is
958 * enabled because the driver can't update out-of-order rasterization
961 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo
))
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant
= {
966 .zs
= true, .pass_set
= true
970 struct radv_render_pass_attachment
*attachment
=
971 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
972 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
973 struct radv_dsa_order_invariance order_invariance
[2];
974 struct radv_shader_variant
*ps
=
975 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
980 bool zfunc_is_ordered
=
981 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
982 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
983 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
984 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
985 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
987 bool nozwrite_and_order_invariant_stencil
=
988 !radv_is_ds_write_enabled(vkds
) ||
989 (!radv_is_depth_write_enabled(vkds
) &&
990 radv_order_invariant_stencil_state(&vkds
->front
) &&
991 radv_order_invariant_stencil_state(&vkds
->back
));
993 order_invariance
[1].zs
=
994 nozwrite_and_order_invariant_stencil
||
995 (!radv_is_stencil_write_enabled(vkds
) &&
997 order_invariance
[0].zs
=
998 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1000 order_invariance
[1].pass_set
=
1001 nozwrite_and_order_invariant_stencil
||
1002 (!radv_is_stencil_write_enabled(vkds
) &&
1003 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1004 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1005 order_invariance
[0].pass_set
=
1006 !radv_is_depth_write_enabled(vkds
) ||
1007 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1008 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1010 dsa_order_invariant
= order_invariance
[has_stencil
];
1011 if (!dsa_order_invariant
.zs
)
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1018 ps
->info
.ps
.writes_memory
&&
1019 ps
->info
.ps
.early_fragment_test
&&
1020 !dsa_order_invariant
.pass_set
)
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1026 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1027 !dsa_order_invariant
.pass_set
;
1030 /* No color buffers are enabled for writing. */
1034 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1037 /* Only commutative blending. */
1038 if (blendmask
& ~blend
->commutative_4bit
)
1041 if (!dsa_order_invariant
.pass_set
)
1045 if (colormask
& ~blendmask
)
1052 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1053 struct radv_blend_state
*blend
,
1054 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1056 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1057 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1058 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1059 bool out_of_order_rast
= false;
1060 int ps_iter_samples
= 1;
1061 uint32_t mask
= 0xffff;
1064 ms
->num_samples
= vkms
->rasterizationSamples
;
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1068 * "Sample shading is enabled for a graphics pipeline:
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1080 * Otherwise, sample shading is considered disabled."
1082 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1083 ps_iter_samples
= ms
->num_samples
;
1085 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1088 ms
->num_samples
= 1;
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1092 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1093 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1097 out_of_order_rast
= true;
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1103 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1106 ms
->pa_sc_aa_config
= 0;
1107 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1108 S_028804_INCOHERENT_EQAA_READS(1) |
1109 S_028804_INTERPOLATE_COMP_Z(1) |
1110 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1111 ms
->pa_sc_mode_cntl_1
=
1112 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1113 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1114 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1115 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1117 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1118 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1119 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1121 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1123 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1124 S_028A48_VPORT_SCISSOR_ENABLE(1);
1126 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1127 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1128 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1130 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1131 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1132 /* From the Vulkan spec 1.1.129:
1134 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1135 * are being rasterized, sample locations may all be
1136 * treated as being at the pixel center (this may
1137 * affect attribute and depth interpolation)."
1139 ms
->num_samples
= 1;
1143 if (ms
->num_samples
> 1) {
1144 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1145 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1146 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1147 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1148 unsigned log_z_samples
= util_logbase2(z_samples
);
1149 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1150 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1151 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1152 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1153 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1154 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1155 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1156 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1157 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1158 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1159 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1160 if (ps_iter_samples
> 1)
1161 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1164 if (vkms
&& vkms
->pSampleMask
) {
1165 mask
= vkms
->pSampleMask
[0] & 0xffff;
1168 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1169 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1173 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1176 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1177 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1187 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1190 unreachable("unhandled primitive type");
1195 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1198 case 0: /* GL_POINTS */
1199 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1200 case 1: /* GL_LINES */
1201 case 3: /* GL_LINE_STRIP */
1202 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1203 case 0x8E7A: /* GL_ISOLINES */
1204 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1206 case 4: /* GL_TRIANGLES */
1207 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1208 case 5: /* GL_TRIANGLE_STRIP */
1209 case 7: /* GL_QUADS */
1210 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1218 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1221 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1222 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1223 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1224 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1228 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1234 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1241 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1244 case VK_DYNAMIC_STATE_VIEWPORT
:
1245 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
1246 return RADV_DYNAMIC_VIEWPORT
;
1247 case VK_DYNAMIC_STATE_SCISSOR
:
1248 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
1249 return RADV_DYNAMIC_SCISSOR
;
1250 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1251 return RADV_DYNAMIC_LINE_WIDTH
;
1252 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1253 return RADV_DYNAMIC_DEPTH_BIAS
;
1254 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1255 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1256 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1257 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1258 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1259 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1260 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1261 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1262 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1263 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1264 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1265 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1266 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1267 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1268 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1269 return RADV_DYNAMIC_LINE_STIPPLE
;
1270 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1271 return RADV_DYNAMIC_CULL_MODE
;
1272 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1273 return RADV_DYNAMIC_FRONT_FACE
;
1274 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1275 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1276 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
1277 return RADV_DYNAMIC_DEPTH_TEST_ENABLE
;
1278 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
1279 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE
;
1280 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
1281 return RADV_DYNAMIC_DEPTH_COMPARE_OP
;
1282 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
1283 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
1284 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
1285 return RADV_DYNAMIC_STENCIL_TEST_ENABLE
;
1286 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
1287 return RADV_DYNAMIC_STENCIL_OP
;
1288 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
1289 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1291 unreachable("Unhandled dynamic state");
1295 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1297 uint32_t states
= RADV_DYNAMIC_ALL
;
1299 /* If rasterization is disabled we do not care about any of the
1300 * dynamic states, since they are all rasterization related only,
1301 * except primitive topology and vertex binding stride.
1303 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1304 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
|
1305 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1307 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1308 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1310 if (!pCreateInfo
->pDepthStencilState
||
1311 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1312 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1314 if (!pCreateInfo
->pDepthStencilState
||
1315 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1316 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1317 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1318 RADV_DYNAMIC_STENCIL_REFERENCE
);
1320 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1321 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1323 if (!pCreateInfo
->pMultisampleState
||
1324 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1325 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1326 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1328 if (!pCreateInfo
->pRasterizationState
||
1329 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1330 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1331 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1333 /* TODO: blend constants & line width. */
1340 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1341 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1342 const struct radv_graphics_pipeline_create_info
*extra
)
1344 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1345 uint32_t states
= needed_states
;
1346 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1347 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1349 pipeline
->dynamic_state
= default_dynamic_state
;
1350 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1352 if (pCreateInfo
->pDynamicState
) {
1353 /* Remove all of the states that are marked as dynamic */
1354 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1355 for (uint32_t s
= 0; s
< count
; s
++)
1356 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1359 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1361 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1362 assert(pCreateInfo
->pViewportState
);
1364 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1365 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1366 typed_memcpy(dynamic
->viewport
.viewports
,
1367 pCreateInfo
->pViewportState
->pViewports
,
1368 pCreateInfo
->pViewportState
->viewportCount
);
1372 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1373 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1374 if (states
& RADV_DYNAMIC_SCISSOR
) {
1375 typed_memcpy(dynamic
->scissor
.scissors
,
1376 pCreateInfo
->pViewportState
->pScissors
,
1377 pCreateInfo
->pViewportState
->scissorCount
);
1381 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1382 assert(pCreateInfo
->pRasterizationState
);
1383 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1386 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1387 assert(pCreateInfo
->pRasterizationState
);
1388 dynamic
->depth_bias
.bias
=
1389 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1390 dynamic
->depth_bias
.clamp
=
1391 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1392 dynamic
->depth_bias
.slope
=
1393 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1396 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1398 * pColorBlendState is [...] NULL if the pipeline has rasterization
1399 * disabled or if the subpass of the render pass the pipeline is
1400 * created against does not use any color attachments.
1402 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1403 assert(pCreateInfo
->pColorBlendState
);
1404 typed_memcpy(dynamic
->blend_constants
,
1405 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1408 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1409 dynamic
->cull_mode
=
1410 pCreateInfo
->pRasterizationState
->cullMode
;
1413 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1414 dynamic
->front_face
=
1415 pCreateInfo
->pRasterizationState
->frontFace
;
1418 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1419 dynamic
->primitive_topology
=
1420 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1421 if (extra
&& extra
->use_rectlist
) {
1422 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1426 /* If there is no depthstencil attachment, then don't read
1427 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1428 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1429 * no need to override the depthstencil defaults in
1430 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1432 * Section 9.2 of the Vulkan 1.0.15 spec says:
1434 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1435 * disabled or if the subpass of the render pass the pipeline is created
1436 * against does not use a depth/stencil attachment.
1438 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1439 assert(pCreateInfo
->pDepthStencilState
);
1441 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1442 dynamic
->depth_bounds
.min
=
1443 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1444 dynamic
->depth_bounds
.max
=
1445 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1448 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1449 dynamic
->stencil_compare_mask
.front
=
1450 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1451 dynamic
->stencil_compare_mask
.back
=
1452 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1455 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1456 dynamic
->stencil_write_mask
.front
=
1457 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1458 dynamic
->stencil_write_mask
.back
=
1459 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1462 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1463 dynamic
->stencil_reference
.front
=
1464 pCreateInfo
->pDepthStencilState
->front
.reference
;
1465 dynamic
->stencil_reference
.back
=
1466 pCreateInfo
->pDepthStencilState
->back
.reference
;
1469 if (states
& RADV_DYNAMIC_DEPTH_TEST_ENABLE
) {
1470 dynamic
->depth_test_enable
=
1471 pCreateInfo
->pDepthStencilState
->depthTestEnable
;
1474 if (states
& RADV_DYNAMIC_DEPTH_WRITE_ENABLE
) {
1475 dynamic
->depth_write_enable
=
1476 pCreateInfo
->pDepthStencilState
->depthWriteEnable
;
1479 if (states
& RADV_DYNAMIC_DEPTH_COMPARE_OP
) {
1480 dynamic
->depth_compare_op
=
1481 pCreateInfo
->pDepthStencilState
->depthCompareOp
;
1484 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
1485 dynamic
->depth_bounds_test_enable
=
1486 pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
;
1489 if (states
& RADV_DYNAMIC_STENCIL_TEST_ENABLE
) {
1490 dynamic
->stencil_test_enable
=
1491 pCreateInfo
->pDepthStencilState
->stencilTestEnable
;
1494 if (states
& RADV_DYNAMIC_STENCIL_OP
) {
1495 dynamic
->stencil_op
.front
.compare_op
=
1496 pCreateInfo
->pDepthStencilState
->front
.compareOp
;
1497 dynamic
->stencil_op
.front
.fail_op
=
1498 pCreateInfo
->pDepthStencilState
->front
.failOp
;
1499 dynamic
->stencil_op
.front
.pass_op
=
1500 pCreateInfo
->pDepthStencilState
->front
.passOp
;
1501 dynamic
->stencil_op
.front
.depth_fail_op
=
1502 pCreateInfo
->pDepthStencilState
->front
.depthFailOp
;
1504 dynamic
->stencil_op
.back
.compare_op
=
1505 pCreateInfo
->pDepthStencilState
->back
.compareOp
;
1506 dynamic
->stencil_op
.back
.fail_op
=
1507 pCreateInfo
->pDepthStencilState
->back
.failOp
;
1508 dynamic
->stencil_op
.back
.pass_op
=
1509 pCreateInfo
->pDepthStencilState
->back
.passOp
;
1510 dynamic
->stencil_op
.back
.depth_fail_op
=
1511 pCreateInfo
->pDepthStencilState
->back
.depthFailOp
;
1515 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1516 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1517 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1518 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1519 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1520 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1521 discard_rectangle_info
->pDiscardRectangles
,
1522 discard_rectangle_info
->discardRectangleCount
);
1526 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1527 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1528 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1529 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1530 /* If sampleLocationsEnable is VK_FALSE, the default sample
1531 * locations are used and the values specified in
1532 * sampleLocationsInfo are ignored.
1534 if (sample_location_info
->sampleLocationsEnable
) {
1535 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1536 &sample_location_info
->sampleLocationsInfo
;
1538 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1540 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1541 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1542 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1543 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1544 pSampleLocationsInfo
->pSampleLocations
,
1545 pSampleLocationsInfo
->sampleLocationsCount
);
1549 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1550 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1551 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1552 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1553 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1554 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1557 if (!(states
& RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
))
1558 pipeline
->graphics
.uses_dynamic_stride
= true;
1560 pipeline
->dynamic_state
.mask
= states
;
1564 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1565 const struct radv_pipeline
*pipeline
,
1567 struct radv_shader_info
*infos
,
1568 struct gfx9_gs_info
*out
)
1570 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1571 struct radv_es_output_info
*es_info
;
1572 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1573 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1575 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1576 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1577 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1579 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1580 bool uses_adjacency
;
1581 switch(key
->topology
) {
1582 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1583 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1584 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1585 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1586 uses_adjacency
= true;
1589 uses_adjacency
= false;
1593 /* All these are in dwords: */
1594 /* We can't allow using the whole LDS, because GS waves compete with
1595 * other shader stages for LDS space. */
1596 const unsigned max_lds_size
= 8 * 1024;
1597 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1598 unsigned esgs_lds_size
;
1600 /* All these are per subgroup: */
1601 const unsigned max_out_prims
= 32 * 1024;
1602 const unsigned max_es_verts
= 255;
1603 const unsigned ideal_gs_prims
= 64;
1604 unsigned max_gs_prims
, gs_prims
;
1605 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1607 if (uses_adjacency
|| gs_num_invocations
> 1)
1608 max_gs_prims
= 127 / gs_num_invocations
;
1612 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1613 * Make sure we don't go over the maximum value.
1615 if (gs_info
->gs
.vertices_out
> 0) {
1616 max_gs_prims
= MIN2(max_gs_prims
,
1618 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1620 assert(max_gs_prims
> 0);
1622 /* If the primitive has adjacency, halve the number of vertices
1623 * that will be reused in multiple primitives.
1625 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1627 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1628 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1630 /* Compute ESGS LDS size based on the worst case number of ES vertices
1631 * needed to create the target number of GS prims per subgroup.
1633 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1635 /* If total LDS usage is too big, refactor partitions based on ratio
1636 * of ESGS item sizes.
1638 if (esgs_lds_size
> max_lds_size
) {
1639 /* Our target GS Prims Per Subgroup was too large. Calculate
1640 * the maximum number of GS Prims Per Subgroup that will fit
1641 * into LDS, capped by the maximum that the hardware can support.
1643 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1645 assert(gs_prims
> 0);
1646 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1649 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1650 assert(esgs_lds_size
<= max_lds_size
);
1653 /* Now calculate remaining ESGS information. */
1655 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1657 es_verts
= max_es_verts
;
1659 /* Vertices for adjacency primitives are not always reused, so restore
1660 * it for ES_VERTS_PER_SUBGRP.
1662 min_es_verts
= gs_info
->gs
.vertices_in
;
1664 /* For normal primitives, the VGT only checks if they are past the ES
1665 * verts per subgroup after allocating a full GS primitive and if they
1666 * are, kick off a new subgroup. But if those additional ES verts are
1667 * unique (e.g. not reused) we need to make sure there is enough LDS
1668 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1670 es_verts
-= min_es_verts
- 1;
1672 uint32_t es_verts_per_subgroup
= es_verts
;
1673 uint32_t gs_prims_per_subgroup
= gs_prims
;
1674 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1675 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1676 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1677 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1678 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1679 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1680 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1681 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1682 assert(max_prims_per_subgroup
<= max_out_prims
);
1685 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1686 unsigned min_verts_per_prim
, bool use_adjacency
)
1688 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1691 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1695 radv_get_num_input_vertices(nir_shader
**nir
)
1697 if (nir
[MESA_SHADER_GEOMETRY
]) {
1698 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1700 return gs
->info
.gs
.vertices_in
;
1703 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1704 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1706 if (tes
->info
.tess
.point_mode
)
1708 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1717 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1718 struct radv_pipeline
*pipeline
,
1720 struct radv_shader_info
*infos
,
1721 struct gfx10_ngg_info
*ngg
)
1723 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1724 struct radv_es_output_info
*es_info
=
1725 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1726 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1727 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1728 unsigned min_verts_per_prim
=
1729 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1730 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1731 bool uses_adjacency
;
1732 switch(key
->topology
) {
1733 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1734 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1735 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1736 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1737 uses_adjacency
= true;
1740 uses_adjacency
= false;
1744 /* All these are in dwords: */
1745 /* We can't allow using the whole LDS, because GS waves compete with
1746 * other shader stages for LDS space.
1748 * TODO: We should really take the shader's internal LDS use into
1749 * account. The linker will fail if the size is greater than
1752 const unsigned max_lds_size
= 8 * 1024 - 768;
1753 const unsigned target_lds_size
= max_lds_size
;
1754 unsigned esvert_lds_size
= 0;
1755 unsigned gsprim_lds_size
= 0;
1757 /* All these are per subgroup: */
1758 bool max_vert_out_per_gs_instance
= false;
1759 unsigned max_esverts_base
= 256;
1760 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1762 /* Hardware has the following non-natural restrictions on the value
1763 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1765 * - at most 252 for any line input primitive type
1766 * - at most 251 for any quad input primitive type
1767 * - at most 251 for triangle strips with adjacency (this happens to
1768 * be the natural limit for triangle *lists* with adjacency)
1770 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1772 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1773 unsigned max_out_verts_per_gsprim
=
1774 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1776 if (max_out_verts_per_gsprim
<= 256) {
1777 if (max_out_verts_per_gsprim
) {
1778 max_gsprims_base
= MIN2(max_gsprims_base
,
1779 256 / max_out_verts_per_gsprim
);
1782 /* Use special multi-cycling mode in which each GS
1783 * instance gets its own subgroup. Does not work with
1785 max_vert_out_per_gs_instance
= true;
1786 max_gsprims_base
= 1;
1787 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1790 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1791 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1794 /* LDS size for passing data from GS to ES. */
1795 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1796 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1797 : &infos
[MESA_SHADER_VERTEX
].so
;
1799 if (so_info
->num_outputs
)
1800 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1802 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1803 * corresponding to the ES thread of the provoking vertex. All
1804 * ES threads load and export PrimitiveID for their thread.
1806 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1807 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1808 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1811 unsigned max_gsprims
= max_gsprims_base
;
1812 unsigned max_esverts
= max_esverts_base
;
1814 if (esvert_lds_size
)
1815 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1816 if (gsprim_lds_size
)
1817 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1819 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1820 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1821 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1823 if (esvert_lds_size
|| gsprim_lds_size
) {
1824 /* Now that we have a rough proportionality between esverts
1825 * and gsprims based on the primitive type, scale both of them
1826 * down simultaneously based on required LDS space.
1828 * We could be smarter about this if we knew how much vertex
1831 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1832 max_gsprims
* gsprim_lds_size
;
1833 if (lds_total
> target_lds_size
) {
1834 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1835 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1837 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1838 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1839 min_verts_per_prim
, uses_adjacency
);
1840 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1844 /* Round up towards full wave sizes for better ALU utilization. */
1845 if (!max_vert_out_per_gs_instance
) {
1846 unsigned orig_max_esverts
;
1847 unsigned orig_max_gsprims
;
1850 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1851 wavesize
= gs_info
->wave_size
;
1853 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1854 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1855 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1859 orig_max_esverts
= max_esverts
;
1860 orig_max_gsprims
= max_gsprims
;
1862 max_esverts
= align(max_esverts
, wavesize
);
1863 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1864 if (esvert_lds_size
)
1865 max_esverts
= MIN2(max_esverts
,
1866 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1868 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1870 max_gsprims
= align(max_gsprims
, wavesize
);
1871 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1872 if (gsprim_lds_size
)
1873 max_gsprims
= MIN2(max_gsprims
,
1874 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1876 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1877 min_verts_per_prim
, uses_adjacency
);
1878 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1879 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1882 /* Hardware restriction: minimum value of max_esverts */
1883 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1885 unsigned max_out_vertices
=
1886 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1887 gs_type
== MESA_SHADER_GEOMETRY
?
1888 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1890 assert(max_out_vertices
<= 256);
1892 unsigned prim_amp_factor
= 1;
1893 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1894 /* Number of output primitives per GS input primitive after
1896 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1899 /* The GE only checks against the maximum number of ES verts after
1900 * allocating a full GS primitive. So we need to ensure that whenever
1901 * this check passes, there is enough space for a full primitive without
1904 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1905 ngg
->max_gsprims
= max_gsprims
;
1906 ngg
->max_out_verts
= max_out_vertices
;
1907 ngg
->prim_amp_factor
= prim_amp_factor
;
1908 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1909 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1910 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1912 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1913 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1915 ngg
->vgt_esgs_ring_itemsize
= 1;
1918 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1920 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1924 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1925 const struct gfx9_gs_info
*gs
)
1927 struct radv_device
*device
= pipeline
->device
;
1928 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1929 unsigned wave_size
= 64;
1930 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1931 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1932 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1934 unsigned gs_vertex_reuse
=
1935 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1936 unsigned alignment
= 256 * num_se
;
1937 /* The maximum size is 63.999 MB per SE. */
1938 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1939 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1941 /* Calculate the minimum size. */
1942 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1943 wave_size
, alignment
);
1944 /* These are recommended sizes, not minimum sizes. */
1945 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1946 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1947 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1948 gs_info
->gs
.max_gsvs_emit_size
;
1950 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1951 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1952 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1954 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1955 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1957 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1960 struct radv_shader_variant
*
1961 radv_get_shader(struct radv_pipeline
*pipeline
,
1962 gl_shader_stage stage
)
1964 if (stage
== MESA_SHADER_VERTEX
) {
1965 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1966 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1967 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1968 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1969 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1970 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1971 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1972 if (!radv_pipeline_has_tess(pipeline
))
1974 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1975 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1976 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1977 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1979 return pipeline
->shaders
[stage
];
1982 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
1984 if (radv_pipeline_has_gs(pipeline
))
1985 if (radv_pipeline_has_ngg(pipeline
))
1986 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
1988 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
1989 else if (radv_pipeline_has_tess(pipeline
))
1990 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
1992 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
1996 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
1998 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
1999 int shader_count
= 0;
2001 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2002 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2004 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2005 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2007 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2008 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2010 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2011 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2013 if(shaders
[MESA_SHADER_VERTEX
]) {
2014 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2017 if (shader_count
> 1) {
2018 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2019 unsigned last
= ordered_shaders
[0]->info
.stage
;
2021 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2022 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2023 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2025 for (int i
= 0; i
< shader_count
; ++i
) {
2026 nir_variable_mode mask
= 0;
2028 if (ordered_shaders
[i
]->info
.stage
!= first
)
2029 mask
= mask
| nir_var_shader_in
;
2031 if (ordered_shaders
[i
]->info
.stage
!= last
)
2032 mask
= mask
| nir_var_shader_out
;
2034 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2035 radv_optimize_nir(ordered_shaders
[i
], false, false);
2039 for (int i
= 1; i
< shader_count
; ++i
) {
2040 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2041 ordered_shaders
[i
- 1]);
2043 if (nir_link_opt_varyings(ordered_shaders
[i
],
2044 ordered_shaders
[i
- 1]))
2045 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2047 nir_remove_dead_variables(ordered_shaders
[i
],
2048 nir_var_shader_out
, NULL
);
2049 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2050 nir_var_shader_in
, NULL
);
2052 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2053 ordered_shaders
[i
- 1]);
2055 nir_compact_varyings(ordered_shaders
[i
],
2056 ordered_shaders
[i
- 1], true);
2059 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2060 ac_lower_indirect_derefs(ordered_shaders
[i
],
2061 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2063 radv_optimize_nir(ordered_shaders
[i
], false, false);
2065 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2066 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2067 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2069 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2075 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2076 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2078 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2079 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2081 if (!has_tess
&& !has_gs
)
2084 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2085 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2087 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2088 /* These are merged into the next stage */
2089 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2090 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2094 nir_linked_io_var_info vs2tcs
=
2095 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2096 nir_linked_io_var_info tcs2tes
=
2097 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2099 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2100 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2101 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2102 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2103 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2104 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2107 nir_linked_io_var_info tes2gs
=
2108 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2110 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2111 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2113 } else if (has_gs
) {
2114 nir_linked_io_var_info vs2gs
=
2115 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2117 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2118 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2123 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2124 uint32_t attrib_binding
)
2126 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2127 const VkVertexInputBindingDescription
*input_binding
=
2128 &input_state
->pVertexBindingDescriptions
[i
];
2130 if (input_binding
->binding
== attrib_binding
)
2131 return input_binding
->stride
;
2137 static struct radv_pipeline_key
2138 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2139 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2140 const struct radv_blend_state
*blend
)
2142 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2143 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2144 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2145 pCreateInfo
->pVertexInputState
;
2146 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2147 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2149 struct radv_pipeline_key key
;
2150 memset(&key
, 0, sizeof(key
));
2152 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2153 key
.optimisations_disabled
= 1;
2155 key
.has_multiview_view_index
= !!subpass
->view_mask
;
2157 uint32_t binding_input_rate
= 0;
2158 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2159 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2160 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2161 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2162 binding_input_rate
|= 1u << binding
;
2163 instance_rate_divisors
[binding
] = 1;
2166 if (divisor_state
) {
2167 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2168 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2169 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2173 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2174 const VkVertexInputAttributeDescription
*desc
=
2175 &input_state
->pVertexAttributeDescriptions
[i
];
2176 const struct vk_format_description
*format_desc
;
2177 unsigned location
= desc
->location
;
2178 unsigned binding
= desc
->binding
;
2179 unsigned num_format
, data_format
;
2182 if (binding_input_rate
& (1u << binding
)) {
2183 key
.instance_rate_inputs
|= 1u << location
;
2184 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2187 format_desc
= vk_format_description(desc
->format
);
2188 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2190 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2191 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2193 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2194 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2195 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2196 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2198 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2199 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2200 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2203 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2204 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2205 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2207 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2208 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2209 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2211 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2212 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2213 adjust
= RADV_ALPHA_ADJUST_SINT
;
2219 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2222 switch (desc
->format
) {
2223 case VK_FORMAT_B8G8R8A8_UNORM
:
2224 case VK_FORMAT_B8G8R8A8_SNORM
:
2225 case VK_FORMAT_B8G8R8A8_USCALED
:
2226 case VK_FORMAT_B8G8R8A8_SSCALED
:
2227 case VK_FORMAT_B8G8R8A8_UINT
:
2228 case VK_FORMAT_B8G8R8A8_SINT
:
2229 case VK_FORMAT_B8G8R8A8_SRGB
:
2230 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2231 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2232 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2233 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2234 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2235 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2236 key
.vertex_post_shuffle
|= 1 << location
;
2243 const VkPipelineTessellationStateCreateInfo
*tess
=
2244 radv_pipeline_get_tessellation_state(pCreateInfo
);
2246 key
.tess_input_vertices
= tess
->patchControlPoints
;
2248 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2249 radv_pipeline_get_multisample_state(pCreateInfo
);
2250 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2251 uint32_t num_samples
= vkms
->rasterizationSamples
;
2252 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2253 key
.num_samples
= num_samples
;
2254 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2257 key
.col_format
= blend
->spi_shader_col_format
;
2258 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2259 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2260 key
.is_int8
= blend
->col_format_is_int8
;
2261 key
.is_int10
= blend
->col_format_is_int10
;
2264 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2265 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2271 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2273 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2274 bool uses_xfb
= !!xfb
;
2281 radv_fill_shader_keys(struct radv_device
*device
,
2282 struct radv_shader_variant_key
*keys
,
2283 const struct radv_pipeline_key
*key
,
2286 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2287 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2288 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2289 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2290 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2291 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2292 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2293 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2294 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2296 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2298 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2299 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2300 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2301 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2302 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2304 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2307 if (nir
[MESA_SHADER_GEOMETRY
]) {
2308 if (nir
[MESA_SHADER_TESS_CTRL
])
2309 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2311 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2314 if (device
->physical_device
->use_ngg
) {
2315 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2316 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2318 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2321 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2322 nir
[MESA_SHADER_GEOMETRY
] &&
2323 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2324 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2325 /* Fallback to the legacy path if tessellation is
2326 * enabled with extreme geometry because
2327 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2330 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2333 if (!device
->physical_device
->use_ngg_gs
) {
2334 if (nir
[MESA_SHADER_GEOMETRY
]) {
2335 if (nir
[MESA_SHADER_TESS_CTRL
])
2336 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2338 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2342 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2344 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2349 bool uses_xfb
= nir
[last_xfb_stage
] &&
2350 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2352 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2353 if (nir
[MESA_SHADER_TESS_CTRL
])
2354 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2356 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2359 /* Determine if the pipeline is eligible for the NGG passthrough
2360 * mode. It can't be enabled for geometry shaders, for NGG
2361 * streamout or for vertex shaders that export the primitive ID
2362 * (this is checked later because we don't have the info here.)
2364 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2365 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2366 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2367 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2368 } else if (nir
[MESA_SHADER_VERTEX
] &&
2369 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2370 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2375 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2376 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2378 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2379 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2380 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2381 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2382 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2383 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2385 if (nir
[MESA_SHADER_COMPUTE
]) {
2386 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2391 radv_get_wave_size(struct radv_device
*device
,
2392 const VkPipelineShaderStageCreateInfo
*pStage
,
2393 gl_shader_stage stage
,
2394 const struct radv_shader_variant_key
*key
)
2396 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2398 else if (stage
== MESA_SHADER_COMPUTE
) {
2399 if (key
->cs
.subgroup_size
) {
2400 /* Return the required subgroup size if specified. */
2401 return key
->cs
.subgroup_size
;
2403 return device
->physical_device
->cs_wave_size
;
2405 else if (stage
== MESA_SHADER_FRAGMENT
)
2406 return device
->physical_device
->ps_wave_size
;
2408 return device
->physical_device
->ge_wave_size
;
2412 radv_get_ballot_bit_size(struct radv_device
*device
,
2413 const VkPipelineShaderStageCreateInfo
*pStage
,
2414 gl_shader_stage stage
,
2415 const struct radv_shader_variant_key
*key
)
2417 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2418 return key
->cs
.subgroup_size
;
2423 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2424 const VkPipelineShaderStageCreateInfo
**pStages
,
2425 struct radv_shader_variant_key
*keys
,
2426 struct radv_shader_info
*infos
,
2429 unsigned active_stages
= 0;
2430 unsigned filled_stages
= 0;
2432 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2434 active_stages
|= (1 << i
);
2437 if (nir
[MESA_SHADER_FRAGMENT
]) {
2438 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2439 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2441 &keys
[MESA_SHADER_FRAGMENT
],
2442 &infos
[MESA_SHADER_FRAGMENT
],
2443 pipeline
->device
->physical_device
->use_llvm
);
2445 /* TODO: These are no longer used as keys we should refactor this */
2446 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2447 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2448 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2449 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2450 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2451 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2452 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2453 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2454 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2455 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2456 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2457 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2458 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2459 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2460 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2461 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2463 /* NGG passthrough mode can't be enabled for vertex shaders
2464 * that export the primitive ID.
2466 * TODO: I should really refactor the keys logic.
2468 if (nir
[MESA_SHADER_VERTEX
] &&
2469 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2470 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2473 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2476 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2477 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2478 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2479 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2480 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2483 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2484 nir
[MESA_SHADER_TESS_CTRL
]) {
2485 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2486 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2487 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2489 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2491 for (int i
= 0; i
< 2; i
++) {
2492 radv_nir_shader_info_pass(combined_nir
[i
],
2493 pipeline
->layout
, &key
,
2494 &infos
[MESA_SHADER_TESS_CTRL
],
2495 pipeline
->device
->physical_device
->use_llvm
);
2498 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2499 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2500 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2501 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2503 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2504 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2507 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2508 nir
[MESA_SHADER_GEOMETRY
]) {
2509 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2510 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2512 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2514 for (int i
= 0; i
< 2; i
++) {
2515 radv_nir_shader_info_pass(combined_nir
[i
],
2518 &infos
[MESA_SHADER_GEOMETRY
],
2519 pipeline
->device
->physical_device
->use_llvm
);
2522 filled_stages
|= (1 << pre_stage
);
2523 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2526 active_stages
^= filled_stages
;
2527 while (active_stages
) {
2528 int i
= u_bit_scan(&active_stages
);
2530 if (i
== MESA_SHADER_TESS_CTRL
) {
2531 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2532 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2535 if (i
== MESA_SHADER_TESS_EVAL
) {
2536 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2537 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2538 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2539 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2542 radv_nir_shader_info_init(&infos
[i
]);
2543 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2544 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2547 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2549 infos
[i
].wave_size
=
2550 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2552 infos
[i
].ballot_bit_size
=
2553 radv_get_ballot_bit_size(pipeline
->device
,
2561 merge_tess_info(struct shader_info
*tes_info
,
2562 const struct shader_info
*tcs_info
)
2564 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2566 * "PointMode. Controls generation of points rather than triangles
2567 * or lines. This functionality defaults to disabled, and is
2568 * enabled if either shader stage includes the execution mode.
2570 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2571 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2572 * and OutputVertices, it says:
2574 * "One mode must be set in at least one of the tessellation
2577 * So, the fields can be set in either the TCS or TES, but they must
2578 * agree if set in both. Our backend looks at TES, so bitwise-or in
2579 * the values from the TCS.
2581 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2582 tes_info
->tess
.tcs_vertices_out
== 0 ||
2583 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2584 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2586 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2587 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2588 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2589 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2591 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2592 tes_info
->tess
.primitive_mode
== 0 ||
2593 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2594 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2595 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2596 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2600 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2605 if (ext
->pPipelineCreationFeedback
) {
2606 ext
->pPipelineCreationFeedback
->flags
= 0;
2607 ext
->pPipelineCreationFeedback
->duration
= 0;
2610 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2611 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2612 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2617 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2622 feedback
->duration
-= radv_get_current_time();
2623 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2627 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2632 feedback
->duration
+= radv_get_current_time();
2633 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2634 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2637 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2638 struct radv_device
*device
,
2639 struct radv_pipeline_cache
*cache
,
2640 const struct radv_pipeline_key
*key
,
2641 const VkPipelineShaderStageCreateInfo
**pStages
,
2642 const VkPipelineCreateFlags flags
,
2643 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2644 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2646 struct radv_shader_module fs_m
= {0};
2647 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2648 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2649 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2650 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2651 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2652 unsigned char hash
[20], gs_copy_hash
[20];
2653 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2654 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2655 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2656 device
->keep_shader_info
;
2658 radv_start_feedback(pipeline_feedback
);
2660 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2662 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2663 if (modules
[i
]->nir
)
2664 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2665 strlen(modules
[i
]->nir
->info
.name
),
2668 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2672 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2673 memcpy(gs_copy_hash
, hash
, 20);
2674 gs_copy_hash
[0] ^= 1;
2676 bool found_in_application_cache
= true;
2677 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2678 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2679 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2680 &found_in_application_cache
);
2681 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2684 if (!keep_executable_info
&& !keep_statistic_info
&&
2685 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2686 &found_in_application_cache
) &&
2687 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2688 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2692 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2693 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2694 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2697 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2699 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2700 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2701 fs_m
.nir
= fs_b
.shader
;
2702 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2705 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2706 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2707 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2712 radv_start_feedback(stage_feedbacks
[i
]);
2714 if (key
->compute_subgroup_size
) {
2715 /* Only compute shaders currently support requiring a
2716 * specific subgroup size.
2718 assert(i
== MESA_SHADER_COMPUTE
);
2719 subgroup_size
= key
->compute_subgroup_size
;
2720 ballot_bit_size
= key
->compute_subgroup_size
;
2723 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2724 stage
? stage
->pName
: "main", i
,
2725 stage
? stage
->pSpecializationInfo
: NULL
,
2726 flags
, pipeline
->layout
,
2727 subgroup_size
, ballot_bit_size
);
2729 /* We don't want to alter meta shaders IR directly so clone it
2732 if (nir
[i
]->info
.name
) {
2733 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2736 radv_stop_feedback(stage_feedbacks
[i
], false);
2739 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2740 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2741 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2744 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2745 radv_link_shaders(pipeline
, nir
);
2747 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2749 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2751 /* do this again since information such as outputs_read can be out-of-date */
2752 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2754 if (device
->physical_device
->use_llvm
) {
2755 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2757 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2758 nir_lower_non_uniform_ubo_access
|
2759 nir_lower_non_uniform_ssbo_access
|
2760 nir_lower_non_uniform_texture_access
|
2761 nir_lower_non_uniform_image_access
);
2766 if (nir
[MESA_SHADER_FRAGMENT
])
2767 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2769 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2770 if (radv_can_dump_shader(device
, modules
[i
], false))
2771 nir_print_shader(nir
[i
], stderr
);
2774 radv_fill_shader_keys(device
, keys
, key
, nir
);
2776 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2778 if ((nir
[MESA_SHADER_VERTEX
] &&
2779 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2780 (nir
[MESA_SHADER_TESS_EVAL
] &&
2781 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2782 struct gfx10_ngg_info
*ngg_info
;
2784 if (nir
[MESA_SHADER_GEOMETRY
])
2785 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2786 else if (nir
[MESA_SHADER_TESS_CTRL
])
2787 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2789 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2791 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2792 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2793 struct gfx9_gs_info
*gs_info
=
2794 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2796 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2799 if(modules
[MESA_SHADER_GEOMETRY
]) {
2800 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2801 if (!pipeline
->gs_copy_shader
&&
2802 !radv_pipeline_has_ngg(pipeline
)) {
2803 struct radv_shader_info info
= {};
2804 struct radv_shader_variant_key key
= {};
2806 key
.has_multiview_view_index
=
2807 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2809 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2810 pipeline
->layout
, &key
,
2811 &info
, pipeline
->device
->physical_device
->use_llvm
);
2812 info
.wave_size
= 64; /* Wave32 not supported. */
2813 info
.ballot_bit_size
= 64;
2815 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2816 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2817 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2818 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2821 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2822 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2823 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2825 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2826 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2828 radv_pipeline_cache_insert_shaders(device
, cache
,
2833 free(gs_copy_binary
);
2836 if (nir
[MESA_SHADER_FRAGMENT
]) {
2837 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2838 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2840 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2841 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2842 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2843 infos
+ MESA_SHADER_FRAGMENT
,
2844 keep_executable_info
, keep_statistic_info
,
2845 &binaries
[MESA_SHADER_FRAGMENT
]);
2847 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2851 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2852 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2853 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2854 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2855 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2857 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2859 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2861 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2862 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2864 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2866 modules
[MESA_SHADER_VERTEX
] = NULL
;
2867 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2868 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2871 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2872 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2873 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2874 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2876 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2878 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2880 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2881 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2883 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2885 modules
[pre_stage
] = NULL
;
2888 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2889 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2890 if (i
== MESA_SHADER_TESS_CTRL
) {
2891 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2893 if (i
== MESA_SHADER_TESS_EVAL
) {
2894 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2895 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2898 radv_start_feedback(stage_feedbacks
[i
]);
2900 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2902 keys
+ i
, infos
+ i
, keep_executable_info
,
2903 keep_statistic_info
, &binaries
[i
]);
2905 radv_stop_feedback(stage_feedbacks
[i
], false);
2909 if (!keep_executable_info
&& !keep_statistic_info
) {
2910 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2914 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2917 ralloc_free(nir
[i
]);
2919 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2920 radv_shader_dump_stats(device
,
2921 pipeline
->shaders
[i
],
2927 ralloc_free(fs_m
.nir
);
2929 radv_stop_feedback(pipeline_feedback
, false);
2934 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2935 gl_shader_stage stage
, enum chip_class chip_class
)
2937 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2938 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2939 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2942 case MESA_SHADER_FRAGMENT
:
2943 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2944 case MESA_SHADER_VERTEX
:
2946 if (chip_class
>= GFX10
) {
2947 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2948 } else if (chip_class
== GFX9
) {
2949 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2951 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2957 if (chip_class
>= GFX10
) {
2958 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2960 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2965 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2967 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2968 case MESA_SHADER_GEOMETRY
:
2969 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2970 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2971 case MESA_SHADER_COMPUTE
:
2972 return R_00B900_COMPUTE_USER_DATA_0
;
2973 case MESA_SHADER_TESS_CTRL
:
2974 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2975 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2976 case MESA_SHADER_TESS_EVAL
:
2978 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2979 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2980 } else if (has_ngg
) {
2981 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2983 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2986 unreachable("unknown shader");
2990 struct radv_bin_size_entry
{
2996 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2998 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3002 /* One shader engine */
3008 { UINT_MAX
, { 0, 0}},
3011 /* Two shader engines */
3017 { UINT_MAX
, { 0, 0}},
3020 /* Four shader engines */
3025 { UINT_MAX
, { 0, 0}},
3031 /* One shader engine */
3037 { UINT_MAX
, { 0, 0}},
3040 /* Two shader engines */
3046 { UINT_MAX
, { 0, 0}},
3049 /* Four shader engines */
3056 { UINT_MAX
, { 0, 0}},
3062 /* One shader engine */
3069 { UINT_MAX
, { 0, 0}},
3072 /* Two shader engines */
3080 { UINT_MAX
, { 0, 0}},
3083 /* Four shader engines */
3091 { UINT_MAX
, { 0, 0}},
3095 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3099 // One shader engine
3106 { UINT_MAX
, { 0, 0}},
3109 // Two shader engines
3117 { UINT_MAX
, { 0, 0}},
3120 // Four shader engines
3128 { UINT_MAX
, { 0, 0}},
3134 // One shader engine
3142 { UINT_MAX
, { 0, 0}},
3145 // Two shader engines
3154 { UINT_MAX
, { 0, 0}},
3157 // Four shader engines
3166 { UINT_MAX
, { 0, 0}},
3172 // One shader engine
3180 { UINT_MAX
, { 0, 0}},
3183 // Two shader engines
3192 { UINT_MAX
, { 0, 0}},
3195 // Four shader engines
3203 { UINT_MAX
, { 0, 0}},
3208 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3209 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3210 VkExtent2D extent
= {512, 512};
3212 unsigned log_num_rb_per_se
=
3213 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3214 pipeline
->device
->physical_device
->rad_info
.max_se
);
3215 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3217 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3218 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3219 unsigned effective_samples
= total_samples
;
3220 unsigned color_bytes_per_pixel
= 0;
3222 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3223 radv_pipeline_get_color_blend_state(pCreateInfo
);
3225 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3226 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3229 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3232 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3233 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3236 /* MSAA images typically don't use all samples all the time. */
3237 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3238 effective_samples
= 2;
3239 color_bytes_per_pixel
*= effective_samples
;
3242 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3243 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3246 extent
= color_entry
->extent
;
3248 if (subpass
->depth_stencil_attachment
) {
3249 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3251 /* Coefficients taken from AMDVLK */
3252 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3253 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3254 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3256 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3257 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3260 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3261 extent
= ds_entry
->extent
;
3268 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3270 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3271 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3272 VkExtent2D extent
= {512, 512};
3274 const unsigned db_tag_size
= 64;
3275 const unsigned db_tag_count
= 312;
3276 const unsigned color_tag_size
= 1024;
3277 const unsigned color_tag_count
= 31;
3278 const unsigned fmask_tag_size
= 256;
3279 const unsigned fmask_tag_count
= 44;
3281 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3282 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3284 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3285 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3286 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3288 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3289 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3291 unsigned color_bytes_per_pixel
= 0;
3292 unsigned fmask_bytes_per_pixel
= 0;
3294 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3295 radv_pipeline_get_color_blend_state(pCreateInfo
);
3297 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3298 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3301 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3304 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3305 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3307 if (total_samples
> 1) {
3308 assert(samples_log
<= 3);
3309 const unsigned fmask_array
[] = {0, 1, 1, 4};
3310 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3314 color_bytes_per_pixel
*= total_samples
;
3316 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3318 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3319 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3320 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3322 if (fmask_bytes_per_pixel
) {
3323 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3325 const VkExtent2D fmask_extent
= (VkExtent2D
){
3326 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3327 .height
= 1ull << (color_pixel_count_log
/ 2)
3330 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3331 extent
= fmask_extent
;
3334 if (subpass
->depth_stencil_attachment
) {
3335 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3337 /* Coefficients taken from AMDVLK */
3338 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3339 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3340 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3342 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3344 const VkExtent2D db_extent
= (VkExtent2D
){
3345 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3346 .height
= 1ull << (color_pixel_count_log
/ 2)
3349 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3353 extent
.width
= MAX2(extent
.width
, 128);
3354 extent
.height
= MAX2(extent
.width
, 64);
3360 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3361 struct radv_pipeline
*pipeline
,
3362 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3364 uint32_t pa_sc_binner_cntl_0
=
3365 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3366 S_028C44_DISABLE_START_OF_PRIM(1);
3367 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3369 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3370 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3371 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3372 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3373 radv_pipeline_get_color_blend_state(pCreateInfo
);
3374 unsigned min_bytes_per_pixel
= 0;
3377 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3378 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3381 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3384 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3385 unsigned bytes
= vk_format_get_blocksize(format
);
3386 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3387 min_bytes_per_pixel
= bytes
;
3391 pa_sc_binner_cntl_0
=
3392 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3393 S_028C44_BIN_SIZE_X(0) |
3394 S_028C44_BIN_SIZE_Y(0) |
3395 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3396 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3397 S_028C44_DISABLE_START_OF_PRIM(1);
3400 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3401 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3404 struct radv_binning_settings
3405 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3407 struct radv_binning_settings settings
;
3408 if (pdev
->rad_info
.has_dedicated_vram
) {
3409 if (pdev
->rad_info
.num_render_backends
> 4) {
3410 settings
.context_states_per_bin
= 1;
3411 settings
.persistent_states_per_bin
= 1;
3413 settings
.context_states_per_bin
= 3;
3414 settings
.persistent_states_per_bin
= 8;
3416 settings
.fpovs_per_batch
= 63;
3418 /* The context states are affected by the scissor bug. */
3419 settings
.context_states_per_bin
= 6;
3420 /* 32 causes hangs for RAVEN. */
3421 settings
.persistent_states_per_bin
= 16;
3422 settings
.fpovs_per_batch
= 63;
3425 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3426 settings
.context_states_per_bin
= 1;
3432 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3433 struct radv_pipeline
*pipeline
,
3434 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3435 const struct radv_blend_state
*blend
)
3437 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3440 VkExtent2D bin_size
;
3441 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3442 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3443 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3444 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3446 unreachable("Unhandled generation for binning bin size calculation");
3448 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3449 struct radv_binning_settings settings
=
3450 radv_get_binning_settings(pipeline
->device
->physical_device
);
3452 bool disable_start_of_prim
= true;
3453 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3455 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3457 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3458 !ps
->info
.ps
.can_discard
&&
3459 !ps
->info
.ps
.writes_memory
&&
3460 blend
->cb_target_enabled_4bit
) {
3461 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3462 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3465 const uint32_t pa_sc_binner_cntl_0
=
3466 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3467 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3468 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3469 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3470 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3471 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3472 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3473 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3474 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3475 S_028C44_OPTIMAL_BIN_SELECTION(1);
3477 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3478 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3480 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3485 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3486 struct radv_pipeline
*pipeline
,
3487 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3488 const struct radv_graphics_pipeline_create_info
*extra
)
3490 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3491 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3492 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3493 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3494 struct radv_render_pass_attachment
*attachment
= NULL
;
3495 uint32_t db_depth_control
= 0;
3496 uint32_t db_render_control
= 0, db_render_override2
= 0;
3497 uint32_t db_render_override
= 0;
3499 if (subpass
->depth_stencil_attachment
)
3500 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3502 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3503 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3505 if (vkds
&& has_depth_attachment
) {
3506 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3507 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3508 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3509 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3511 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3512 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3514 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3515 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3518 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3519 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3520 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3522 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3525 if (attachment
&& extra
) {
3526 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3527 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3529 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3530 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3531 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3532 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3533 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3536 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3537 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3539 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3540 ps
->info
.ps
.writes_z
) {
3541 /* From VK_EXT_depth_range_unrestricted spec:
3543 * "The behavior described in Primitive Clipping still applies.
3544 * If depth clamping is disabled the depth values are still
3545 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3546 * depth clamping is enabled the above equation is ignored and
3547 * the depth values are instead clamped to the VkViewport
3548 * minDepth and maxDepth values, which in the case of this
3549 * extension can be outside of the 0.0 to 1.0 range."
3551 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3554 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3555 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3556 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3558 pipeline
->graphics
.db_depth_control
= db_depth_control
;
3562 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3563 struct radv_pipeline
*pipeline
,
3564 const struct radv_blend_state
*blend
)
3566 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3567 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3569 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3570 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3572 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3574 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3575 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3578 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3580 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3581 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3583 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3584 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3587 static const VkConservativeRasterizationModeEXT
3588 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3590 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3591 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3593 if (!conservative_raster
)
3594 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3595 return conservative_raster
->conservativeRasterizationMode
;
3599 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3600 struct radv_pipeline
*pipeline
,
3601 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3603 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3604 const VkConservativeRasterizationModeEXT mode
=
3605 radv_get_conservative_raster_mode(vkraster
);
3606 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3607 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3609 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3610 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3611 if (depth_clip_state
) {
3612 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3615 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3616 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3617 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3618 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3619 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3620 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3622 pipeline
->graphics
.pa_su_sc_mode_cntl
=
3623 S_028814_FACE(vkraster
->frontFace
) |
3624 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3625 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3626 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3627 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3628 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3629 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3630 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3631 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
3633 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
,
3634 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3636 /* Conservative rasterization. */
3637 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3638 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3640 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3641 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3642 S_028804_OVERRASTERIZATION_AMOUNT(4);
3644 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3645 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3646 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3648 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3649 pa_sc_conservative_rast
|=
3650 S_028C4C_OVER_RAST_ENABLE(1) |
3651 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3652 S_028C4C_UNDER_RAST_ENABLE(0) |
3653 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3654 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3656 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3657 pa_sc_conservative_rast
|=
3658 S_028C4C_OVER_RAST_ENABLE(0) |
3659 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3660 S_028C4C_UNDER_RAST_ENABLE(1) |
3661 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3662 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3666 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3667 pa_sc_conservative_rast
);
3672 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3673 struct radv_pipeline
*pipeline
)
3675 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3677 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3678 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3679 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3681 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3682 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3683 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3684 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3686 /* The exclusion bits can be set to improve rasterization efficiency
3687 * if no sample lies on the pixel boundary (-8 sample offset). It's
3688 * currently always TRUE because the driver doesn't support 16 samples.
3690 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3691 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3692 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3693 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3695 /* GFX9: Flush DFSM when the AA mode changes. */
3696 if (pipeline
->device
->dfsm_allowed
) {
3697 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3698 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3703 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3704 struct radv_pipeline
*pipeline
)
3706 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3707 const struct radv_shader_variant
*vs
=
3708 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3709 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3710 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3711 unsigned vgt_primitiveid_en
= 0;
3712 uint32_t vgt_gs_mode
= 0;
3714 if (radv_pipeline_has_ngg(pipeline
))
3717 if (radv_pipeline_has_gs(pipeline
)) {
3718 const struct radv_shader_variant
*gs
=
3719 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3721 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3722 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3723 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3724 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3725 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3728 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3729 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3733 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3734 struct radeon_cmdbuf
*cs
,
3735 struct radv_pipeline
*pipeline
,
3736 struct radv_shader_variant
*shader
)
3738 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3740 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3741 radeon_emit(cs
, va
>> 8);
3742 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3743 radeon_emit(cs
, shader
->config
.rsrc1
);
3744 radeon_emit(cs
, shader
->config
.rsrc2
);
3746 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3747 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3748 clip_dist_mask
= outinfo
->clip_dist_mask
;
3749 cull_dist_mask
= outinfo
->cull_dist_mask
;
3750 total_mask
= clip_dist_mask
| cull_dist_mask
;
3751 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3752 outinfo
->writes_layer
||
3753 outinfo
->writes_viewport_index
;
3754 unsigned spi_vs_out_config
, nparams
;
3756 /* VS is required to export at least one param. */
3757 nparams
= MAX2(outinfo
->param_exports
, 1);
3758 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3760 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3761 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3764 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3766 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3767 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3768 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3769 V_02870C_SPI_SHADER_4COMP
:
3770 V_02870C_SPI_SHADER_NONE
) |
3771 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3772 V_02870C_SPI_SHADER_4COMP
:
3773 V_02870C_SPI_SHADER_NONE
) |
3774 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3775 V_02870C_SPI_SHADER_4COMP
:
3776 V_02870C_SPI_SHADER_NONE
));
3778 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3779 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3780 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3781 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3782 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3783 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3784 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3785 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3786 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3787 cull_dist_mask
<< 8 |
3790 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3791 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3792 outinfo
->writes_viewport_index
);
3796 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3797 struct radv_pipeline
*pipeline
,
3798 struct radv_shader_variant
*shader
)
3800 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3802 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3803 radeon_emit(cs
, va
>> 8);
3804 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3805 radeon_emit(cs
, shader
->config
.rsrc1
);
3806 radeon_emit(cs
, shader
->config
.rsrc2
);
3810 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3811 struct radv_pipeline
*pipeline
,
3812 struct radv_shader_variant
*shader
)
3814 unsigned num_lds_blocks
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_lds_blocks
;
3815 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3816 uint32_t rsrc2
= shader
->config
.rsrc2
;
3818 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3819 radeon_emit(cs
, va
>> 8);
3820 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3822 rsrc2
|= S_00B52C_LDS_SIZE(num_lds_blocks
);
3823 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3824 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3825 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3827 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3828 radeon_emit(cs
, shader
->config
.rsrc1
);
3829 radeon_emit(cs
, rsrc2
);
3833 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3834 struct radeon_cmdbuf
*cs
,
3835 struct radv_pipeline
*pipeline
,
3836 struct radv_shader_variant
*shader
)
3838 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3839 gl_shader_stage es_type
=
3840 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3841 struct radv_shader_variant
*es
=
3842 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3843 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3845 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3846 radeon_emit(cs
, va
>> 8);
3847 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3848 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3849 radeon_emit(cs
, shader
->config
.rsrc1
);
3850 radeon_emit(cs
, shader
->config
.rsrc2
);
3852 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3853 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3854 clip_dist_mask
= outinfo
->clip_dist_mask
;
3855 cull_dist_mask
= outinfo
->cull_dist_mask
;
3856 total_mask
= clip_dist_mask
| cull_dist_mask
;
3857 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3858 outinfo
->writes_layer
||
3859 outinfo
->writes_viewport_index
;
3860 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3861 (es
&& es
->info
.uses_prim_id
);
3862 bool break_wave_at_eoi
= false;
3866 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3867 struct radv_shader_variant
*gs
=
3868 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3870 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3871 break_wave_at_eoi
= true;
3874 nparams
= MAX2(outinfo
->param_exports
, 1);
3875 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3876 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3877 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3879 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3880 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3881 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3882 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3883 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3884 V_02870C_SPI_SHADER_4COMP
:
3885 V_02870C_SPI_SHADER_NONE
) |
3886 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3887 V_02870C_SPI_SHADER_4COMP
:
3888 V_02870C_SPI_SHADER_NONE
) |
3889 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3890 V_02870C_SPI_SHADER_4COMP
:
3891 V_02870C_SPI_SHADER_NONE
));
3893 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3894 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3895 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3896 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3897 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3898 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3899 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3900 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3901 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3902 cull_dist_mask
<< 8 |
3905 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3906 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3907 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3909 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3910 ngg_state
->vgt_esgs_ring_itemsize
);
3912 /* NGG specific registers. */
3913 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3914 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3916 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3917 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3918 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3919 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3920 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3921 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3922 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3923 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3924 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3925 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3926 S_028B90_CNT(gs_num_invocations
) |
3927 S_028B90_ENABLE(gs_num_invocations
> 1) |
3928 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3930 /* User edge flags are set by the pos exports. If user edge flags are
3931 * not used, we must use hw-generated edge flags and pass them via
3932 * the prim export to prevent drawing lines on internal edges of
3933 * decomposed primitives (such as quads) with polygon mode = lines.
3935 * TODO: We should combine hw-generated edge flags with user edge
3936 * flags in the shader.
3938 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3939 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3940 !radv_pipeline_has_gs(pipeline
)) |
3941 /* Reuse for NGG. */
3942 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
3944 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3945 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
3946 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3948 /* Bug workaround for a possible hang with non-tessellation cases.
3949 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3951 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3953 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
3954 !radv_pipeline_has_tess(pipeline
) &&
3955 ngg_state
->hw_max_esverts
!= 256) {
3956 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3958 if (ngg_state
->hw_max_esverts
> 5) {
3959 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3963 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3967 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3968 struct radv_pipeline
*pipeline
,
3969 struct radv_shader_variant
*shader
)
3971 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3973 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3974 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3975 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3976 radeon_emit(cs
, va
>> 8);
3977 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3979 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3980 radeon_emit(cs
, va
>> 8);
3981 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3984 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3985 radeon_emit(cs
, shader
->config
.rsrc1
);
3986 radeon_emit(cs
, shader
->config
.rsrc2
);
3988 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3989 radeon_emit(cs
, va
>> 8);
3990 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3991 radeon_emit(cs
, shader
->config
.rsrc1
);
3992 radeon_emit(cs
, shader
->config
.rsrc2
);
3997 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3998 struct radeon_cmdbuf
*cs
,
3999 struct radv_pipeline
*pipeline
)
4001 struct radv_shader_variant
*vs
;
4003 /* Skip shaders merged into HS/GS */
4004 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4008 if (vs
->info
.vs
.as_ls
)
4009 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
);
4010 else if (vs
->info
.vs
.as_es
)
4011 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4012 else if (vs
->info
.is_ngg
)
4013 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4015 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4019 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4020 struct radeon_cmdbuf
*cs
,
4021 struct radv_pipeline
*pipeline
)
4023 struct radv_shader_variant
*tes
, *tcs
;
4025 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4026 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4029 if (tes
->info
.is_ngg
) {
4030 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4031 } else if (tes
->info
.tes
.as_es
)
4032 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4034 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4037 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
);
4039 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4040 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4041 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4042 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4043 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4044 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4049 radv_pipeline_generate_tess_state(struct radeon_cmdbuf
*ctx_cs
,
4050 struct radv_pipeline
*pipeline
,
4051 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4053 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
4054 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
4055 unsigned num_tcs_input_cp
, num_tcs_output_cp
, num_patches
;
4056 unsigned ls_hs_config
;
4058 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4059 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
4060 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4062 ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
4063 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
4064 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
4066 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4067 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4070 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4074 switch (tes
->info
.tes
.primitive_mode
) {
4076 type
= V_028B6C_TESS_TRIANGLE
;
4079 type
= V_028B6C_TESS_QUAD
;
4082 type
= V_028B6C_TESS_ISOLINE
;
4086 switch (tes
->info
.tes
.spacing
) {
4087 case TESS_SPACING_EQUAL
:
4088 partitioning
= V_028B6C_PART_INTEGER
;
4090 case TESS_SPACING_FRACTIONAL_ODD
:
4091 partitioning
= V_028B6C_PART_FRAC_ODD
;
4093 case TESS_SPACING_FRACTIONAL_EVEN
:
4094 partitioning
= V_028B6C_PART_FRAC_EVEN
;
4100 bool ccw
= tes
->info
.tes
.ccw
;
4101 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
4102 vk_find_struct_const(pCreateInfo
->pTessellationState
,
4103 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
4105 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
4108 if (tes
->info
.tes
.point_mode
)
4109 topology
= V_028B6C_OUTPUT_POINT
;
4110 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
4111 topology
= V_028B6C_OUTPUT_LINE
;
4113 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
4115 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
4117 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
4118 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4119 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
4120 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
4122 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
4124 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
4126 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4127 S_028B6C_TYPE(type
) |
4128 S_028B6C_PARTITIONING(partitioning
) |
4129 S_028B6C_TOPOLOGY(topology
) |
4130 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
4134 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4135 struct radeon_cmdbuf
*cs
,
4136 struct radv_pipeline
*pipeline
,
4137 struct radv_shader_variant
*gs
)
4139 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4140 unsigned gs_max_out_vertices
;
4141 uint8_t *num_components
;
4146 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4147 max_stream
= gs
->info
.gs
.max_stream
;
4148 num_components
= gs
->info
.gs
.num_stream_output_components
;
4150 offset
= num_components
[0] * gs_max_out_vertices
;
4152 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4153 radeon_emit(ctx_cs
, offset
);
4154 if (max_stream
>= 1)
4155 offset
+= num_components
[1] * gs_max_out_vertices
;
4156 radeon_emit(ctx_cs
, offset
);
4157 if (max_stream
>= 2)
4158 offset
+= num_components
[2] * gs_max_out_vertices
;
4159 radeon_emit(ctx_cs
, offset
);
4160 if (max_stream
>= 3)
4161 offset
+= num_components
[3] * gs_max_out_vertices
;
4162 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4164 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4165 radeon_emit(ctx_cs
, num_components
[0]);
4166 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4167 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4168 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4170 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4171 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4172 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4173 S_028B90_ENABLE(gs_num_invocations
> 0));
4175 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4176 gs_state
->vgt_esgs_ring_itemsize
);
4178 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4180 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4181 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4182 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4183 radeon_emit(cs
, va
>> 8);
4184 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4186 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4187 radeon_emit(cs
, va
>> 8);
4188 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4191 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4192 radeon_emit(cs
, gs
->config
.rsrc1
);
4193 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4195 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4196 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4198 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4199 radeon_emit(cs
, va
>> 8);
4200 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4201 radeon_emit(cs
, gs
->config
.rsrc1
);
4202 radeon_emit(cs
, gs
->config
.rsrc2
);
4205 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4209 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4210 struct radeon_cmdbuf
*cs
,
4211 struct radv_pipeline
*pipeline
)
4213 struct radv_shader_variant
*gs
;
4215 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4219 if (gs
->info
.is_ngg
)
4220 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4222 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4224 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4225 gs
->info
.gs
.vertices_out
);
4228 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4229 bool explicit, bool float16
)
4231 uint32_t ps_input_cntl
;
4232 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4233 ps_input_cntl
= S_028644_OFFSET(offset
);
4234 if (flat_shade
|| explicit)
4235 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4237 /* Force parameter cache to be read in passthrough
4240 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4243 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4244 S_028644_ATTR0_VALID(1);
4247 /* The input is a DEFAULT_VAL constant. */
4248 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4249 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4250 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4251 ps_input_cntl
= S_028644_OFFSET(0x20) |
4252 S_028644_DEFAULT_VAL(offset
);
4254 return ps_input_cntl
;
4258 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4259 struct radv_pipeline
*pipeline
)
4261 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4262 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4263 uint32_t ps_input_cntl
[32];
4265 unsigned ps_offset
= 0;
4267 if (ps
->info
.ps
.prim_id_input
) {
4268 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4269 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4270 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4275 if (ps
->info
.ps
.layer_input
||
4276 ps
->info
.needs_multiview_view_index
) {
4277 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4278 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4279 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4281 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4285 if (ps
->info
.ps
.viewport_index_input
) {
4286 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4287 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4288 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4290 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4294 if (ps
->info
.ps
.has_pcoord
) {
4296 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4297 ps_input_cntl
[ps_offset
] = val
;
4301 if (ps
->info
.ps
.num_input_clips_culls
) {
4304 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4305 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4306 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4310 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4311 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4312 ps
->info
.ps
.num_input_clips_culls
> 4) {
4313 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4318 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4323 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4326 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4327 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4328 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4333 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4334 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4335 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4337 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4342 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4343 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4344 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4350 radv_compute_db_shader_control(const struct radv_device
*device
,
4351 const struct radv_pipeline
*pipeline
,
4352 const struct radv_shader_variant
*ps
)
4354 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4356 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4357 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4359 z_order
= V_02880C_LATE_Z
;
4361 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4362 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4363 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4364 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4366 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4367 !device
->physical_device
->rad_info
.rbplus_allowed
;
4369 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4370 * but this appears to break Project Cars (DXVK). See
4371 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4373 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4375 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4376 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4377 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4378 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4379 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4380 S_02880C_Z_ORDER(z_order
) |
4381 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4382 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4383 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4384 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4385 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4389 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4390 struct radeon_cmdbuf
*cs
,
4391 struct radv_pipeline
*pipeline
)
4393 struct radv_shader_variant
*ps
;
4395 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4397 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4398 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4400 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4401 radeon_emit(cs
, va
>> 8);
4402 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4403 radeon_emit(cs
, ps
->config
.rsrc1
);
4404 radeon_emit(cs
, ps
->config
.rsrc2
);
4406 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4407 radv_compute_db_shader_control(pipeline
->device
,
4410 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4411 ps
->config
.spi_ps_input_ena
);
4413 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4414 ps
->config
.spi_ps_input_addr
);
4416 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4417 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4418 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4420 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4422 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4423 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4424 ps
->info
.ps
.writes_stencil
,
4425 ps
->info
.ps
.writes_sample_mask
));
4427 if (pipeline
->device
->dfsm_allowed
) {
4428 /* optimise this? */
4429 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4430 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4435 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4436 struct radv_pipeline
*pipeline
)
4438 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4439 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4442 unsigned vtx_reuse_depth
= 30;
4443 if (radv_pipeline_has_tess(pipeline
) &&
4444 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4445 vtx_reuse_depth
= 14;
4447 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4448 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4452 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf
*ctx_cs
,
4453 const struct radv_pipeline
*pipeline
)
4455 uint32_t stages
= 0;
4456 if (radv_pipeline_has_tess(pipeline
)) {
4457 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4458 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4460 if (radv_pipeline_has_gs(pipeline
))
4461 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4463 else if (radv_pipeline_has_ngg(pipeline
))
4464 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4466 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4467 } else if (radv_pipeline_has_gs(pipeline
)) {
4468 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4470 } else if (radv_pipeline_has_ngg(pipeline
)) {
4471 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4474 if (radv_pipeline_has_ngg(pipeline
)) {
4475 stages
|= S_028B54_PRIMGEN_EN(1);
4476 if (pipeline
->streamout_shader
)
4477 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4478 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4479 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4480 } else if (radv_pipeline_has_gs(pipeline
)) {
4481 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4484 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4485 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4487 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4488 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4490 if (radv_pipeline_has_tess(pipeline
))
4491 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4493 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4494 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4495 if (pipeline
->gs_copy_shader
)
4496 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4497 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4498 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4499 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4500 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4502 if (radv_pipeline_has_ngg(pipeline
))
4505 /* legacy GS only supports Wave64 */
4506 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4507 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4508 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4511 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
4515 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf
*ctx_cs
,
4516 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4518 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4519 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4520 uint32_t cliprect_rule
= 0;
4522 if (!discard_rectangle_info
) {
4523 cliprect_rule
= 0xffff;
4525 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4526 /* Interpret i as a bitmask, and then set the bit in
4527 * the mask if that combination of rectangles in which
4528 * the pixel is contained should pass the cliprect
4531 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4533 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4537 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4541 cliprect_rule
|= 1u << i
;
4545 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, cliprect_rule
);
4549 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4550 struct radv_pipeline
*pipeline
)
4552 bool break_wave_at_eoi
= false;
4553 unsigned primgroup_size
;
4554 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4556 if (radv_pipeline_has_tess(pipeline
)) {
4557 primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4558 } else if (radv_pipeline_has_gs(pipeline
)) {
4559 const struct gfx9_gs_info
*gs_state
=
4560 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4561 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4562 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4564 primgroup_size
= 128; /* recommended without a GS and tess */
4567 if (radv_pipeline_has_tess(pipeline
)) {
4568 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4569 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4570 break_wave_at_eoi
= true;
4573 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4574 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4575 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4576 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4577 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4581 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4582 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4583 const struct radv_graphics_pipeline_create_info
*extra
,
4584 const struct radv_blend_state
*blend
,
4587 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4588 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4591 ctx_cs
->max_dw
= 256;
4592 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4593 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4595 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4596 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4597 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4598 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4599 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4600 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
);
4602 if (radv_pipeline_has_tess(pipeline
)) {
4603 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
);
4604 radv_pipeline_generate_tess_state(ctx_cs
, pipeline
, pCreateInfo
);
4607 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4608 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4609 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4610 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4611 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4612 radv_pipeline_generate_vgt_shader_config(ctx_cs
, pipeline
);
4613 radv_pipeline_generate_cliprect_rule(ctx_cs
, pCreateInfo
);
4615 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4616 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
);
4618 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4620 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4622 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4623 assert(cs
->cdw
<= cs
->max_dw
);
4626 static struct radv_ia_multi_vgt_param_helpers
4627 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
)
4629 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4630 const struct radv_device
*device
= pipeline
->device
;
4632 if (radv_pipeline_has_tess(pipeline
))
4633 ia_multi_vgt_param
.primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4634 else if (radv_pipeline_has_gs(pipeline
))
4635 ia_multi_vgt_param
.primgroup_size
= 64;
4637 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4639 /* GS requirement. */
4640 ia_multi_vgt_param
.partial_es_wave
= false;
4641 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4642 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4643 ia_multi_vgt_param
.partial_es_wave
= true;
4645 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4646 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4647 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4648 if (radv_pipeline_has_gs(pipeline
) &&
4649 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4650 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4651 if (radv_pipeline_has_tess(pipeline
)) {
4652 /* SWITCH_ON_EOI must be set if PrimID is used. */
4653 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4654 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4655 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4658 ia_multi_vgt_param
.partial_vs_wave
= false;
4659 if (radv_pipeline_has_tess(pipeline
)) {
4660 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4661 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4662 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4663 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4664 radv_pipeline_has_gs(pipeline
))
4665 ia_multi_vgt_param
.partial_vs_wave
= true;
4666 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4667 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4668 if (radv_pipeline_has_gs(pipeline
)) {
4669 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4670 ia_multi_vgt_param
.partial_es_wave
= true;
4672 ia_multi_vgt_param
.partial_vs_wave
= true;
4677 if (radv_pipeline_has_gs(pipeline
)) {
4678 /* On these chips there is the possibility of a hang if the
4679 * pipeline uses a GS and partial_vs_wave is not set.
4681 * This mostly does not hit 4-SE chips, as those typically set
4682 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4683 * with GS due to another workaround.
4685 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4687 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4688 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4689 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4690 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4691 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4692 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4693 ia_multi_vgt_param
.partial_vs_wave
= true;
4697 ia_multi_vgt_param
.base
=
4698 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4699 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4700 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4701 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4702 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4704 return ia_multi_vgt_param
;
4709 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4710 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4712 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4713 pCreateInfo
->pVertexInputState
;
4715 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4716 const VkVertexInputBindingDescription
*desc
=
4717 &vi_info
->pVertexBindingDescriptions
[i
];
4719 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4720 pipeline
->num_vertex_bindings
=
4721 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4725 static struct radv_shader_variant
*
4726 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4730 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4731 struct radv_shader_variant
*shader
=
4732 radv_get_shader(pipeline
, i
);
4734 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4742 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4743 struct radv_device
*device
,
4744 struct radv_pipeline_cache
*cache
,
4745 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4746 const struct radv_graphics_pipeline_create_info
*extra
)
4750 pipeline
->device
= device
;
4751 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4752 assert(pipeline
->layout
);
4754 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4756 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4757 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4758 radv_init_feedback(creation_feedback
);
4760 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4762 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4763 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4764 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4765 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4766 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4767 if(creation_feedback
)
4768 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4771 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
);
4773 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4774 pCreateInfo
->flags
, pipeline_feedback
,
4776 if (result
!= VK_SUCCESS
)
4779 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4780 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4783 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4785 if (radv_pipeline_has_gs(pipeline
)) {
4786 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4787 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4788 } else if (radv_pipeline_has_tess(pipeline
)) {
4789 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4790 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4792 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4793 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4795 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4797 if (extra
&& extra
->use_rectlist
) {
4798 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4799 pipeline
->graphics
.can_use_guardband
= true;
4800 if (radv_pipeline_has_ngg(pipeline
))
4801 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4803 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4805 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4807 /* Ensure that some export memory is always allocated, for two reasons:
4809 * 1) Correctness: The hardware ignores the EXEC mask if no export
4810 * memory is allocated, so KILL and alpha test do not work correctly
4812 * 2) Performance: Every shader needs at least a NULL export, even when
4813 * it writes no color/depth output. The NULL export instruction
4814 * stalls without this setting.
4816 * Don't add this to CB_SHADER_MASK.
4818 * GFX10 supports pixel shaders without exports by setting both the
4819 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4820 * instructions if any are present.
4822 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4823 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4824 ps
->info
.ps
.can_discard
) &&
4825 !blend
.spi_shader_col_format
) {
4826 if (!ps
->info
.ps
.writes_z
&&
4827 !ps
->info
.ps
.writes_stencil
&&
4828 !ps
->info
.ps
.writes_sample_mask
)
4829 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4832 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4835 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4836 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4837 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4838 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4839 /* According to the CB spec states, CB_SHADER_MASK should be
4840 * set to enable writes to all four channels of MRT0.
4842 blend
.cb_shader_mask
= 0xf;
4845 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4846 if (pipeline
->shaders
[i
]) {
4847 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4851 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4852 struct radv_shader_variant
*gs
=
4853 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4855 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4858 if (radv_pipeline_has_tess(pipeline
)) {
4859 pipeline
->graphics
.tess_patch_control_points
=
4860 pCreateInfo
->pTessellationState
->patchControlPoints
;
4863 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
);
4865 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4867 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4868 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4870 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4871 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4872 if (loc
->sgpr_idx
!= -1) {
4873 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4874 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4875 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4876 pipeline
->graphics
.vtx_emit_num
= 3;
4878 pipeline
->graphics
.vtx_emit_num
= 2;
4881 /* Find the last vertex shader stage that eventually uses streamout. */
4882 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4884 result
= radv_pipeline_scratch_init(device
, pipeline
);
4885 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, gs_out
);
4891 radv_graphics_pipeline_create(
4893 VkPipelineCache _cache
,
4894 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4895 const struct radv_graphics_pipeline_create_info
*extra
,
4896 const VkAllocationCallbacks
*pAllocator
,
4897 VkPipeline
*pPipeline
)
4899 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4900 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4901 struct radv_pipeline
*pipeline
;
4904 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4905 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4906 if (pipeline
== NULL
)
4907 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4909 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4910 VK_OBJECT_TYPE_PIPELINE
);
4912 result
= radv_pipeline_init(pipeline
, device
, cache
,
4913 pCreateInfo
, extra
);
4914 if (result
!= VK_SUCCESS
) {
4915 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4919 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4924 VkResult
radv_CreateGraphicsPipelines(
4926 VkPipelineCache pipelineCache
,
4928 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4929 const VkAllocationCallbacks
* pAllocator
,
4930 VkPipeline
* pPipelines
)
4932 VkResult result
= VK_SUCCESS
;
4935 for (; i
< count
; i
++) {
4937 r
= radv_graphics_pipeline_create(_device
,
4940 NULL
, pAllocator
, &pPipelines
[i
]);
4941 if (r
!= VK_SUCCESS
) {
4943 pPipelines
[i
] = VK_NULL_HANDLE
;
4945 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
4950 for (; i
< count
; ++i
)
4951 pPipelines
[i
] = VK_NULL_HANDLE
;
4957 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf
*cs
,
4958 struct radv_pipeline
*pipeline
)
4960 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4961 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4962 struct radv_device
*device
= pipeline
->device
;
4964 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
4965 radeon_emit(cs
, va
>> 8);
4966 radeon_emit(cs
, S_00B834_DATA(va
>> 40));
4968 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
4969 radeon_emit(cs
, shader
->config
.rsrc1
);
4970 radeon_emit(cs
, shader
->config
.rsrc2
);
4971 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4972 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, shader
->config
.rsrc3
);
4977 radv_pipeline_generate_compute_state(struct radeon_cmdbuf
*cs
,
4978 struct radv_pipeline
*pipeline
)
4980 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4981 struct radv_device
*device
= pipeline
->device
;
4982 unsigned threads_per_threadgroup
;
4983 unsigned threadgroups_per_cu
= 1;
4984 unsigned waves_per_threadgroup
;
4985 unsigned max_waves_per_sh
= 0;
4987 /* Calculate best compute resource limits. */
4988 threads_per_threadgroup
= shader
->info
.cs
.block_size
[0] *
4989 shader
->info
.cs
.block_size
[1] *
4990 shader
->info
.cs
.block_size
[2];
4991 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
4992 shader
->info
.wave_size
);
4994 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4995 waves_per_threadgroup
== 1)
4996 threadgroups_per_cu
= 2;
4998 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
4999 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5000 waves_per_threadgroup
,
5002 threadgroups_per_cu
));
5004 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5005 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[0]));
5006 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[1]));
5007 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[2]));
5011 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5013 struct radv_device
*device
= pipeline
->device
;
5014 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
5016 cs
->max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 19 : 16;
5017 cs
->buf
= malloc(cs
->max_dw
* 4);
5019 radv_pipeline_generate_hw_cs(cs
, pipeline
);
5020 radv_pipeline_generate_compute_state(cs
, pipeline
);
5022 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5025 static struct radv_pipeline_key
5026 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5027 const VkComputePipelineCreateInfo
*pCreateInfo
)
5029 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5030 struct radv_pipeline_key key
;
5031 memset(&key
, 0, sizeof(key
));
5033 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5034 key
.optimisations_disabled
= 1;
5036 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5037 vk_find_struct_const(stage
->pNext
,
5038 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5040 if (subgroup_size
) {
5041 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5042 subgroup_size
->requiredSubgroupSize
== 64);
5043 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5049 static VkResult
radv_compute_pipeline_create(
5051 VkPipelineCache _cache
,
5052 const VkComputePipelineCreateInfo
* pCreateInfo
,
5053 const VkAllocationCallbacks
* pAllocator
,
5054 VkPipeline
* pPipeline
)
5056 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5057 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5058 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5059 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5060 struct radv_pipeline
*pipeline
;
5063 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5064 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5065 if (pipeline
== NULL
)
5066 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5068 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5069 VK_OBJECT_TYPE_PIPELINE
);
5071 pipeline
->device
= device
;
5072 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5073 assert(pipeline
->layout
);
5075 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5076 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5077 radv_init_feedback(creation_feedback
);
5079 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5080 if (creation_feedback
)
5081 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5083 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5085 struct radv_pipeline_key key
=
5086 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5088 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5089 pCreateInfo
->flags
, pipeline_feedback
,
5091 if (result
!= VK_SUCCESS
) {
5092 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5096 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5097 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5098 result
= radv_pipeline_scratch_init(device
, pipeline
);
5099 if (result
!= VK_SUCCESS
) {
5100 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5104 radv_compute_generate_pm4(pipeline
);
5106 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5111 VkResult
radv_CreateComputePipelines(
5113 VkPipelineCache pipelineCache
,
5115 const VkComputePipelineCreateInfo
* pCreateInfos
,
5116 const VkAllocationCallbacks
* pAllocator
,
5117 VkPipeline
* pPipelines
)
5119 VkResult result
= VK_SUCCESS
;
5122 for (; i
< count
; i
++) {
5124 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5126 pAllocator
, &pPipelines
[i
]);
5127 if (r
!= VK_SUCCESS
) {
5129 pPipelines
[i
] = VK_NULL_HANDLE
;
5131 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5136 for (; i
< count
; ++i
)
5137 pPipelines
[i
] = VK_NULL_HANDLE
;
5143 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5146 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5147 if (!pipeline
->shaders
[i
])
5150 if (i
== MESA_SHADER_GEOMETRY
&&
5151 !radv_pipeline_has_ngg(pipeline
)) {
5161 static struct radv_shader_variant
*
5162 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5164 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5165 if (!pipeline
->shaders
[i
])
5169 return pipeline
->shaders
[i
];
5174 if (i
== MESA_SHADER_GEOMETRY
&&
5175 !radv_pipeline_has_ngg(pipeline
)) {
5178 return pipeline
->gs_copy_shader
;
5188 /* Basically strlcpy (which does not exist on linux) specialized for
5190 static void desc_copy(char *desc
, const char *src
) {
5191 int len
= strlen(src
);
5192 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5193 memcpy(desc
, src
, len
);
5194 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5197 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5199 const VkPipelineInfoKHR
* pPipelineInfo
,
5200 uint32_t* pExecutableCount
,
5201 VkPipelineExecutablePropertiesKHR
* pProperties
)
5203 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5204 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5207 *pExecutableCount
= total_count
;
5211 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5212 for (unsigned i
= 0, executable_idx
= 0;
5213 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5214 if (!pipeline
->shaders
[i
])
5216 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5217 const char *name
= NULL
;
5218 const char *description
= NULL
;
5220 case MESA_SHADER_VERTEX
:
5221 name
= "Vertex Shader";
5222 description
= "Vulkan Vertex Shader";
5224 case MESA_SHADER_TESS_CTRL
:
5225 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5226 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5227 name
= "Vertex + Tessellation Control Shaders";
5228 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5230 name
= "Tessellation Control Shader";
5231 description
= "Vulkan Tessellation Control Shader";
5234 case MESA_SHADER_TESS_EVAL
:
5235 name
= "Tessellation Evaluation Shader";
5236 description
= "Vulkan Tessellation Evaluation Shader";
5238 case MESA_SHADER_GEOMETRY
:
5239 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5240 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5241 name
= "Tessellation Evaluation + Geometry Shaders";
5242 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5243 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5244 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5245 name
= "Vertex + Geometry Shader";
5246 description
= "Combined Vulkan Vertex and Geometry Shaders";
5248 name
= "Geometry Shader";
5249 description
= "Vulkan Geometry Shader";
5252 case MESA_SHADER_FRAGMENT
:
5253 name
= "Fragment Shader";
5254 description
= "Vulkan Fragment Shader";
5256 case MESA_SHADER_COMPUTE
:
5257 name
= "Compute Shader";
5258 description
= "Vulkan Compute Shader";
5262 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5263 desc_copy(pProperties
[executable_idx
].name
, name
);
5264 desc_copy(pProperties
[executable_idx
].description
, description
);
5267 if (i
== MESA_SHADER_GEOMETRY
&&
5268 !radv_pipeline_has_ngg(pipeline
)) {
5269 assert(pipeline
->gs_copy_shader
);
5270 if (executable_idx
>= count
)
5273 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5274 pProperties
[executable_idx
].subgroupSize
= 64;
5275 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5276 desc_copy(pProperties
[executable_idx
].description
,
5277 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5283 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5284 *pExecutableCount
= count
;
5288 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5290 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5291 uint32_t* pStatisticCount
,
5292 VkPipelineExecutableStatisticKHR
* pStatistics
)
5294 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5295 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5296 gl_shader_stage stage
;
5297 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5299 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5300 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5301 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5303 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5304 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5305 VkResult result
= VK_SUCCESS
;
5308 desc_copy(s
->name
, "SGPRs");
5309 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5310 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5311 s
->value
.u64
= shader
->config
.num_sgprs
;
5316 desc_copy(s
->name
, "VGPRs");
5317 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5318 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5319 s
->value
.u64
= shader
->config
.num_vgprs
;
5324 desc_copy(s
->name
, "Spilled SGPRs");
5325 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5326 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5327 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5332 desc_copy(s
->name
, "Spilled VGPRs");
5333 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5334 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5335 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5340 desc_copy(s
->name
, "PrivMem VGPRs");
5341 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5342 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5343 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5348 desc_copy(s
->name
, "Code size");
5349 desc_copy(s
->description
, "Code size in bytes");
5350 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5351 s
->value
.u64
= shader
->exec_size
;
5356 desc_copy(s
->name
, "LDS size");
5357 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5358 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5359 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5364 desc_copy(s
->name
, "Scratch size");
5365 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5366 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5367 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5372 desc_copy(s
->name
, "Subgroups per SIMD");
5373 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5374 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5375 s
->value
.u64
= max_waves
;
5379 if (shader
->statistics
) {
5380 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5381 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5382 uint32_t value
= shader
->statistics
->values
[i
];
5384 desc_copy(s
->name
, info
->name
);
5385 desc_copy(s
->description
, info
->desc
);
5386 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5387 s
->value
.u64
= value
;
5394 *pStatisticCount
= s
- pStatistics
;
5396 *pStatisticCount
= end
- pStatistics
;
5397 result
= VK_INCOMPLETE
;
5399 *pStatisticCount
= s
- pStatistics
;
5405 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5407 size_t total_size
= strlen(src
) + 1;
5410 *data_size
= total_size
;
5414 size_t size
= MIN2(total_size
, *data_size
);
5416 memcpy(data
, src
, size
);
5418 *((char*)data
+ size
- 1) = 0;
5419 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5422 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5424 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5425 uint32_t* pInternalRepresentationCount
,
5426 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5428 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5429 gl_shader_stage stage
;
5430 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5432 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5433 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5434 VkResult result
= VK_SUCCESS
;
5438 desc_copy(p
->name
, "NIR Shader(s)");
5439 desc_copy(p
->description
, "The optimized NIR shader(s)");
5440 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5441 result
= VK_INCOMPLETE
;
5448 if (pipeline
->device
->physical_device
->use_llvm
) {
5449 desc_copy(p
->name
, "LLVM IR");
5450 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5452 desc_copy(p
->name
, "ACO IR");
5453 desc_copy(p
->description
, "The ACO IR after some optimizations");
5455 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5456 result
= VK_INCOMPLETE
;
5463 desc_copy(p
->name
, "Assembly");
5464 desc_copy(p
->description
, "Final Assembly");
5465 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5466 result
= VK_INCOMPLETE
;
5470 if (!pInternalRepresentations
)
5471 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5473 result
= VK_INCOMPLETE
;
5474 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5476 *pInternalRepresentationCount
= p
- pInternalRepresentations
;