2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
34 struct cache_entry_variant_info
{
35 struct ac_shader_variant_info variant_info
;
36 struct ac_shader_config config
;
37 uint32_t rsrc1
, rsrc2
;
42 unsigned char sha1
[20];
45 uint32_t code_sizes
[MESA_SHADER_STAGES
];
46 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
51 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
52 struct radv_device
*device
)
54 cache
->device
= device
;
55 pthread_mutex_init(&cache
->mutex
, NULL
);
57 cache
->modified
= false;
58 cache
->kernel_count
= 0;
59 cache
->total_size
= 0;
60 cache
->table_size
= 1024;
61 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
62 cache
->hash_table
= malloc(byte_size
);
64 /* We don't consider allocation failure fatal, we just start with a 0-sized
66 if (cache
->hash_table
== NULL
||
67 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
))
68 cache
->table_size
= 0;
70 memset(cache
->hash_table
, 0, byte_size
);
74 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
76 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
77 if (cache
->hash_table
[i
]) {
78 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
79 if (cache
->hash_table
[i
]->variants
[j
])
80 radv_shader_variant_destroy(cache
->device
,
81 cache
->hash_table
[i
]->variants
[j
]);
83 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
85 pthread_mutex_destroy(&cache
->mutex
);
86 free(cache
->hash_table
);
90 entry_size(struct cache_entry
*entry
)
92 size_t ret
= sizeof(*entry
);
93 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
94 if (entry
->code_sizes
[i
])
95 ret
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
100 radv_hash_shaders(unsigned char *hash
,
101 const VkPipelineShaderStageCreateInfo
**stages
,
102 const struct radv_pipeline_layout
*layout
,
103 const struct ac_shader_variant_key
*keys
,
106 struct mesa_sha1 ctx
;
108 _mesa_sha1_init(&ctx
);
110 _mesa_sha1_update(&ctx
, keys
, sizeof(*keys
) * MESA_SHADER_STAGES
);
112 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
114 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
116 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
117 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
119 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
120 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
122 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
123 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
124 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
128 _mesa_sha1_update(&ctx
, &flags
, 4);
129 _mesa_sha1_final(&ctx
, hash
);
133 static struct cache_entry
*
134 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
135 const unsigned char *sha1
)
137 const uint32_t mask
= cache
->table_size
- 1;
138 const uint32_t start
= (*(uint32_t *) sha1
);
140 if (cache
->table_size
== 0)
143 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
144 const uint32_t index
= (start
+ i
) & mask
;
145 struct cache_entry
*entry
= cache
->hash_table
[index
];
150 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
155 unreachable("hash table should never be full");
158 static struct cache_entry
*
159 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
160 const unsigned char *sha1
)
162 struct cache_entry
*entry
;
164 pthread_mutex_lock(&cache
->mutex
);
166 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
168 pthread_mutex_unlock(&cache
->mutex
);
174 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
175 struct radv_pipeline_cache
*cache
,
176 const unsigned char *sha1
,
177 struct radv_shader_variant
**variants
)
179 struct cache_entry
*entry
;
182 cache
= device
->mem_cache
;
184 pthread_mutex_lock(&cache
->mutex
);
186 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
189 if (!device
->physical_device
->disk_cache
||
190 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
)) {
191 pthread_mutex_unlock(&cache
->mutex
);
195 uint8_t disk_sha1
[20];
196 disk_cache_compute_key(device
->physical_device
->disk_cache
,
197 sha1
, 20, disk_sha1
);
198 entry
= (struct cache_entry
*)
199 disk_cache_get(device
->physical_device
->disk_cache
,
202 pthread_mutex_unlock(&cache
->mutex
);
207 char *p
= entry
->code
;
208 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
209 if (!entry
->variants
[i
] && entry
->code_sizes
[i
]) {
210 struct radv_shader_variant
*variant
;
211 struct cache_entry_variant_info info
;
213 variant
= calloc(1, sizeof(struct radv_shader_variant
));
215 pthread_mutex_unlock(&cache
->mutex
);
219 memcpy(&info
, p
, sizeof(struct cache_entry_variant_info
));
220 p
+= sizeof(struct cache_entry_variant_info
);
222 variant
->config
= info
.config
;
223 variant
->info
= info
.variant_info
;
224 variant
->rsrc1
= info
.rsrc1
;
225 variant
->rsrc2
= info
.rsrc2
;
226 variant
->code_size
= entry
->code_sizes
[i
];
227 variant
->ref_count
= 1;
229 void *ptr
= radv_alloc_shader_memory(device
, variant
);
230 memcpy(ptr
, p
, entry
->code_sizes
[i
]);
231 p
+= entry
->code_sizes
[i
];
233 entry
->variants
[i
] = variant
;
238 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
239 if (entry
->variants
[i
])
240 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
242 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
243 pthread_mutex_unlock(&cache
->mutex
);
249 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
250 struct cache_entry
*entry
)
252 const uint32_t mask
= cache
->table_size
- 1;
253 const uint32_t start
= entry
->sha1_dw
[0];
255 /* We'll always be able to insert when we get here. */
256 assert(cache
->kernel_count
< cache
->table_size
/ 2);
258 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
259 const uint32_t index
= (start
+ i
) & mask
;
260 if (!cache
->hash_table
[index
]) {
261 cache
->hash_table
[index
] = entry
;
266 cache
->total_size
+= entry_size(entry
);
267 cache
->kernel_count
++;
272 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
274 const uint32_t table_size
= cache
->table_size
* 2;
275 const uint32_t old_table_size
= cache
->table_size
;
276 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
277 struct cache_entry
**table
;
278 struct cache_entry
**old_table
= cache
->hash_table
;
280 table
= malloc(byte_size
);
282 return VK_ERROR_OUT_OF_HOST_MEMORY
;
284 cache
->hash_table
= table
;
285 cache
->table_size
= table_size
;
286 cache
->kernel_count
= 0;
287 cache
->total_size
= 0;
289 memset(cache
->hash_table
, 0, byte_size
);
290 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
291 struct cache_entry
*entry
= old_table
[i
];
295 radv_pipeline_cache_set_entry(cache
, entry
);
304 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
305 struct cache_entry
*entry
)
307 if (cache
->kernel_count
== cache
->table_size
/ 2)
308 radv_pipeline_cache_grow(cache
);
310 /* Failing to grow that hash table isn't fatal, but may mean we don't
311 * have enough space to add this new kernel. Only add it if there's room.
313 if (cache
->kernel_count
< cache
->table_size
/ 2)
314 radv_pipeline_cache_set_entry(cache
, entry
);
318 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
319 struct radv_pipeline_cache
*cache
,
320 const unsigned char *sha1
,
321 struct radv_shader_variant
**variants
,
322 const void *const *codes
,
323 const unsigned *code_sizes
)
326 cache
= device
->mem_cache
;
328 pthread_mutex_lock(&cache
->mutex
);
329 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
331 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
332 if (entry
->variants
[i
]) {
333 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
334 variants
[i
] = entry
->variants
[i
];
336 entry
->variants
[i
] = variants
[i
];
339 p_atomic_inc(&variants
[i
]->ref_count
);
341 pthread_mutex_unlock(&cache
->mutex
);
344 size_t size
= sizeof(*entry
);
345 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
347 size
+= sizeof(struct cache_entry_variant_info
) + code_sizes
[i
];
350 entry
= vk_alloc(&cache
->alloc
, size
, 8,
351 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
353 pthread_mutex_unlock(&cache
->mutex
);
357 memset(entry
, 0, sizeof(*entry
));
358 memcpy(entry
->sha1
, sha1
, 20);
360 char* p
= entry
->code
;
361 struct cache_entry_variant_info info
;
363 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
367 entry
->code_sizes
[i
] = code_sizes
[i
];
369 info
.config
= variants
[i
]->config
;
370 info
.variant_info
= variants
[i
]->info
;
371 info
.rsrc1
= variants
[i
]->rsrc1
;
372 info
.rsrc2
= variants
[i
]->rsrc2
;
373 memcpy(p
, &info
, sizeof(struct cache_entry_variant_info
));
374 p
+= sizeof(struct cache_entry_variant_info
);
376 memcpy(p
, codes
[i
], code_sizes
[i
]);
380 /* Always add cache items to disk. This will allow collection of
381 * compiled shaders by third parties such as steam, even if the app
382 * implements its own pipeline cache.
384 if (device
->physical_device
->disk_cache
) {
385 uint8_t disk_sha1
[20];
386 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
388 disk_cache_put(device
->physical_device
->disk_cache
,
389 disk_sha1
, entry
, entry_size(entry
), NULL
);
392 /* We delay setting the variant so we have reproducible disk cache
395 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
399 entry
->variants
[i
] = variants
[i
];
400 p_atomic_inc(&variants
[i
]->ref_count
);
403 radv_pipeline_cache_add_entry(cache
, entry
);
405 cache
->modified
= true;
406 pthread_mutex_unlock(&cache
->mutex
);
410 struct cache_header
{
411 uint32_t header_size
;
412 uint32_t header_version
;
415 uint8_t uuid
[VK_UUID_SIZE
];
419 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
420 const void *data
, size_t size
)
422 struct radv_device
*device
= cache
->device
;
423 struct cache_header header
;
425 if (size
< sizeof(header
))
427 memcpy(&header
, data
, sizeof(header
));
428 if (header
.header_size
< sizeof(header
))
430 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
432 if (header
.vendor_id
!= ATI_VENDOR_ID
)
434 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
436 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
439 char *end
= (void *) data
+ size
;
440 char *p
= (void *) data
+ header
.header_size
;
442 while (end
- p
>= sizeof(struct cache_entry
)) {
443 struct cache_entry
*entry
= (struct cache_entry
*)p
;
444 struct cache_entry
*dest_entry
;
445 size_t size
= entry_size(entry
);
449 dest_entry
= vk_alloc(&cache
->alloc
, size
,
450 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
452 memcpy(dest_entry
, entry
, size
);
453 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
454 dest_entry
->variants
[i
] = NULL
;
455 radv_pipeline_cache_add_entry(cache
, dest_entry
);
461 VkResult
radv_CreatePipelineCache(
463 const VkPipelineCacheCreateInfo
* pCreateInfo
,
464 const VkAllocationCallbacks
* pAllocator
,
465 VkPipelineCache
* pPipelineCache
)
467 RADV_FROM_HANDLE(radv_device
, device
, _device
);
468 struct radv_pipeline_cache
*cache
;
470 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
471 assert(pCreateInfo
->flags
== 0);
473 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
475 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
477 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
480 cache
->alloc
= *pAllocator
;
482 cache
->alloc
= device
->alloc
;
484 radv_pipeline_cache_init(cache
, device
);
486 if (pCreateInfo
->initialDataSize
> 0) {
487 radv_pipeline_cache_load(cache
,
488 pCreateInfo
->pInitialData
,
489 pCreateInfo
->initialDataSize
);
492 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
497 void radv_DestroyPipelineCache(
499 VkPipelineCache _cache
,
500 const VkAllocationCallbacks
* pAllocator
)
502 RADV_FROM_HANDLE(radv_device
, device
, _device
);
503 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
507 radv_pipeline_cache_finish(cache
);
509 vk_free2(&device
->alloc
, pAllocator
, cache
);
512 VkResult
radv_GetPipelineCacheData(
514 VkPipelineCache _cache
,
518 RADV_FROM_HANDLE(radv_device
, device
, _device
);
519 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
520 struct cache_header
*header
;
521 VkResult result
= VK_SUCCESS
;
523 pthread_mutex_lock(&cache
->mutex
);
525 const size_t size
= sizeof(*header
) + cache
->total_size
;
527 pthread_mutex_unlock(&cache
->mutex
);
531 if (*pDataSize
< sizeof(*header
)) {
532 pthread_mutex_unlock(&cache
->mutex
);
534 return VK_INCOMPLETE
;
536 void *p
= pData
, *end
= pData
+ *pDataSize
;
538 header
->header_size
= sizeof(*header
);
539 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
540 header
->vendor_id
= ATI_VENDOR_ID
;
541 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
542 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
543 p
+= header
->header_size
;
545 struct cache_entry
*entry
;
546 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
547 if (!cache
->hash_table
[i
])
549 entry
= cache
->hash_table
[i
];
550 const uint32_t size
= entry_size(entry
);
551 if (end
< p
+ size
) {
552 result
= VK_INCOMPLETE
;
556 memcpy(p
, entry
, size
);
557 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
558 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
561 *pDataSize
= p
- pData
;
563 pthread_mutex_unlock(&cache
->mutex
);
568 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
569 struct radv_pipeline_cache
*src
)
571 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
572 struct cache_entry
*entry
= src
->hash_table
[i
];
573 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
576 radv_pipeline_cache_add_entry(dst
, entry
);
578 src
->hash_table
[i
] = NULL
;
582 VkResult
radv_MergePipelineCaches(
584 VkPipelineCache destCache
,
585 uint32_t srcCacheCount
,
586 const VkPipelineCache
* pSrcCaches
)
588 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
590 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
591 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
593 radv_pipeline_cache_merge(dst
, src
);