2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
34 struct cache_entry_variant_info
{
35 struct ac_shader_variant_info variant_info
;
36 struct ac_shader_config config
;
37 uint32_t rsrc1
, rsrc2
;
42 unsigned char sha1
[20];
45 uint32_t code_sizes
[MESA_SHADER_STAGES
];
46 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
51 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
52 struct radv_device
*device
)
54 cache
->device
= device
;
55 pthread_mutex_init(&cache
->mutex
, NULL
);
57 cache
->modified
= false;
58 cache
->kernel_count
= 0;
59 cache
->total_size
= 0;
60 cache
->table_size
= 1024;
61 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
62 cache
->hash_table
= malloc(byte_size
);
64 /* We don't consider allocation failure fatal, we just start with a 0-sized
66 if (cache
->hash_table
== NULL
||
67 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
))
68 cache
->table_size
= 0;
70 memset(cache
->hash_table
, 0, byte_size
);
74 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
76 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
77 if (cache
->hash_table
[i
]) {
78 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
79 if (cache
->hash_table
[i
]->variants
[j
])
80 radv_shader_variant_destroy(cache
->device
,
81 cache
->hash_table
[i
]->variants
[j
]);
83 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
85 pthread_mutex_destroy(&cache
->mutex
);
86 free(cache
->hash_table
);
90 entry_size(struct cache_entry
*entry
)
92 size_t ret
= sizeof(*entry
);
93 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
94 if (entry
->code_sizes
[i
])
95 ret
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
100 radv_hash_shader(unsigned char *hash
, struct radv_shader_module
*module
,
101 const char *entrypoint
,
102 const VkSpecializationInfo
*spec_info
,
103 const struct radv_pipeline_layout
*layout
,
104 const struct ac_shader_variant_key
*key
,
107 struct mesa_sha1 ctx
;
109 _mesa_sha1_init(&ctx
);
111 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
112 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
113 _mesa_sha1_update(&ctx
, entrypoint
, strlen(entrypoint
));
115 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
117 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
118 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
119 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
121 _mesa_sha1_update(&ctx
, &flags
, 4);
122 _mesa_sha1_final(&ctx
, hash
);
126 static struct cache_entry
*
127 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
128 const unsigned char *sha1
)
130 const uint32_t mask
= cache
->table_size
- 1;
131 const uint32_t start
= (*(uint32_t *) sha1
);
133 if (cache
->table_size
== 0)
136 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
137 const uint32_t index
= (start
+ i
) & mask
;
138 struct cache_entry
*entry
= cache
->hash_table
[index
];
143 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
148 unreachable("hash table should never be full");
151 static struct cache_entry
*
152 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
153 const unsigned char *sha1
)
155 struct cache_entry
*entry
;
157 pthread_mutex_lock(&cache
->mutex
);
159 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
161 pthread_mutex_unlock(&cache
->mutex
);
166 struct radv_shader_variant
*
167 radv_create_shader_variant_from_pipeline_cache(struct radv_device
*device
,
168 struct radv_pipeline_cache
*cache
,
169 const unsigned char *sha1
)
171 struct cache_entry
*entry
= NULL
;
174 entry
= radv_pipeline_cache_search(cache
, sha1
);
176 entry
= radv_pipeline_cache_search(device
->mem_cache
, sha1
);
179 if (!device
->physical_device
->disk_cache
)
181 uint8_t disk_sha1
[20];
182 disk_cache_compute_key(device
->physical_device
->disk_cache
,
183 sha1
, 20, disk_sha1
);
184 entry
= (struct cache_entry
*)
185 disk_cache_get(device
->physical_device
->disk_cache
,
191 if (!entry
->variants
[0]) {
192 struct radv_shader_variant
*variant
;
193 char *p
= entry
->code
;
194 struct cache_entry_variant_info info
;
196 variant
= calloc(1, sizeof(struct radv_shader_variant
));
200 memcpy(&info
, p
, sizeof(struct cache_entry_variant_info
));
201 p
+= sizeof(struct cache_entry_variant_info
);
203 variant
->code_size
= entry
->code_sizes
[0];
204 variant
->config
= info
.config
;
205 variant
->info
= info
.variant_info
;
206 variant
->rsrc1
= info
.rsrc1
;
207 variant
->rsrc2
= info
.rsrc2
;
208 variant
->ref_count
= 1;
210 void *ptr
= radv_alloc_shader_memory(device
, variant
);
211 memcpy(ptr
, p
, entry
->code_sizes
[0]);
213 entry
->variants
[0] = variant
;
216 p_atomic_inc(&entry
->variants
[0]->ref_count
);
217 return entry
->variants
[0];
222 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
223 struct cache_entry
*entry
)
225 const uint32_t mask
= cache
->table_size
- 1;
226 const uint32_t start
= entry
->sha1_dw
[0];
228 /* We'll always be able to insert when we get here. */
229 assert(cache
->kernel_count
< cache
->table_size
/ 2);
231 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
232 const uint32_t index
= (start
+ i
) & mask
;
233 if (!cache
->hash_table
[index
]) {
234 cache
->hash_table
[index
] = entry
;
239 cache
->total_size
+= entry_size(entry
);
240 cache
->kernel_count
++;
245 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
247 const uint32_t table_size
= cache
->table_size
* 2;
248 const uint32_t old_table_size
= cache
->table_size
;
249 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
250 struct cache_entry
**table
;
251 struct cache_entry
**old_table
= cache
->hash_table
;
253 table
= malloc(byte_size
);
255 return VK_ERROR_OUT_OF_HOST_MEMORY
;
257 cache
->hash_table
= table
;
258 cache
->table_size
= table_size
;
259 cache
->kernel_count
= 0;
260 cache
->total_size
= 0;
262 memset(cache
->hash_table
, 0, byte_size
);
263 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
264 struct cache_entry
*entry
= old_table
[i
];
268 radv_pipeline_cache_set_entry(cache
, entry
);
277 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
278 struct cache_entry
*entry
)
280 if (cache
->kernel_count
== cache
->table_size
/ 2)
281 radv_pipeline_cache_grow(cache
);
283 /* Failing to grow that hash table isn't fatal, but may mean we don't
284 * have enough space to add this new kernel. Only add it if there's room.
286 if (cache
->kernel_count
< cache
->table_size
/ 2)
287 radv_pipeline_cache_set_entry(cache
, entry
);
290 struct radv_shader_variant
*
291 radv_pipeline_cache_insert_shader(struct radv_device
*device
,
292 struct radv_pipeline_cache
*cache
,
293 const unsigned char *sha1
,
294 struct radv_shader_variant
*variant
,
295 const void *code
, unsigned code_size
)
298 cache
= device
->mem_cache
;
300 pthread_mutex_lock(&cache
->mutex
);
301 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
303 if (entry
->variants
[0]) {
304 radv_shader_variant_destroy(cache
->device
, variant
);
305 variant
= entry
->variants
[0];
307 entry
->variants
[0] = variant
;
309 p_atomic_inc(&variant
->ref_count
);
310 pthread_mutex_unlock(&cache
->mutex
);
314 entry
= vk_alloc(&cache
->alloc
, sizeof(*entry
) + sizeof(struct cache_entry_variant_info
) + code_size
, 8,
315 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
317 pthread_mutex_unlock(&cache
->mutex
);
321 memset(entry
, 0, sizeof(*entry
));
323 char* p
= entry
->code
;
324 struct cache_entry_variant_info info
;
326 info
.config
= variant
->config
;
327 info
.variant_info
= variant
->info
;
328 info
.rsrc1
= variant
->rsrc1
;
329 info
.rsrc2
= variant
->rsrc2
;
330 memcpy(p
, &info
, sizeof(struct cache_entry_variant_info
));
331 p
+= sizeof(struct cache_entry_variant_info
);
333 memcpy(entry
->sha1
, sha1
, 20);
334 memcpy(p
, code
, code_size
);
336 entry
->code_sizes
[0] = code_size
;
338 /* Set variant to NULL so we have reproducible cache items */
339 entry
->variants
[0] = NULL
;
341 /* Always add cache items to disk. This will allow collection of
342 * compiled shaders by third parties such as steam, even if the app
343 * implements its own pipeline cache.
345 if (device
->physical_device
->disk_cache
) {
346 uint8_t disk_sha1
[20];
347 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
349 disk_cache_put(device
->physical_device
->disk_cache
,
350 disk_sha1
, entry
, entry_size(entry
), NULL
);
353 entry
->variants
[0] = variant
;
354 p_atomic_inc(&variant
->ref_count
);
356 radv_pipeline_cache_add_entry(cache
, entry
);
358 cache
->modified
= true;
359 pthread_mutex_unlock(&cache
->mutex
);
363 struct cache_header
{
364 uint32_t header_size
;
365 uint32_t header_version
;
368 uint8_t uuid
[VK_UUID_SIZE
];
372 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
373 const void *data
, size_t size
)
375 struct radv_device
*device
= cache
->device
;
376 struct cache_header header
;
378 if (size
< sizeof(header
))
380 memcpy(&header
, data
, sizeof(header
));
381 if (header
.header_size
< sizeof(header
))
383 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
385 if (header
.vendor_id
!= ATI_VENDOR_ID
)
387 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
389 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
392 char *end
= (void *) data
+ size
;
393 char *p
= (void *) data
+ header
.header_size
;
395 while (end
- p
>= sizeof(struct cache_entry
)) {
396 struct cache_entry
*entry
= (struct cache_entry
*)p
;
397 struct cache_entry
*dest_entry
;
398 size_t size
= entry_size(entry
);
402 dest_entry
= vk_alloc(&cache
->alloc
, size
,
403 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
405 memcpy(dest_entry
, entry
, size
);
406 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
407 dest_entry
->variants
[i
] = NULL
;
408 radv_pipeline_cache_add_entry(cache
, dest_entry
);
414 VkResult
radv_CreatePipelineCache(
416 const VkPipelineCacheCreateInfo
* pCreateInfo
,
417 const VkAllocationCallbacks
* pAllocator
,
418 VkPipelineCache
* pPipelineCache
)
420 RADV_FROM_HANDLE(radv_device
, device
, _device
);
421 struct radv_pipeline_cache
*cache
;
423 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
424 assert(pCreateInfo
->flags
== 0);
426 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
428 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
430 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
433 cache
->alloc
= *pAllocator
;
435 cache
->alloc
= device
->alloc
;
437 radv_pipeline_cache_init(cache
, device
);
439 if (pCreateInfo
->initialDataSize
> 0) {
440 radv_pipeline_cache_load(cache
,
441 pCreateInfo
->pInitialData
,
442 pCreateInfo
->initialDataSize
);
445 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
450 void radv_DestroyPipelineCache(
452 VkPipelineCache _cache
,
453 const VkAllocationCallbacks
* pAllocator
)
455 RADV_FROM_HANDLE(radv_device
, device
, _device
);
456 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
460 radv_pipeline_cache_finish(cache
);
462 vk_free2(&device
->alloc
, pAllocator
, cache
);
465 VkResult
radv_GetPipelineCacheData(
467 VkPipelineCache _cache
,
471 RADV_FROM_HANDLE(radv_device
, device
, _device
);
472 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
473 struct cache_header
*header
;
474 VkResult result
= VK_SUCCESS
;
475 const size_t size
= sizeof(*header
) + cache
->total_size
;
480 if (*pDataSize
< sizeof(*header
)) {
482 return VK_INCOMPLETE
;
484 void *p
= pData
, *end
= pData
+ *pDataSize
;
486 header
->header_size
= sizeof(*header
);
487 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
488 header
->vendor_id
= ATI_VENDOR_ID
;
489 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
490 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
491 p
+= header
->header_size
;
493 struct cache_entry
*entry
;
494 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
495 if (!cache
->hash_table
[i
])
497 entry
= cache
->hash_table
[i
];
498 const uint32_t size
= entry_size(entry
);
499 if (end
< p
+ size
) {
500 result
= VK_INCOMPLETE
;
504 memcpy(p
, entry
, size
);
505 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
506 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
509 *pDataSize
= p
- pData
;
515 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
516 struct radv_pipeline_cache
*src
)
518 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
519 struct cache_entry
*entry
= src
->hash_table
[i
];
520 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
523 radv_pipeline_cache_add_entry(dst
, entry
);
525 src
->hash_table
[i
] = NULL
;
529 VkResult
radv_MergePipelineCaches(
531 VkPipelineCache destCache
,
532 uint32_t srcCacheCount
,
533 const VkPipelineCache
* pSrcCaches
)
535 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
537 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
538 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
540 radv_pipeline_cache_merge(dst
, src
);