src/amd/vulkan/radv_pipeline_cache.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/mesa-sha1.h"
  25 #include "util/debug.h"
  26 #include "util/u_atomic.h"
  27 #include "radv_private.h"
  28
  29 #include "ac_nir_to_llvm.h"
  30
  31 struct cache_entry {
  32         union {
  33                 unsigned char sha1[20];
  34                 uint32_t sha1_dw[5];
  35         };
  36         uint32_t code_size;
  37         struct ac_shader_variant_info variant_info;
  38         struct ac_shader_config config;
  39         uint32_t rsrc1, rsrc2;
  40         struct radv_shader_variant *variant;
  41         uint32_t code[0];
  42 };
  43
  44 void
  45 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
  46                          struct radv_device *device)
  47 {
  48         cache->device = device;
  49         pthread_mutex_init(&cache->mutex, NULL);
  50
  51         cache->modified = false;
  52         cache->kernel_count = 0;
  53         cache->total_size = 0;
  54         cache->table_size = 1024;
  55         const size_t byte_size = cache->table_size * sizeof(cache->hash_table[0]);
  56         cache->hash_table = malloc(byte_size);
  57
  58         /* We don't consider allocation failure fatal, we just start with a 0-sized
  59          * cache. */
  60         if (cache->hash_table == NULL ||
  61             (device->debug_flags & RADV_DEBUG_NO_CACHE))
  62                 cache->table_size = 0;
  63         else
  64                 memset(cache->hash_table, 0, byte_size);
  65 }
  66
  67 void
  68 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache)
  69 {
  70         for (unsigned i = 0; i < cache->table_size; ++i)
  71                 if (cache->hash_table[i]) {
  72                         if (cache->hash_table[i]->variant)
  73                                 radv_shader_variant_destroy(cache->device,
  74                                                             cache->hash_table[i]->variant);
  75                         vk_free(&cache->alloc, cache->hash_table[i]);
  76                 }
  77         pthread_mutex_destroy(&cache->mutex);
  78         free(cache->hash_table);
  79 }
  80
  81 static uint32_t
  82 entry_size(struct cache_entry *entry)
  83 {
  84         return sizeof(*entry) + entry->code_size;
  85 }
  86
  87 void
  88 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
  89                  const char *entrypoint,
  90                  const VkSpecializationInfo *spec_info,
  91                  const struct radv_pipeline_layout *layout,
  92                  const union ac_shader_variant_key *key,
  93                  uint32_t is_geom_copy_shader)
  94 {
  95         struct mesa_sha1 ctx;
  96
  97         _mesa_sha1_init(&ctx);
  98         if (key)
  99                 _mesa_sha1_update(&ctx, key, sizeof(*key));
 100         _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
 101         _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
 102         if (layout)
 103                 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
 104         if (spec_info) {
 105                 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
 106                                   spec_info->mapEntryCount * sizeof spec_info->pMapEntries[0]);
 107                 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
 108         }
 109         _mesa_sha1_update(&ctx, &is_geom_copy_shader, 4);
 110         _mesa_sha1_final(&ctx, hash);
 111 }
 112
 113
 114 static struct cache_entry *
 115 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache *cache,
 116                                     const unsigned char *sha1)
 117 {
 118         const uint32_t mask = cache->table_size - 1;
 119         const uint32_t start = (*(uint32_t *) sha1);
 120
 121         for (uint32_t i = 0; i < cache->table_size; i++) {
 122                 const uint32_t index = (start + i) & mask;
 123                 struct cache_entry *entry = cache->hash_table[index];
 124
 125                 if (!entry)
 126                         return NULL;
 127
 128                 if (memcmp(entry->sha1, sha1, sizeof(entry->sha1)) == 0) {
 129                         return entry;
 130                 }
 131         }
 132
 133         unreachable("hash table should never be full");
 134 }
 135
 136 static struct cache_entry *
 137 radv_pipeline_cache_search(struct radv_pipeline_cache *cache,
 138                            const unsigned char *sha1)
 139 {
 140         struct cache_entry *entry;
 141
 142         pthread_mutex_lock(&cache->mutex);
 143
 144         entry = radv_pipeline_cache_search_unlocked(cache, sha1);
 145
 146         pthread_mutex_unlock(&cache->mutex);
 147
 148         return entry;
 149 }
 150
 151 struct radv_shader_variant *
 152 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
 153                                                struct radv_pipeline_cache *cache,
 154                                                const unsigned char *sha1)
 155 {
 156         struct cache_entry *entry = NULL;
 157
 158         if (cache)
 159                 entry = radv_pipeline_cache_search(cache, sha1);
 160
 161         if (!entry)
 162                 return NULL;
 163
 164         if (!entry->variant) {
 165                 struct radv_shader_variant *variant;
 166
 167                 variant = calloc(1, sizeof(struct radv_shader_variant));
 168                 if (!variant)
 169                         return NULL;
 170
 171                 variant->config = entry->config;
 172                 variant->info = entry->variant_info;
 173                 variant->rsrc1 = entry->rsrc1;
 174                 variant->rsrc2 = entry->rsrc2;
 175                 variant->code_size = entry->code_size;
 176                 variant->ref_count = 1;
 177
 178                 variant->bo = device->ws->buffer_create(device->ws, entry->code_size, 256,
 179                                                 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
 180
 181                 void *ptr = device->ws->buffer_map(variant->bo);
 182                 memcpy(ptr, entry->code, entry->code_size);
 183                 device->ws->buffer_unmap(variant->bo);
 184
 185                 entry->variant = variant;
 186         }
 187
 188         p_atomic_inc(&entry->variant->ref_count);
 189         return entry->variant;
 190 }
 191
 192
 193 static void
 194 radv_pipeline_cache_set_entry(struct radv_pipeline_cache *cache,
 195                               struct cache_entry *entry)
 196 {
 197         const uint32_t mask = cache->table_size - 1;
 198         const uint32_t start = entry->sha1_dw[0];
 199
 200         /* We'll always be able to insert when we get here. */
 201         assert(cache->kernel_count < cache->table_size / 2);
 202
 203         for (uint32_t i = 0; i < cache->table_size; i++) {
 204                 const uint32_t index = (start + i) & mask;
 205                 if (!cache->hash_table[index]) {
 206                         cache->hash_table[index] = entry;
 207                         break;
 208                 }
 209         }
 210
 211         cache->total_size += entry_size(entry);
 212         cache->kernel_count++;
 213 }
 214
 215
 216 static VkResult
 217 radv_pipeline_cache_grow(struct radv_pipeline_cache *cache)
 218 {
 219         const uint32_t table_size = cache->table_size * 2;
 220         const uint32_t old_table_size = cache->table_size;
 221         const size_t byte_size = table_size * sizeof(cache->hash_table[0]);
 222         struct cache_entry **table;
 223         struct cache_entry **old_table = cache->hash_table;
 224
 225         table = malloc(byte_size);
 226         if (table == NULL)
 227                 return VK_ERROR_OUT_OF_HOST_MEMORY;
 228
 229         cache->hash_table = table;
 230         cache->table_size = table_size;
 231         cache->kernel_count = 0;
 232         cache->total_size = 0;
 233
 234         memset(cache->hash_table, 0, byte_size);
 235         for (uint32_t i = 0; i < old_table_size; i++) {
 236                 struct cache_entry *entry = old_table[i];
 237                 if (!entry)
 238                         continue;
 239
 240                 radv_pipeline_cache_set_entry(cache, entry);
 241         }
 242
 243         free(old_table);
 244
 245         return VK_SUCCESS;
 246 }
 247
 248 static void
 249 radv_pipeline_cache_add_entry(struct radv_pipeline_cache *cache,
 250                               struct cache_entry *entry)
 251 {
 252         if (cache->kernel_count == cache->table_size / 2)
 253                 radv_pipeline_cache_grow(cache);
 254
 255         /* Failing to grow that hash table isn't fatal, but may mean we don't
 256          * have enough space to add this new kernel. Only add it if there's room.
 257          */
 258         if (cache->kernel_count < cache->table_size / 2)
 259                 radv_pipeline_cache_set_entry(cache, entry);
 260 }
 261
 262 struct radv_shader_variant *
 263 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
 264                                   const unsigned char *sha1,
 265                                   struct radv_shader_variant *variant,
 266                                   const void *code, unsigned code_size)
 267 {
 268         if (!cache)
 269                 return variant;
 270
 271         pthread_mutex_lock(&cache->mutex);
 272         struct cache_entry *entry = radv_pipeline_cache_search_unlocked(cache, sha1);
 273         if (entry) {
 274                 if (entry->variant) {
 275                         radv_shader_variant_destroy(cache->device, variant);
 276                         variant = entry->variant;
 277                 } else {
 278                         entry->variant = variant;
 279                 }
 280                 p_atomic_inc(&variant->ref_count);
 281                 pthread_mutex_unlock(&cache->mutex);
 282                 return variant;
 283         }
 284
 285         entry = vk_alloc(&cache->alloc, sizeof(*entry) + code_size, 8,
 286                            VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
 287         if (!entry) {
 288                 pthread_mutex_unlock(&cache->mutex);
 289                 return variant;
 290         }
 291
 292         memcpy(entry->sha1, sha1, 20);
 293         memcpy(entry->code, code, code_size);
 294         entry->config = variant->config;
 295         entry->variant_info = variant->info;
 296         entry->rsrc1 = variant->rsrc1;
 297         entry->rsrc2 = variant->rsrc2;
 298         entry->code_size = code_size;
 299         entry->variant = variant;
 300         p_atomic_inc(&variant->ref_count);
 301
 302         radv_pipeline_cache_add_entry(cache, entry);
 303
 304         cache->modified = true;
 305         pthread_mutex_unlock(&cache->mutex);
 306         return variant;
 307 }
 308
 309 struct cache_header {
 310         uint32_t header_size;
 311         uint32_t header_version;
 312         uint32_t vendor_id;
 313         uint32_t device_id;
 314         uint8_t  uuid[VK_UUID_SIZE];
 315 };
 316
 317 void
 318 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 319                          const void *data, size_t size)
 320 {
 321         struct radv_device *device = cache->device;
 322         struct cache_header header;
 323
 324         if (size < sizeof(header))
 325                 return;
 326         memcpy(&header, data, sizeof(header));
 327         if (header.header_size < sizeof(header))
 328                 return;
 329         if (header.header_version != VK_PIPELINE_CACHE_HEADER_VERSION_ONE)
 330                 return;
 331         if (header.vendor_id != 0x1002)
 332                 return;
 333         if (header.device_id != device->physical_device->rad_info.pci_id)
 334                 return;
 335         if (memcmp(header.uuid, device->physical_device->uuid, VK_UUID_SIZE) != 0)
 336                 return;
 337
 338         char *end = (void *) data + size;
 339         char *p = (void *) data + header.header_size;
 340
 341         while (end - p >= sizeof(struct cache_entry)) {
 342                 struct cache_entry *entry = (struct cache_entry*)p;
 343                 struct cache_entry *dest_entry;
 344                 if(end - p < sizeof(*entry) + entry->code_size)
 345                         break;
 346
 347                 dest_entry = vk_alloc(&cache->alloc, sizeof(*entry) + entry->code_size,
 348                                         8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
 349                 if (dest_entry) {
 350                         memcpy(dest_entry, entry, sizeof(*entry) + entry->code_size);
 351                         dest_entry->variant = NULL;
 352                         radv_pipeline_cache_add_entry(cache, dest_entry);
 353                 }
 354                 p += sizeof (*entry) + entry->code_size;
 355         }
 356 }
 357
 358 VkResult radv_CreatePipelineCache(
 359         VkDevice                                    _device,
 360         const VkPipelineCacheCreateInfo*            pCreateInfo,
 361         const VkAllocationCallbacks*                pAllocator,
 362         VkPipelineCache*                            pPipelineCache)
 363 {
 364         RADV_FROM_HANDLE(radv_device, device, _device);
 365         struct radv_pipeline_cache *cache;
 366
 367         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
 368         assert(pCreateInfo->flags == 0);
 369
 370         cache = vk_alloc2(&device->alloc, pAllocator,
 371                             sizeof(*cache), 8,
 372                             VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 373         if (cache == NULL)
 374                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 375
 376         if (pAllocator)
 377                 cache->alloc = *pAllocator;
 378         else
 379                 cache->alloc = device->alloc;
 380
 381         radv_pipeline_cache_init(cache, device);
 382
 383         if (pCreateInfo->initialDataSize > 0) {
 384                 radv_pipeline_cache_load(cache,
 385                                          pCreateInfo->pInitialData,
 386                                          pCreateInfo->initialDataSize);
 387         }
 388
 389         *pPipelineCache = radv_pipeline_cache_to_handle(cache);
 390
 391         return VK_SUCCESS;
 392 }
 393
 394 void radv_DestroyPipelineCache(
 395         VkDevice                                    _device,
 396         VkPipelineCache                             _cache,
 397         const VkAllocationCallbacks*                pAllocator)
 398 {
 399         RADV_FROM_HANDLE(radv_device, device, _device);
 400         RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
 401
 402         if (!cache)
 403                 return;
 404         radv_pipeline_cache_finish(cache);
 405
 406         vk_free2(&device->alloc, pAllocator, cache);
 407 }
 408
 409 VkResult radv_GetPipelineCacheData(
 410         VkDevice                                    _device,
 411         VkPipelineCache                             _cache,
 412         size_t*                                     pDataSize,
 413         void*                                       pData)
 414 {
 415         RADV_FROM_HANDLE(radv_device, device, _device);
 416         RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
 417         struct cache_header *header;
 418         VkResult result = VK_SUCCESS;
 419         const size_t size = sizeof(*header) + cache->total_size;
 420         if (pData == NULL) {
 421                 *pDataSize = size;
 422                 return VK_SUCCESS;
 423         }
 424         if (*pDataSize < sizeof(*header)) {
 425                 *pDataSize = 0;
 426                 return VK_INCOMPLETE;
 427         }
 428         void *p = pData, *end = pData + *pDataSize;
 429         header = p;
 430         header->header_size = sizeof(*header);
 431         header->header_version = VK_PIPELINE_CACHE_HEADER_VERSION_ONE;
 432         header->vendor_id = 0x1002;
 433         header->device_id = device->physical_device->rad_info.pci_id;
 434         memcpy(header->uuid, device->physical_device->uuid, VK_UUID_SIZE);
 435         p += header->header_size;
 436
 437         struct cache_entry *entry;
 438         for (uint32_t i = 0; i < cache->table_size; i++) {
 439                 if (!cache->hash_table[i])
 440                         continue;
 441                 entry = cache->hash_table[i];
 442                 const uint32_t size = entry_size(entry);
 443                 if (end < p + size) {
 444                         result = VK_INCOMPLETE;
 445                         break;
 446                 }
 447
 448                 memcpy(p, entry, size);
 449                 ((struct cache_entry*)p)->variant = NULL;
 450                 p += size;
 451         }
 452         *pDataSize = p - pData;
 453
 454         return result;
 455 }
 456
 457 static void
 458 radv_pipeline_cache_merge(struct radv_pipeline_cache *dst,
 459                           struct radv_pipeline_cache *src)
 460 {
 461         for (uint32_t i = 0; i < src->table_size; i++) {
 462                 struct cache_entry *entry = src->hash_table[i];
 463                 if (!entry || radv_pipeline_cache_search(dst, entry->sha1))
 464                         continue;
 465
 466                 radv_pipeline_cache_add_entry(dst, entry);
 467
 468                 src->hash_table[i] = NULL;
 469         }
 470 }
 471
 472 VkResult radv_MergePipelineCaches(
 473         VkDevice                                    _device,
 474         VkPipelineCache                             destCache,
 475         uint32_t                                    srcCacheCount,
 476         const VkPipelineCache*                      pSrcCaches)
 477 {
 478         RADV_FROM_HANDLE(radv_pipeline_cache, dst, destCache);
 479
 480         for (uint32_t i = 0; i < srcCacheCount; i++) {
 481                 RADV_FROM_HANDLE(radv_pipeline_cache, src, pSrcCaches[i]);
 482
 483                 radv_pipeline_cache_merge(dst, src);
 484         }
 485
 486         return VK_SUCCESS;
 487 }