util/sha1: rework _mesa_sha1_{init,final}
[mesa.git] / src / amd / vulkan / radv_pipeline_cache.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "radv_private.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 struct cache_entry {
31 union {
32 unsigned char sha1[20];
33 uint32_t sha1_dw[5];
34 };
35 uint32_t code_size;
36 struct ac_shader_variant_info variant_info;
37 struct ac_shader_config config;
38 uint32_t rsrc1, rsrc2;
39 struct radv_shader_variant *variant;
40 uint32_t code[0];
41 };
42
43 void
44 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
45 struct radv_device *device)
46 {
47 cache->device = device;
48 pthread_mutex_init(&cache->mutex, NULL);
49
50 cache->modified = false;
51 cache->kernel_count = 0;
52 cache->total_size = 0;
53 cache->table_size = 1024;
54 const size_t byte_size = cache->table_size * sizeof(cache->hash_table[0]);
55 cache->hash_table = malloc(byte_size);
56
57 /* We don't consider allocation failure fatal, we just start with a 0-sized
58 * cache. */
59 if (cache->hash_table == NULL ||
60 (device->debug_flags & RADV_DEBUG_NO_CACHE))
61 cache->table_size = 0;
62 else
63 memset(cache->hash_table, 0, byte_size);
64 }
65
66 void
67 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache)
68 {
69 for (unsigned i = 0; i < cache->table_size; ++i)
70 if (cache->hash_table[i]) {
71 if (cache->hash_table[i]->variant)
72 radv_shader_variant_destroy(cache->device,
73 cache->hash_table[i]->variant);
74 vk_free(&cache->alloc, cache->hash_table[i]);
75 }
76 pthread_mutex_destroy(&cache->mutex);
77 free(cache->hash_table);
78 }
79
80 static uint32_t
81 entry_size(struct cache_entry *entry)
82 {
83 return sizeof(*entry) + entry->code_size;
84 }
85
86 void
87 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
88 const char *entrypoint,
89 const VkSpecializationInfo *spec_info,
90 const struct radv_pipeline_layout *layout,
91 const union ac_shader_variant_key *key,
92 uint32_t is_geom_copy_shader)
93 {
94 struct mesa_sha1 ctx;
95
96 _mesa_sha1_init(&ctx);
97 if (key)
98 _mesa_sha1_update(&ctx, key, sizeof(*key));
99 _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
100 _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
101 if (layout)
102 _mesa_sha1_update(&ctx, layout->sha1, sizeof(layout->sha1));
103 if (spec_info) {
104 _mesa_sha1_update(&ctx, spec_info->pMapEntries,
105 spec_info->mapEntryCount * sizeof spec_info->pMapEntries[0]);
106 _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
107 }
108 _mesa_sha1_update(&ctx, &is_geom_copy_shader, 4);
109 _mesa_sha1_final(&ctx, hash);
110 }
111
112
113 static struct cache_entry *
114 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache *cache,
115 const unsigned char *sha1)
116 {
117 const uint32_t mask = cache->table_size - 1;
118 const uint32_t start = (*(uint32_t *) sha1);
119
120 for (uint32_t i = 0; i < cache->table_size; i++) {
121 const uint32_t index = (start + i) & mask;
122 struct cache_entry *entry = cache->hash_table[index];
123
124 if (!entry)
125 return NULL;
126
127 if (memcmp(entry->sha1, sha1, sizeof(entry->sha1)) == 0) {
128 return entry;
129 }
130 }
131
132 unreachable("hash table should never be full");
133 }
134
135 static struct cache_entry *
136 radv_pipeline_cache_search(struct radv_pipeline_cache *cache,
137 const unsigned char *sha1)
138 {
139 struct cache_entry *entry;
140
141 pthread_mutex_lock(&cache->mutex);
142
143 entry = radv_pipeline_cache_search_unlocked(cache, sha1);
144
145 pthread_mutex_unlock(&cache->mutex);
146
147 return entry;
148 }
149
150 struct radv_shader_variant *
151 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
152 struct radv_pipeline_cache *cache,
153 const unsigned char *sha1)
154 {
155 struct cache_entry *entry = radv_pipeline_cache_search(cache, sha1);
156
157 if (!entry)
158 return NULL;
159
160 if (!entry->variant) {
161 struct radv_shader_variant *variant;
162
163 variant = calloc(1, sizeof(struct radv_shader_variant));
164 if (!variant)
165 return NULL;
166
167 variant->config = entry->config;
168 variant->info = entry->variant_info;
169 variant->rsrc1 = entry->rsrc1;
170 variant->rsrc2 = entry->rsrc2;
171 variant->ref_count = 1;
172
173 variant->bo = device->ws->buffer_create(device->ws, entry->code_size, 256,
174 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
175
176 void *ptr = device->ws->buffer_map(variant->bo);
177 memcpy(ptr, entry->code, entry->code_size);
178 device->ws->buffer_unmap(variant->bo);
179
180 entry->variant = variant;
181 }
182
183 __sync_fetch_and_add(&entry->variant->ref_count, 1);
184 return entry->variant;
185 }
186
187
188 static void
189 radv_pipeline_cache_set_entry(struct radv_pipeline_cache *cache,
190 struct cache_entry *entry)
191 {
192 const uint32_t mask = cache->table_size - 1;
193 const uint32_t start = entry->sha1_dw[0];
194
195 /* We'll always be able to insert when we get here. */
196 assert(cache->kernel_count < cache->table_size / 2);
197
198 for (uint32_t i = 0; i < cache->table_size; i++) {
199 const uint32_t index = (start + i) & mask;
200 if (!cache->hash_table[index]) {
201 cache->hash_table[index] = entry;
202 break;
203 }
204 }
205
206 cache->total_size += entry_size(entry);
207 cache->kernel_count++;
208 }
209
210
211 static VkResult
212 radv_pipeline_cache_grow(struct radv_pipeline_cache *cache)
213 {
214 const uint32_t table_size = cache->table_size * 2;
215 const uint32_t old_table_size = cache->table_size;
216 const size_t byte_size = table_size * sizeof(cache->hash_table[0]);
217 struct cache_entry **table;
218 struct cache_entry **old_table = cache->hash_table;
219
220 table = malloc(byte_size);
221 if (table == NULL)
222 return VK_ERROR_OUT_OF_HOST_MEMORY;
223
224 cache->hash_table = table;
225 cache->table_size = table_size;
226 cache->kernel_count = 0;
227 cache->total_size = 0;
228
229 memset(cache->hash_table, 0, byte_size);
230 for (uint32_t i = 0; i < old_table_size; i++) {
231 struct cache_entry *entry = old_table[i];
232 if (!entry)
233 continue;
234
235 radv_pipeline_cache_set_entry(cache, entry);
236 }
237
238 free(old_table);
239
240 return VK_SUCCESS;
241 }
242
243 static void
244 radv_pipeline_cache_add_entry(struct radv_pipeline_cache *cache,
245 struct cache_entry *entry)
246 {
247 if (cache->kernel_count == cache->table_size / 2)
248 radv_pipeline_cache_grow(cache);
249
250 /* Failing to grow that hash table isn't fatal, but may mean we don't
251 * have enough space to add this new kernel. Only add it if there's room.
252 */
253 if (cache->kernel_count < cache->table_size / 2)
254 radv_pipeline_cache_set_entry(cache, entry);
255 }
256
257 struct radv_shader_variant *
258 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
259 const unsigned char *sha1,
260 struct radv_shader_variant *variant,
261 const void *code, unsigned code_size)
262 {
263 pthread_mutex_lock(&cache->mutex);
264 struct cache_entry *entry = radv_pipeline_cache_search_unlocked(cache, sha1);
265 if (entry) {
266 if (entry->variant) {
267 radv_shader_variant_destroy(cache->device, variant);
268 variant = entry->variant;
269 } else {
270 entry->variant = variant;
271 }
272 __sync_fetch_and_add(&variant->ref_count, 1);
273 pthread_mutex_unlock(&cache->mutex);
274 return variant;
275 }
276
277 entry = vk_alloc(&cache->alloc, sizeof(*entry) + code_size, 8,
278 VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
279 if (!entry) {
280 pthread_mutex_unlock(&cache->mutex);
281 return variant;
282 }
283
284 memcpy(entry->sha1, sha1, 20);
285 memcpy(entry->code, code, code_size);
286 entry->config = variant->config;
287 entry->variant_info = variant->info;
288 entry->rsrc1 = variant->rsrc1;
289 entry->rsrc2 = variant->rsrc2;
290 entry->code_size = code_size;
291 entry->variant = variant;
292 __sync_fetch_and_add(&variant->ref_count, 1);
293
294 radv_pipeline_cache_add_entry(cache, entry);
295
296 cache->modified = true;
297 pthread_mutex_unlock(&cache->mutex);
298 return variant;
299 }
300
301 struct cache_header {
302 uint32_t header_size;
303 uint32_t header_version;
304 uint32_t vendor_id;
305 uint32_t device_id;
306 uint8_t uuid[VK_UUID_SIZE];
307 };
308
309 void
310 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
311 const void *data, size_t size)
312 {
313 struct radv_device *device = cache->device;
314 struct cache_header header;
315
316 if (size < sizeof(header))
317 return;
318 memcpy(&header, data, sizeof(header));
319 if (header.header_size < sizeof(header))
320 return;
321 if (header.header_version != VK_PIPELINE_CACHE_HEADER_VERSION_ONE)
322 return;
323 if (header.vendor_id != 0x1002)
324 return;
325 if (header.device_id != device->physical_device->rad_info.pci_id)
326 return;
327 if (memcmp(header.uuid, device->physical_device->uuid, VK_UUID_SIZE) != 0)
328 return;
329
330 char *end = (void *) data + size;
331 char *p = (void *) data + header.header_size;
332
333 while (end - p >= sizeof(struct cache_entry)) {
334 struct cache_entry *entry = (struct cache_entry*)p;
335 struct cache_entry *dest_entry;
336 if(end - p < sizeof(*entry) + entry->code_size)
337 break;
338
339 dest_entry = vk_alloc(&cache->alloc, sizeof(*entry) + entry->code_size,
340 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
341 if (dest_entry) {
342 memcpy(dest_entry, entry, sizeof(*entry) + entry->code_size);
343 dest_entry->variant = NULL;
344 radv_pipeline_cache_add_entry(cache, dest_entry);
345 }
346 p += sizeof (*entry) + entry->code_size;
347 }
348 }
349
350 VkResult radv_CreatePipelineCache(
351 VkDevice _device,
352 const VkPipelineCacheCreateInfo* pCreateInfo,
353 const VkAllocationCallbacks* pAllocator,
354 VkPipelineCache* pPipelineCache)
355 {
356 RADV_FROM_HANDLE(radv_device, device, _device);
357 struct radv_pipeline_cache *cache;
358
359 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO);
360 assert(pCreateInfo->flags == 0);
361
362 cache = vk_alloc2(&device->alloc, pAllocator,
363 sizeof(*cache), 8,
364 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
365 if (cache == NULL)
366 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
367
368 if (pAllocator)
369 cache->alloc = *pAllocator;
370 else
371 cache->alloc = device->alloc;
372
373 radv_pipeline_cache_init(cache, device);
374
375 if (pCreateInfo->initialDataSize > 0) {
376 radv_pipeline_cache_load(cache,
377 pCreateInfo->pInitialData,
378 pCreateInfo->initialDataSize);
379 }
380
381 *pPipelineCache = radv_pipeline_cache_to_handle(cache);
382
383 return VK_SUCCESS;
384 }
385
386 void radv_DestroyPipelineCache(
387 VkDevice _device,
388 VkPipelineCache _cache,
389 const VkAllocationCallbacks* pAllocator)
390 {
391 RADV_FROM_HANDLE(radv_device, device, _device);
392 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
393
394 if (!cache)
395 return;
396 radv_pipeline_cache_finish(cache);
397
398 vk_free2(&device->alloc, pAllocator, cache);
399 }
400
401 VkResult radv_GetPipelineCacheData(
402 VkDevice _device,
403 VkPipelineCache _cache,
404 size_t* pDataSize,
405 void* pData)
406 {
407 RADV_FROM_HANDLE(radv_device, device, _device);
408 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
409 struct cache_header *header;
410 VkResult result = VK_SUCCESS;
411 const size_t size = sizeof(*header) + cache->total_size;
412 if (pData == NULL) {
413 *pDataSize = size;
414 return VK_SUCCESS;
415 }
416 if (*pDataSize < sizeof(*header)) {
417 *pDataSize = 0;
418 return VK_INCOMPLETE;
419 }
420 void *p = pData, *end = pData + *pDataSize;
421 header = p;
422 header->header_size = sizeof(*header);
423 header->header_version = VK_PIPELINE_CACHE_HEADER_VERSION_ONE;
424 header->vendor_id = 0x1002;
425 header->device_id = device->physical_device->rad_info.pci_id;
426 memcpy(header->uuid, device->physical_device->uuid, VK_UUID_SIZE);
427 p += header->header_size;
428
429 struct cache_entry *entry;
430 for (uint32_t i = 0; i < cache->table_size; i++) {
431 if (!cache->hash_table[i])
432 continue;
433 entry = cache->hash_table[i];
434 const uint32_t size = entry_size(entry);
435 if (end < p + size) {
436 result = VK_INCOMPLETE;
437 break;
438 }
439
440 memcpy(p, entry, size);
441 ((struct cache_entry*)p)->variant = NULL;
442 p += size;
443 }
444 *pDataSize = p - pData;
445
446 return result;
447 }
448
449 static void
450 radv_pipeline_cache_merge(struct radv_pipeline_cache *dst,
451 struct radv_pipeline_cache *src)
452 {
453 for (uint32_t i = 0; i < src->table_size; i++) {
454 struct cache_entry *entry = src->hash_table[i];
455 if (!entry || radv_pipeline_cache_search(dst, entry->sha1))
456 continue;
457
458 radv_pipeline_cache_add_entry(dst, entry);
459
460 src->hash_table[i] = NULL;
461 }
462 }
463
464 VkResult radv_MergePipelineCaches(
465 VkDevice _device,
466 VkPipelineCache destCache,
467 uint32_t srcCacheCount,
468 const VkPipelineCache* pSrcCaches)
469 {
470 RADV_FROM_HANDLE(radv_pipeline_cache, dst, destCache);
471
472 for (uint32_t i = 0; i < srcCacheCount; i++) {
473 RADV_FROM_HANDLE(radv_pipeline_cache, src, pSrcCaches[i]);
474
475 radv_pipeline_cache_merge(dst, src);
476 }
477
478 return VK_SUCCESS;
479 }