2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
34 struct cache_entry_variant_info
{
35 struct ac_shader_variant_info variant_info
;
36 struct ac_shader_config config
;
37 uint32_t rsrc1
, rsrc2
;
42 unsigned char sha1
[20];
45 uint32_t code_sizes
[MESA_SHADER_STAGES
];
46 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
51 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
52 struct radv_device
*device
)
54 cache
->device
= device
;
55 pthread_mutex_init(&cache
->mutex
, NULL
);
57 cache
->modified
= false;
58 cache
->kernel_count
= 0;
59 cache
->total_size
= 0;
60 cache
->table_size
= 1024;
61 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
62 cache
->hash_table
= malloc(byte_size
);
64 /* We don't consider allocation failure fatal, we just start with a 0-sized
66 if (cache
->hash_table
== NULL
||
67 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
))
68 cache
->table_size
= 0;
70 memset(cache
->hash_table
, 0, byte_size
);
74 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
76 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
77 if (cache
->hash_table
[i
]) {
78 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
79 if (cache
->hash_table
[i
]->variants
[j
])
80 radv_shader_variant_destroy(cache
->device
,
81 cache
->hash_table
[i
]->variants
[j
]);
83 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
85 pthread_mutex_destroy(&cache
->mutex
);
86 free(cache
->hash_table
);
90 entry_size(struct cache_entry
*entry
)
92 size_t ret
= sizeof(*entry
);
93 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
94 if (entry
->code_sizes
[i
])
95 ret
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
100 radv_hash_shaders(unsigned char *hash
,
101 const VkPipelineShaderStageCreateInfo
**stages
,
102 const struct radv_pipeline_layout
*layout
,
103 const struct ac_shader_variant_key
*keys
,
106 struct mesa_sha1 ctx
;
108 _mesa_sha1_init(&ctx
);
110 _mesa_sha1_update(&ctx
, keys
, sizeof(*keys
) * MESA_SHADER_STAGES
);
112 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
114 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
116 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
117 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
119 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
120 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
122 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
123 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
124 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
128 _mesa_sha1_update(&ctx
, &flags
, 4);
129 _mesa_sha1_final(&ctx
, hash
);
133 static struct cache_entry
*
134 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
135 const unsigned char *sha1
)
137 const uint32_t mask
= cache
->table_size
- 1;
138 const uint32_t start
= (*(uint32_t *) sha1
);
140 if (cache
->table_size
== 0)
143 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
144 const uint32_t index
= (start
+ i
) & mask
;
145 struct cache_entry
*entry
= cache
->hash_table
[index
];
150 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
155 unreachable("hash table should never be full");
158 static struct cache_entry
*
159 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
160 const unsigned char *sha1
)
162 struct cache_entry
*entry
;
164 pthread_mutex_lock(&cache
->mutex
);
166 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
168 pthread_mutex_unlock(&cache
->mutex
);
174 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
175 struct radv_pipeline_cache
*cache
,
176 const unsigned char *sha1
,
177 struct radv_shader_variant
**variants
)
179 struct cache_entry
*entry
;
181 entry
= radv_pipeline_cache_search(cache
, sha1
);
183 entry
= radv_pipeline_cache_search(device
->mem_cache
, sha1
);
186 if (!device
->physical_device
->disk_cache
)
189 uint8_t disk_sha1
[20];
190 disk_cache_compute_key(device
->physical_device
->disk_cache
,
191 sha1
, 20, disk_sha1
);
192 entry
= (struct cache_entry
*)
193 disk_cache_get(device
->physical_device
->disk_cache
,
199 char *p
= entry
->code
;
200 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
201 if (!entry
->variants
[i
] && entry
->code_sizes
[i
]) {
202 struct radv_shader_variant
*variant
;
203 struct cache_entry_variant_info info
;
205 variant
= calloc(1, sizeof(struct radv_shader_variant
));
209 memcpy(&info
, p
, sizeof(struct cache_entry_variant_info
));
210 p
+= sizeof(struct cache_entry_variant_info
);
212 variant
->config
= info
.config
;
213 variant
->info
= info
.variant_info
;
214 variant
->rsrc1
= info
.rsrc1
;
215 variant
->rsrc2
= info
.rsrc2
;
216 variant
->code_size
= entry
->code_sizes
[i
];
217 variant
->ref_count
= 1;
219 void *ptr
= radv_alloc_shader_memory(device
, variant
);
220 memcpy(ptr
, p
, entry
->code_sizes
[i
]);
221 p
+= entry
->code_sizes
[i
];
223 entry
->variants
[i
] = variant
;
228 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
229 if (entry
->variants
[i
])
230 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
232 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
238 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
239 struct cache_entry
*entry
)
241 const uint32_t mask
= cache
->table_size
- 1;
242 const uint32_t start
= entry
->sha1_dw
[0];
244 /* We'll always be able to insert when we get here. */
245 assert(cache
->kernel_count
< cache
->table_size
/ 2);
247 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
248 const uint32_t index
= (start
+ i
) & mask
;
249 if (!cache
->hash_table
[index
]) {
250 cache
->hash_table
[index
] = entry
;
255 cache
->total_size
+= entry_size(entry
);
256 cache
->kernel_count
++;
261 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
263 const uint32_t table_size
= cache
->table_size
* 2;
264 const uint32_t old_table_size
= cache
->table_size
;
265 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
266 struct cache_entry
**table
;
267 struct cache_entry
**old_table
= cache
->hash_table
;
269 table
= malloc(byte_size
);
271 return VK_ERROR_OUT_OF_HOST_MEMORY
;
273 cache
->hash_table
= table
;
274 cache
->table_size
= table_size
;
275 cache
->kernel_count
= 0;
276 cache
->total_size
= 0;
278 memset(cache
->hash_table
, 0, byte_size
);
279 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
280 struct cache_entry
*entry
= old_table
[i
];
284 radv_pipeline_cache_set_entry(cache
, entry
);
293 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
294 struct cache_entry
*entry
)
296 if (cache
->kernel_count
== cache
->table_size
/ 2)
297 radv_pipeline_cache_grow(cache
);
299 /* Failing to grow that hash table isn't fatal, but may mean we don't
300 * have enough space to add this new kernel. Only add it if there's room.
302 if (cache
->kernel_count
< cache
->table_size
/ 2)
303 radv_pipeline_cache_set_entry(cache
, entry
);
307 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
308 struct radv_pipeline_cache
*cache
,
309 const unsigned char *sha1
,
310 struct radv_shader_variant
**variants
,
311 const void *const *codes
,
312 const unsigned *code_sizes
)
315 cache
= device
->mem_cache
;
317 pthread_mutex_lock(&cache
->mutex
);
318 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
320 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
321 if (entry
->variants
[i
]) {
322 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
323 variants
[i
] = entry
->variants
[i
];
325 entry
->variants
[i
] = variants
[i
];
328 p_atomic_inc(&variants
[i
]->ref_count
);
330 pthread_mutex_unlock(&cache
->mutex
);
333 size_t size
= sizeof(*entry
);
334 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
336 size
+= sizeof(struct cache_entry_variant_info
) + code_sizes
[i
];
339 entry
= vk_alloc(&cache
->alloc
, size
, 8,
340 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
342 pthread_mutex_unlock(&cache
->mutex
);
346 memset(entry
, 0, sizeof(*entry
));
347 memcpy(entry
->sha1
, sha1
, 20);
349 char* p
= entry
->code
;
350 struct cache_entry_variant_info info
;
352 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
356 entry
->code_sizes
[i
] = code_sizes
[i
];
358 info
.config
= variants
[i
]->config
;
359 info
.variant_info
= variants
[i
]->info
;
360 info
.rsrc1
= variants
[i
]->rsrc1
;
361 info
.rsrc2
= variants
[i
]->rsrc2
;
362 memcpy(p
, &info
, sizeof(struct cache_entry_variant_info
));
363 p
+= sizeof(struct cache_entry_variant_info
);
365 memcpy(p
, codes
[i
], code_sizes
[i
]);
369 /* Always add cache items to disk. This will allow collection of
370 * compiled shaders by third parties such as steam, even if the app
371 * implements its own pipeline cache.
373 if (device
->physical_device
->disk_cache
) {
374 uint8_t disk_sha1
[20];
375 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
377 disk_cache_put(device
->physical_device
->disk_cache
,
378 disk_sha1
, entry
, entry_size(entry
), NULL
);
381 /* We delay setting the variant so we have reproducible disk cache
384 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
388 entry
->variants
[i
] = variants
[i
];
389 p_atomic_inc(&variants
[i
]->ref_count
);
392 radv_pipeline_cache_add_entry(cache
, entry
);
394 cache
->modified
= true;
395 pthread_mutex_unlock(&cache
->mutex
);
399 struct cache_header
{
400 uint32_t header_size
;
401 uint32_t header_version
;
404 uint8_t uuid
[VK_UUID_SIZE
];
408 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
409 const void *data
, size_t size
)
411 struct radv_device
*device
= cache
->device
;
412 struct cache_header header
;
414 if (size
< sizeof(header
))
416 memcpy(&header
, data
, sizeof(header
));
417 if (header
.header_size
< sizeof(header
))
419 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
421 if (header
.vendor_id
!= ATI_VENDOR_ID
)
423 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
425 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
428 char *end
= (void *) data
+ size
;
429 char *p
= (void *) data
+ header
.header_size
;
431 while (end
- p
>= sizeof(struct cache_entry
)) {
432 struct cache_entry
*entry
= (struct cache_entry
*)p
;
433 struct cache_entry
*dest_entry
;
434 size_t size
= entry_size(entry
);
438 dest_entry
= vk_alloc(&cache
->alloc
, size
,
439 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
441 memcpy(dest_entry
, entry
, size
);
442 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
443 dest_entry
->variants
[i
] = NULL
;
444 radv_pipeline_cache_add_entry(cache
, dest_entry
);
450 VkResult
radv_CreatePipelineCache(
452 const VkPipelineCacheCreateInfo
* pCreateInfo
,
453 const VkAllocationCallbacks
* pAllocator
,
454 VkPipelineCache
* pPipelineCache
)
456 RADV_FROM_HANDLE(radv_device
, device
, _device
);
457 struct radv_pipeline_cache
*cache
;
459 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
460 assert(pCreateInfo
->flags
== 0);
462 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
464 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
466 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
469 cache
->alloc
= *pAllocator
;
471 cache
->alloc
= device
->alloc
;
473 radv_pipeline_cache_init(cache
, device
);
475 if (pCreateInfo
->initialDataSize
> 0) {
476 radv_pipeline_cache_load(cache
,
477 pCreateInfo
->pInitialData
,
478 pCreateInfo
->initialDataSize
);
481 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
486 void radv_DestroyPipelineCache(
488 VkPipelineCache _cache
,
489 const VkAllocationCallbacks
* pAllocator
)
491 RADV_FROM_HANDLE(radv_device
, device
, _device
);
492 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
496 radv_pipeline_cache_finish(cache
);
498 vk_free2(&device
->alloc
, pAllocator
, cache
);
501 VkResult
radv_GetPipelineCacheData(
503 VkPipelineCache _cache
,
507 RADV_FROM_HANDLE(radv_device
, device
, _device
);
508 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
509 struct cache_header
*header
;
510 VkResult result
= VK_SUCCESS
;
511 const size_t size
= sizeof(*header
) + cache
->total_size
;
516 if (*pDataSize
< sizeof(*header
)) {
518 return VK_INCOMPLETE
;
520 void *p
= pData
, *end
= pData
+ *pDataSize
;
522 header
->header_size
= sizeof(*header
);
523 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
524 header
->vendor_id
= ATI_VENDOR_ID
;
525 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
526 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
527 p
+= header
->header_size
;
529 struct cache_entry
*entry
;
530 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
531 if (!cache
->hash_table
[i
])
533 entry
= cache
->hash_table
[i
];
534 const uint32_t size
= entry_size(entry
);
535 if (end
< p
+ size
) {
536 result
= VK_INCOMPLETE
;
540 memcpy(p
, entry
, size
);
541 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
542 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
545 *pDataSize
= p
- pData
;
551 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
552 struct radv_pipeline_cache
*src
)
554 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
555 struct cache_entry
*entry
= src
->hash_table
[i
];
556 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
559 radv_pipeline_cache_add_entry(dst
, entry
);
561 src
->hash_table
[i
] = NULL
;
565 VkResult
radv_MergePipelineCaches(
567 VkPipelineCache destCache
,
568 uint32_t srcCacheCount
,
569 const VkPipelineCache
* pSrcCaches
)
571 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
573 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
574 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
576 radv_pipeline_cache_merge(dst
, src
);