2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/mesa-sha1.h"
25 #include "util/debug.h"
26 #include "util/disk_cache.h"
27 #include "util/u_atomic.h"
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "radv_shader.h"
32 #include "ac_nir_to_llvm.h"
34 struct cache_entry_variant_info
{
35 struct radv_shader_variant_info variant_info
;
36 struct ac_shader_config config
;
37 uint32_t rsrc1
, rsrc2
;
42 unsigned char sha1
[20];
45 uint32_t code_sizes
[MESA_SHADER_STAGES
];
46 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
];
51 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
52 struct radv_device
*device
)
54 cache
->device
= device
;
55 pthread_mutex_init(&cache
->mutex
, NULL
);
57 cache
->modified
= false;
58 cache
->kernel_count
= 0;
59 cache
->total_size
= 0;
60 cache
->table_size
= 1024;
61 const size_t byte_size
= cache
->table_size
* sizeof(cache
->hash_table
[0]);
62 cache
->hash_table
= malloc(byte_size
);
64 /* We don't consider allocation failure fatal, we just start with a 0-sized
65 * cache. Disable caching when we want to keep shader debug info, since
66 * we don't get the debug info on cached shaders. */
67 if (cache
->hash_table
== NULL
||
68 (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
) ||
69 device
->keep_shader_info
)
70 cache
->table_size
= 0;
72 memset(cache
->hash_table
, 0, byte_size
);
76 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
)
78 for (unsigned i
= 0; i
< cache
->table_size
; ++i
)
79 if (cache
->hash_table
[i
]) {
80 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
) {
81 if (cache
->hash_table
[i
]->variants
[j
])
82 radv_shader_variant_destroy(cache
->device
,
83 cache
->hash_table
[i
]->variants
[j
]);
85 vk_free(&cache
->alloc
, cache
->hash_table
[i
]);
87 pthread_mutex_destroy(&cache
->mutex
);
88 free(cache
->hash_table
);
92 entry_size(struct cache_entry
*entry
)
94 size_t ret
= sizeof(*entry
);
95 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
96 if (entry
->code_sizes
[i
])
97 ret
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
102 radv_hash_shaders(unsigned char *hash
,
103 const VkPipelineShaderStageCreateInfo
**stages
,
104 const struct radv_pipeline_layout
*layout
,
105 const struct radv_pipeline_key
*key
,
108 struct mesa_sha1 ctx
;
110 _mesa_sha1_init(&ctx
);
112 _mesa_sha1_update(&ctx
, key
, sizeof(*key
));
114 _mesa_sha1_update(&ctx
, layout
->sha1
, sizeof(layout
->sha1
));
116 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
118 RADV_FROM_HANDLE(radv_shader_module
, module
, stages
[i
]->module
);
119 const VkSpecializationInfo
*spec_info
= stages
[i
]->pSpecializationInfo
;
121 _mesa_sha1_update(&ctx
, module
->sha1
, sizeof(module
->sha1
));
122 _mesa_sha1_update(&ctx
, stages
[i
]->pName
, strlen(stages
[i
]->pName
));
124 _mesa_sha1_update(&ctx
, spec_info
->pMapEntries
,
125 spec_info
->mapEntryCount
* sizeof spec_info
->pMapEntries
[0]);
126 _mesa_sha1_update(&ctx
, spec_info
->pData
, spec_info
->dataSize
);
130 _mesa_sha1_update(&ctx
, &flags
, 4);
131 _mesa_sha1_final(&ctx
, hash
);
135 static struct cache_entry
*
136 radv_pipeline_cache_search_unlocked(struct radv_pipeline_cache
*cache
,
137 const unsigned char *sha1
)
139 const uint32_t mask
= cache
->table_size
- 1;
140 const uint32_t start
= (*(uint32_t *) sha1
);
142 if (cache
->table_size
== 0)
145 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
146 const uint32_t index
= (start
+ i
) & mask
;
147 struct cache_entry
*entry
= cache
->hash_table
[index
];
152 if (memcmp(entry
->sha1
, sha1
, sizeof(entry
->sha1
)) == 0) {
157 unreachable("hash table should never be full");
160 static struct cache_entry
*
161 radv_pipeline_cache_search(struct radv_pipeline_cache
*cache
,
162 const unsigned char *sha1
)
164 struct cache_entry
*entry
;
166 pthread_mutex_lock(&cache
->mutex
);
168 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
170 pthread_mutex_unlock(&cache
->mutex
);
176 radv_pipeline_cache_set_entry(struct radv_pipeline_cache
*cache
,
177 struct cache_entry
*entry
)
179 const uint32_t mask
= cache
->table_size
- 1;
180 const uint32_t start
= entry
->sha1_dw
[0];
182 /* We'll always be able to insert when we get here. */
183 assert(cache
->kernel_count
< cache
->table_size
/ 2);
185 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
186 const uint32_t index
= (start
+ i
) & mask
;
187 if (!cache
->hash_table
[index
]) {
188 cache
->hash_table
[index
] = entry
;
193 cache
->total_size
+= entry_size(entry
);
194 cache
->kernel_count
++;
199 radv_pipeline_cache_grow(struct radv_pipeline_cache
*cache
)
201 const uint32_t table_size
= cache
->table_size
* 2;
202 const uint32_t old_table_size
= cache
->table_size
;
203 const size_t byte_size
= table_size
* sizeof(cache
->hash_table
[0]);
204 struct cache_entry
**table
;
205 struct cache_entry
**old_table
= cache
->hash_table
;
207 table
= malloc(byte_size
);
209 return vk_error(cache
->device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
211 cache
->hash_table
= table
;
212 cache
->table_size
= table_size
;
213 cache
->kernel_count
= 0;
214 cache
->total_size
= 0;
216 memset(cache
->hash_table
, 0, byte_size
);
217 for (uint32_t i
= 0; i
< old_table_size
; i
++) {
218 struct cache_entry
*entry
= old_table
[i
];
222 radv_pipeline_cache_set_entry(cache
, entry
);
231 radv_pipeline_cache_add_entry(struct radv_pipeline_cache
*cache
,
232 struct cache_entry
*entry
)
234 if (cache
->kernel_count
== cache
->table_size
/ 2)
235 radv_pipeline_cache_grow(cache
);
237 /* Failing to grow that hash table isn't fatal, but may mean we don't
238 * have enough space to add this new kernel. Only add it if there's room.
240 if (cache
->kernel_count
< cache
->table_size
/ 2)
241 radv_pipeline_cache_set_entry(cache
, entry
);
245 radv_is_cache_disabled(struct radv_device
*device
)
247 /* Pipeline caches can be disabled with RADV_DEBUG=nocache, with
248 * MESA_GLSL_CACHE_DISABLE=1, and when VK_AMD_shader_info is requested.
250 return (device
->instance
->debug_flags
& RADV_DEBUG_NO_CACHE
) ||
251 device
->keep_shader_info
;
255 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
256 struct radv_pipeline_cache
*cache
,
257 const unsigned char *sha1
,
258 struct radv_shader_variant
**variants
)
260 struct cache_entry
*entry
;
263 cache
= device
->mem_cache
;
265 pthread_mutex_lock(&cache
->mutex
);
267 entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
270 /* Don't cache when we want debug info, since this isn't
271 * present in the cache.
273 if (radv_is_cache_disabled(device
) || !device
->physical_device
->disk_cache
) {
274 pthread_mutex_unlock(&cache
->mutex
);
278 uint8_t disk_sha1
[20];
279 disk_cache_compute_key(device
->physical_device
->disk_cache
,
280 sha1
, 20, disk_sha1
);
281 entry
= (struct cache_entry
*)
282 disk_cache_get(device
->physical_device
->disk_cache
,
285 pthread_mutex_unlock(&cache
->mutex
);
288 size_t size
= entry_size(entry
);
289 struct cache_entry
*new_entry
= vk_alloc(&cache
->alloc
, size
, 8,
290 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
293 pthread_mutex_unlock(&cache
->mutex
);
297 memcpy(new_entry
, entry
, entry_size(entry
));
301 radv_pipeline_cache_add_entry(cache
, new_entry
);
305 char *p
= entry
->code
;
306 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
307 if (!entry
->variants
[i
] && entry
->code_sizes
[i
]) {
308 struct radv_shader_variant
*variant
;
309 struct cache_entry_variant_info info
;
311 variant
= calloc(1, sizeof(struct radv_shader_variant
));
313 pthread_mutex_unlock(&cache
->mutex
);
317 memcpy(&info
, p
, sizeof(struct cache_entry_variant_info
));
318 p
+= sizeof(struct cache_entry_variant_info
);
320 variant
->config
= info
.config
;
321 variant
->info
= info
.variant_info
;
322 variant
->rsrc1
= info
.rsrc1
;
323 variant
->rsrc2
= info
.rsrc2
;
324 variant
->code_size
= entry
->code_sizes
[i
];
325 variant
->ref_count
= 1;
327 void *ptr
= radv_alloc_shader_memory(device
, variant
);
328 memcpy(ptr
, p
, entry
->code_sizes
[i
]);
329 p
+= entry
->code_sizes
[i
];
331 entry
->variants
[i
] = variant
;
332 } else if (entry
->code_sizes
[i
]) {
333 p
+= sizeof(struct cache_entry_variant_info
) + entry
->code_sizes
[i
];
338 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
339 if (entry
->variants
[i
])
340 p_atomic_inc(&entry
->variants
[i
]->ref_count
);
342 memcpy(variants
, entry
->variants
, sizeof(entry
->variants
));
343 pthread_mutex_unlock(&cache
->mutex
);
348 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
349 struct radv_pipeline_cache
*cache
,
350 const unsigned char *sha1
,
351 struct radv_shader_variant
**variants
,
352 const void *const *codes
,
353 const unsigned *code_sizes
)
356 cache
= device
->mem_cache
;
358 pthread_mutex_lock(&cache
->mutex
);
359 struct cache_entry
*entry
= radv_pipeline_cache_search_unlocked(cache
, sha1
);
361 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
362 if (entry
->variants
[i
]) {
363 radv_shader_variant_destroy(cache
->device
, variants
[i
]);
364 variants
[i
] = entry
->variants
[i
];
366 entry
->variants
[i
] = variants
[i
];
369 p_atomic_inc(&variants
[i
]->ref_count
);
371 pthread_mutex_unlock(&cache
->mutex
);
375 /* Don't cache when we want debug info, since this isn't
376 * present in the cache.
378 if (radv_is_cache_disabled(device
)) {
379 pthread_mutex_unlock(&cache
->mutex
);
383 size_t size
= sizeof(*entry
);
384 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
386 size
+= sizeof(struct cache_entry_variant_info
) + code_sizes
[i
];
389 entry
= vk_alloc(&cache
->alloc
, size
, 8,
390 VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
392 pthread_mutex_unlock(&cache
->mutex
);
396 memset(entry
, 0, sizeof(*entry
));
397 memcpy(entry
->sha1
, sha1
, 20);
399 char* p
= entry
->code
;
400 struct cache_entry_variant_info info
;
401 memset(&info
, 0, sizeof(info
));
403 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
407 entry
->code_sizes
[i
] = code_sizes
[i
];
409 info
.config
= variants
[i
]->config
;
410 info
.variant_info
= variants
[i
]->info
;
411 info
.rsrc1
= variants
[i
]->rsrc1
;
412 info
.rsrc2
= variants
[i
]->rsrc2
;
413 memcpy(p
, &info
, sizeof(struct cache_entry_variant_info
));
414 p
+= sizeof(struct cache_entry_variant_info
);
416 memcpy(p
, codes
[i
], code_sizes
[i
]);
420 /* Always add cache items to disk. This will allow collection of
421 * compiled shaders by third parties such as steam, even if the app
422 * implements its own pipeline cache.
424 if (device
->physical_device
->disk_cache
) {
425 uint8_t disk_sha1
[20];
426 disk_cache_compute_key(device
->physical_device
->disk_cache
, sha1
, 20,
428 disk_cache_put(device
->physical_device
->disk_cache
,
429 disk_sha1
, entry
, entry_size(entry
), NULL
);
432 /* We delay setting the variant so we have reproducible disk cache
435 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
439 entry
->variants
[i
] = variants
[i
];
440 p_atomic_inc(&variants
[i
]->ref_count
);
443 radv_pipeline_cache_add_entry(cache
, entry
);
445 cache
->modified
= true;
446 pthread_mutex_unlock(&cache
->mutex
);
450 struct cache_header
{
451 uint32_t header_size
;
452 uint32_t header_version
;
455 uint8_t uuid
[VK_UUID_SIZE
];
459 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
460 const void *data
, size_t size
)
462 struct radv_device
*device
= cache
->device
;
463 struct cache_header header
;
465 if (size
< sizeof(header
))
467 memcpy(&header
, data
, sizeof(header
));
468 if (header
.header_size
< sizeof(header
))
470 if (header
.header_version
!= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
)
472 if (header
.vendor_id
!= ATI_VENDOR_ID
)
474 if (header
.device_id
!= device
->physical_device
->rad_info
.pci_id
)
476 if (memcmp(header
.uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
) != 0)
479 char *end
= (void *) data
+ size
;
480 char *p
= (void *) data
+ header
.header_size
;
482 while (end
- p
>= sizeof(struct cache_entry
)) {
483 struct cache_entry
*entry
= (struct cache_entry
*)p
;
484 struct cache_entry
*dest_entry
;
485 size_t size
= entry_size(entry
);
489 dest_entry
= vk_alloc(&cache
->alloc
, size
,
490 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE
);
492 memcpy(dest_entry
, entry
, size
);
493 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
494 dest_entry
->variants
[i
] = NULL
;
495 radv_pipeline_cache_add_entry(cache
, dest_entry
);
503 VkResult
radv_CreatePipelineCache(
505 const VkPipelineCacheCreateInfo
* pCreateInfo
,
506 const VkAllocationCallbacks
* pAllocator
,
507 VkPipelineCache
* pPipelineCache
)
509 RADV_FROM_HANDLE(radv_device
, device
, _device
);
510 struct radv_pipeline_cache
*cache
;
512 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
);
513 assert(pCreateInfo
->flags
== 0);
515 cache
= vk_alloc2(&device
->alloc
, pAllocator
,
517 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
519 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
522 cache
->alloc
= *pAllocator
;
524 cache
->alloc
= device
->alloc
;
526 radv_pipeline_cache_init(cache
, device
);
528 if (pCreateInfo
->initialDataSize
> 0) {
529 radv_pipeline_cache_load(cache
,
530 pCreateInfo
->pInitialData
,
531 pCreateInfo
->initialDataSize
);
534 *pPipelineCache
= radv_pipeline_cache_to_handle(cache
);
539 void radv_DestroyPipelineCache(
541 VkPipelineCache _cache
,
542 const VkAllocationCallbacks
* pAllocator
)
544 RADV_FROM_HANDLE(radv_device
, device
, _device
);
545 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
549 radv_pipeline_cache_finish(cache
);
551 vk_free2(&device
->alloc
, pAllocator
, cache
);
554 VkResult
radv_GetPipelineCacheData(
556 VkPipelineCache _cache
,
560 RADV_FROM_HANDLE(radv_device
, device
, _device
);
561 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
562 struct cache_header
*header
;
563 VkResult result
= VK_SUCCESS
;
565 pthread_mutex_lock(&cache
->mutex
);
567 const size_t size
= sizeof(*header
) + cache
->total_size
;
569 pthread_mutex_unlock(&cache
->mutex
);
573 if (*pDataSize
< sizeof(*header
)) {
574 pthread_mutex_unlock(&cache
->mutex
);
576 return VK_INCOMPLETE
;
578 void *p
= pData
, *end
= pData
+ *pDataSize
;
580 header
->header_size
= sizeof(*header
);
581 header
->header_version
= VK_PIPELINE_CACHE_HEADER_VERSION_ONE
;
582 header
->vendor_id
= ATI_VENDOR_ID
;
583 header
->device_id
= device
->physical_device
->rad_info
.pci_id
;
584 memcpy(header
->uuid
, device
->physical_device
->cache_uuid
, VK_UUID_SIZE
);
585 p
+= header
->header_size
;
587 struct cache_entry
*entry
;
588 for (uint32_t i
= 0; i
< cache
->table_size
; i
++) {
589 if (!cache
->hash_table
[i
])
591 entry
= cache
->hash_table
[i
];
592 const uint32_t size
= entry_size(entry
);
593 if (end
< p
+ size
) {
594 result
= VK_INCOMPLETE
;
598 memcpy(p
, entry
, size
);
599 for(int j
= 0; j
< MESA_SHADER_STAGES
; ++j
)
600 ((struct cache_entry
*)p
)->variants
[j
] = NULL
;
603 *pDataSize
= p
- pData
;
605 pthread_mutex_unlock(&cache
->mutex
);
610 radv_pipeline_cache_merge(struct radv_pipeline_cache
*dst
,
611 struct radv_pipeline_cache
*src
)
613 for (uint32_t i
= 0; i
< src
->table_size
; i
++) {
614 struct cache_entry
*entry
= src
->hash_table
[i
];
615 if (!entry
|| radv_pipeline_cache_search(dst
, entry
->sha1
))
618 radv_pipeline_cache_add_entry(dst
, entry
);
620 src
->hash_table
[i
] = NULL
;
624 VkResult
radv_MergePipelineCaches(
626 VkPipelineCache destCache
,
627 uint32_t srcCacheCount
,
628 const VkPipelineCache
* pSrcCaches
)
630 RADV_FROM_HANDLE(radv_pipeline_cache
, dst
, destCache
);
632 for (uint32_t i
= 0; i
< srcCacheCount
; i
++) {
633 RADV_FROM_HANDLE(radv_pipeline_cache
, src
, pSrcCaches
[i
]);
635 radv_pipeline_cache_merge(dst
, src
);