2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 /* Pre-declarations needed for WSI entrypoints */
71 typedef struct xcb_connection_t xcb_connection_t
;
72 typedef uint32_t xcb_visualid_t
;
73 typedef uint32_t xcb_window_t
;
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "radv_entrypoints.h"
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
89 * To actually enable the ext we also need
90 * the necessary kernel support.
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
100 static inline uint32_t
101 align_u32(uint32_t v
, uint32_t a
)
103 assert(a
!= 0 && a
== (a
& -a
));
104 return (v
+ a
- 1) & ~(a
- 1);
107 static inline uint32_t
108 align_u32_npot(uint32_t v
, uint32_t a
)
110 return (v
+ a
- 1) / a
* a
;
113 static inline uint64_t
114 align_u64(uint64_t v
, uint64_t a
)
116 assert(a
!= 0 && a
== (a
& -a
));
117 return (v
+ a
- 1) & ~(a
- 1);
120 static inline int32_t
121 align_i32(int32_t v
, int32_t a
)
123 assert(a
!= 0 && a
== (a
& -a
));
124 return (v
+ a
- 1) & ~(a
- 1);
127 /** Alignment must be a power of 2. */
129 radv_is_aligned(uintmax_t n
, uintmax_t a
)
131 assert(a
== (a
& -a
));
132 return (n
& (a
- 1)) == 0;
135 static inline uint32_t
136 round_up_u32(uint32_t v
, uint32_t a
)
138 return (v
+ a
- 1) / a
;
141 static inline uint64_t
142 round_up_u64(uint64_t v
, uint64_t a
)
144 return (v
+ a
- 1) / a
;
147 static inline uint32_t
148 radv_minify(uint32_t n
, uint32_t levels
)
150 if (unlikely(n
== 0))
153 return MAX2(n
>> levels
, 1);
156 radv_clamp_f(float f
, float min
, float max
)
169 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
171 if (*inout_mask
& clear_mask
) {
172 *inout_mask
&= ~clear_mask
;
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
194 struct radv_image_view
;
195 struct radv_instance
;
197 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
199 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
200 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
202 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
203 radv_printflike(3, 4);
204 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
205 void radv_loge_v(const char *format
, va_list va
);
206 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
207 void radv_logi_v(const char *format
, va_list va
);
210 * Print a FINISHME message, including its source location.
212 #define radv_finishme(format, ...) \
214 static bool reported = false; \
216 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
221 /* A non-fatal assert. Useful for debugging. */
223 #define radv_assert(x) ({ \
224 if (unlikely(!(x))) \
225 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
228 #define radv_assert(x) do {} while(0)
231 #define stub_return(v) \
233 radv_finishme("stub %s", __func__); \
239 radv_finishme("stub %s", __func__); \
243 int radv_get_instance_entrypoint_index(const char *name
);
244 int radv_get_device_entrypoint_index(const char *name
);
245 int radv_get_physical_device_entrypoint_index(const char *name
);
247 const char *radv_get_instance_entry_name(int index
);
248 const char *radv_get_physical_device_entry_name(int index
);
249 const char *radv_get_device_entry_name(int index
);
251 bool radv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
252 const struct radv_instance_extension_table
*instance
);
253 bool radv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
254 const struct radv_instance_extension_table
*instance
);
255 bool radv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
256 const struct radv_instance_extension_table
*instance
,
257 const struct radv_device_extension_table
*device
);
259 void *radv_lookup_entrypoint(const char *name
);
261 struct radv_physical_device
{
262 VK_LOADER_DATA _loader_data
;
264 /* Link in radv_instance::physical_devices */
265 struct list_head link
;
267 struct radv_instance
* instance
;
269 struct radeon_winsys
*ws
;
270 struct radeon_info rad_info
;
271 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
272 uint8_t driver_uuid
[VK_UUID_SIZE
];
273 uint8_t device_uuid
[VK_UUID_SIZE
];
274 uint8_t cache_uuid
[VK_UUID_SIZE
];
278 struct wsi_device wsi_device
;
280 bool out_of_order_rast_allowed
;
282 /* Whether DCC should be enabled for MSAA textures. */
283 bool dcc_msaa_allowed
;
285 /* Whether to enable NGG. */
288 /* Whether to enable NGG GS. */
291 /* Whether to enable NGG streamout. */
292 bool use_ngg_streamout
;
294 /* Number of threads per wave. */
295 uint8_t ps_wave_size
;
296 uint8_t cs_wave_size
;
297 uint8_t ge_wave_size
;
299 /* Whether to use the LLVM compiler backend */
302 /* This is the drivers on-disk cache used as a fallback as opposed to
303 * the pipeline cache defined by apps.
305 struct disk_cache
* disk_cache
;
307 VkPhysicalDeviceMemoryProperties memory_properties
;
308 enum radeon_bo_domain memory_domains
[VK_MAX_MEMORY_TYPES
];
309 enum radeon_bo_flag memory_flags
[VK_MAX_MEMORY_TYPES
];
311 drmPciBusInfo bus_info
;
313 struct radv_device_extension_table supported_extensions
;
316 struct radv_instance
{
317 struct vk_object_base base
;
319 VkAllocationCallbacks alloc
;
324 uint32_t engineVersion
;
326 uint64_t debug_flags
;
327 uint64_t perftest_flags
;
329 struct vk_debug_report_instance debug_report_callbacks
;
331 struct radv_instance_extension_table enabled_extensions
;
332 struct radv_instance_dispatch_table dispatch
;
333 struct radv_physical_device_dispatch_table physical_device_dispatch
;
334 struct radv_device_dispatch_table device_dispatch
;
336 bool physical_devices_enumerated
;
337 struct list_head physical_devices
;
339 struct driOptionCache dri_options
;
340 struct driOptionCache available_dri_options
;
343 * Workarounds for game bugs.
345 bool enable_mrt_output_nan_fixup
;
348 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
349 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
351 bool radv_instance_extension_supported(const char *name
);
352 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
353 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
358 struct radv_pipeline_cache
{
359 struct vk_object_base base
;
360 struct radv_device
* device
;
361 pthread_mutex_t mutex
;
362 VkPipelineCacheCreateFlags flags
;
366 uint32_t kernel_count
;
367 struct cache_entry
** hash_table
;
370 VkAllocationCallbacks alloc
;
373 struct radv_pipeline_key
{
374 uint32_t instance_rate_inputs
;
375 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
376 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
377 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
378 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
379 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
380 uint64_t vertex_alpha_adjust
;
381 uint32_t vertex_post_shuffle
;
382 unsigned tess_input_vertices
;
386 uint8_t log2_ps_iter_samples
;
389 uint32_t has_multiview_view_index
: 1;
390 uint32_t optimisations_disabled
: 1;
393 /* Non-zero if a required subgroup size is specified via
394 * VK_EXT_subgroup_size_control.
396 uint8_t compute_subgroup_size
;
399 struct radv_shader_binary
;
400 struct radv_shader_variant
;
403 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
404 struct radv_device
*device
);
406 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
408 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
409 const void *data
, size_t size
);
412 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
413 struct radv_pipeline_cache
*cache
,
414 const unsigned char *sha1
,
415 struct radv_shader_variant
**variants
,
416 bool *found_in_application_cache
);
419 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
420 struct radv_pipeline_cache
*cache
,
421 const unsigned char *sha1
,
422 struct radv_shader_variant
**variants
,
423 struct radv_shader_binary
*const *binaries
);
425 enum radv_blit_ds_layout
{
426 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
427 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
428 RADV_BLIT_DS_LAYOUT_COUNT
,
431 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
433 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
436 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
438 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
441 enum radv_meta_dst_layout
{
442 RADV_META_DST_LAYOUT_GENERAL
,
443 RADV_META_DST_LAYOUT_OPTIMAL
,
444 RADV_META_DST_LAYOUT_COUNT
,
447 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
449 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
452 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
454 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
457 struct radv_meta_state
{
458 VkAllocationCallbacks alloc
;
460 struct radv_pipeline_cache cache
;
463 * For on-demand pipeline creation, makes sure that
464 * only one thread tries to build a pipeline at the same time.
469 * Use array element `i` for images with `2^i` samples.
472 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
473 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
475 VkRenderPass depthstencil_rp
;
476 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
477 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
478 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
480 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
481 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
482 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
483 } clear
[MAX_SAMPLES_LOG2
];
485 VkPipelineLayout clear_color_p_layout
;
486 VkPipelineLayout clear_depth_p_layout
;
487 VkPipelineLayout clear_depth_unrestricted_p_layout
;
489 /* Optimized compute fast HTILE clear for stencil or depth only. */
490 VkPipeline clear_htile_mask_pipeline
;
491 VkPipelineLayout clear_htile_mask_p_layout
;
492 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
495 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
497 /** Pipeline that blits from a 1D image. */
498 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
500 /** Pipeline that blits from a 2D image. */
501 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
503 /** Pipeline that blits from a 3D image. */
504 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
506 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
507 VkPipeline depth_only_1d_pipeline
;
508 VkPipeline depth_only_2d_pipeline
;
509 VkPipeline depth_only_3d_pipeline
;
511 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
512 VkPipeline stencil_only_1d_pipeline
;
513 VkPipeline stencil_only_2d_pipeline
;
514 VkPipeline stencil_only_3d_pipeline
;
515 VkPipelineLayout pipeline_layout
;
516 VkDescriptorSetLayout ds_layout
;
520 VkPipelineLayout p_layouts
[5];
521 VkDescriptorSetLayout ds_layouts
[5];
522 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
524 VkPipeline depth_only_pipeline
[5];
526 VkPipeline stencil_only_pipeline
[5];
527 } blit2d
[MAX_SAMPLES_LOG2
];
529 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
530 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
531 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
534 VkPipelineLayout img_p_layout
;
535 VkDescriptorSetLayout img_ds_layout
;
537 VkPipeline pipeline_3d
;
540 VkPipelineLayout img_p_layout
;
541 VkDescriptorSetLayout img_ds_layout
;
543 VkPipeline pipeline_3d
;
546 VkPipelineLayout img_p_layout
;
547 VkDescriptorSetLayout img_ds_layout
;
551 VkPipelineLayout img_p_layout
;
552 VkDescriptorSetLayout img_ds_layout
;
554 VkPipeline pipeline_3d
;
557 VkPipelineLayout img_p_layout
;
558 VkDescriptorSetLayout img_ds_layout
;
562 VkPipelineLayout img_p_layout
;
563 VkDescriptorSetLayout img_ds_layout
;
565 VkPipeline pipeline_3d
;
568 VkPipelineLayout img_p_layout
;
569 VkDescriptorSetLayout img_ds_layout
;
574 VkPipelineLayout p_layout
;
575 VkPipeline pipeline
[NUM_META_FS_KEYS
];
576 VkRenderPass pass
[NUM_META_FS_KEYS
];
580 VkDescriptorSetLayout ds_layout
;
581 VkPipelineLayout p_layout
;
584 VkPipeline i_pipeline
;
585 VkPipeline srgb_pipeline
;
586 } rc
[MAX_SAMPLES_LOG2
];
588 VkPipeline depth_zero_pipeline
;
590 VkPipeline average_pipeline
;
591 VkPipeline max_pipeline
;
592 VkPipeline min_pipeline
;
593 } depth
[MAX_SAMPLES_LOG2
];
595 VkPipeline stencil_zero_pipeline
;
597 VkPipeline max_pipeline
;
598 VkPipeline min_pipeline
;
599 } stencil
[MAX_SAMPLES_LOG2
];
603 VkDescriptorSetLayout ds_layout
;
604 VkPipelineLayout p_layout
;
607 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
608 VkPipeline pipeline
[NUM_META_FS_KEYS
];
609 } rc
[MAX_SAMPLES_LOG2
];
611 VkRenderPass depth_render_pass
;
612 VkPipeline depth_zero_pipeline
;
614 VkPipeline average_pipeline
;
615 VkPipeline max_pipeline
;
616 VkPipeline min_pipeline
;
617 } depth
[MAX_SAMPLES_LOG2
];
619 VkRenderPass stencil_render_pass
;
620 VkPipeline stencil_zero_pipeline
;
622 VkPipeline max_pipeline
;
623 VkPipeline min_pipeline
;
624 } stencil
[MAX_SAMPLES_LOG2
];
628 VkPipelineLayout p_layout
;
629 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
630 VkPipeline resummarize_pipeline
;
632 } depth_decomp
[MAX_SAMPLES_LOG2
];
635 VkPipelineLayout p_layout
;
636 VkPipeline cmask_eliminate_pipeline
;
637 VkPipeline fmask_decompress_pipeline
;
638 VkPipeline dcc_decompress_pipeline
;
641 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
642 VkPipelineLayout dcc_decompress_compute_p_layout
;
643 VkPipeline dcc_decompress_compute_pipeline
;
647 VkPipelineLayout fill_p_layout
;
648 VkPipelineLayout copy_p_layout
;
649 VkDescriptorSetLayout fill_ds_layout
;
650 VkDescriptorSetLayout copy_ds_layout
;
651 VkPipeline fill_pipeline
;
652 VkPipeline copy_pipeline
;
656 VkDescriptorSetLayout ds_layout
;
657 VkPipelineLayout p_layout
;
658 VkPipeline occlusion_query_pipeline
;
659 VkPipeline pipeline_statistics_query_pipeline
;
660 VkPipeline tfb_query_pipeline
;
661 VkPipeline timestamp_query_pipeline
;
665 VkDescriptorSetLayout ds_layout
;
666 VkPipelineLayout p_layout
;
667 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
672 #define RADV_QUEUE_GENERAL 0
673 #define RADV_QUEUE_COMPUTE 1
674 #define RADV_QUEUE_TRANSFER 2
676 #define RADV_MAX_QUEUE_FAMILIES 3
678 enum ring_type
radv_queue_family_to_ring(int f
);
681 VK_LOADER_DATA _loader_data
;
682 struct radv_device
* device
;
683 struct radeon_winsys_ctx
*hw_ctx
;
684 enum radeon_ctx_priority priority
;
685 uint32_t queue_family_index
;
687 VkDeviceQueueCreateFlags flags
;
689 uint32_t scratch_size_per_wave
;
690 uint32_t scratch_waves
;
691 uint32_t compute_scratch_size_per_wave
;
692 uint32_t compute_scratch_waves
;
693 uint32_t esgs_ring_size
;
694 uint32_t gsvs_ring_size
;
698 bool has_sample_positions
;
700 struct radeon_winsys_bo
*scratch_bo
;
701 struct radeon_winsys_bo
*descriptor_bo
;
702 struct radeon_winsys_bo
*compute_scratch_bo
;
703 struct radeon_winsys_bo
*esgs_ring_bo
;
704 struct radeon_winsys_bo
*gsvs_ring_bo
;
705 struct radeon_winsys_bo
*tess_rings_bo
;
706 struct radeon_winsys_bo
*gds_bo
;
707 struct radeon_winsys_bo
*gds_oa_bo
;
708 struct radeon_cmdbuf
*initial_preamble_cs
;
709 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
710 struct radeon_cmdbuf
*continue_preamble_cs
;
712 struct list_head pending_submissions
;
713 pthread_mutex_t pending_mutex
;
716 struct radv_bo_list
{
717 struct radv_winsys_bo_list list
;
719 pthread_mutex_t mutex
;
722 VkResult
radv_bo_list_add(struct radv_device
*device
,
723 struct radeon_winsys_bo
*bo
);
724 void radv_bo_list_remove(struct radv_device
*device
,
725 struct radeon_winsys_bo
*bo
);
727 #define RADV_BORDER_COLOR_COUNT 4096
728 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
730 struct radv_device_border_color_data
{
731 bool used
[RADV_BORDER_COLOR_COUNT
];
733 struct radeon_winsys_bo
*bo
;
734 VkClearColorValue
*colors_gpu_ptr
;
736 /* Mutex is required to guarantee vkCreateSampler thread safety
737 * given that we are writing to a buffer and checking color occupation */
738 pthread_mutex_t mutex
;
744 struct radv_instance
* instance
;
745 struct radeon_winsys
*ws
;
747 struct radv_meta_state meta_state
;
749 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
750 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
751 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
753 bool always_use_syncobj
;
756 uint32_t tess_offchip_block_dw_size
;
757 uint32_t scratch_waves
;
758 uint32_t dispatch_initiator
;
760 uint32_t gs_table_depth
;
762 /* MSAA sample locations.
763 * The first index is the sample index.
764 * The second index is the coordinate: X, Y. */
765 float sample_locations_1x
[1][2];
766 float sample_locations_2x
[2][2];
767 float sample_locations_4x
[4][2];
768 float sample_locations_8x
[8][2];
771 uint32_t gfx_init_size_dw
;
772 struct radeon_winsys_bo
*gfx_init
;
774 struct radeon_winsys_bo
*trace_bo
;
775 uint32_t *trace_id_ptr
;
777 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
778 bool keep_shader_info
;
780 struct radv_physical_device
*physical_device
;
782 /* Backup in-memory cache to be used if the app doesn't provide one */
783 struct radv_pipeline_cache
* mem_cache
;
786 * use different counters so MSAA MRTs get consecutive surface indices,
787 * even if MASK is allocated in between.
789 uint32_t image_mrt_offset_counter
;
790 uint32_t fmask_mrt_offset_counter
;
791 struct list_head shader_slabs
;
792 mtx_t shader_slab_mutex
;
794 /* For detecting VM faults reported by dmesg. */
795 uint64_t dmesg_timestamp
;
797 struct radv_device_extension_table enabled_extensions
;
798 struct radv_device_dispatch_table dispatch
;
800 /* Whether the app has enabled the robustBufferAccess feature. */
801 bool robust_buffer_access
;
803 /* Whether the driver uses a global BO list. */
804 bool use_global_bo_list
;
806 struct radv_bo_list bo_list
;
808 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
811 struct radv_device_border_color_data border_color_data
;
813 /* Condition variable for legacy timelines, to notify waiters when a
814 * new point gets submitted. */
815 pthread_cond_t timeline_cond
;
818 struct radeon_cmdbuf
*thread_trace_start_cs
[2];
819 struct radeon_cmdbuf
*thread_trace_stop_cs
[2];
820 struct radeon_winsys_bo
*thread_trace_bo
;
821 void *thread_trace_ptr
;
822 uint32_t thread_trace_buffer_size
;
823 int thread_trace_start_frame
;
825 /* Overallocation. */
826 bool overallocation_disallowed
;
827 uint64_t allocated_memory_size
[VK_MAX_MEMORY_HEAPS
];
828 mtx_t overallocation_mutex
;
831 struct radv_device_memory
{
832 struct vk_object_base base
;
833 struct radeon_winsys_bo
*bo
;
834 /* for dedicated allocations */
835 struct radv_image
*image
;
836 struct radv_buffer
*buffer
;
842 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
843 struct AHardwareBuffer
* android_hardware_buffer
;
848 struct radv_descriptor_range
{
853 struct radv_descriptor_set
{
854 struct vk_object_base base
;
855 const struct radv_descriptor_set_layout
*layout
;
857 uint32_t buffer_count
;
859 struct radeon_winsys_bo
*bo
;
861 uint32_t *mapped_ptr
;
862 struct radv_descriptor_range
*dynamic_descriptors
;
864 struct radeon_winsys_bo
*descriptors
[0];
867 struct radv_push_descriptor_set
869 struct radv_descriptor_set set
;
873 struct radv_descriptor_pool_entry
{
876 struct radv_descriptor_set
*set
;
879 struct radv_descriptor_pool
{
880 struct vk_object_base base
;
881 struct radeon_winsys_bo
*bo
;
883 uint64_t current_offset
;
886 uint8_t *host_memory_base
;
887 uint8_t *host_memory_ptr
;
888 uint8_t *host_memory_end
;
890 uint32_t entry_count
;
891 uint32_t max_entry_count
;
892 struct radv_descriptor_pool_entry entries
[0];
895 struct radv_descriptor_update_template_entry
{
896 VkDescriptorType descriptor_type
;
898 /* The number of descriptors to update */
899 uint32_t descriptor_count
;
901 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
904 /* In dwords. Not valid/used for dynamic descriptors */
907 uint32_t buffer_offset
;
909 /* Only valid for combined image samplers and samplers */
911 uint8_t sampler_offset
;
917 /* For push descriptors */
918 const uint32_t *immutable_samplers
;
921 struct radv_descriptor_update_template
{
922 struct vk_object_base base
;
923 uint32_t entry_count
;
924 VkPipelineBindPoint bind_point
;
925 struct radv_descriptor_update_template_entry entry
[0];
929 struct vk_object_base base
;
932 VkBufferUsageFlags usage
;
933 VkBufferCreateFlags flags
;
936 struct radeon_winsys_bo
* bo
;
942 enum radv_dynamic_state_bits
{
943 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
944 RADV_DYNAMIC_SCISSOR
= 1 << 1,
945 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
946 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
947 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
948 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
949 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
950 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
951 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
952 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
953 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
954 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
955 RADV_DYNAMIC_CULL_MODE
= 1 << 12,
956 RADV_DYNAMIC_FRONT_FACE
= 1 << 13,
957 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
= 1 << 14,
958 RADV_DYNAMIC_DEPTH_TEST_ENABLE
= 1 << 15,
959 RADV_DYNAMIC_DEPTH_WRITE_ENABLE
= 1 << 16,
960 RADV_DYNAMIC_DEPTH_COMPARE_OP
= 1 << 17,
961 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
= 1 << 18,
962 RADV_DYNAMIC_STENCIL_TEST_ENABLE
= 1 << 19,
963 RADV_DYNAMIC_STENCIL_OP
= 1 << 20,
964 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
= 1 << 21,
965 RADV_DYNAMIC_ALL
= (1 << 22) - 1,
968 enum radv_cmd_dirty_bits
{
969 /* Keep the dynamic state dirty bits in sync with
970 * enum radv_dynamic_state_bits */
971 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
972 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
973 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
974 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
975 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
976 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
977 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
978 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
979 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
980 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
981 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
982 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
983 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE
= 1 << 12,
984 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE
= 1 << 13,
985 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY
= 1 << 14,
986 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE
= 1 << 15,
987 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE
= 1 << 16,
988 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP
= 1 << 17,
989 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
= 1 << 18,
990 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE
= 1 << 19,
991 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP
= 1 << 20,
992 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
= 1 << 21,
993 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 22) - 1,
994 RADV_CMD_DIRTY_PIPELINE
= 1 << 22,
995 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 23,
996 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 24,
997 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 25,
998 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 26,
1001 enum radv_cmd_flush_bits
{
1002 /* Instruction cache. */
1003 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1004 /* Scalar L1 cache. */
1005 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1006 /* Vector L1 cache. */
1007 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1008 /* L2 cache + L2 metadata cache writeback & invalidate.
1009 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1010 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1011 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1012 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1013 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1014 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1015 /* Framebuffer caches */
1016 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1017 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1018 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1019 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1020 /* Engine synchronization. */
1021 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1022 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1023 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1024 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1025 /* Pipeline query controls. */
1026 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1027 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1028 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1030 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1032 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1033 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1036 struct radv_vertex_binding
{
1037 struct radv_buffer
* buffer
;
1038 VkDeviceSize offset
;
1040 VkDeviceSize stride
;
1043 struct radv_streamout_binding
{
1044 struct radv_buffer
*buffer
;
1045 VkDeviceSize offset
;
1049 struct radv_streamout_state
{
1050 /* Mask of bound streamout buffers. */
1051 uint8_t enabled_mask
;
1053 /* External state that comes from the last vertex stage, it must be
1054 * set explicitely when binding a new graphics pipeline.
1056 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1057 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1059 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1060 uint32_t hw_enabled_mask
;
1062 /* State of VGT_STRMOUT_(CONFIG|EN) */
1063 bool streamout_enabled
;
1066 struct radv_viewport_state
{
1068 VkViewport viewports
[MAX_VIEWPORTS
];
1071 struct radv_scissor_state
{
1073 VkRect2D scissors
[MAX_SCISSORS
];
1076 struct radv_discard_rectangle_state
{
1078 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1081 struct radv_sample_locations_state
{
1082 VkSampleCountFlagBits per_pixel
;
1083 VkExtent2D grid_size
;
1085 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1088 struct radv_dynamic_state
{
1090 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1091 * Defines the set of saved dynamic state.
1095 struct radv_viewport_state viewport
;
1097 struct radv_scissor_state scissor
;
1107 float blend_constants
[4];
1117 } stencil_compare_mask
;
1122 } stencil_write_mask
;
1126 VkStencilOp fail_op
;
1127 VkStencilOp pass_op
;
1128 VkStencilOp depth_fail_op
;
1129 VkCompareOp compare_op
;
1133 VkStencilOp fail_op
;
1134 VkStencilOp pass_op
;
1135 VkStencilOp depth_fail_op
;
1136 VkCompareOp compare_op
;
1143 } stencil_reference
;
1145 struct radv_discard_rectangle_state discard_rectangle
;
1147 struct radv_sample_locations_state sample_location
;
1154 VkCullModeFlags cull_mode
;
1155 VkFrontFace front_face
;
1156 unsigned primitive_topology
;
1158 bool depth_test_enable
;
1159 bool depth_write_enable
;
1160 VkCompareOp depth_compare_op
;
1161 bool depth_bounds_test_enable
;
1162 bool stencil_test_enable
;
1165 extern const struct radv_dynamic_state default_dynamic_state
;
1168 radv_get_debug_option_name(int id
);
1171 radv_get_perftest_option_name(int id
);
1173 struct radv_color_buffer_info
{
1174 uint64_t cb_color_base
;
1175 uint64_t cb_color_cmask
;
1176 uint64_t cb_color_fmask
;
1177 uint64_t cb_dcc_base
;
1178 uint32_t cb_color_slice
;
1179 uint32_t cb_color_view
;
1180 uint32_t cb_color_info
;
1181 uint32_t cb_color_attrib
;
1182 uint32_t cb_color_attrib2
; /* GFX9 and later */
1183 uint32_t cb_color_attrib3
; /* GFX10 and later */
1184 uint32_t cb_dcc_control
;
1185 uint32_t cb_color_cmask_slice
;
1186 uint32_t cb_color_fmask_slice
;
1188 uint32_t cb_color_pitch
; // GFX6-GFX8
1189 uint32_t cb_mrt_epitch
; // GFX9+
1193 struct radv_ds_buffer_info
{
1194 uint64_t db_z_read_base
;
1195 uint64_t db_stencil_read_base
;
1196 uint64_t db_z_write_base
;
1197 uint64_t db_stencil_write_base
;
1198 uint64_t db_htile_data_base
;
1199 uint32_t db_depth_info
;
1201 uint32_t db_stencil_info
;
1202 uint32_t db_depth_view
;
1203 uint32_t db_depth_size
;
1204 uint32_t db_depth_slice
;
1205 uint32_t db_htile_surface
;
1206 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1207 uint32_t db_z_info2
; /* GFX9 only */
1208 uint32_t db_stencil_info2
; /* GFX9 only */
1213 radv_initialise_color_surface(struct radv_device
*device
,
1214 struct radv_color_buffer_info
*cb
,
1215 struct radv_image_view
*iview
);
1217 radv_initialise_ds_surface(struct radv_device
*device
,
1218 struct radv_ds_buffer_info
*ds
,
1219 struct radv_image_view
*iview
);
1222 * Attachment state when recording a renderpass instance.
1224 * The clear value is valid only if there exists a pending clear.
1226 struct radv_attachment_state
{
1227 VkImageAspectFlags pending_clear_aspects
;
1228 uint32_t cleared_views
;
1229 VkClearValue clear_value
;
1230 VkImageLayout current_layout
;
1231 VkImageLayout current_stencil_layout
;
1232 bool current_in_render_loop
;
1233 struct radv_sample_locations_state sample_location
;
1236 struct radv_color_buffer_info cb
;
1237 struct radv_ds_buffer_info ds
;
1239 struct radv_image_view
*iview
;
1242 struct radv_descriptor_state
{
1243 struct radv_descriptor_set
*sets
[MAX_SETS
];
1246 struct radv_push_descriptor_set push_set
;
1248 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1251 struct radv_subpass_sample_locs_state
{
1252 uint32_t subpass_idx
;
1253 struct radv_sample_locations_state sample_location
;
1256 struct radv_cmd_state
{
1257 /* Vertex descriptors */
1264 uint32_t prefetch_L2_mask
;
1266 struct radv_pipeline
* pipeline
;
1267 struct radv_pipeline
* emitted_pipeline
;
1268 struct radv_pipeline
* compute_pipeline
;
1269 struct radv_pipeline
* emitted_compute_pipeline
;
1270 struct radv_framebuffer
* framebuffer
;
1271 struct radv_render_pass
* pass
;
1272 const struct radv_subpass
* subpass
;
1273 struct radv_dynamic_state dynamic
;
1274 struct radv_attachment_state
* attachments
;
1275 struct radv_streamout_state streamout
;
1276 VkRect2D render_area
;
1278 uint32_t num_subpass_sample_locs
;
1279 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1282 struct radv_buffer
*index_buffer
;
1283 uint64_t index_offset
;
1284 uint32_t index_type
;
1285 uint32_t max_index_count
;
1287 int32_t last_index_type
;
1289 int32_t last_primitive_reset_en
;
1290 uint32_t last_primitive_reset_index
;
1291 enum radv_cmd_flush_bits flush_bits
;
1292 unsigned active_occlusion_queries
;
1293 bool perfect_occlusion_queries_enabled
;
1294 unsigned active_pipeline_queries
;
1295 unsigned active_pipeline_gds_queries
;
1298 uint32_t last_ia_multi_vgt_param
;
1300 uint32_t last_num_instances
;
1301 uint32_t last_first_instance
;
1302 uint32_t last_vertex_offset
;
1304 uint32_t last_sx_ps_downconvert
;
1305 uint32_t last_sx_blend_opt_epsilon
;
1306 uint32_t last_sx_blend_opt_control
;
1308 /* Whether CP DMA is busy/idle. */
1311 /* Conditional rendering info. */
1312 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1313 uint64_t predication_va
;
1315 /* Inheritance info. */
1316 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1318 bool context_roll_without_scissor_emitted
;
1320 /* SQTT related state. */
1321 uint32_t current_event_type
;
1322 uint32_t num_events
;
1323 uint32_t num_layout_transitions
;
1326 struct radv_cmd_pool
{
1327 struct vk_object_base base
;
1328 VkAllocationCallbacks alloc
;
1329 struct list_head cmd_buffers
;
1330 struct list_head free_cmd_buffers
;
1331 uint32_t queue_family_index
;
1334 struct radv_cmd_buffer_upload
{
1338 struct radeon_winsys_bo
*upload_bo
;
1339 struct list_head list
;
1342 enum radv_cmd_buffer_status
{
1343 RADV_CMD_BUFFER_STATUS_INVALID
,
1344 RADV_CMD_BUFFER_STATUS_INITIAL
,
1345 RADV_CMD_BUFFER_STATUS_RECORDING
,
1346 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1347 RADV_CMD_BUFFER_STATUS_PENDING
,
1350 struct radv_cmd_buffer
{
1351 struct vk_object_base base
;
1353 struct radv_device
* device
;
1355 struct radv_cmd_pool
* pool
;
1356 struct list_head pool_link
;
1358 VkCommandBufferUsageFlags usage_flags
;
1359 VkCommandBufferLevel level
;
1360 enum radv_cmd_buffer_status status
;
1361 struct radeon_cmdbuf
*cs
;
1362 struct radv_cmd_state state
;
1363 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1364 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1365 uint32_t queue_family_index
;
1367 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1368 VkShaderStageFlags push_constant_stages
;
1369 struct radv_descriptor_set meta_push_descriptors
;
1371 struct radv_descriptor_state descriptors
[MAX_BIND_POINTS
];
1373 struct radv_cmd_buffer_upload upload
;
1375 uint32_t scratch_size_per_wave_needed
;
1376 uint32_t scratch_waves_wanted
;
1377 uint32_t compute_scratch_size_per_wave_needed
;
1378 uint32_t compute_scratch_waves_wanted
;
1379 uint32_t esgs_ring_size_needed
;
1380 uint32_t gsvs_ring_size_needed
;
1381 bool tess_rings_needed
;
1382 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1383 bool gds_oa_needed
; /* for GFX10 streamout */
1384 bool sample_positions_needed
;
1386 VkResult record_result
;
1388 uint64_t gfx9_fence_va
;
1389 uint32_t gfx9_fence_idx
;
1390 uint64_t gfx9_eop_bug_va
;
1393 * Whether a query pool has been resetted and we have to flush caches.
1395 bool pending_reset_query
;
1398 * Bitmask of pending active query flushes.
1400 enum radv_cmd_flush_bits active_query_flush_bits
;
1404 struct radv_image_view
;
1406 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1408 void si_emit_graphics(struct radv_device
*device
,
1409 struct radeon_cmdbuf
*cs
);
1410 void si_emit_compute(struct radv_physical_device
*physical_device
,
1411 struct radeon_cmdbuf
*cs
);
1413 void cik_create_gfx_config(struct radv_device
*device
);
1415 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1416 int count
, const VkViewport
*viewports
);
1417 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1418 int count
, const VkRect2D
*scissors
,
1419 const VkViewport
*viewports
, bool can_use_guardband
);
1420 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1421 bool instanced_draw
, bool indirect_draw
,
1422 bool count_from_stream_output
,
1423 uint32_t draw_vertex_count
,
1425 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1426 enum chip_class chip_class
,
1428 unsigned event
, unsigned event_flags
,
1429 unsigned dst_sel
, unsigned data_sel
,
1432 uint64_t gfx9_eop_bug_va
);
1434 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1435 uint32_t ref
, uint32_t mask
);
1436 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1437 enum chip_class chip_class
,
1438 uint32_t *fence_ptr
, uint64_t va
,
1440 enum radv_cmd_flush_bits flush_bits
,
1441 uint64_t gfx9_eop_bug_va
);
1442 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1443 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1444 bool inverted
, uint64_t va
);
1445 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1446 uint64_t src_va
, uint64_t dest_va
,
1448 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1450 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1451 uint64_t size
, unsigned value
);
1452 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1454 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1456 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1459 unsigned *out_offset
,
1462 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1463 const struct radv_subpass
*subpass
);
1465 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1466 unsigned size
, unsigned alignmnet
,
1467 const void *data
, unsigned *out_offset
);
1469 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1470 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1471 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1472 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1473 VkImageAspectFlags aspects
,
1474 VkResolveModeFlagBits resolve_mode
);
1475 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1476 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1477 VkImageAspectFlags aspects
,
1478 VkResolveModeFlagBits resolve_mode
);
1479 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1480 unsigned radv_get_default_max_sample_dist(int log_samples
);
1481 void radv_device_init_msaa(struct radv_device
*device
);
1483 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1484 const struct radv_image_view
*iview
,
1485 VkClearDepthStencilValue ds_clear_value
,
1486 VkImageAspectFlags aspects
);
1488 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1489 const struct radv_image_view
*iview
,
1491 uint32_t color_values
[2]);
1493 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1494 struct radv_image
*image
,
1495 const VkImageSubresourceRange
*range
, bool value
);
1497 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1498 struct radv_image
*image
,
1499 const VkImageSubresourceRange
*range
, bool value
);
1501 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1502 struct radeon_winsys_bo
*bo
,
1503 uint64_t offset
, uint64_t size
, uint32_t value
);
1504 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1505 bool radv_get_memory_fd(struct radv_device
*device
,
1506 struct radv_device_memory
*memory
,
1508 void radv_free_memory(struct radv_device
*device
,
1509 const VkAllocationCallbacks
* pAllocator
,
1510 struct radv_device_memory
*mem
);
1513 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1514 unsigned sh_offset
, unsigned pointer_count
,
1515 bool use_32bit_pointers
)
1517 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1518 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1522 radv_emit_shader_pointer_body(struct radv_device
*device
,
1523 struct radeon_cmdbuf
*cs
,
1524 uint64_t va
, bool use_32bit_pointers
)
1526 radeon_emit(cs
, va
);
1528 if (use_32bit_pointers
) {
1530 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1532 radeon_emit(cs
, va
>> 32);
1537 radv_emit_shader_pointer(struct radv_device
*device
,
1538 struct radeon_cmdbuf
*cs
,
1539 uint32_t sh_offset
, uint64_t va
, bool global
)
1541 bool use_32bit_pointers
= !global
;
1543 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1544 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1547 static inline struct radv_descriptor_state
*
1548 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1549 VkPipelineBindPoint bind_point
)
1551 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1552 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1553 return &cmd_buffer
->descriptors
[bind_point
];
1557 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1559 * Limitations: Can't call normal dispatch functions without binding or rebinding
1560 * the compute pipeline.
1562 void radv_unaligned_dispatch(
1563 struct radv_cmd_buffer
*cmd_buffer
,
1569 struct vk_object_base base
;
1570 struct radeon_winsys_bo
*bo
;
1574 struct radv_shader_module
;
1576 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1577 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1578 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1579 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1580 #define RADV_HASH_SHADER_LLVM (1 << 4)
1583 radv_hash_shaders(unsigned char *hash
,
1584 const VkPipelineShaderStageCreateInfo
**stages
,
1585 const struct radv_pipeline_layout
*layout
,
1586 const struct radv_pipeline_key
*key
,
1589 static inline gl_shader_stage
1590 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1592 assert(__builtin_popcount(vk_stage
) == 1);
1593 return ffs(vk_stage
) - 1;
1596 static inline VkShaderStageFlagBits
1597 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1599 return (1 << mesa_stage
);
1602 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1604 #define radv_foreach_stage(stage, stage_bits) \
1605 for (gl_shader_stage stage, \
1606 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1607 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1608 __tmp &= ~(1 << (stage)))
1610 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1611 unsigned radv_format_meta_fs_key(VkFormat format
);
1613 struct radv_multisample_state
{
1615 uint32_t pa_sc_line_cntl
;
1616 uint32_t pa_sc_mode_cntl_0
;
1617 uint32_t pa_sc_mode_cntl_1
;
1618 uint32_t pa_sc_aa_config
;
1619 uint32_t pa_sc_aa_mask
[2];
1620 unsigned num_samples
;
1623 struct radv_prim_vertex_count
{
1628 struct radv_vertex_elements_info
{
1629 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1632 struct radv_ia_multi_vgt_param_helpers
{
1634 bool partial_es_wave
;
1635 uint8_t primgroup_size
;
1636 bool ia_switch_on_eoi
;
1637 bool partial_vs_wave
;
1640 struct radv_binning_state
{
1641 uint32_t pa_sc_binner_cntl_0
;
1642 uint32_t db_dfsm_control
;
1645 #define SI_GS_PER_ES 128
1647 struct radv_pipeline
{
1648 struct vk_object_base base
;
1649 struct radv_device
* device
;
1650 struct radv_dynamic_state dynamic_state
;
1652 struct radv_pipeline_layout
* layout
;
1654 bool need_indirect_descriptor_sets
;
1655 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1656 struct radv_shader_variant
*gs_copy_shader
;
1657 VkShaderStageFlags active_stages
;
1659 struct radeon_cmdbuf cs
;
1660 uint32_t ctx_cs_hash
;
1661 struct radeon_cmdbuf ctx_cs
;
1663 struct radv_vertex_elements_info vertex_elements
;
1665 uint32_t binding_stride
[MAX_VBS
];
1666 uint8_t num_vertex_bindings
;
1668 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1671 struct radv_multisample_state ms
;
1672 struct radv_binning_state binning
;
1673 uint32_t spi_baryc_cntl
;
1674 bool prim_restart_enable
;
1675 unsigned esgs_ring_size
;
1676 unsigned gsvs_ring_size
;
1677 uint32_t vtx_base_sgpr
;
1678 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1679 uint8_t vtx_emit_num
;
1680 bool can_use_guardband
;
1681 uint32_t needed_dynamic_state
;
1682 bool disable_out_of_order_rast_for_occlusion
;
1683 unsigned tess_patch_control_points
;
1684 unsigned pa_su_sc_mode_cntl
;
1685 unsigned db_depth_control
;
1686 bool uses_dynamic_stride
;
1688 /* Used for rbplus */
1689 uint32_t col_format
;
1690 uint32_t cb_target_mask
;
1696 unsigned scratch_bytes_per_wave
;
1698 /* Not NULL if graphics pipeline uses streamout. */
1699 struct radv_shader_variant
*streamout_shader
;
1702 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1704 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1707 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1709 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1712 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1714 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1716 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1718 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1719 gl_shader_stage stage
,
1722 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1723 gl_shader_stage stage
);
1725 struct radv_graphics_pipeline_create_info
{
1727 bool db_depth_clear
;
1728 bool db_stencil_clear
;
1729 bool db_depth_disable_expclear
;
1730 bool db_stencil_disable_expclear
;
1731 bool depth_compress_disable
;
1732 bool stencil_compress_disable
;
1733 bool resummarize_enable
;
1734 uint32_t custom_blend_mode
;
1738 radv_graphics_pipeline_create(VkDevice device
,
1739 VkPipelineCache cache
,
1740 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1741 const struct radv_graphics_pipeline_create_info
*extra
,
1742 const VkAllocationCallbacks
*alloc
,
1743 VkPipeline
*pPipeline
);
1745 struct radv_binning_settings
{
1746 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1747 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1748 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1751 struct radv_binning_settings
1752 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1754 struct vk_format_description
;
1755 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1756 int first_non_void
);
1757 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1758 int first_non_void
);
1759 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1760 uint32_t radv_translate_colorformat(VkFormat format
);
1761 uint32_t radv_translate_color_numformat(VkFormat format
,
1762 const struct vk_format_description
*desc
,
1763 int first_non_void
);
1764 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1765 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1766 uint32_t radv_translate_dbformat(VkFormat format
);
1767 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1768 const struct vk_format_description
*desc
,
1769 int first_non_void
);
1770 uint32_t radv_translate_tex_numformat(VkFormat format
,
1771 const struct vk_format_description
*desc
,
1772 int first_non_void
);
1773 bool radv_format_pack_clear_color(VkFormat format
,
1774 uint32_t clear_vals
[2],
1775 VkClearColorValue
*value
);
1776 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1777 bool radv_dcc_formats_compatible(VkFormat format1
,
1779 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1781 struct radv_image_plane
{
1783 struct radeon_surf surface
;
1788 struct vk_object_base base
;
1790 /* The original VkFormat provided by the client. This may not match any
1791 * of the actual surface formats.
1794 VkImageAspectFlags aspects
;
1795 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1796 struct ac_surf_info info
;
1797 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1798 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1803 unsigned queue_family_mask
;
1807 /* Set when bound */
1808 struct radeon_winsys_bo
*bo
;
1809 VkDeviceSize offset
;
1810 bool tc_compatible_htile
;
1811 bool tc_compatible_cmask
;
1813 uint64_t clear_value_offset
;
1814 uint64_t fce_pred_offset
;
1815 uint64_t dcc_pred_offset
;
1818 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1819 * stored at this offset is UINT_MAX, the driver will emit
1820 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1821 * SET_CONTEXT_REG packet.
1823 uint64_t tc_compat_zrange_offset
;
1825 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1826 VkDeviceMemory owned_memory
;
1828 unsigned plane_count
;
1829 struct radv_image_plane planes
[0];
1832 /* Whether the image has a htile that is known consistent with the contents of
1833 * the image and is allowed to be in compressed form.
1835 * If this is false reads that don't use the htile should be able to return
1838 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1839 VkImageLayout layout
,
1840 bool in_render_loop
,
1841 unsigned queue_mask
);
1843 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1844 VkImageLayout layout
,
1845 bool in_render_loop
,
1846 unsigned queue_mask
);
1848 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1849 const struct radv_image
*image
,
1850 VkImageLayout layout
,
1851 bool in_render_loop
,
1852 unsigned queue_mask
);
1855 * Return whether the image has CMASK metadata for color surfaces.
1858 radv_image_has_cmask(const struct radv_image
*image
)
1860 return image
->planes
[0].surface
.cmask_offset
;
1864 * Return whether the image has FMASK metadata for color surfaces.
1867 radv_image_has_fmask(const struct radv_image
*image
)
1869 return image
->planes
[0].surface
.fmask_offset
;
1873 * Return whether the image has DCC metadata for color surfaces.
1876 radv_image_has_dcc(const struct radv_image
*image
)
1878 return image
->planes
[0].surface
.dcc_size
;
1882 * Return whether the image is TC-compatible CMASK.
1885 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1887 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1891 * Return whether DCC metadata is enabled for a level.
1894 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1896 return radv_image_has_dcc(image
) &&
1897 level
< image
->planes
[0].surface
.num_dcc_levels
;
1901 * Return whether the image has CB metadata.
1904 radv_image_has_CB_metadata(const struct radv_image
*image
)
1906 return radv_image_has_cmask(image
) ||
1907 radv_image_has_fmask(image
) ||
1908 radv_image_has_dcc(image
);
1912 * Return whether the image has HTILE metadata for depth surfaces.
1915 radv_image_has_htile(const struct radv_image
*image
)
1917 return image
->planes
[0].surface
.htile_size
;
1921 * Return whether HTILE metadata is enabled for a level.
1924 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1926 return radv_image_has_htile(image
) && level
== 0;
1930 * Return whether the image is TC-compatible HTILE.
1933 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1935 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1938 static inline uint64_t
1939 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1940 uint32_t base_level
)
1942 uint64_t va
= radv_buffer_get_va(image
->bo
);
1943 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1947 static inline uint64_t
1948 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1949 uint32_t base_level
)
1951 uint64_t va
= radv_buffer_get_va(image
->bo
);
1952 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1956 static inline uint64_t
1957 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1958 uint32_t base_level
)
1960 uint64_t va
= radv_buffer_get_va(image
->bo
);
1961 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1965 static inline uint64_t
1966 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1967 uint32_t base_level
)
1969 uint64_t va
= radv_buffer_get_va(image
->bo
);
1970 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1974 static inline uint64_t
1975 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1976 uint32_t base_level
)
1978 uint64_t va
= radv_buffer_get_va(image
->bo
);
1979 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1983 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1985 static inline uint32_t
1986 radv_get_layerCount(const struct radv_image
*image
,
1987 const VkImageSubresourceRange
*range
)
1989 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1990 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1993 static inline uint32_t
1994 radv_get_levelCount(const struct radv_image
*image
,
1995 const VkImageSubresourceRange
*range
)
1997 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1998 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
2001 struct radeon_bo_metadata
;
2003 radv_init_metadata(struct radv_device
*device
,
2004 struct radv_image
*image
,
2005 struct radeon_bo_metadata
*metadata
);
2008 radv_image_override_offset_stride(struct radv_device
*device
,
2009 struct radv_image
*image
,
2010 uint64_t offset
, uint32_t stride
);
2012 union radv_descriptor
{
2014 uint32_t plane0_descriptor
[8];
2015 uint32_t fmask_descriptor
[8];
2018 uint32_t plane_descriptors
[3][8];
2022 struct radv_image_view
{
2023 struct vk_object_base base
;
2024 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
2025 struct radeon_winsys_bo
*bo
;
2027 VkImageViewType type
;
2028 VkImageAspectFlags aspect_mask
;
2031 bool multiple_planes
;
2032 uint32_t base_layer
;
2033 uint32_t layer_count
;
2035 uint32_t level_count
;
2036 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2038 union radv_descriptor descriptor
;
2040 /* Descriptor for use as a storage image as opposed to a sampled image.
2041 * This has a few differences for cube maps (e.g. type).
2043 union radv_descriptor storage_descriptor
;
2046 struct radv_image_create_info
{
2047 const VkImageCreateInfo
*vk_info
;
2049 bool no_metadata_planes
;
2050 const struct radeon_bo_metadata
*bo_metadata
;
2054 radv_image_create_layout(struct radv_device
*device
,
2055 struct radv_image_create_info create_info
,
2056 struct radv_image
*image
);
2058 VkResult
radv_image_create(VkDevice _device
,
2059 const struct radv_image_create_info
*info
,
2060 const VkAllocationCallbacks
* alloc
,
2063 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2066 radv_image_from_gralloc(VkDevice device_h
,
2067 const VkImageCreateInfo
*base_info
,
2068 const VkNativeBufferANDROID
*gralloc_info
,
2069 const VkAllocationCallbacks
*alloc
,
2070 VkImage
*out_image_h
);
2072 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2073 const VkImageUsageFlags vk_usage
);
2075 radv_import_ahb_memory(struct radv_device
*device
,
2076 struct radv_device_memory
*mem
,
2078 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2080 radv_create_ahb_memory(struct radv_device
*device
,
2081 struct radv_device_memory
*mem
,
2083 const VkMemoryAllocateInfo
*pAllocateInfo
);
2086 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2088 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2090 struct radv_image_view_extra_create_info
{
2091 bool disable_compression
;
2094 void radv_image_view_init(struct radv_image_view
*view
,
2095 struct radv_device
*device
,
2096 const VkImageViewCreateInfo
*pCreateInfo
,
2097 const struct radv_image_view_extra_create_info
* extra_create_info
);
2099 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2101 struct radv_sampler_ycbcr_conversion
{
2102 struct vk_object_base base
;
2104 VkSamplerYcbcrModelConversion ycbcr_model
;
2105 VkSamplerYcbcrRange ycbcr_range
;
2106 VkComponentMapping components
;
2107 VkChromaLocation chroma_offsets
[2];
2108 VkFilter chroma_filter
;
2111 struct radv_buffer_view
{
2112 struct vk_object_base base
;
2113 struct radeon_winsys_bo
*bo
;
2115 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2118 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2119 struct radv_device
*device
,
2120 const VkBufferViewCreateInfo
* pCreateInfo
);
2122 static inline struct VkExtent3D
2123 radv_sanitize_image_extent(const VkImageType imageType
,
2124 const struct VkExtent3D imageExtent
)
2126 switch (imageType
) {
2127 case VK_IMAGE_TYPE_1D
:
2128 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2129 case VK_IMAGE_TYPE_2D
:
2130 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2131 case VK_IMAGE_TYPE_3D
:
2134 unreachable("invalid image type");
2138 static inline struct VkOffset3D
2139 radv_sanitize_image_offset(const VkImageType imageType
,
2140 const struct VkOffset3D imageOffset
)
2142 switch (imageType
) {
2143 case VK_IMAGE_TYPE_1D
:
2144 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2145 case VK_IMAGE_TYPE_2D
:
2146 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2147 case VK_IMAGE_TYPE_3D
:
2150 unreachable("invalid image type");
2155 radv_image_extent_compare(const struct radv_image
*image
,
2156 const VkExtent3D
*extent
)
2158 if (extent
->width
!= image
->info
.width
||
2159 extent
->height
!= image
->info
.height
||
2160 extent
->depth
!= image
->info
.depth
)
2165 struct radv_sampler
{
2166 struct vk_object_base base
;
2168 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2169 uint32_t border_color_slot
;
2172 struct radv_framebuffer
{
2173 struct vk_object_base base
;
2178 uint32_t attachment_count
;
2179 struct radv_image_view
*attachments
[0];
2182 struct radv_subpass_barrier
{
2183 VkPipelineStageFlags src_stage_mask
;
2184 VkAccessFlags src_access_mask
;
2185 VkAccessFlags dst_access_mask
;
2188 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2189 const struct radv_subpass_barrier
*barrier
);
2191 struct radv_subpass_attachment
{
2192 uint32_t attachment
;
2193 VkImageLayout layout
;
2194 VkImageLayout stencil_layout
;
2195 bool in_render_loop
;
2198 struct radv_subpass
{
2199 uint32_t attachment_count
;
2200 struct radv_subpass_attachment
* attachments
;
2202 uint32_t input_count
;
2203 uint32_t color_count
;
2204 struct radv_subpass_attachment
* input_attachments
;
2205 struct radv_subpass_attachment
* color_attachments
;
2206 struct radv_subpass_attachment
* resolve_attachments
;
2207 struct radv_subpass_attachment
* depth_stencil_attachment
;
2208 struct radv_subpass_attachment
* ds_resolve_attachment
;
2209 VkResolveModeFlagBits depth_resolve_mode
;
2210 VkResolveModeFlagBits stencil_resolve_mode
;
2212 /** Subpass has at least one color resolve attachment */
2213 bool has_color_resolve
;
2215 /** Subpass has at least one color attachment */
2218 struct radv_subpass_barrier start_barrier
;
2222 VkSampleCountFlagBits color_sample_count
;
2223 VkSampleCountFlagBits depth_sample_count
;
2224 VkSampleCountFlagBits max_sample_count
;
2228 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2230 struct radv_render_pass_attachment
{
2233 VkAttachmentLoadOp load_op
;
2234 VkAttachmentLoadOp stencil_load_op
;
2235 VkImageLayout initial_layout
;
2236 VkImageLayout final_layout
;
2237 VkImageLayout stencil_initial_layout
;
2238 VkImageLayout stencil_final_layout
;
2240 /* The subpass id in which the attachment will be used first/last. */
2241 uint32_t first_subpass_idx
;
2242 uint32_t last_subpass_idx
;
2245 struct radv_render_pass
{
2246 struct vk_object_base base
;
2247 uint32_t attachment_count
;
2248 uint32_t subpass_count
;
2249 struct radv_subpass_attachment
* subpass_attachments
;
2250 struct radv_render_pass_attachment
* attachments
;
2251 struct radv_subpass_barrier end_barrier
;
2252 struct radv_subpass subpasses
[0];
2255 VkResult
radv_device_init_meta(struct radv_device
*device
);
2256 void radv_device_finish_meta(struct radv_device
*device
);
2258 struct radv_query_pool
{
2259 struct vk_object_base base
;
2260 struct radeon_winsys_bo
*bo
;
2262 uint32_t availability_offset
;
2266 uint32_t pipeline_stats_mask
;
2270 RADV_SEMAPHORE_NONE
,
2271 RADV_SEMAPHORE_WINSYS
,
2272 RADV_SEMAPHORE_SYNCOBJ
,
2273 RADV_SEMAPHORE_TIMELINE
,
2274 } radv_semaphore_kind
;
2276 struct radv_deferred_queue_submission
;
2278 struct radv_timeline_waiter
{
2279 struct list_head list
;
2280 struct radv_deferred_queue_submission
*submission
;
2284 struct radv_timeline_point
{
2285 struct list_head list
;
2290 /* Separate from the list to accomodate CPU wait being async, as well
2291 * as prevent point deletion during submission. */
2292 unsigned wait_count
;
2295 struct radv_timeline
{
2296 /* Using a pthread mutex to be compatible with condition variables. */
2297 pthread_mutex_t mutex
;
2299 uint64_t highest_signaled
;
2300 uint64_t highest_submitted
;
2302 struct list_head points
;
2304 /* Keep free points on hand so we do not have to recreate syncobjs all
2306 struct list_head free_points
;
2308 /* Submissions that are deferred waiting for a specific value to be
2310 struct list_head waiters
;
2313 struct radv_semaphore_part
{
2314 radv_semaphore_kind kind
;
2317 struct radeon_winsys_sem
*ws_sem
;
2318 struct radv_timeline timeline
;
2322 struct radv_semaphore
{
2323 struct vk_object_base base
;
2324 struct radv_semaphore_part permanent
;
2325 struct radv_semaphore_part temporary
;
2328 bool radv_queue_internal_submit(struct radv_queue
*queue
,
2329 struct radeon_cmdbuf
*cs
);
2331 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2332 VkPipelineBindPoint bind_point
,
2333 struct radv_descriptor_set
*set
,
2337 radv_update_descriptor_sets(struct radv_device
*device
,
2338 struct radv_cmd_buffer
*cmd_buffer
,
2339 VkDescriptorSet overrideSet
,
2340 uint32_t descriptorWriteCount
,
2341 const VkWriteDescriptorSet
*pDescriptorWrites
,
2342 uint32_t descriptorCopyCount
,
2343 const VkCopyDescriptorSet
*pDescriptorCopies
);
2346 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2347 struct radv_cmd_buffer
*cmd_buffer
,
2348 struct radv_descriptor_set
*set
,
2349 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2352 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2353 VkPipelineBindPoint pipelineBindPoint
,
2354 VkPipelineLayout _layout
,
2356 uint32_t descriptorWriteCount
,
2357 const VkWriteDescriptorSet
*pDescriptorWrites
);
2359 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2360 struct radv_image
*image
,
2361 const VkImageSubresourceRange
*range
, uint32_t value
);
2363 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2364 struct radv_image
*image
,
2365 const VkImageSubresourceRange
*range
);
2374 struct radv_fence_part
{
2375 radv_fence_kind kind
;
2378 /* AMDGPU winsys fence. */
2379 struct radeon_winsys_fence
*fence
;
2381 /* DRM syncobj handle for syncobj-based fences. */
2385 struct wsi_fence
*fence_wsi
;
2390 struct vk_object_base base
;
2391 struct radv_fence_part permanent
;
2392 struct radv_fence_part temporary
;
2395 /* radv_nir_to_llvm.c */
2396 struct radv_shader_args
;
2398 void llvm_compile_shader(struct radv_device
*device
,
2399 unsigned shader_count
,
2400 struct nir_shader
*const *shaders
,
2401 struct radv_shader_binary
**binary
,
2402 struct radv_shader_args
*args
);
2404 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2405 gl_shader_stage stage
,
2406 const struct nir_shader
*nir
);
2408 /* radv_shader_info.h */
2409 struct radv_shader_info
;
2410 struct radv_shader_variant_key
;
2412 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2413 const struct radv_pipeline_layout
*layout
,
2414 const struct radv_shader_variant_key
*key
,
2415 struct radv_shader_info
*info
,
2418 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2421 struct radv_thread_trace_info
{
2422 uint32_t cur_offset
;
2423 uint32_t trace_status
;
2425 uint32_t gfx9_write_counter
;
2426 uint32_t gfx10_dropped_cntr
;
2430 struct radv_thread_trace_se
{
2431 struct radv_thread_trace_info info
;
2433 uint32_t shader_engine
;
2434 uint32_t compute_unit
;
2437 struct radv_thread_trace
{
2438 uint32_t num_traces
;
2439 struct radv_thread_trace_se traces
[4];
2442 bool radv_thread_trace_init(struct radv_device
*device
);
2443 void radv_thread_trace_finish(struct radv_device
*device
);
2444 bool radv_begin_thread_trace(struct radv_queue
*queue
);
2445 bool radv_end_thread_trace(struct radv_queue
*queue
);
2446 bool radv_get_thread_trace(struct radv_queue
*queue
,
2447 struct radv_thread_trace
*thread_trace
);
2448 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf
*cs
,
2449 const void *data
, uint32_t num_dwords
);
2452 int radv_dump_thread_trace(struct radv_device
*device
,
2453 const struct radv_thread_trace
*trace
);
2455 /* radv_sqtt_layer_.c */
2456 struct radv_barrier_data
{
2459 uint16_t depth_stencil_expand
: 1;
2460 uint16_t htile_hiz_range_expand
: 1;
2461 uint16_t depth_stencil_resummarize
: 1;
2462 uint16_t dcc_decompress
: 1;
2463 uint16_t fmask_decompress
: 1;
2464 uint16_t fast_clear_eliminate
: 1;
2465 uint16_t fmask_color_expand
: 1;
2466 uint16_t init_mask_ram
: 1;
2467 uint16_t reserved
: 8;
2470 } layout_transitions
;
2474 * Value for the reason field of an RGP barrier start marker originating from
2475 * the Vulkan client (does not include PAL-defined values). (Table 15)
2477 enum rgp_barrier_reason
{
2478 RGP_BARRIER_UNKNOWN_REASON
= 0xFFFFFFFF,
2480 /* External app-generated barrier reasons, i.e. API synchronization
2481 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2483 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
= 0x00000001,
2484 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
= 0x00000002,
2485 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
= 0x00000003,
2487 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2488 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2490 RGP_BARRIER_INTERNAL_BASE
= 0xC0000000,
2491 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 0,
2492 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 1,
2493 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL
= RGP_BARRIER_INTERNAL_BASE
+ 2,
2494 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 3
2497 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2498 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2499 void radv_describe_draw(struct radv_cmd_buffer
*cmd_buffer
);
2500 void radv_describe_dispatch(struct radv_cmd_buffer
*cmd_buffer
, int x
, int y
, int z
);
2501 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
,
2502 VkImageAspectFlagBits aspects
);
2503 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
);
2504 void radv_describe_barrier_start(struct radv_cmd_buffer
*cmd_buffer
,
2505 enum rgp_barrier_reason reason
);
2506 void radv_describe_barrier_end(struct radv_cmd_buffer
*cmd_buffer
);
2507 void radv_describe_layout_transition(struct radv_cmd_buffer
*cmd_buffer
,
2508 const struct radv_barrier_data
*barrier
);
2510 struct radeon_winsys_sem
;
2512 uint64_t radv_get_current_time(void);
2514 static inline uint32_t
2515 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2518 case 0: /* GL_POINTS */
2520 case 1: /* GL_LINES */
2521 case 3: /* GL_LINE_STRIP */
2523 case 4: /* GL_TRIANGLES */
2524 case 5: /* GL_TRIANGLE_STRIP */
2526 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2528 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2530 case 7: /* GL_QUADS */
2531 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2538 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
2539 const VkRenderPassBeginInfo
*pRenderPassBegin
);
2540 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
);
2542 static inline uint32_t si_translate_prim(unsigned topology
)
2545 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
2546 return V_008958_DI_PT_POINTLIST
;
2547 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
2548 return V_008958_DI_PT_LINELIST
;
2549 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
2550 return V_008958_DI_PT_LINESTRIP
;
2551 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
2552 return V_008958_DI_PT_TRILIST
;
2553 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
2554 return V_008958_DI_PT_TRISTRIP
;
2555 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
2556 return V_008958_DI_PT_TRIFAN
;
2557 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
2558 return V_008958_DI_PT_LINELIST_ADJ
;
2559 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
2560 return V_008958_DI_PT_LINESTRIP_ADJ
;
2561 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
2562 return V_008958_DI_PT_TRILIST_ADJ
;
2563 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
2564 return V_008958_DI_PT_TRISTRIP_ADJ
;
2565 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
2566 return V_008958_DI_PT_PATCH
;
2573 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op
)
2576 case VK_STENCIL_OP_KEEP
:
2577 return V_02842C_STENCIL_KEEP
;
2578 case VK_STENCIL_OP_ZERO
:
2579 return V_02842C_STENCIL_ZERO
;
2580 case VK_STENCIL_OP_REPLACE
:
2581 return V_02842C_STENCIL_REPLACE_TEST
;
2582 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
2583 return V_02842C_STENCIL_ADD_CLAMP
;
2584 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
2585 return V_02842C_STENCIL_SUB_CLAMP
;
2586 case VK_STENCIL_OP_INVERT
:
2587 return V_02842C_STENCIL_INVERT
;
2588 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
2589 return V_02842C_STENCIL_ADD_WRAP
;
2590 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
2591 return V_02842C_STENCIL_SUB_WRAP
;
2597 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2599 static inline struct __radv_type * \
2600 __radv_type ## _from_handle(__VkType _handle) \
2602 return (struct __radv_type *) _handle; \
2605 static inline __VkType \
2606 __radv_type ## _to_handle(struct __radv_type *_obj) \
2608 return (__VkType) _obj; \
2611 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2613 static inline struct __radv_type * \
2614 __radv_type ## _from_handle(__VkType _handle) \
2616 return (struct __radv_type *)(uintptr_t) _handle; \
2619 static inline __VkType \
2620 __radv_type ## _to_handle(struct __radv_type *_obj) \
2622 return (__VkType)(uintptr_t) _obj; \
2625 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2626 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2628 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2629 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2630 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2631 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2632 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2634 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2635 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2636 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2637 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2638 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2639 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2640 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2641 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2642 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2643 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2644 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2645 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2646 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2657 #endif /* RADV_PRIVATE_H */