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radv: track and report if a logical device is lost
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorv(struct radv_instance *instance, const void *object,
198 VkDebugReportObjectTypeEXT type, VkResult error,
199 const char *file, int line, const char *format,
200 va_list args);
201
202 VkResult __vk_errorf(struct radv_instance *instance, const void *object,
203 VkDebugReportObjectTypeEXT type, VkResult error,
204 const char *file, int line, const char *format, ...)
205 radv_printflike(7, 8);
206
207 #define vk_error(instance, error) \
208 __vk_errorf(instance, NULL, \
209 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
210 error, __FILE__, __LINE__, NULL);
211 #define vk_errorf(instance, error, format, ...) \
212 __vk_errorf(instance, NULL, \
213 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
214 error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220 void radv_logi(const char *format, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x) do {} while(0)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 int radv_get_instance_entrypoint_index(const char *name);
258 int radv_get_device_entrypoint_index(const char *name);
259 int radv_get_physical_device_entrypoint_index(const char *name);
260
261 const char *radv_get_instance_entry_name(int index);
262 const char *radv_get_physical_device_entry_name(int index);
263 const char *radv_get_device_entry_name(int index);
264
265 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
266 const struct radv_instance_extension_table *instance);
267 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
268 const struct radv_instance_extension_table *instance);
269 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
272
273 void *radv_lookup_entrypoint(const char *name);
274
275 struct radv_physical_device {
276 VK_LOADER_DATA _loader_data;
277
278 /* Link in radv_instance::physical_devices */
279 struct list_head link;
280
281 struct radv_instance * instance;
282
283 struct radeon_winsys *ws;
284 struct radeon_info rad_info;
285 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
286 uint8_t driver_uuid[VK_UUID_SIZE];
287 uint8_t device_uuid[VK_UUID_SIZE];
288 uint8_t cache_uuid[VK_UUID_SIZE];
289
290 int local_fd;
291 int master_fd;
292 struct wsi_device wsi_device;
293
294 bool out_of_order_rast_allowed;
295
296 /* Whether DCC should be enabled for MSAA textures. */
297 bool dcc_msaa_allowed;
298
299 /* Whether to enable NGG. */
300 bool use_ngg;
301
302 /* Whether to enable NGG GS. */
303 bool use_ngg_gs;
304
305 /* Whether to enable NGG streamout. */
306 bool use_ngg_streamout;
307
308 /* Number of threads per wave. */
309 uint8_t ps_wave_size;
310 uint8_t cs_wave_size;
311 uint8_t ge_wave_size;
312
313 /* Whether to use the LLVM compiler backend */
314 bool use_llvm;
315
316 /* This is the drivers on-disk cache used as a fallback as opposed to
317 * the pipeline cache defined by apps.
318 */
319 struct disk_cache * disk_cache;
320
321 VkPhysicalDeviceMemoryProperties memory_properties;
322 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
323 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
324
325 drmPciBusInfo bus_info;
326
327 struct radv_device_extension_table supported_extensions;
328 };
329
330 struct radv_instance {
331 struct vk_object_base base;
332
333 VkAllocationCallbacks alloc;
334
335 uint32_t apiVersion;
336
337 char * applicationName;
338 uint32_t applicationVersion;
339 char * engineName;
340 uint32_t engineVersion;
341
342 uint64_t debug_flags;
343 uint64_t perftest_flags;
344
345 struct vk_debug_report_instance debug_report_callbacks;
346
347 struct radv_instance_extension_table enabled_extensions;
348 struct radv_instance_dispatch_table dispatch;
349 struct radv_physical_device_dispatch_table physical_device_dispatch;
350 struct radv_device_dispatch_table device_dispatch;
351
352 bool physical_devices_enumerated;
353 struct list_head physical_devices;
354
355 struct driOptionCache dri_options;
356 struct driOptionCache available_dri_options;
357
358 /**
359 * Workarounds for game bugs.
360 */
361 bool enable_mrt_output_nan_fixup;
362 };
363
364 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
365 void radv_finish_wsi(struct radv_physical_device *physical_device);
366
367 bool radv_instance_extension_supported(const char *name);
368 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
369 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
370 const char *name);
371
372 struct cache_entry;
373
374 struct radv_pipeline_cache {
375 struct vk_object_base base;
376 struct radv_device * device;
377 pthread_mutex_t mutex;
378 VkPipelineCacheCreateFlags flags;
379
380 uint32_t total_size;
381 uint32_t table_size;
382 uint32_t kernel_count;
383 struct cache_entry ** hash_table;
384 bool modified;
385
386 VkAllocationCallbacks alloc;
387 };
388
389 struct radv_pipeline_key {
390 uint32_t instance_rate_inputs;
391 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
392 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
393 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
394 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
395 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
396 uint64_t vertex_alpha_adjust;
397 uint32_t vertex_post_shuffle;
398 unsigned tess_input_vertices;
399 uint32_t col_format;
400 uint32_t is_int8;
401 uint32_t is_int10;
402 uint8_t log2_ps_iter_samples;
403 uint8_t num_samples;
404 bool is_dual_src;
405 uint32_t has_multiview_view_index : 1;
406 uint32_t optimisations_disabled : 1;
407 uint8_t topology;
408
409 /* Non-zero if a required subgroup size is specified via
410 * VK_EXT_subgroup_size_control.
411 */
412 uint8_t compute_subgroup_size;
413 };
414
415 struct radv_shader_binary;
416 struct radv_shader_variant;
417
418 void
419 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
420 struct radv_device *device);
421 void
422 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
423 bool
424 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
425 const void *data, size_t size);
426
427 bool
428 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
429 struct radv_pipeline_cache *cache,
430 const unsigned char *sha1,
431 struct radv_shader_variant **variants,
432 bool *found_in_application_cache);
433
434 void
435 radv_pipeline_cache_insert_shaders(struct radv_device *device,
436 struct radv_pipeline_cache *cache,
437 const unsigned char *sha1,
438 struct radv_shader_variant **variants,
439 struct radv_shader_binary *const *binaries);
440
441 enum radv_blit_ds_layout {
442 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
443 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
444 RADV_BLIT_DS_LAYOUT_COUNT,
445 };
446
447 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
448 {
449 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
450 }
451
452 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
453 {
454 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
455 }
456
457 enum radv_meta_dst_layout {
458 RADV_META_DST_LAYOUT_GENERAL,
459 RADV_META_DST_LAYOUT_OPTIMAL,
460 RADV_META_DST_LAYOUT_COUNT,
461 };
462
463 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
464 {
465 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
466 }
467
468 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
469 {
470 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
471 }
472
473 struct radv_meta_state {
474 VkAllocationCallbacks alloc;
475
476 struct radv_pipeline_cache cache;
477
478 /*
479 * For on-demand pipeline creation, makes sure that
480 * only one thread tries to build a pipeline at the same time.
481 */
482 mtx_t mtx;
483
484 /**
485 * Use array element `i` for images with `2^i` samples.
486 */
487 struct {
488 VkRenderPass render_pass[NUM_META_FS_KEYS];
489 VkPipeline color_pipelines[NUM_META_FS_KEYS];
490
491 VkRenderPass depthstencil_rp;
492 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
493 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
494 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
495
496 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
497 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
498 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
499 } clear[MAX_SAMPLES_LOG2];
500
501 VkPipelineLayout clear_color_p_layout;
502 VkPipelineLayout clear_depth_p_layout;
503 VkPipelineLayout clear_depth_unrestricted_p_layout;
504
505 /* Optimized compute fast HTILE clear for stencil or depth only. */
506 VkPipeline clear_htile_mask_pipeline;
507 VkPipelineLayout clear_htile_mask_p_layout;
508 VkDescriptorSetLayout clear_htile_mask_ds_layout;
509
510 struct {
511 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
512
513 /** Pipeline that blits from a 1D image. */
514 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
515
516 /** Pipeline that blits from a 2D image. */
517 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
518
519 /** Pipeline that blits from a 3D image. */
520 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
521
522 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
523 VkPipeline depth_only_1d_pipeline;
524 VkPipeline depth_only_2d_pipeline;
525 VkPipeline depth_only_3d_pipeline;
526
527 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
528 VkPipeline stencil_only_1d_pipeline;
529 VkPipeline stencil_only_2d_pipeline;
530 VkPipeline stencil_only_3d_pipeline;
531 VkPipelineLayout pipeline_layout;
532 VkDescriptorSetLayout ds_layout;
533 } blit;
534
535 struct {
536 VkPipelineLayout p_layouts[5];
537 VkDescriptorSetLayout ds_layouts[5];
538 VkPipeline pipelines[5][NUM_META_FS_KEYS];
539
540 VkPipeline depth_only_pipeline[5];
541
542 VkPipeline stencil_only_pipeline[5];
543 } blit2d[MAX_SAMPLES_LOG2];
544
545 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
546 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
547 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
548
549 struct {
550 VkPipelineLayout img_p_layout;
551 VkDescriptorSetLayout img_ds_layout;
552 VkPipeline pipeline;
553 VkPipeline pipeline_3d;
554 } itob;
555 struct {
556 VkPipelineLayout img_p_layout;
557 VkDescriptorSetLayout img_ds_layout;
558 VkPipeline pipeline;
559 VkPipeline pipeline_3d;
560 } btoi;
561 struct {
562 VkPipelineLayout img_p_layout;
563 VkDescriptorSetLayout img_ds_layout;
564 VkPipeline pipeline;
565 } btoi_r32g32b32;
566 struct {
567 VkPipelineLayout img_p_layout;
568 VkDescriptorSetLayout img_ds_layout;
569 VkPipeline pipeline;
570 VkPipeline pipeline_3d;
571 } itoi;
572 struct {
573 VkPipelineLayout img_p_layout;
574 VkDescriptorSetLayout img_ds_layout;
575 VkPipeline pipeline;
576 } itoi_r32g32b32;
577 struct {
578 VkPipelineLayout img_p_layout;
579 VkDescriptorSetLayout img_ds_layout;
580 VkPipeline pipeline;
581 VkPipeline pipeline_3d;
582 } cleari;
583 struct {
584 VkPipelineLayout img_p_layout;
585 VkDescriptorSetLayout img_ds_layout;
586 VkPipeline pipeline;
587 } cleari_r32g32b32;
588
589 struct {
590 VkPipelineLayout p_layout;
591 VkPipeline pipeline[NUM_META_FS_KEYS];
592 VkRenderPass pass[NUM_META_FS_KEYS];
593 } resolve;
594
595 struct {
596 VkDescriptorSetLayout ds_layout;
597 VkPipelineLayout p_layout;
598 struct {
599 VkPipeline pipeline;
600 VkPipeline i_pipeline;
601 VkPipeline srgb_pipeline;
602 } rc[MAX_SAMPLES_LOG2];
603
604 VkPipeline depth_zero_pipeline;
605 struct {
606 VkPipeline average_pipeline;
607 VkPipeline max_pipeline;
608 VkPipeline min_pipeline;
609 } depth[MAX_SAMPLES_LOG2];
610
611 VkPipeline stencil_zero_pipeline;
612 struct {
613 VkPipeline max_pipeline;
614 VkPipeline min_pipeline;
615 } stencil[MAX_SAMPLES_LOG2];
616 } resolve_compute;
617
618 struct {
619 VkDescriptorSetLayout ds_layout;
620 VkPipelineLayout p_layout;
621
622 struct {
623 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
624 VkPipeline pipeline[NUM_META_FS_KEYS];
625 } rc[MAX_SAMPLES_LOG2];
626
627 VkRenderPass depth_render_pass;
628 VkPipeline depth_zero_pipeline;
629 struct {
630 VkPipeline average_pipeline;
631 VkPipeline max_pipeline;
632 VkPipeline min_pipeline;
633 } depth[MAX_SAMPLES_LOG2];
634
635 VkRenderPass stencil_render_pass;
636 VkPipeline stencil_zero_pipeline;
637 struct {
638 VkPipeline max_pipeline;
639 VkPipeline min_pipeline;
640 } stencil[MAX_SAMPLES_LOG2];
641 } resolve_fragment;
642
643 struct {
644 VkPipelineLayout p_layout;
645 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
646 VkPipeline resummarize_pipeline;
647 VkRenderPass pass;
648 } depth_decomp[MAX_SAMPLES_LOG2];
649
650 struct {
651 VkPipelineLayout p_layout;
652 VkPipeline cmask_eliminate_pipeline;
653 VkPipeline fmask_decompress_pipeline;
654 VkPipeline dcc_decompress_pipeline;
655 VkRenderPass pass;
656
657 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
658 VkPipelineLayout dcc_decompress_compute_p_layout;
659 VkPipeline dcc_decompress_compute_pipeline;
660 } fast_clear_flush;
661
662 struct {
663 VkPipelineLayout fill_p_layout;
664 VkPipelineLayout copy_p_layout;
665 VkDescriptorSetLayout fill_ds_layout;
666 VkDescriptorSetLayout copy_ds_layout;
667 VkPipeline fill_pipeline;
668 VkPipeline copy_pipeline;
669 } buffer;
670
671 struct {
672 VkDescriptorSetLayout ds_layout;
673 VkPipelineLayout p_layout;
674 VkPipeline occlusion_query_pipeline;
675 VkPipeline pipeline_statistics_query_pipeline;
676 VkPipeline tfb_query_pipeline;
677 VkPipeline timestamp_query_pipeline;
678 } query;
679
680 struct {
681 VkDescriptorSetLayout ds_layout;
682 VkPipelineLayout p_layout;
683 VkPipeline pipeline[MAX_SAMPLES_LOG2];
684 } fmask_expand;
685 };
686
687 /* queue types */
688 #define RADV_QUEUE_GENERAL 0
689 #define RADV_QUEUE_COMPUTE 1
690 #define RADV_QUEUE_TRANSFER 2
691
692 #define RADV_MAX_QUEUE_FAMILIES 3
693
694 struct radv_deferred_queue_submission;
695
696 enum ring_type radv_queue_family_to_ring(int f);
697
698 struct radv_queue {
699 VK_LOADER_DATA _loader_data;
700 struct radv_device * device;
701 struct radeon_winsys_ctx *hw_ctx;
702 enum radeon_ctx_priority priority;
703 uint32_t queue_family_index;
704 int queue_idx;
705 VkDeviceQueueCreateFlags flags;
706
707 uint32_t scratch_size_per_wave;
708 uint32_t scratch_waves;
709 uint32_t compute_scratch_size_per_wave;
710 uint32_t compute_scratch_waves;
711 uint32_t esgs_ring_size;
712 uint32_t gsvs_ring_size;
713 bool has_tess_rings;
714 bool has_gds;
715 bool has_gds_oa;
716 bool has_sample_positions;
717
718 struct radeon_winsys_bo *scratch_bo;
719 struct radeon_winsys_bo *descriptor_bo;
720 struct radeon_winsys_bo *compute_scratch_bo;
721 struct radeon_winsys_bo *esgs_ring_bo;
722 struct radeon_winsys_bo *gsvs_ring_bo;
723 struct radeon_winsys_bo *tess_rings_bo;
724 struct radeon_winsys_bo *gds_bo;
725 struct radeon_winsys_bo *gds_oa_bo;
726 struct radeon_cmdbuf *initial_preamble_cs;
727 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
728 struct radeon_cmdbuf *continue_preamble_cs;
729
730 struct list_head pending_submissions;
731 pthread_mutex_t pending_mutex;
732
733 pthread_mutex_t thread_mutex;
734 pthread_cond_t thread_cond;
735 struct radv_deferred_queue_submission *thread_submission;
736 pthread_t submission_thread;
737 bool thread_exit;
738 bool thread_running;
739 };
740
741 struct radv_bo_list {
742 struct radv_winsys_bo_list list;
743 unsigned capacity;
744 pthread_mutex_t mutex;
745 };
746
747 VkResult radv_bo_list_add(struct radv_device *device,
748 struct radeon_winsys_bo *bo);
749 void radv_bo_list_remove(struct radv_device *device,
750 struct radeon_winsys_bo *bo);
751
752 #define RADV_BORDER_COLOR_COUNT 4096
753 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
754
755 struct radv_device_border_color_data {
756 bool used[RADV_BORDER_COLOR_COUNT];
757
758 struct radeon_winsys_bo *bo;
759 VkClearColorValue *colors_gpu_ptr;
760
761 /* Mutex is required to guarantee vkCreateSampler thread safety
762 * given that we are writing to a buffer and checking color occupation */
763 pthread_mutex_t mutex;
764 };
765
766 struct radv_device {
767 struct vk_device vk;
768
769 struct radv_instance * instance;
770 struct radeon_winsys *ws;
771
772 struct radv_meta_state meta_state;
773
774 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
775 int queue_count[RADV_MAX_QUEUE_FAMILIES];
776 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
777
778 bool always_use_syncobj;
779 bool pbb_allowed;
780 bool dfsm_allowed;
781 uint32_t tess_offchip_block_dw_size;
782 uint32_t scratch_waves;
783 uint32_t dispatch_initiator;
784
785 uint32_t gs_table_depth;
786
787 /* MSAA sample locations.
788 * The first index is the sample index.
789 * The second index is the coordinate: X, Y. */
790 float sample_locations_1x[1][2];
791 float sample_locations_2x[2][2];
792 float sample_locations_4x[4][2];
793 float sample_locations_8x[8][2];
794
795 /* GFX7 and later */
796 uint32_t gfx_init_size_dw;
797 struct radeon_winsys_bo *gfx_init;
798
799 struct radeon_winsys_bo *trace_bo;
800 uint32_t *trace_id_ptr;
801
802 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
803 bool keep_shader_info;
804
805 struct radv_physical_device *physical_device;
806
807 /* Backup in-memory cache to be used if the app doesn't provide one */
808 struct radv_pipeline_cache * mem_cache;
809
810 /*
811 * use different counters so MSAA MRTs get consecutive surface indices,
812 * even if MASK is allocated in between.
813 */
814 uint32_t image_mrt_offset_counter;
815 uint32_t fmask_mrt_offset_counter;
816 struct list_head shader_slabs;
817 mtx_t shader_slab_mutex;
818
819 /* For detecting VM faults reported by dmesg. */
820 uint64_t dmesg_timestamp;
821
822 struct radv_device_extension_table enabled_extensions;
823 struct radv_device_dispatch_table dispatch;
824
825 /* Whether the app has enabled the robustBufferAccess feature. */
826 bool robust_buffer_access;
827
828 /* Whether the driver uses a global BO list. */
829 bool use_global_bo_list;
830
831 struct radv_bo_list bo_list;
832
833 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
834 int force_aniso;
835
836 struct radv_device_border_color_data border_color_data;
837
838 /* Condition variable for legacy timelines, to notify waiters when a
839 * new point gets submitted. */
840 pthread_cond_t timeline_cond;
841
842 /* Thread trace. */
843 struct radeon_cmdbuf *thread_trace_start_cs[2];
844 struct radeon_cmdbuf *thread_trace_stop_cs[2];
845 struct radeon_winsys_bo *thread_trace_bo;
846 void *thread_trace_ptr;
847 uint32_t thread_trace_buffer_size;
848 int thread_trace_start_frame;
849
850 /* Overallocation. */
851 bool overallocation_disallowed;
852 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
853 mtx_t overallocation_mutex;
854
855 /* Track the number of device loss occurs. */
856 int lost;
857 };
858
859 VkResult _radv_device_set_lost(struct radv_device *device,
860 const char *file, int line,
861 const char *msg, ...)
862 radv_printflike(4, 5);
863
864 #define radv_device_set_lost(dev, ...) \
865 _radv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
866
867 static inline bool
868 radv_device_is_lost(const struct radv_device *device)
869 {
870 return unlikely(p_atomic_read(&device->lost));
871 }
872
873 struct radv_device_memory {
874 struct vk_object_base base;
875 struct radeon_winsys_bo *bo;
876 /* for dedicated allocations */
877 struct radv_image *image;
878 struct radv_buffer *buffer;
879 uint32_t heap_index;
880 uint64_t alloc_size;
881 void * map;
882 void * user_ptr;
883
884 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
885 struct AHardwareBuffer * android_hardware_buffer;
886 #endif
887 };
888
889
890 struct radv_descriptor_range {
891 uint64_t va;
892 uint32_t size;
893 };
894
895 struct radv_descriptor_set {
896 struct vk_object_base base;
897 const struct radv_descriptor_set_layout *layout;
898 uint32_t size;
899 uint32_t buffer_count;
900
901 struct radeon_winsys_bo *bo;
902 uint64_t va;
903 uint32_t *mapped_ptr;
904 struct radv_descriptor_range *dynamic_descriptors;
905
906 struct radeon_winsys_bo *descriptors[0];
907 };
908
909 struct radv_push_descriptor_set
910 {
911 struct radv_descriptor_set set;
912 uint32_t capacity;
913 };
914
915 struct radv_descriptor_pool_entry {
916 uint32_t offset;
917 uint32_t size;
918 struct radv_descriptor_set *set;
919 };
920
921 struct radv_descriptor_pool {
922 struct vk_object_base base;
923 struct radeon_winsys_bo *bo;
924 uint8_t *mapped_ptr;
925 uint64_t current_offset;
926 uint64_t size;
927
928 uint8_t *host_memory_base;
929 uint8_t *host_memory_ptr;
930 uint8_t *host_memory_end;
931
932 uint32_t entry_count;
933 uint32_t max_entry_count;
934 struct radv_descriptor_pool_entry entries[0];
935 };
936
937 struct radv_descriptor_update_template_entry {
938 VkDescriptorType descriptor_type;
939
940 /* The number of descriptors to update */
941 uint32_t descriptor_count;
942
943 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
944 uint32_t dst_offset;
945
946 /* In dwords. Not valid/used for dynamic descriptors */
947 uint32_t dst_stride;
948
949 uint32_t buffer_offset;
950
951 /* Only valid for combined image samplers and samplers */
952 uint8_t has_sampler;
953 uint8_t sampler_offset;
954
955 /* In bytes */
956 size_t src_offset;
957 size_t src_stride;
958
959 /* For push descriptors */
960 const uint32_t *immutable_samplers;
961 };
962
963 struct radv_descriptor_update_template {
964 struct vk_object_base base;
965 uint32_t entry_count;
966 VkPipelineBindPoint bind_point;
967 struct radv_descriptor_update_template_entry entry[0];
968 };
969
970 struct radv_buffer {
971 struct vk_object_base base;
972 VkDeviceSize size;
973
974 VkBufferUsageFlags usage;
975 VkBufferCreateFlags flags;
976
977 /* Set when bound */
978 struct radeon_winsys_bo * bo;
979 VkDeviceSize offset;
980
981 bool shareable;
982 };
983
984 enum radv_dynamic_state_bits {
985 RADV_DYNAMIC_VIEWPORT = 1 << 0,
986 RADV_DYNAMIC_SCISSOR = 1 << 1,
987 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
988 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
989 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
990 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
991 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
992 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
993 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
994 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
995 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
996 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
997 RADV_DYNAMIC_CULL_MODE = 1 << 12,
998 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
999 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
1000 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
1001 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
1002 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
1003 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
1004 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1005 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
1006 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1007 RADV_DYNAMIC_ALL = (1 << 22) - 1,
1008 };
1009
1010 enum radv_cmd_dirty_bits {
1011 /* Keep the dynamic state dirty bits in sync with
1012 * enum radv_dynamic_state_bits */
1013 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
1014 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
1015 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
1016 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
1017 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
1018 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
1019 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
1020 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
1021 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
1022 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
1023 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
1024 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
1025 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
1026 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
1027 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
1028 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
1029 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
1030 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
1031 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
1032 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1033 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
1034 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1035 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
1036 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
1037 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
1038 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
1039 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
1040 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
1041 };
1042
1043 enum radv_cmd_flush_bits {
1044 /* Instruction cache. */
1045 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1046 /* Scalar L1 cache. */
1047 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1048 /* Vector L1 cache. */
1049 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1050 /* L2 cache + L2 metadata cache writeback & invalidate.
1051 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1052 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1053 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1054 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1055 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1056 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1057 /* Framebuffer caches */
1058 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1059 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1060 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1061 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1062 /* Engine synchronization. */
1063 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1064 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1065 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1066 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1067 /* Pipeline query controls. */
1068 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1069 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1070 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1071
1072 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1073 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1074 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1075 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1076 };
1077
1078 struct radv_vertex_binding {
1079 struct radv_buffer * buffer;
1080 VkDeviceSize offset;
1081 VkDeviceSize size;
1082 VkDeviceSize stride;
1083 };
1084
1085 struct radv_streamout_binding {
1086 struct radv_buffer *buffer;
1087 VkDeviceSize offset;
1088 VkDeviceSize size;
1089 };
1090
1091 struct radv_streamout_state {
1092 /* Mask of bound streamout buffers. */
1093 uint8_t enabled_mask;
1094
1095 /* External state that comes from the last vertex stage, it must be
1096 * set explicitely when binding a new graphics pipeline.
1097 */
1098 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1099 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1100
1101 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1102 uint32_t hw_enabled_mask;
1103
1104 /* State of VGT_STRMOUT_(CONFIG|EN) */
1105 bool streamout_enabled;
1106 };
1107
1108 struct radv_viewport_state {
1109 uint32_t count;
1110 VkViewport viewports[MAX_VIEWPORTS];
1111 };
1112
1113 struct radv_scissor_state {
1114 uint32_t count;
1115 VkRect2D scissors[MAX_SCISSORS];
1116 };
1117
1118 struct radv_discard_rectangle_state {
1119 uint32_t count;
1120 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1121 };
1122
1123 struct radv_sample_locations_state {
1124 VkSampleCountFlagBits per_pixel;
1125 VkExtent2D grid_size;
1126 uint32_t count;
1127 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1128 };
1129
1130 struct radv_dynamic_state {
1131 /**
1132 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1133 * Defines the set of saved dynamic state.
1134 */
1135 uint32_t mask;
1136
1137 struct radv_viewport_state viewport;
1138
1139 struct radv_scissor_state scissor;
1140
1141 float line_width;
1142
1143 struct {
1144 float bias;
1145 float clamp;
1146 float slope;
1147 } depth_bias;
1148
1149 float blend_constants[4];
1150
1151 struct {
1152 float min;
1153 float max;
1154 } depth_bounds;
1155
1156 struct {
1157 uint32_t front;
1158 uint32_t back;
1159 } stencil_compare_mask;
1160
1161 struct {
1162 uint32_t front;
1163 uint32_t back;
1164 } stencil_write_mask;
1165
1166 struct {
1167 struct {
1168 VkStencilOp fail_op;
1169 VkStencilOp pass_op;
1170 VkStencilOp depth_fail_op;
1171 VkCompareOp compare_op;
1172 } front;
1173
1174 struct {
1175 VkStencilOp fail_op;
1176 VkStencilOp pass_op;
1177 VkStencilOp depth_fail_op;
1178 VkCompareOp compare_op;
1179 } back;
1180 } stencil_op;
1181
1182 struct {
1183 uint32_t front;
1184 uint32_t back;
1185 } stencil_reference;
1186
1187 struct radv_discard_rectangle_state discard_rectangle;
1188
1189 struct radv_sample_locations_state sample_location;
1190
1191 struct {
1192 uint32_t factor;
1193 uint16_t pattern;
1194 } line_stipple;
1195
1196 VkCullModeFlags cull_mode;
1197 VkFrontFace front_face;
1198 unsigned primitive_topology;
1199
1200 bool depth_test_enable;
1201 bool depth_write_enable;
1202 VkCompareOp depth_compare_op;
1203 bool depth_bounds_test_enable;
1204 bool stencil_test_enable;
1205 };
1206
1207 extern const struct radv_dynamic_state default_dynamic_state;
1208
1209 const char *
1210 radv_get_debug_option_name(int id);
1211
1212 const char *
1213 radv_get_perftest_option_name(int id);
1214
1215 struct radv_color_buffer_info {
1216 uint64_t cb_color_base;
1217 uint64_t cb_color_cmask;
1218 uint64_t cb_color_fmask;
1219 uint64_t cb_dcc_base;
1220 uint32_t cb_color_slice;
1221 uint32_t cb_color_view;
1222 uint32_t cb_color_info;
1223 uint32_t cb_color_attrib;
1224 uint32_t cb_color_attrib2; /* GFX9 and later */
1225 uint32_t cb_color_attrib3; /* GFX10 and later */
1226 uint32_t cb_dcc_control;
1227 uint32_t cb_color_cmask_slice;
1228 uint32_t cb_color_fmask_slice;
1229 union {
1230 uint32_t cb_color_pitch; // GFX6-GFX8
1231 uint32_t cb_mrt_epitch; // GFX9+
1232 };
1233 };
1234
1235 struct radv_ds_buffer_info {
1236 uint64_t db_z_read_base;
1237 uint64_t db_stencil_read_base;
1238 uint64_t db_z_write_base;
1239 uint64_t db_stencil_write_base;
1240 uint64_t db_htile_data_base;
1241 uint32_t db_depth_info;
1242 uint32_t db_z_info;
1243 uint32_t db_stencil_info;
1244 uint32_t db_depth_view;
1245 uint32_t db_depth_size;
1246 uint32_t db_depth_slice;
1247 uint32_t db_htile_surface;
1248 uint32_t pa_su_poly_offset_db_fmt_cntl;
1249 uint32_t db_z_info2; /* GFX9 only */
1250 uint32_t db_stencil_info2; /* GFX9 only */
1251 float offset_scale;
1252 };
1253
1254 void
1255 radv_initialise_color_surface(struct radv_device *device,
1256 struct radv_color_buffer_info *cb,
1257 struct radv_image_view *iview);
1258 void
1259 radv_initialise_ds_surface(struct radv_device *device,
1260 struct radv_ds_buffer_info *ds,
1261 struct radv_image_view *iview);
1262
1263 /**
1264 * Attachment state when recording a renderpass instance.
1265 *
1266 * The clear value is valid only if there exists a pending clear.
1267 */
1268 struct radv_attachment_state {
1269 VkImageAspectFlags pending_clear_aspects;
1270 uint32_t cleared_views;
1271 VkClearValue clear_value;
1272 VkImageLayout current_layout;
1273 VkImageLayout current_stencil_layout;
1274 bool current_in_render_loop;
1275 struct radv_sample_locations_state sample_location;
1276
1277 union {
1278 struct radv_color_buffer_info cb;
1279 struct radv_ds_buffer_info ds;
1280 };
1281 struct radv_image_view *iview;
1282 };
1283
1284 struct radv_descriptor_state {
1285 struct radv_descriptor_set *sets[MAX_SETS];
1286 uint32_t dirty;
1287 uint32_t valid;
1288 struct radv_push_descriptor_set push_set;
1289 bool push_dirty;
1290 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1291 };
1292
1293 struct radv_subpass_sample_locs_state {
1294 uint32_t subpass_idx;
1295 struct radv_sample_locations_state sample_location;
1296 };
1297
1298 struct radv_cmd_state {
1299 /* Vertex descriptors */
1300 uint64_t vb_va;
1301 unsigned vb_size;
1302
1303 bool predicating;
1304 uint32_t dirty;
1305
1306 uint32_t prefetch_L2_mask;
1307
1308 struct radv_pipeline * pipeline;
1309 struct radv_pipeline * emitted_pipeline;
1310 struct radv_pipeline * compute_pipeline;
1311 struct radv_pipeline * emitted_compute_pipeline;
1312 struct radv_framebuffer * framebuffer;
1313 struct radv_render_pass * pass;
1314 const struct radv_subpass * subpass;
1315 struct radv_dynamic_state dynamic;
1316 struct radv_attachment_state * attachments;
1317 struct radv_streamout_state streamout;
1318 VkRect2D render_area;
1319
1320 uint32_t num_subpass_sample_locs;
1321 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1322
1323 /* Index buffer */
1324 struct radv_buffer *index_buffer;
1325 uint64_t index_offset;
1326 uint32_t index_type;
1327 uint32_t max_index_count;
1328 uint64_t index_va;
1329 int32_t last_index_type;
1330
1331 int32_t last_primitive_reset_en;
1332 uint32_t last_primitive_reset_index;
1333 enum radv_cmd_flush_bits flush_bits;
1334 unsigned active_occlusion_queries;
1335 bool perfect_occlusion_queries_enabled;
1336 unsigned active_pipeline_queries;
1337 unsigned active_pipeline_gds_queries;
1338 float offset_scale;
1339 uint32_t trace_id;
1340 uint32_t last_ia_multi_vgt_param;
1341
1342 uint32_t last_num_instances;
1343 uint32_t last_first_instance;
1344 uint32_t last_vertex_offset;
1345
1346 uint32_t last_sx_ps_downconvert;
1347 uint32_t last_sx_blend_opt_epsilon;
1348 uint32_t last_sx_blend_opt_control;
1349
1350 /* Whether CP DMA is busy/idle. */
1351 bool dma_is_busy;
1352
1353 /* Conditional rendering info. */
1354 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1355 uint64_t predication_va;
1356
1357 /* Inheritance info. */
1358 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1359
1360 bool context_roll_without_scissor_emitted;
1361
1362 /* SQTT related state. */
1363 uint32_t current_event_type;
1364 uint32_t num_events;
1365 uint32_t num_layout_transitions;
1366 };
1367
1368 struct radv_cmd_pool {
1369 struct vk_object_base base;
1370 VkAllocationCallbacks alloc;
1371 struct list_head cmd_buffers;
1372 struct list_head free_cmd_buffers;
1373 uint32_t queue_family_index;
1374 };
1375
1376 struct radv_cmd_buffer_upload {
1377 uint8_t *map;
1378 unsigned offset;
1379 uint64_t size;
1380 struct radeon_winsys_bo *upload_bo;
1381 struct list_head list;
1382 };
1383
1384 enum radv_cmd_buffer_status {
1385 RADV_CMD_BUFFER_STATUS_INVALID,
1386 RADV_CMD_BUFFER_STATUS_INITIAL,
1387 RADV_CMD_BUFFER_STATUS_RECORDING,
1388 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1389 RADV_CMD_BUFFER_STATUS_PENDING,
1390 };
1391
1392 struct radv_cmd_buffer {
1393 struct vk_object_base base;
1394
1395 struct radv_device * device;
1396
1397 struct radv_cmd_pool * pool;
1398 struct list_head pool_link;
1399
1400 VkCommandBufferUsageFlags usage_flags;
1401 VkCommandBufferLevel level;
1402 enum radv_cmd_buffer_status status;
1403 struct radeon_cmdbuf *cs;
1404 struct radv_cmd_state state;
1405 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1406 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1407 uint32_t queue_family_index;
1408
1409 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1410 VkShaderStageFlags push_constant_stages;
1411 struct radv_descriptor_set meta_push_descriptors;
1412
1413 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1414
1415 struct radv_cmd_buffer_upload upload;
1416
1417 uint32_t scratch_size_per_wave_needed;
1418 uint32_t scratch_waves_wanted;
1419 uint32_t compute_scratch_size_per_wave_needed;
1420 uint32_t compute_scratch_waves_wanted;
1421 uint32_t esgs_ring_size_needed;
1422 uint32_t gsvs_ring_size_needed;
1423 bool tess_rings_needed;
1424 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1425 bool gds_oa_needed; /* for GFX10 streamout */
1426 bool sample_positions_needed;
1427
1428 VkResult record_result;
1429
1430 uint64_t gfx9_fence_va;
1431 uint32_t gfx9_fence_idx;
1432 uint64_t gfx9_eop_bug_va;
1433
1434 /**
1435 * Whether a query pool has been resetted and we have to flush caches.
1436 */
1437 bool pending_reset_query;
1438
1439 /**
1440 * Bitmask of pending active query flushes.
1441 */
1442 enum radv_cmd_flush_bits active_query_flush_bits;
1443 };
1444
1445 struct radv_image;
1446 struct radv_image_view;
1447
1448 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1449
1450 void si_emit_graphics(struct radv_device *device,
1451 struct radeon_cmdbuf *cs);
1452 void si_emit_compute(struct radv_device *device,
1453 struct radeon_cmdbuf *cs);
1454
1455 void cik_create_gfx_config(struct radv_device *device);
1456
1457 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1458 int count, const VkViewport *viewports);
1459 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1460 int count, const VkRect2D *scissors,
1461 const VkViewport *viewports, bool can_use_guardband);
1462 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1463 bool instanced_draw, bool indirect_draw,
1464 bool count_from_stream_output,
1465 uint32_t draw_vertex_count,
1466 unsigned topology);
1467 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1468 enum chip_class chip_class,
1469 bool is_mec,
1470 unsigned event, unsigned event_flags,
1471 unsigned dst_sel, unsigned data_sel,
1472 uint64_t va,
1473 uint32_t new_fence,
1474 uint64_t gfx9_eop_bug_va);
1475
1476 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1477 uint32_t ref, uint32_t mask);
1478 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1479 enum chip_class chip_class,
1480 uint32_t *fence_ptr, uint64_t va,
1481 bool is_mec,
1482 enum radv_cmd_flush_bits flush_bits,
1483 uint64_t gfx9_eop_bug_va);
1484 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1485 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1486 bool inverted, uint64_t va);
1487 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1488 uint64_t src_va, uint64_t dest_va,
1489 uint64_t size);
1490 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1491 unsigned size);
1492 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1493 uint64_t size, unsigned value);
1494 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1495
1496 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1497 bool
1498 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1499 unsigned size,
1500 unsigned alignment,
1501 unsigned *out_offset,
1502 void **ptr);
1503 void
1504 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1505 const struct radv_subpass *subpass);
1506 bool
1507 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1508 unsigned size, unsigned alignmnet,
1509 const void *data, unsigned *out_offset);
1510
1511 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1512 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1513 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1514 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1515 VkImageAspectFlags aspects,
1516 VkResolveModeFlagBits resolve_mode);
1517 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1518 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1519 VkImageAspectFlags aspects,
1520 VkResolveModeFlagBits resolve_mode);
1521 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1522 unsigned radv_get_default_max_sample_dist(int log_samples);
1523 void radv_device_init_msaa(struct radv_device *device);
1524
1525 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1526 const struct radv_image_view *iview,
1527 VkClearDepthStencilValue ds_clear_value,
1528 VkImageAspectFlags aspects);
1529
1530 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1531 const struct radv_image_view *iview,
1532 int cb_idx,
1533 uint32_t color_values[2]);
1534
1535 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1536 struct radv_image *image,
1537 const VkImageSubresourceRange *range, bool value);
1538
1539 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1540 struct radv_image *image,
1541 const VkImageSubresourceRange *range, bool value);
1542
1543 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1544 struct radeon_winsys_bo *bo,
1545 uint64_t offset, uint64_t size, uint32_t value);
1546 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1547 bool radv_get_memory_fd(struct radv_device *device,
1548 struct radv_device_memory *memory,
1549 int *pFD);
1550 void radv_free_memory(struct radv_device *device,
1551 const VkAllocationCallbacks* pAllocator,
1552 struct radv_device_memory *mem);
1553
1554 static inline void
1555 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1556 unsigned sh_offset, unsigned pointer_count,
1557 bool use_32bit_pointers)
1558 {
1559 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1560 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1561 }
1562
1563 static inline void
1564 radv_emit_shader_pointer_body(struct radv_device *device,
1565 struct radeon_cmdbuf *cs,
1566 uint64_t va, bool use_32bit_pointers)
1567 {
1568 radeon_emit(cs, va);
1569
1570 if (use_32bit_pointers) {
1571 assert(va == 0 ||
1572 (va >> 32) == device->physical_device->rad_info.address32_hi);
1573 } else {
1574 radeon_emit(cs, va >> 32);
1575 }
1576 }
1577
1578 static inline void
1579 radv_emit_shader_pointer(struct radv_device *device,
1580 struct radeon_cmdbuf *cs,
1581 uint32_t sh_offset, uint64_t va, bool global)
1582 {
1583 bool use_32bit_pointers = !global;
1584
1585 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1586 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1587 }
1588
1589 static inline struct radv_descriptor_state *
1590 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1591 VkPipelineBindPoint bind_point)
1592 {
1593 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1594 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1595 return &cmd_buffer->descriptors[bind_point];
1596 }
1597
1598 /*
1599 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1600 *
1601 * Limitations: Can't call normal dispatch functions without binding or rebinding
1602 * the compute pipeline.
1603 */
1604 void radv_unaligned_dispatch(
1605 struct radv_cmd_buffer *cmd_buffer,
1606 uint32_t x,
1607 uint32_t y,
1608 uint32_t z);
1609
1610 struct radv_event {
1611 struct vk_object_base base;
1612 struct radeon_winsys_bo *bo;
1613 uint64_t *map;
1614 };
1615
1616 struct radv_shader_module;
1617
1618 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1619 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1620 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1621 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1622 #define RADV_HASH_SHADER_LLVM (1 << 4)
1623
1624 void
1625 radv_hash_shaders(unsigned char *hash,
1626 const VkPipelineShaderStageCreateInfo **stages,
1627 const struct radv_pipeline_layout *layout,
1628 const struct radv_pipeline_key *key,
1629 uint32_t flags);
1630
1631 static inline gl_shader_stage
1632 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1633 {
1634 assert(__builtin_popcount(vk_stage) == 1);
1635 return ffs(vk_stage) - 1;
1636 }
1637
1638 static inline VkShaderStageFlagBits
1639 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1640 {
1641 return (1 << mesa_stage);
1642 }
1643
1644 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1645
1646 #define radv_foreach_stage(stage, stage_bits) \
1647 for (gl_shader_stage stage, \
1648 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1649 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1650 __tmp &= ~(1 << (stage)))
1651
1652 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1653 unsigned radv_format_meta_fs_key(VkFormat format);
1654
1655 struct radv_multisample_state {
1656 uint32_t db_eqaa;
1657 uint32_t pa_sc_mode_cntl_0;
1658 uint32_t pa_sc_mode_cntl_1;
1659 uint32_t pa_sc_aa_config;
1660 uint32_t pa_sc_aa_mask[2];
1661 unsigned num_samples;
1662 };
1663
1664 struct radv_prim_vertex_count {
1665 uint8_t min;
1666 uint8_t incr;
1667 };
1668
1669 struct radv_ia_multi_vgt_param_helpers {
1670 uint32_t base;
1671 bool partial_es_wave;
1672 uint8_t primgroup_size;
1673 bool ia_switch_on_eoi;
1674 bool partial_vs_wave;
1675 };
1676
1677 struct radv_binning_state {
1678 uint32_t pa_sc_binner_cntl_0;
1679 uint32_t db_dfsm_control;
1680 };
1681
1682 #define SI_GS_PER_ES 128
1683
1684 struct radv_pipeline {
1685 struct vk_object_base base;
1686 struct radv_device * device;
1687 struct radv_dynamic_state dynamic_state;
1688
1689 struct radv_pipeline_layout * layout;
1690
1691 bool need_indirect_descriptor_sets;
1692 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1693 struct radv_shader_variant *gs_copy_shader;
1694 VkShaderStageFlags active_stages;
1695
1696 struct radeon_cmdbuf cs;
1697 uint32_t ctx_cs_hash;
1698 struct radeon_cmdbuf ctx_cs;
1699
1700 uint32_t binding_stride[MAX_VBS];
1701 uint8_t num_vertex_bindings;
1702
1703 uint32_t user_data_0[MESA_SHADER_STAGES];
1704 union {
1705 struct {
1706 struct radv_multisample_state ms;
1707 struct radv_binning_state binning;
1708 uint32_t spi_baryc_cntl;
1709 bool prim_restart_enable;
1710 unsigned esgs_ring_size;
1711 unsigned gsvs_ring_size;
1712 uint32_t vtx_base_sgpr;
1713 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1714 uint8_t vtx_emit_num;
1715 bool can_use_guardband;
1716 uint32_t needed_dynamic_state;
1717 bool disable_out_of_order_rast_for_occlusion;
1718 unsigned tess_patch_control_points;
1719 unsigned pa_su_sc_mode_cntl;
1720 unsigned db_depth_control;
1721 bool uses_dynamic_stride;
1722
1723 /* Used for rbplus */
1724 uint32_t col_format;
1725 uint32_t cb_target_mask;
1726 } graphics;
1727 };
1728
1729 unsigned max_waves;
1730 unsigned scratch_bytes_per_wave;
1731
1732 /* Not NULL if graphics pipeline uses streamout. */
1733 struct radv_shader_variant *streamout_shader;
1734 };
1735
1736 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1737 {
1738 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1739 }
1740
1741 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1742 {
1743 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1744 }
1745
1746 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1747
1748 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1749
1750 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1751
1752 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1753 gl_shader_stage stage,
1754 int idx);
1755
1756 struct radv_shader_variant *radv_get_shader(const struct radv_pipeline *pipeline,
1757 gl_shader_stage stage);
1758
1759 struct radv_graphics_pipeline_create_info {
1760 bool use_rectlist;
1761 bool db_depth_clear;
1762 bool db_stencil_clear;
1763 bool db_depth_disable_expclear;
1764 bool db_stencil_disable_expclear;
1765 bool depth_compress_disable;
1766 bool stencil_compress_disable;
1767 bool resummarize_enable;
1768 uint32_t custom_blend_mode;
1769 };
1770
1771 VkResult
1772 radv_graphics_pipeline_create(VkDevice device,
1773 VkPipelineCache cache,
1774 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1775 const struct radv_graphics_pipeline_create_info *extra,
1776 const VkAllocationCallbacks *alloc,
1777 VkPipeline *pPipeline);
1778
1779 struct radv_binning_settings {
1780 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1781 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1782 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1783 };
1784
1785 struct radv_binning_settings
1786 radv_get_binning_settings(const struct radv_physical_device *pdev);
1787
1788 struct vk_format_description;
1789 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1790 int first_non_void);
1791 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1792 int first_non_void);
1793 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1794 uint32_t radv_translate_colorformat(VkFormat format);
1795 uint32_t radv_translate_color_numformat(VkFormat format,
1796 const struct vk_format_description *desc,
1797 int first_non_void);
1798 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1799 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1800 uint32_t radv_translate_dbformat(VkFormat format);
1801 uint32_t radv_translate_tex_dataformat(VkFormat format,
1802 const struct vk_format_description *desc,
1803 int first_non_void);
1804 uint32_t radv_translate_tex_numformat(VkFormat format,
1805 const struct vk_format_description *desc,
1806 int first_non_void);
1807 bool radv_format_pack_clear_color(VkFormat format,
1808 uint32_t clear_vals[2],
1809 VkClearColorValue *value);
1810 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1811 bool radv_dcc_formats_compatible(VkFormat format1,
1812 VkFormat format2);
1813 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1814
1815 struct radv_image_plane {
1816 VkFormat format;
1817 struct radeon_surf surface;
1818 uint64_t offset;
1819 };
1820
1821 struct radv_image {
1822 struct vk_object_base base;
1823 VkImageType type;
1824 /* The original VkFormat provided by the client. This may not match any
1825 * of the actual surface formats.
1826 */
1827 VkFormat vk_format;
1828 VkImageAspectFlags aspects;
1829 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1830 struct ac_surf_info info;
1831 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1832 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1833
1834 VkDeviceSize size;
1835 uint32_t alignment;
1836
1837 unsigned queue_family_mask;
1838 bool exclusive;
1839 bool shareable;
1840
1841 /* Set when bound */
1842 struct radeon_winsys_bo *bo;
1843 VkDeviceSize offset;
1844 bool tc_compatible_htile;
1845 bool tc_compatible_cmask;
1846
1847 uint64_t clear_value_offset;
1848 uint64_t fce_pred_offset;
1849 uint64_t dcc_pred_offset;
1850
1851 /*
1852 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1853 * stored at this offset is UINT_MAX, the driver will emit
1854 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1855 * SET_CONTEXT_REG packet.
1856 */
1857 uint64_t tc_compat_zrange_offset;
1858
1859 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1860 VkDeviceMemory owned_memory;
1861
1862 unsigned plane_count;
1863 struct radv_image_plane planes[0];
1864 };
1865
1866 /* Whether the image has a htile that is known consistent with the contents of
1867 * the image and is allowed to be in compressed form.
1868 *
1869 * If this is false reads that don't use the htile should be able to return
1870 * correct results.
1871 */
1872 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1873 VkImageLayout layout,
1874 bool in_render_loop,
1875 unsigned queue_mask);
1876
1877 bool radv_layout_can_fast_clear(const struct radv_image *image,
1878 VkImageLayout layout,
1879 bool in_render_loop,
1880 unsigned queue_mask);
1881
1882 bool radv_layout_dcc_compressed(const struct radv_device *device,
1883 const struct radv_image *image,
1884 VkImageLayout layout,
1885 bool in_render_loop,
1886 unsigned queue_mask);
1887
1888 /**
1889 * Return whether the image has CMASK metadata for color surfaces.
1890 */
1891 static inline bool
1892 radv_image_has_cmask(const struct radv_image *image)
1893 {
1894 return image->planes[0].surface.cmask_offset;
1895 }
1896
1897 /**
1898 * Return whether the image has FMASK metadata for color surfaces.
1899 */
1900 static inline bool
1901 radv_image_has_fmask(const struct radv_image *image)
1902 {
1903 return image->planes[0].surface.fmask_offset;
1904 }
1905
1906 /**
1907 * Return whether the image has DCC metadata for color surfaces.
1908 */
1909 static inline bool
1910 radv_image_has_dcc(const struct radv_image *image)
1911 {
1912 return image->planes[0].surface.dcc_size;
1913 }
1914
1915 /**
1916 * Return whether the image is TC-compatible CMASK.
1917 */
1918 static inline bool
1919 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1920 {
1921 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1922 }
1923
1924 /**
1925 * Return whether DCC metadata is enabled for a level.
1926 */
1927 static inline bool
1928 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1929 {
1930 return radv_image_has_dcc(image) &&
1931 level < image->planes[0].surface.num_dcc_levels;
1932 }
1933
1934 /**
1935 * Return whether the image has CB metadata.
1936 */
1937 static inline bool
1938 radv_image_has_CB_metadata(const struct radv_image *image)
1939 {
1940 return radv_image_has_cmask(image) ||
1941 radv_image_has_fmask(image) ||
1942 radv_image_has_dcc(image);
1943 }
1944
1945 /**
1946 * Return whether the image has HTILE metadata for depth surfaces.
1947 */
1948 static inline bool
1949 radv_image_has_htile(const struct radv_image *image)
1950 {
1951 return image->planes[0].surface.htile_size;
1952 }
1953
1954 /**
1955 * Return whether HTILE metadata is enabled for a level.
1956 */
1957 static inline bool
1958 radv_htile_enabled(const struct radv_image *image, unsigned level)
1959 {
1960 return radv_image_has_htile(image) && level == 0;
1961 }
1962
1963 /**
1964 * Return whether the image is TC-compatible HTILE.
1965 */
1966 static inline bool
1967 radv_image_is_tc_compat_htile(const struct radv_image *image)
1968 {
1969 return radv_image_has_htile(image) && image->tc_compatible_htile;
1970 }
1971
1972 static inline uint64_t
1973 radv_image_get_fast_clear_va(const struct radv_image *image,
1974 uint32_t base_level)
1975 {
1976 uint64_t va = radv_buffer_get_va(image->bo);
1977 va += image->offset + image->clear_value_offset + base_level * 8;
1978 return va;
1979 }
1980
1981 static inline uint64_t
1982 radv_image_get_fce_pred_va(const struct radv_image *image,
1983 uint32_t base_level)
1984 {
1985 uint64_t va = radv_buffer_get_va(image->bo);
1986 va += image->offset + image->fce_pred_offset + base_level * 8;
1987 return va;
1988 }
1989
1990 static inline uint64_t
1991 radv_image_get_dcc_pred_va(const struct radv_image *image,
1992 uint32_t base_level)
1993 {
1994 uint64_t va = radv_buffer_get_va(image->bo);
1995 va += image->offset + image->dcc_pred_offset + base_level * 8;
1996 return va;
1997 }
1998
1999 static inline uint64_t
2000 radv_get_tc_compat_zrange_va(const struct radv_image *image,
2001 uint32_t base_level)
2002 {
2003 uint64_t va = radv_buffer_get_va(image->bo);
2004 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
2005 return va;
2006 }
2007
2008 static inline uint64_t
2009 radv_get_ds_clear_value_va(const struct radv_image *image,
2010 uint32_t base_level)
2011 {
2012 uint64_t va = radv_buffer_get_va(image->bo);
2013 va += image->offset + image->clear_value_offset + base_level * 8;
2014 return va;
2015 }
2016
2017 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
2018
2019 static inline uint32_t
2020 radv_get_layerCount(const struct radv_image *image,
2021 const VkImageSubresourceRange *range)
2022 {
2023 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
2024 image->info.array_size - range->baseArrayLayer : range->layerCount;
2025 }
2026
2027 static inline uint32_t
2028 radv_get_levelCount(const struct radv_image *image,
2029 const VkImageSubresourceRange *range)
2030 {
2031 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2032 image->info.levels - range->baseMipLevel : range->levelCount;
2033 }
2034
2035 struct radeon_bo_metadata;
2036 void
2037 radv_init_metadata(struct radv_device *device,
2038 struct radv_image *image,
2039 struct radeon_bo_metadata *metadata);
2040
2041 void
2042 radv_image_override_offset_stride(struct radv_device *device,
2043 struct radv_image *image,
2044 uint64_t offset, uint32_t stride);
2045
2046 union radv_descriptor {
2047 struct {
2048 uint32_t plane0_descriptor[8];
2049 uint32_t fmask_descriptor[8];
2050 };
2051 struct {
2052 uint32_t plane_descriptors[3][8];
2053 };
2054 };
2055
2056 struct radv_image_view {
2057 struct vk_object_base base;
2058 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2059 struct radeon_winsys_bo *bo;
2060
2061 VkImageViewType type;
2062 VkImageAspectFlags aspect_mask;
2063 VkFormat vk_format;
2064 unsigned plane_id;
2065 bool multiple_planes;
2066 uint32_t base_layer;
2067 uint32_t layer_count;
2068 uint32_t base_mip;
2069 uint32_t level_count;
2070 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2071
2072 union radv_descriptor descriptor;
2073
2074 /* Descriptor for use as a storage image as opposed to a sampled image.
2075 * This has a few differences for cube maps (e.g. type).
2076 */
2077 union radv_descriptor storage_descriptor;
2078 };
2079
2080 struct radv_image_create_info {
2081 const VkImageCreateInfo *vk_info;
2082 bool scanout;
2083 bool no_metadata_planes;
2084 const struct radeon_bo_metadata *bo_metadata;
2085 };
2086
2087 VkResult
2088 radv_image_create_layout(struct radv_device *device,
2089 struct radv_image_create_info create_info,
2090 struct radv_image *image);
2091
2092 VkResult radv_image_create(VkDevice _device,
2093 const struct radv_image_create_info *info,
2094 const VkAllocationCallbacks* alloc,
2095 VkImage *pImage);
2096
2097 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2098
2099 VkResult
2100 radv_image_from_gralloc(VkDevice device_h,
2101 const VkImageCreateInfo *base_info,
2102 const VkNativeBufferANDROID *gralloc_info,
2103 const VkAllocationCallbacks *alloc,
2104 VkImage *out_image_h);
2105 uint64_t
2106 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2107 const VkImageUsageFlags vk_usage);
2108 VkResult
2109 radv_import_ahb_memory(struct radv_device *device,
2110 struct radv_device_memory *mem,
2111 unsigned priority,
2112 const VkImportAndroidHardwareBufferInfoANDROID *info);
2113 VkResult
2114 radv_create_ahb_memory(struct radv_device *device,
2115 struct radv_device_memory *mem,
2116 unsigned priority,
2117 const VkMemoryAllocateInfo *pAllocateInfo);
2118
2119 VkFormat
2120 radv_select_android_external_format(const void *next, VkFormat default_format);
2121
2122 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2123
2124 struct radv_image_view_extra_create_info {
2125 bool disable_compression;
2126 };
2127
2128 void radv_image_view_init(struct radv_image_view *view,
2129 struct radv_device *device,
2130 const VkImageViewCreateInfo *pCreateInfo,
2131 const struct radv_image_view_extra_create_info* extra_create_info);
2132
2133 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2134
2135 struct radv_sampler_ycbcr_conversion {
2136 struct vk_object_base base;
2137 VkFormat format;
2138 VkSamplerYcbcrModelConversion ycbcr_model;
2139 VkSamplerYcbcrRange ycbcr_range;
2140 VkComponentMapping components;
2141 VkChromaLocation chroma_offsets[2];
2142 VkFilter chroma_filter;
2143 };
2144
2145 struct radv_buffer_view {
2146 struct vk_object_base base;
2147 struct radeon_winsys_bo *bo;
2148 VkFormat vk_format;
2149 uint64_t range; /**< VkBufferViewCreateInfo::range */
2150 uint32_t state[4];
2151 };
2152 void radv_buffer_view_init(struct radv_buffer_view *view,
2153 struct radv_device *device,
2154 const VkBufferViewCreateInfo* pCreateInfo);
2155
2156 static inline struct VkExtent3D
2157 radv_sanitize_image_extent(const VkImageType imageType,
2158 const struct VkExtent3D imageExtent)
2159 {
2160 switch (imageType) {
2161 case VK_IMAGE_TYPE_1D:
2162 return (VkExtent3D) { imageExtent.width, 1, 1 };
2163 case VK_IMAGE_TYPE_2D:
2164 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2165 case VK_IMAGE_TYPE_3D:
2166 return imageExtent;
2167 default:
2168 unreachable("invalid image type");
2169 }
2170 }
2171
2172 static inline struct VkOffset3D
2173 radv_sanitize_image_offset(const VkImageType imageType,
2174 const struct VkOffset3D imageOffset)
2175 {
2176 switch (imageType) {
2177 case VK_IMAGE_TYPE_1D:
2178 return (VkOffset3D) { imageOffset.x, 0, 0 };
2179 case VK_IMAGE_TYPE_2D:
2180 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2181 case VK_IMAGE_TYPE_3D:
2182 return imageOffset;
2183 default:
2184 unreachable("invalid image type");
2185 }
2186 }
2187
2188 static inline bool
2189 radv_image_extent_compare(const struct radv_image *image,
2190 const VkExtent3D *extent)
2191 {
2192 if (extent->width != image->info.width ||
2193 extent->height != image->info.height ||
2194 extent->depth != image->info.depth)
2195 return false;
2196 return true;
2197 }
2198
2199 struct radv_sampler {
2200 struct vk_object_base base;
2201 uint32_t state[4];
2202 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2203 uint32_t border_color_slot;
2204 };
2205
2206 struct radv_framebuffer {
2207 struct vk_object_base base;
2208 uint32_t width;
2209 uint32_t height;
2210 uint32_t layers;
2211
2212 uint32_t attachment_count;
2213 struct radv_image_view *attachments[0];
2214 };
2215
2216 struct radv_subpass_barrier {
2217 VkPipelineStageFlags src_stage_mask;
2218 VkAccessFlags src_access_mask;
2219 VkAccessFlags dst_access_mask;
2220 };
2221
2222 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2223 const struct radv_subpass_barrier *barrier);
2224
2225 struct radv_subpass_attachment {
2226 uint32_t attachment;
2227 VkImageLayout layout;
2228 VkImageLayout stencil_layout;
2229 bool in_render_loop;
2230 };
2231
2232 struct radv_subpass {
2233 uint32_t attachment_count;
2234 struct radv_subpass_attachment * attachments;
2235
2236 uint32_t input_count;
2237 uint32_t color_count;
2238 struct radv_subpass_attachment * input_attachments;
2239 struct radv_subpass_attachment * color_attachments;
2240 struct radv_subpass_attachment * resolve_attachments;
2241 struct radv_subpass_attachment * depth_stencil_attachment;
2242 struct radv_subpass_attachment * ds_resolve_attachment;
2243 VkResolveModeFlagBits depth_resolve_mode;
2244 VkResolveModeFlagBits stencil_resolve_mode;
2245
2246 /** Subpass has at least one color resolve attachment */
2247 bool has_color_resolve;
2248
2249 /** Subpass has at least one color attachment */
2250 bool has_color_att;
2251
2252 struct radv_subpass_barrier start_barrier;
2253
2254 uint32_t view_mask;
2255
2256 VkSampleCountFlagBits color_sample_count;
2257 VkSampleCountFlagBits depth_sample_count;
2258 VkSampleCountFlagBits max_sample_count;
2259 };
2260
2261 uint32_t
2262 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2263
2264 struct radv_render_pass_attachment {
2265 VkFormat format;
2266 uint32_t samples;
2267 VkAttachmentLoadOp load_op;
2268 VkAttachmentLoadOp stencil_load_op;
2269 VkImageLayout initial_layout;
2270 VkImageLayout final_layout;
2271 VkImageLayout stencil_initial_layout;
2272 VkImageLayout stencil_final_layout;
2273
2274 /* The subpass id in which the attachment will be used first/last. */
2275 uint32_t first_subpass_idx;
2276 uint32_t last_subpass_idx;
2277 };
2278
2279 struct radv_render_pass {
2280 struct vk_object_base base;
2281 uint32_t attachment_count;
2282 uint32_t subpass_count;
2283 struct radv_subpass_attachment * subpass_attachments;
2284 struct radv_render_pass_attachment * attachments;
2285 struct radv_subpass_barrier end_barrier;
2286 struct radv_subpass subpasses[0];
2287 };
2288
2289 VkResult radv_device_init_meta(struct radv_device *device);
2290 void radv_device_finish_meta(struct radv_device *device);
2291
2292 struct radv_query_pool {
2293 struct vk_object_base base;
2294 struct radeon_winsys_bo *bo;
2295 uint32_t stride;
2296 uint32_t availability_offset;
2297 uint64_t size;
2298 char *ptr;
2299 VkQueryType type;
2300 uint32_t pipeline_stats_mask;
2301 };
2302
2303 typedef enum {
2304 RADV_SEMAPHORE_NONE,
2305 RADV_SEMAPHORE_WINSYS,
2306 RADV_SEMAPHORE_SYNCOBJ,
2307 RADV_SEMAPHORE_TIMELINE_SYNCOBJ,
2308 RADV_SEMAPHORE_TIMELINE,
2309 } radv_semaphore_kind;
2310
2311 struct radv_deferred_queue_submission;
2312
2313 struct radv_timeline_waiter {
2314 struct list_head list;
2315 struct radv_deferred_queue_submission *submission;
2316 uint64_t value;
2317 };
2318
2319 struct radv_timeline_point {
2320 struct list_head list;
2321
2322 uint64_t value;
2323 uint32_t syncobj;
2324
2325 /* Separate from the list to accomodate CPU wait being async, as well
2326 * as prevent point deletion during submission. */
2327 unsigned wait_count;
2328 };
2329
2330 struct radv_timeline {
2331 /* Using a pthread mutex to be compatible with condition variables. */
2332 pthread_mutex_t mutex;
2333
2334 uint64_t highest_signaled;
2335 uint64_t highest_submitted;
2336
2337 struct list_head points;
2338
2339 /* Keep free points on hand so we do not have to recreate syncobjs all
2340 * the time. */
2341 struct list_head free_points;
2342
2343 /* Submissions that are deferred waiting for a specific value to be
2344 * submitted. */
2345 struct list_head waiters;
2346 };
2347
2348 struct radv_timeline_syncobj {
2349 /* Keep syncobj first, so common-code can just handle this as
2350 * non-timeline syncobj. */
2351 uint32_t syncobj;
2352 uint64_t max_point; /* max submitted point. */
2353 };
2354
2355 struct radv_semaphore_part {
2356 radv_semaphore_kind kind;
2357 union {
2358 uint32_t syncobj;
2359 struct radeon_winsys_sem *ws_sem;
2360 struct radv_timeline timeline;
2361 struct radv_timeline_syncobj timeline_syncobj;
2362 };
2363 };
2364
2365 struct radv_semaphore {
2366 struct vk_object_base base;
2367 struct radv_semaphore_part permanent;
2368 struct radv_semaphore_part temporary;
2369 };
2370
2371 bool radv_queue_internal_submit(struct radv_queue *queue,
2372 struct radeon_cmdbuf *cs);
2373
2374 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2375 VkPipelineBindPoint bind_point,
2376 struct radv_descriptor_set *set,
2377 unsigned idx);
2378
2379 void
2380 radv_update_descriptor_sets(struct radv_device *device,
2381 struct radv_cmd_buffer *cmd_buffer,
2382 VkDescriptorSet overrideSet,
2383 uint32_t descriptorWriteCount,
2384 const VkWriteDescriptorSet *pDescriptorWrites,
2385 uint32_t descriptorCopyCount,
2386 const VkCopyDescriptorSet *pDescriptorCopies);
2387
2388 void
2389 radv_update_descriptor_set_with_template(struct radv_device *device,
2390 struct radv_cmd_buffer *cmd_buffer,
2391 struct radv_descriptor_set *set,
2392 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2393 const void *pData);
2394
2395 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2396 VkPipelineBindPoint pipelineBindPoint,
2397 VkPipelineLayout _layout,
2398 uint32_t set,
2399 uint32_t descriptorWriteCount,
2400 const VkWriteDescriptorSet *pDescriptorWrites);
2401
2402 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2403 struct radv_image *image,
2404 const VkImageSubresourceRange *range, uint32_t value);
2405
2406 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2407 struct radv_image *image,
2408 const VkImageSubresourceRange *range);
2409
2410 typedef enum {
2411 RADV_FENCE_NONE,
2412 RADV_FENCE_WINSYS,
2413 RADV_FENCE_SYNCOBJ,
2414 RADV_FENCE_WSI,
2415 } radv_fence_kind;
2416
2417 struct radv_fence_part {
2418 radv_fence_kind kind;
2419
2420 union {
2421 /* AMDGPU winsys fence. */
2422 struct radeon_winsys_fence *fence;
2423
2424 /* DRM syncobj handle for syncobj-based fences. */
2425 uint32_t syncobj;
2426
2427 /* WSI fence. */
2428 struct wsi_fence *fence_wsi;
2429 };
2430 };
2431
2432 struct radv_fence {
2433 struct vk_object_base base;
2434 struct radv_fence_part permanent;
2435 struct radv_fence_part temporary;
2436 };
2437
2438 /* radv_nir_to_llvm.c */
2439 struct radv_shader_args;
2440
2441 void llvm_compile_shader(struct radv_device *device,
2442 unsigned shader_count,
2443 struct nir_shader *const *shaders,
2444 struct radv_shader_binary **binary,
2445 struct radv_shader_args *args);
2446
2447 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2448 gl_shader_stage stage,
2449 const struct nir_shader *nir);
2450
2451 /* radv_shader_info.h */
2452 struct radv_shader_info;
2453 struct radv_shader_variant_key;
2454
2455 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2456 const struct radv_pipeline_layout *layout,
2457 const struct radv_shader_variant_key *key,
2458 struct radv_shader_info *info,
2459 bool use_llvm);
2460
2461 void radv_nir_shader_info_init(struct radv_shader_info *info);
2462
2463 /* radv_sqtt.c */
2464 struct radv_thread_trace_info {
2465 uint32_t cur_offset;
2466 uint32_t trace_status;
2467 union {
2468 uint32_t gfx9_write_counter;
2469 uint32_t gfx10_dropped_cntr;
2470 };
2471 };
2472
2473 struct radv_thread_trace_se {
2474 struct radv_thread_trace_info info;
2475 void *data_ptr;
2476 uint32_t shader_engine;
2477 uint32_t compute_unit;
2478 };
2479
2480 struct radv_thread_trace {
2481 uint32_t num_traces;
2482 struct radv_thread_trace_se traces[4];
2483 };
2484
2485 bool radv_thread_trace_init(struct radv_device *device);
2486 void radv_thread_trace_finish(struct radv_device *device);
2487 bool radv_begin_thread_trace(struct radv_queue *queue);
2488 bool radv_end_thread_trace(struct radv_queue *queue);
2489 bool radv_get_thread_trace(struct radv_queue *queue,
2490 struct radv_thread_trace *thread_trace);
2491 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2492 const void *data, uint32_t num_dwords);
2493
2494 /* radv_rgp.c */
2495 int radv_dump_thread_trace(struct radv_device *device,
2496 const struct radv_thread_trace *trace);
2497
2498 /* radv_sqtt_layer_.c */
2499 struct radv_barrier_data {
2500 union {
2501 struct {
2502 uint16_t depth_stencil_expand : 1;
2503 uint16_t htile_hiz_range_expand : 1;
2504 uint16_t depth_stencil_resummarize : 1;
2505 uint16_t dcc_decompress : 1;
2506 uint16_t fmask_decompress : 1;
2507 uint16_t fast_clear_eliminate : 1;
2508 uint16_t fmask_color_expand : 1;
2509 uint16_t init_mask_ram : 1;
2510 uint16_t reserved : 8;
2511 };
2512 uint16_t all;
2513 } layout_transitions;
2514 };
2515
2516 /**
2517 * Value for the reason field of an RGP barrier start marker originating from
2518 * the Vulkan client (does not include PAL-defined values). (Table 15)
2519 */
2520 enum rgp_barrier_reason {
2521 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2522
2523 /* External app-generated barrier reasons, i.e. API synchronization
2524 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2525 */
2526 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2527 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2528 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2529
2530 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2531 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2532 */
2533 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2534 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2535 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2536 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2537 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2538 };
2539
2540 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2541 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2542 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2543 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2544 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2545 VkImageAspectFlagBits aspects);
2546 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2547 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2548 enum rgp_barrier_reason reason);
2549 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2550 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2551 const struct radv_barrier_data *barrier);
2552
2553 struct radeon_winsys_sem;
2554
2555 uint64_t radv_get_current_time(void);
2556
2557 static inline uint32_t
2558 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2559 {
2560 switch (gl_prim) {
2561 case 0: /* GL_POINTS */
2562 return 1;
2563 case 1: /* GL_LINES */
2564 case 3: /* GL_LINE_STRIP */
2565 return 2;
2566 case 4: /* GL_TRIANGLES */
2567 case 5: /* GL_TRIANGLE_STRIP */
2568 return 3;
2569 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2570 return 4;
2571 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2572 return 6;
2573 case 7: /* GL_QUADS */
2574 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2575 default:
2576 assert(0);
2577 return 0;
2578 }
2579 }
2580
2581 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2582 const VkRenderPassBeginInfo *pRenderPassBegin);
2583 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2584
2585 static inline uint32_t si_translate_prim(unsigned topology)
2586 {
2587 switch (topology) {
2588 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2589 return V_008958_DI_PT_POINTLIST;
2590 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2591 return V_008958_DI_PT_LINELIST;
2592 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2593 return V_008958_DI_PT_LINESTRIP;
2594 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2595 return V_008958_DI_PT_TRILIST;
2596 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2597 return V_008958_DI_PT_TRISTRIP;
2598 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2599 return V_008958_DI_PT_TRIFAN;
2600 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2601 return V_008958_DI_PT_LINELIST_ADJ;
2602 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2603 return V_008958_DI_PT_LINESTRIP_ADJ;
2604 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2605 return V_008958_DI_PT_TRILIST_ADJ;
2606 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2607 return V_008958_DI_PT_TRISTRIP_ADJ;
2608 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2609 return V_008958_DI_PT_PATCH;
2610 default:
2611 assert(0);
2612 return 0;
2613 }
2614 }
2615
2616 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2617 {
2618 switch (op) {
2619 case VK_STENCIL_OP_KEEP:
2620 return V_02842C_STENCIL_KEEP;
2621 case VK_STENCIL_OP_ZERO:
2622 return V_02842C_STENCIL_ZERO;
2623 case VK_STENCIL_OP_REPLACE:
2624 return V_02842C_STENCIL_REPLACE_TEST;
2625 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2626 return V_02842C_STENCIL_ADD_CLAMP;
2627 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2628 return V_02842C_STENCIL_SUB_CLAMP;
2629 case VK_STENCIL_OP_INVERT:
2630 return V_02842C_STENCIL_INVERT;
2631 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2632 return V_02842C_STENCIL_ADD_WRAP;
2633 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2634 return V_02842C_STENCIL_SUB_WRAP;
2635 default:
2636 return 0;
2637 }
2638 }
2639
2640 /**
2641 * Helper used for debugging compiler issues by enabling/disabling LLVM for a
2642 * specific shader stage (developers only).
2643 */
2644 static inline bool
2645 radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage)
2646 {
2647 return device->physical_device->use_llvm;
2648 }
2649
2650 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2651 \
2652 static inline struct __radv_type * \
2653 __radv_type ## _from_handle(__VkType _handle) \
2654 { \
2655 return (struct __radv_type *) _handle; \
2656 } \
2657 \
2658 static inline __VkType \
2659 __radv_type ## _to_handle(struct __radv_type *_obj) \
2660 { \
2661 return (__VkType) _obj; \
2662 }
2663
2664 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2665 \
2666 static inline struct __radv_type * \
2667 __radv_type ## _from_handle(__VkType _handle) \
2668 { \
2669 return (struct __radv_type *)(uintptr_t) _handle; \
2670 } \
2671 \
2672 static inline __VkType \
2673 __radv_type ## _to_handle(struct __radv_type *_obj) \
2674 { \
2675 return (__VkType)(uintptr_t) _obj; \
2676 }
2677
2678 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2679 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2680
2681 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2682 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2683 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2684 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2685 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2686
2687 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2688 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2689 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2690 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2691 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2692 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2693 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2694 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2695 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2696 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2697 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2698 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2709
2710 #endif /* RADV_PRIVATE_H */