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driconf: Support selection by Vulkan applicationName.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorv(struct radv_instance *instance, const void *object,
198 VkDebugReportObjectTypeEXT type, VkResult error,
199 const char *file, int line, const char *format,
200 va_list args);
201
202 VkResult __vk_errorf(struct radv_instance *instance, const void *object,
203 VkDebugReportObjectTypeEXT type, VkResult error,
204 const char *file, int line, const char *format, ...)
205 radv_printflike(7, 8);
206
207 #define vk_error(instance, error) \
208 __vk_errorf(instance, NULL, \
209 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
210 error, __FILE__, __LINE__, NULL);
211 #define vk_errorf(instance, error, format, ...) \
212 __vk_errorf(instance, NULL, \
213 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
214 error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220 void radv_logi(const char *format, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x) do {} while(0)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 int radv_get_instance_entrypoint_index(const char *name);
258 int radv_get_device_entrypoint_index(const char *name);
259 int radv_get_physical_device_entrypoint_index(const char *name);
260
261 const char *radv_get_instance_entry_name(int index);
262 const char *radv_get_physical_device_entry_name(int index);
263 const char *radv_get_device_entry_name(int index);
264
265 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
266 const struct radv_instance_extension_table *instance);
267 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
268 const struct radv_instance_extension_table *instance);
269 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
272
273 void *radv_lookup_entrypoint(const char *name);
274
275 struct radv_physical_device {
276 VK_LOADER_DATA _loader_data;
277
278 /* Link in radv_instance::physical_devices */
279 struct list_head link;
280
281 struct radv_instance * instance;
282
283 struct radeon_winsys *ws;
284 struct radeon_info rad_info;
285 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
286 uint8_t driver_uuid[VK_UUID_SIZE];
287 uint8_t device_uuid[VK_UUID_SIZE];
288 uint8_t cache_uuid[VK_UUID_SIZE];
289
290 int local_fd;
291 int master_fd;
292 struct wsi_device wsi_device;
293
294 bool out_of_order_rast_allowed;
295
296 /* Whether DCC should be enabled for MSAA textures. */
297 bool dcc_msaa_allowed;
298
299 /* Whether to enable NGG. */
300 bool use_ngg;
301
302 /* Whether to enable NGG GS. */
303 bool use_ngg_gs;
304
305 /* Whether to enable NGG streamout. */
306 bool use_ngg_streamout;
307
308 /* Number of threads per wave. */
309 uint8_t ps_wave_size;
310 uint8_t cs_wave_size;
311 uint8_t ge_wave_size;
312
313 /* Whether to use the LLVM compiler backend */
314 bool use_llvm;
315
316 /* This is the drivers on-disk cache used as a fallback as opposed to
317 * the pipeline cache defined by apps.
318 */
319 struct disk_cache * disk_cache;
320
321 VkPhysicalDeviceMemoryProperties memory_properties;
322 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
323 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
324
325 drmPciBusInfo bus_info;
326
327 struct radv_device_extension_table supported_extensions;
328 };
329
330 struct radv_instance {
331 struct vk_object_base base;
332
333 VkAllocationCallbacks alloc;
334
335 uint32_t apiVersion;
336
337 char * applicationName;
338 uint32_t applicationVersion;
339 char * engineName;
340 uint32_t engineVersion;
341
342 uint64_t debug_flags;
343 uint64_t perftest_flags;
344
345 struct vk_debug_report_instance debug_report_callbacks;
346
347 struct radv_instance_extension_table enabled_extensions;
348 struct radv_instance_dispatch_table dispatch;
349 struct radv_physical_device_dispatch_table physical_device_dispatch;
350 struct radv_device_dispatch_table device_dispatch;
351
352 bool physical_devices_enumerated;
353 struct list_head physical_devices;
354
355 struct driOptionCache dri_options;
356 struct driOptionCache available_dri_options;
357
358 /**
359 * Workarounds for game bugs.
360 */
361 bool enable_mrt_output_nan_fixup;
362 };
363
364 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
365 void radv_finish_wsi(struct radv_physical_device *physical_device);
366
367 bool radv_instance_extension_supported(const char *name);
368 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
369 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
370 const char *name);
371
372 struct cache_entry;
373
374 struct radv_pipeline_cache {
375 struct vk_object_base base;
376 struct radv_device * device;
377 pthread_mutex_t mutex;
378 VkPipelineCacheCreateFlags flags;
379
380 uint32_t total_size;
381 uint32_t table_size;
382 uint32_t kernel_count;
383 struct cache_entry ** hash_table;
384 bool modified;
385
386 VkAllocationCallbacks alloc;
387 };
388
389 struct radv_pipeline_key {
390 uint32_t instance_rate_inputs;
391 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
392 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
393 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
394 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
395 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
396 uint64_t vertex_alpha_adjust;
397 uint32_t vertex_post_shuffle;
398 unsigned tess_input_vertices;
399 uint32_t col_format;
400 uint32_t is_int8;
401 uint32_t is_int10;
402 uint8_t log2_ps_iter_samples;
403 uint8_t num_samples;
404 bool is_dual_src;
405 uint32_t has_multiview_view_index : 1;
406 uint32_t optimisations_disabled : 1;
407 uint8_t topology;
408
409 /* Non-zero if a required subgroup size is specified via
410 * VK_EXT_subgroup_size_control.
411 */
412 uint8_t compute_subgroup_size;
413 };
414
415 struct radv_shader_binary;
416 struct radv_shader_variant;
417
418 void
419 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
420 struct radv_device *device);
421 void
422 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
423 bool
424 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
425 const void *data, size_t size);
426
427 bool
428 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
429 struct radv_pipeline_cache *cache,
430 const unsigned char *sha1,
431 struct radv_shader_variant **variants,
432 bool *found_in_application_cache);
433
434 void
435 radv_pipeline_cache_insert_shaders(struct radv_device *device,
436 struct radv_pipeline_cache *cache,
437 const unsigned char *sha1,
438 struct radv_shader_variant **variants,
439 struct radv_shader_binary *const *binaries);
440
441 enum radv_blit_ds_layout {
442 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
443 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
444 RADV_BLIT_DS_LAYOUT_COUNT,
445 };
446
447 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
448 {
449 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
450 }
451
452 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
453 {
454 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
455 }
456
457 enum radv_meta_dst_layout {
458 RADV_META_DST_LAYOUT_GENERAL,
459 RADV_META_DST_LAYOUT_OPTIMAL,
460 RADV_META_DST_LAYOUT_COUNT,
461 };
462
463 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
464 {
465 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
466 }
467
468 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
469 {
470 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
471 }
472
473 struct radv_meta_state {
474 VkAllocationCallbacks alloc;
475
476 struct radv_pipeline_cache cache;
477
478 /*
479 * For on-demand pipeline creation, makes sure that
480 * only one thread tries to build a pipeline at the same time.
481 */
482 mtx_t mtx;
483
484 /**
485 * Use array element `i` for images with `2^i` samples.
486 */
487 struct {
488 VkRenderPass render_pass[NUM_META_FS_KEYS];
489 VkPipeline color_pipelines[NUM_META_FS_KEYS];
490
491 VkRenderPass depthstencil_rp;
492 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
493 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
494 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
495
496 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
497 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
498 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
499 } clear[MAX_SAMPLES_LOG2];
500
501 VkPipelineLayout clear_color_p_layout;
502 VkPipelineLayout clear_depth_p_layout;
503 VkPipelineLayout clear_depth_unrestricted_p_layout;
504
505 /* Optimized compute fast HTILE clear for stencil or depth only. */
506 VkPipeline clear_htile_mask_pipeline;
507 VkPipelineLayout clear_htile_mask_p_layout;
508 VkDescriptorSetLayout clear_htile_mask_ds_layout;
509
510 struct {
511 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
512
513 /** Pipeline that blits from a 1D image. */
514 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
515
516 /** Pipeline that blits from a 2D image. */
517 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
518
519 /** Pipeline that blits from a 3D image. */
520 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
521
522 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
523 VkPipeline depth_only_1d_pipeline;
524 VkPipeline depth_only_2d_pipeline;
525 VkPipeline depth_only_3d_pipeline;
526
527 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
528 VkPipeline stencil_only_1d_pipeline;
529 VkPipeline stencil_only_2d_pipeline;
530 VkPipeline stencil_only_3d_pipeline;
531 VkPipelineLayout pipeline_layout;
532 VkDescriptorSetLayout ds_layout;
533 } blit;
534
535 struct {
536 VkPipelineLayout p_layouts[5];
537 VkDescriptorSetLayout ds_layouts[5];
538 VkPipeline pipelines[5][NUM_META_FS_KEYS];
539
540 VkPipeline depth_only_pipeline[5];
541
542 VkPipeline stencil_only_pipeline[5];
543 } blit2d[MAX_SAMPLES_LOG2];
544
545 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
546 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
547 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
548
549 struct {
550 VkPipelineLayout img_p_layout;
551 VkDescriptorSetLayout img_ds_layout;
552 VkPipeline pipeline;
553 VkPipeline pipeline_3d;
554 } itob;
555 struct {
556 VkPipelineLayout img_p_layout;
557 VkDescriptorSetLayout img_ds_layout;
558 VkPipeline pipeline;
559 VkPipeline pipeline_3d;
560 } btoi;
561 struct {
562 VkPipelineLayout img_p_layout;
563 VkDescriptorSetLayout img_ds_layout;
564 VkPipeline pipeline;
565 } btoi_r32g32b32;
566 struct {
567 VkPipelineLayout img_p_layout;
568 VkDescriptorSetLayout img_ds_layout;
569 VkPipeline pipeline;
570 VkPipeline pipeline_3d;
571 } itoi;
572 struct {
573 VkPipelineLayout img_p_layout;
574 VkDescriptorSetLayout img_ds_layout;
575 VkPipeline pipeline;
576 } itoi_r32g32b32;
577 struct {
578 VkPipelineLayout img_p_layout;
579 VkDescriptorSetLayout img_ds_layout;
580 VkPipeline pipeline;
581 VkPipeline pipeline_3d;
582 } cleari;
583 struct {
584 VkPipelineLayout img_p_layout;
585 VkDescriptorSetLayout img_ds_layout;
586 VkPipeline pipeline;
587 } cleari_r32g32b32;
588
589 struct {
590 VkPipelineLayout p_layout;
591 VkPipeline pipeline[NUM_META_FS_KEYS];
592 VkRenderPass pass[NUM_META_FS_KEYS];
593 } resolve;
594
595 struct {
596 VkDescriptorSetLayout ds_layout;
597 VkPipelineLayout p_layout;
598 struct {
599 VkPipeline pipeline;
600 VkPipeline i_pipeline;
601 VkPipeline srgb_pipeline;
602 } rc[MAX_SAMPLES_LOG2];
603
604 VkPipeline depth_zero_pipeline;
605 struct {
606 VkPipeline average_pipeline;
607 VkPipeline max_pipeline;
608 VkPipeline min_pipeline;
609 } depth[MAX_SAMPLES_LOG2];
610
611 VkPipeline stencil_zero_pipeline;
612 struct {
613 VkPipeline max_pipeline;
614 VkPipeline min_pipeline;
615 } stencil[MAX_SAMPLES_LOG2];
616 } resolve_compute;
617
618 struct {
619 VkDescriptorSetLayout ds_layout;
620 VkPipelineLayout p_layout;
621
622 struct {
623 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
624 VkPipeline pipeline[NUM_META_FS_KEYS];
625 } rc[MAX_SAMPLES_LOG2];
626
627 VkRenderPass depth_render_pass;
628 VkPipeline depth_zero_pipeline;
629 struct {
630 VkPipeline average_pipeline;
631 VkPipeline max_pipeline;
632 VkPipeline min_pipeline;
633 } depth[MAX_SAMPLES_LOG2];
634
635 VkRenderPass stencil_render_pass;
636 VkPipeline stencil_zero_pipeline;
637 struct {
638 VkPipeline max_pipeline;
639 VkPipeline min_pipeline;
640 } stencil[MAX_SAMPLES_LOG2];
641 } resolve_fragment;
642
643 struct {
644 VkPipelineLayout p_layout;
645 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
646 VkPipeline resummarize_pipeline;
647 VkRenderPass pass;
648 } depth_decomp[MAX_SAMPLES_LOG2];
649
650 struct {
651 VkPipelineLayout p_layout;
652 VkPipeline cmask_eliminate_pipeline;
653 VkPipeline fmask_decompress_pipeline;
654 VkPipeline dcc_decompress_pipeline;
655 VkRenderPass pass;
656
657 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
658 VkPipelineLayout dcc_decompress_compute_p_layout;
659 VkPipeline dcc_decompress_compute_pipeline;
660 } fast_clear_flush;
661
662 struct {
663 VkPipelineLayout fill_p_layout;
664 VkPipelineLayout copy_p_layout;
665 VkDescriptorSetLayout fill_ds_layout;
666 VkDescriptorSetLayout copy_ds_layout;
667 VkPipeline fill_pipeline;
668 VkPipeline copy_pipeline;
669 } buffer;
670
671 struct {
672 VkDescriptorSetLayout ds_layout;
673 VkPipelineLayout p_layout;
674 VkPipeline occlusion_query_pipeline;
675 VkPipeline pipeline_statistics_query_pipeline;
676 VkPipeline tfb_query_pipeline;
677 VkPipeline timestamp_query_pipeline;
678 } query;
679
680 struct {
681 VkDescriptorSetLayout ds_layout;
682 VkPipelineLayout p_layout;
683 VkPipeline pipeline[MAX_SAMPLES_LOG2];
684 } fmask_expand;
685 };
686
687 /* queue types */
688 #define RADV_QUEUE_GENERAL 0
689 #define RADV_QUEUE_COMPUTE 1
690 #define RADV_QUEUE_TRANSFER 2
691
692 #define RADV_MAX_QUEUE_FAMILIES 3
693
694 struct radv_deferred_queue_submission;
695
696 enum ring_type radv_queue_family_to_ring(int f);
697
698 struct radv_queue {
699 VK_LOADER_DATA _loader_data;
700 struct radv_device * device;
701 struct radeon_winsys_ctx *hw_ctx;
702 enum radeon_ctx_priority priority;
703 uint32_t queue_family_index;
704 int queue_idx;
705 VkDeviceQueueCreateFlags flags;
706
707 uint32_t scratch_size_per_wave;
708 uint32_t scratch_waves;
709 uint32_t compute_scratch_size_per_wave;
710 uint32_t compute_scratch_waves;
711 uint32_t esgs_ring_size;
712 uint32_t gsvs_ring_size;
713 bool has_tess_rings;
714 bool has_gds;
715 bool has_gds_oa;
716 bool has_sample_positions;
717
718 struct radeon_winsys_bo *scratch_bo;
719 struct radeon_winsys_bo *descriptor_bo;
720 struct radeon_winsys_bo *compute_scratch_bo;
721 struct radeon_winsys_bo *esgs_ring_bo;
722 struct radeon_winsys_bo *gsvs_ring_bo;
723 struct radeon_winsys_bo *tess_rings_bo;
724 struct radeon_winsys_bo *gds_bo;
725 struct radeon_winsys_bo *gds_oa_bo;
726 struct radeon_cmdbuf *initial_preamble_cs;
727 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
728 struct radeon_cmdbuf *continue_preamble_cs;
729
730 struct list_head pending_submissions;
731 pthread_mutex_t pending_mutex;
732
733 pthread_mutex_t thread_mutex;
734 pthread_cond_t thread_cond;
735 struct radv_deferred_queue_submission *thread_submission;
736 pthread_t submission_thread;
737 bool thread_exit;
738 bool thread_running;
739 };
740
741 struct radv_bo_list {
742 struct radv_winsys_bo_list list;
743 unsigned capacity;
744 pthread_mutex_t mutex;
745 };
746
747 VkResult radv_bo_list_add(struct radv_device *device,
748 struct radeon_winsys_bo *bo);
749 void radv_bo_list_remove(struct radv_device *device,
750 struct radeon_winsys_bo *bo);
751
752 #define RADV_BORDER_COLOR_COUNT 4096
753 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
754
755 struct radv_device_border_color_data {
756 bool used[RADV_BORDER_COLOR_COUNT];
757
758 struct radeon_winsys_bo *bo;
759 VkClearColorValue *colors_gpu_ptr;
760
761 /* Mutex is required to guarantee vkCreateSampler thread safety
762 * given that we are writing to a buffer and checking color occupation */
763 pthread_mutex_t mutex;
764 };
765
766 struct radv_device {
767 struct vk_device vk;
768
769 struct radv_instance * instance;
770 struct radeon_winsys *ws;
771
772 struct radv_meta_state meta_state;
773
774 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
775 int queue_count[RADV_MAX_QUEUE_FAMILIES];
776 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
777
778 bool always_use_syncobj;
779 bool pbb_allowed;
780 bool dfsm_allowed;
781 uint32_t tess_offchip_block_dw_size;
782 uint32_t scratch_waves;
783 uint32_t dispatch_initiator;
784
785 uint32_t gs_table_depth;
786
787 /* MSAA sample locations.
788 * The first index is the sample index.
789 * The second index is the coordinate: X, Y. */
790 float sample_locations_1x[1][2];
791 float sample_locations_2x[2][2];
792 float sample_locations_4x[4][2];
793 float sample_locations_8x[8][2];
794
795 /* GFX7 and later */
796 uint32_t gfx_init_size_dw;
797 struct radeon_winsys_bo *gfx_init;
798
799 struct radeon_winsys_bo *trace_bo;
800 uint32_t *trace_id_ptr;
801
802 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
803 bool keep_shader_info;
804
805 struct radv_physical_device *physical_device;
806
807 /* Backup in-memory cache to be used if the app doesn't provide one */
808 struct radv_pipeline_cache * mem_cache;
809
810 /*
811 * use different counters so MSAA MRTs get consecutive surface indices,
812 * even if MASK is allocated in between.
813 */
814 uint32_t image_mrt_offset_counter;
815 uint32_t fmask_mrt_offset_counter;
816 struct list_head shader_slabs;
817 mtx_t shader_slab_mutex;
818
819 /* For detecting VM faults reported by dmesg. */
820 uint64_t dmesg_timestamp;
821
822 struct radv_device_extension_table enabled_extensions;
823 struct radv_device_dispatch_table dispatch;
824
825 /* Whether the app has enabled the robustBufferAccess feature. */
826 bool robust_buffer_access;
827
828 /* Whether the driver uses a global BO list. */
829 bool use_global_bo_list;
830
831 struct radv_bo_list bo_list;
832
833 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
834 int force_aniso;
835
836 struct radv_device_border_color_data border_color_data;
837
838 /* Condition variable for legacy timelines, to notify waiters when a
839 * new point gets submitted. */
840 pthread_cond_t timeline_cond;
841
842 /* Thread trace. */
843 struct radeon_cmdbuf *thread_trace_start_cs[2];
844 struct radeon_cmdbuf *thread_trace_stop_cs[2];
845 struct radeon_winsys_bo *thread_trace_bo;
846 void *thread_trace_ptr;
847 uint32_t thread_trace_buffer_size;
848 int thread_trace_start_frame;
849
850 /* Overallocation. */
851 bool overallocation_disallowed;
852 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
853 mtx_t overallocation_mutex;
854 };
855
856 struct radv_device_memory {
857 struct vk_object_base base;
858 struct radeon_winsys_bo *bo;
859 /* for dedicated allocations */
860 struct radv_image *image;
861 struct radv_buffer *buffer;
862 uint32_t heap_index;
863 uint64_t alloc_size;
864 void * map;
865 void * user_ptr;
866
867 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
868 struct AHardwareBuffer * android_hardware_buffer;
869 #endif
870 };
871
872
873 struct radv_descriptor_range {
874 uint64_t va;
875 uint32_t size;
876 };
877
878 struct radv_descriptor_set {
879 struct vk_object_base base;
880 const struct radv_descriptor_set_layout *layout;
881 uint32_t size;
882 uint32_t buffer_count;
883
884 struct radeon_winsys_bo *bo;
885 uint64_t va;
886 uint32_t *mapped_ptr;
887 struct radv_descriptor_range *dynamic_descriptors;
888
889 struct radeon_winsys_bo *descriptors[0];
890 };
891
892 struct radv_push_descriptor_set
893 {
894 struct radv_descriptor_set set;
895 uint32_t capacity;
896 };
897
898 struct radv_descriptor_pool_entry {
899 uint32_t offset;
900 uint32_t size;
901 struct radv_descriptor_set *set;
902 };
903
904 struct radv_descriptor_pool {
905 struct vk_object_base base;
906 struct radeon_winsys_bo *bo;
907 uint8_t *mapped_ptr;
908 uint64_t current_offset;
909 uint64_t size;
910
911 uint8_t *host_memory_base;
912 uint8_t *host_memory_ptr;
913 uint8_t *host_memory_end;
914
915 uint32_t entry_count;
916 uint32_t max_entry_count;
917 struct radv_descriptor_pool_entry entries[0];
918 };
919
920 struct radv_descriptor_update_template_entry {
921 VkDescriptorType descriptor_type;
922
923 /* The number of descriptors to update */
924 uint32_t descriptor_count;
925
926 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
927 uint32_t dst_offset;
928
929 /* In dwords. Not valid/used for dynamic descriptors */
930 uint32_t dst_stride;
931
932 uint32_t buffer_offset;
933
934 /* Only valid for combined image samplers and samplers */
935 uint8_t has_sampler;
936 uint8_t sampler_offset;
937
938 /* In bytes */
939 size_t src_offset;
940 size_t src_stride;
941
942 /* For push descriptors */
943 const uint32_t *immutable_samplers;
944 };
945
946 struct radv_descriptor_update_template {
947 struct vk_object_base base;
948 uint32_t entry_count;
949 VkPipelineBindPoint bind_point;
950 struct radv_descriptor_update_template_entry entry[0];
951 };
952
953 struct radv_buffer {
954 struct vk_object_base base;
955 VkDeviceSize size;
956
957 VkBufferUsageFlags usage;
958 VkBufferCreateFlags flags;
959
960 /* Set when bound */
961 struct radeon_winsys_bo * bo;
962 VkDeviceSize offset;
963
964 bool shareable;
965 };
966
967 enum radv_dynamic_state_bits {
968 RADV_DYNAMIC_VIEWPORT = 1 << 0,
969 RADV_DYNAMIC_SCISSOR = 1 << 1,
970 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
971 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
972 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
973 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
974 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
975 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
976 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
977 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
978 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
979 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
980 RADV_DYNAMIC_CULL_MODE = 1 << 12,
981 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
982 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
983 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
984 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
985 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
986 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
987 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
988 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
989 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
990 RADV_DYNAMIC_ALL = (1 << 22) - 1,
991 };
992
993 enum radv_cmd_dirty_bits {
994 /* Keep the dynamic state dirty bits in sync with
995 * enum radv_dynamic_state_bits */
996 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
997 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
998 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
999 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
1000 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
1001 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
1002 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
1003 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
1004 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
1005 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
1006 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
1007 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
1008 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
1009 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
1010 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
1011 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
1012 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
1013 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
1014 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
1015 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1016 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
1017 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1018 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
1019 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
1020 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
1021 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
1022 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
1023 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
1024 };
1025
1026 enum radv_cmd_flush_bits {
1027 /* Instruction cache. */
1028 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1029 /* Scalar L1 cache. */
1030 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1031 /* Vector L1 cache. */
1032 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1033 /* L2 cache + L2 metadata cache writeback & invalidate.
1034 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1035 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1036 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1037 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1038 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1039 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1040 /* Framebuffer caches */
1041 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1043 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1044 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1045 /* Engine synchronization. */
1046 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1047 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1048 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1049 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1050 /* Pipeline query controls. */
1051 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1052 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1053 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1054
1055 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1056 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1057 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1058 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1059 };
1060
1061 struct radv_vertex_binding {
1062 struct radv_buffer * buffer;
1063 VkDeviceSize offset;
1064 VkDeviceSize size;
1065 VkDeviceSize stride;
1066 };
1067
1068 struct radv_streamout_binding {
1069 struct radv_buffer *buffer;
1070 VkDeviceSize offset;
1071 VkDeviceSize size;
1072 };
1073
1074 struct radv_streamout_state {
1075 /* Mask of bound streamout buffers. */
1076 uint8_t enabled_mask;
1077
1078 /* External state that comes from the last vertex stage, it must be
1079 * set explicitely when binding a new graphics pipeline.
1080 */
1081 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1082 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1083
1084 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1085 uint32_t hw_enabled_mask;
1086
1087 /* State of VGT_STRMOUT_(CONFIG|EN) */
1088 bool streamout_enabled;
1089 };
1090
1091 struct radv_viewport_state {
1092 uint32_t count;
1093 VkViewport viewports[MAX_VIEWPORTS];
1094 };
1095
1096 struct radv_scissor_state {
1097 uint32_t count;
1098 VkRect2D scissors[MAX_SCISSORS];
1099 };
1100
1101 struct radv_discard_rectangle_state {
1102 uint32_t count;
1103 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1104 };
1105
1106 struct radv_sample_locations_state {
1107 VkSampleCountFlagBits per_pixel;
1108 VkExtent2D grid_size;
1109 uint32_t count;
1110 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1111 };
1112
1113 struct radv_dynamic_state {
1114 /**
1115 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1116 * Defines the set of saved dynamic state.
1117 */
1118 uint32_t mask;
1119
1120 struct radv_viewport_state viewport;
1121
1122 struct radv_scissor_state scissor;
1123
1124 float line_width;
1125
1126 struct {
1127 float bias;
1128 float clamp;
1129 float slope;
1130 } depth_bias;
1131
1132 float blend_constants[4];
1133
1134 struct {
1135 float min;
1136 float max;
1137 } depth_bounds;
1138
1139 struct {
1140 uint32_t front;
1141 uint32_t back;
1142 } stencil_compare_mask;
1143
1144 struct {
1145 uint32_t front;
1146 uint32_t back;
1147 } stencil_write_mask;
1148
1149 struct {
1150 struct {
1151 VkStencilOp fail_op;
1152 VkStencilOp pass_op;
1153 VkStencilOp depth_fail_op;
1154 VkCompareOp compare_op;
1155 } front;
1156
1157 struct {
1158 VkStencilOp fail_op;
1159 VkStencilOp pass_op;
1160 VkStencilOp depth_fail_op;
1161 VkCompareOp compare_op;
1162 } back;
1163 } stencil_op;
1164
1165 struct {
1166 uint32_t front;
1167 uint32_t back;
1168 } stencil_reference;
1169
1170 struct radv_discard_rectangle_state discard_rectangle;
1171
1172 struct radv_sample_locations_state sample_location;
1173
1174 struct {
1175 uint32_t factor;
1176 uint16_t pattern;
1177 } line_stipple;
1178
1179 VkCullModeFlags cull_mode;
1180 VkFrontFace front_face;
1181 unsigned primitive_topology;
1182
1183 bool depth_test_enable;
1184 bool depth_write_enable;
1185 VkCompareOp depth_compare_op;
1186 bool depth_bounds_test_enable;
1187 bool stencil_test_enable;
1188 };
1189
1190 extern const struct radv_dynamic_state default_dynamic_state;
1191
1192 const char *
1193 radv_get_debug_option_name(int id);
1194
1195 const char *
1196 radv_get_perftest_option_name(int id);
1197
1198 struct radv_color_buffer_info {
1199 uint64_t cb_color_base;
1200 uint64_t cb_color_cmask;
1201 uint64_t cb_color_fmask;
1202 uint64_t cb_dcc_base;
1203 uint32_t cb_color_slice;
1204 uint32_t cb_color_view;
1205 uint32_t cb_color_info;
1206 uint32_t cb_color_attrib;
1207 uint32_t cb_color_attrib2; /* GFX9 and later */
1208 uint32_t cb_color_attrib3; /* GFX10 and later */
1209 uint32_t cb_dcc_control;
1210 uint32_t cb_color_cmask_slice;
1211 uint32_t cb_color_fmask_slice;
1212 union {
1213 uint32_t cb_color_pitch; // GFX6-GFX8
1214 uint32_t cb_mrt_epitch; // GFX9+
1215 };
1216 };
1217
1218 struct radv_ds_buffer_info {
1219 uint64_t db_z_read_base;
1220 uint64_t db_stencil_read_base;
1221 uint64_t db_z_write_base;
1222 uint64_t db_stencil_write_base;
1223 uint64_t db_htile_data_base;
1224 uint32_t db_depth_info;
1225 uint32_t db_z_info;
1226 uint32_t db_stencil_info;
1227 uint32_t db_depth_view;
1228 uint32_t db_depth_size;
1229 uint32_t db_depth_slice;
1230 uint32_t db_htile_surface;
1231 uint32_t pa_su_poly_offset_db_fmt_cntl;
1232 uint32_t db_z_info2; /* GFX9 only */
1233 uint32_t db_stencil_info2; /* GFX9 only */
1234 float offset_scale;
1235 };
1236
1237 void
1238 radv_initialise_color_surface(struct radv_device *device,
1239 struct radv_color_buffer_info *cb,
1240 struct radv_image_view *iview);
1241 void
1242 radv_initialise_ds_surface(struct radv_device *device,
1243 struct radv_ds_buffer_info *ds,
1244 struct radv_image_view *iview);
1245
1246 /**
1247 * Attachment state when recording a renderpass instance.
1248 *
1249 * The clear value is valid only if there exists a pending clear.
1250 */
1251 struct radv_attachment_state {
1252 VkImageAspectFlags pending_clear_aspects;
1253 uint32_t cleared_views;
1254 VkClearValue clear_value;
1255 VkImageLayout current_layout;
1256 VkImageLayout current_stencil_layout;
1257 bool current_in_render_loop;
1258 struct radv_sample_locations_state sample_location;
1259
1260 union {
1261 struct radv_color_buffer_info cb;
1262 struct radv_ds_buffer_info ds;
1263 };
1264 struct radv_image_view *iview;
1265 };
1266
1267 struct radv_descriptor_state {
1268 struct radv_descriptor_set *sets[MAX_SETS];
1269 uint32_t dirty;
1270 uint32_t valid;
1271 struct radv_push_descriptor_set push_set;
1272 bool push_dirty;
1273 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1274 };
1275
1276 struct radv_subpass_sample_locs_state {
1277 uint32_t subpass_idx;
1278 struct radv_sample_locations_state sample_location;
1279 };
1280
1281 struct radv_cmd_state {
1282 /* Vertex descriptors */
1283 uint64_t vb_va;
1284 unsigned vb_size;
1285
1286 bool predicating;
1287 uint32_t dirty;
1288
1289 uint32_t prefetch_L2_mask;
1290
1291 struct radv_pipeline * pipeline;
1292 struct radv_pipeline * emitted_pipeline;
1293 struct radv_pipeline * compute_pipeline;
1294 struct radv_pipeline * emitted_compute_pipeline;
1295 struct radv_framebuffer * framebuffer;
1296 struct radv_render_pass * pass;
1297 const struct radv_subpass * subpass;
1298 struct radv_dynamic_state dynamic;
1299 struct radv_attachment_state * attachments;
1300 struct radv_streamout_state streamout;
1301 VkRect2D render_area;
1302
1303 uint32_t num_subpass_sample_locs;
1304 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1305
1306 /* Index buffer */
1307 struct radv_buffer *index_buffer;
1308 uint64_t index_offset;
1309 uint32_t index_type;
1310 uint32_t max_index_count;
1311 uint64_t index_va;
1312 int32_t last_index_type;
1313
1314 int32_t last_primitive_reset_en;
1315 uint32_t last_primitive_reset_index;
1316 enum radv_cmd_flush_bits flush_bits;
1317 unsigned active_occlusion_queries;
1318 bool perfect_occlusion_queries_enabled;
1319 unsigned active_pipeline_queries;
1320 unsigned active_pipeline_gds_queries;
1321 float offset_scale;
1322 uint32_t trace_id;
1323 uint32_t last_ia_multi_vgt_param;
1324
1325 uint32_t last_num_instances;
1326 uint32_t last_first_instance;
1327 uint32_t last_vertex_offset;
1328
1329 uint32_t last_sx_ps_downconvert;
1330 uint32_t last_sx_blend_opt_epsilon;
1331 uint32_t last_sx_blend_opt_control;
1332
1333 /* Whether CP DMA is busy/idle. */
1334 bool dma_is_busy;
1335
1336 /* Conditional rendering info. */
1337 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1338 uint64_t predication_va;
1339
1340 /* Inheritance info. */
1341 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1342
1343 bool context_roll_without_scissor_emitted;
1344
1345 /* SQTT related state. */
1346 uint32_t current_event_type;
1347 uint32_t num_events;
1348 uint32_t num_layout_transitions;
1349 };
1350
1351 struct radv_cmd_pool {
1352 struct vk_object_base base;
1353 VkAllocationCallbacks alloc;
1354 struct list_head cmd_buffers;
1355 struct list_head free_cmd_buffers;
1356 uint32_t queue_family_index;
1357 };
1358
1359 struct radv_cmd_buffer_upload {
1360 uint8_t *map;
1361 unsigned offset;
1362 uint64_t size;
1363 struct radeon_winsys_bo *upload_bo;
1364 struct list_head list;
1365 };
1366
1367 enum radv_cmd_buffer_status {
1368 RADV_CMD_BUFFER_STATUS_INVALID,
1369 RADV_CMD_BUFFER_STATUS_INITIAL,
1370 RADV_CMD_BUFFER_STATUS_RECORDING,
1371 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1372 RADV_CMD_BUFFER_STATUS_PENDING,
1373 };
1374
1375 struct radv_cmd_buffer {
1376 struct vk_object_base base;
1377
1378 struct radv_device * device;
1379
1380 struct radv_cmd_pool * pool;
1381 struct list_head pool_link;
1382
1383 VkCommandBufferUsageFlags usage_flags;
1384 VkCommandBufferLevel level;
1385 enum radv_cmd_buffer_status status;
1386 struct radeon_cmdbuf *cs;
1387 struct radv_cmd_state state;
1388 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1389 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1390 uint32_t queue_family_index;
1391
1392 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1393 VkShaderStageFlags push_constant_stages;
1394 struct radv_descriptor_set meta_push_descriptors;
1395
1396 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1397
1398 struct radv_cmd_buffer_upload upload;
1399
1400 uint32_t scratch_size_per_wave_needed;
1401 uint32_t scratch_waves_wanted;
1402 uint32_t compute_scratch_size_per_wave_needed;
1403 uint32_t compute_scratch_waves_wanted;
1404 uint32_t esgs_ring_size_needed;
1405 uint32_t gsvs_ring_size_needed;
1406 bool tess_rings_needed;
1407 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1408 bool gds_oa_needed; /* for GFX10 streamout */
1409 bool sample_positions_needed;
1410
1411 VkResult record_result;
1412
1413 uint64_t gfx9_fence_va;
1414 uint32_t gfx9_fence_idx;
1415 uint64_t gfx9_eop_bug_va;
1416
1417 /**
1418 * Whether a query pool has been resetted and we have to flush caches.
1419 */
1420 bool pending_reset_query;
1421
1422 /**
1423 * Bitmask of pending active query flushes.
1424 */
1425 enum radv_cmd_flush_bits active_query_flush_bits;
1426 };
1427
1428 struct radv_image;
1429 struct radv_image_view;
1430
1431 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1432
1433 void si_emit_graphics(struct radv_device *device,
1434 struct radeon_cmdbuf *cs);
1435 void si_emit_compute(struct radv_device *device,
1436 struct radeon_cmdbuf *cs);
1437
1438 void cik_create_gfx_config(struct radv_device *device);
1439
1440 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1441 int count, const VkViewport *viewports);
1442 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1443 int count, const VkRect2D *scissors,
1444 const VkViewport *viewports, bool can_use_guardband);
1445 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1446 bool instanced_draw, bool indirect_draw,
1447 bool count_from_stream_output,
1448 uint32_t draw_vertex_count,
1449 unsigned topology);
1450 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1451 enum chip_class chip_class,
1452 bool is_mec,
1453 unsigned event, unsigned event_flags,
1454 unsigned dst_sel, unsigned data_sel,
1455 uint64_t va,
1456 uint32_t new_fence,
1457 uint64_t gfx9_eop_bug_va);
1458
1459 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1460 uint32_t ref, uint32_t mask);
1461 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1462 enum chip_class chip_class,
1463 uint32_t *fence_ptr, uint64_t va,
1464 bool is_mec,
1465 enum radv_cmd_flush_bits flush_bits,
1466 uint64_t gfx9_eop_bug_va);
1467 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1468 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1469 bool inverted, uint64_t va);
1470 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1471 uint64_t src_va, uint64_t dest_va,
1472 uint64_t size);
1473 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1474 unsigned size);
1475 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1476 uint64_t size, unsigned value);
1477 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1478
1479 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1480 bool
1481 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1482 unsigned size,
1483 unsigned alignment,
1484 unsigned *out_offset,
1485 void **ptr);
1486 void
1487 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1488 const struct radv_subpass *subpass);
1489 bool
1490 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1491 unsigned size, unsigned alignmnet,
1492 const void *data, unsigned *out_offset);
1493
1494 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1495 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1496 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1497 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1498 VkImageAspectFlags aspects,
1499 VkResolveModeFlagBits resolve_mode);
1500 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1501 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1502 VkImageAspectFlags aspects,
1503 VkResolveModeFlagBits resolve_mode);
1504 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1505 unsigned radv_get_default_max_sample_dist(int log_samples);
1506 void radv_device_init_msaa(struct radv_device *device);
1507
1508 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1509 const struct radv_image_view *iview,
1510 VkClearDepthStencilValue ds_clear_value,
1511 VkImageAspectFlags aspects);
1512
1513 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1514 const struct radv_image_view *iview,
1515 int cb_idx,
1516 uint32_t color_values[2]);
1517
1518 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1519 struct radv_image *image,
1520 const VkImageSubresourceRange *range, bool value);
1521
1522 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1523 struct radv_image *image,
1524 const VkImageSubresourceRange *range, bool value);
1525
1526 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1527 struct radeon_winsys_bo *bo,
1528 uint64_t offset, uint64_t size, uint32_t value);
1529 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1530 bool radv_get_memory_fd(struct radv_device *device,
1531 struct radv_device_memory *memory,
1532 int *pFD);
1533 void radv_free_memory(struct radv_device *device,
1534 const VkAllocationCallbacks* pAllocator,
1535 struct radv_device_memory *mem);
1536
1537 static inline void
1538 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1539 unsigned sh_offset, unsigned pointer_count,
1540 bool use_32bit_pointers)
1541 {
1542 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1543 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1544 }
1545
1546 static inline void
1547 radv_emit_shader_pointer_body(struct radv_device *device,
1548 struct radeon_cmdbuf *cs,
1549 uint64_t va, bool use_32bit_pointers)
1550 {
1551 radeon_emit(cs, va);
1552
1553 if (use_32bit_pointers) {
1554 assert(va == 0 ||
1555 (va >> 32) == device->physical_device->rad_info.address32_hi);
1556 } else {
1557 radeon_emit(cs, va >> 32);
1558 }
1559 }
1560
1561 static inline void
1562 radv_emit_shader_pointer(struct radv_device *device,
1563 struct radeon_cmdbuf *cs,
1564 uint32_t sh_offset, uint64_t va, bool global)
1565 {
1566 bool use_32bit_pointers = !global;
1567
1568 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1569 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1570 }
1571
1572 static inline struct radv_descriptor_state *
1573 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1574 VkPipelineBindPoint bind_point)
1575 {
1576 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1577 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1578 return &cmd_buffer->descriptors[bind_point];
1579 }
1580
1581 /*
1582 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1583 *
1584 * Limitations: Can't call normal dispatch functions without binding or rebinding
1585 * the compute pipeline.
1586 */
1587 void radv_unaligned_dispatch(
1588 struct radv_cmd_buffer *cmd_buffer,
1589 uint32_t x,
1590 uint32_t y,
1591 uint32_t z);
1592
1593 struct radv_event {
1594 struct vk_object_base base;
1595 struct radeon_winsys_bo *bo;
1596 uint64_t *map;
1597 };
1598
1599 struct radv_shader_module;
1600
1601 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1602 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1603 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1604 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1605 #define RADV_HASH_SHADER_LLVM (1 << 4)
1606
1607 void
1608 radv_hash_shaders(unsigned char *hash,
1609 const VkPipelineShaderStageCreateInfo **stages,
1610 const struct radv_pipeline_layout *layout,
1611 const struct radv_pipeline_key *key,
1612 uint32_t flags);
1613
1614 static inline gl_shader_stage
1615 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1616 {
1617 assert(__builtin_popcount(vk_stage) == 1);
1618 return ffs(vk_stage) - 1;
1619 }
1620
1621 static inline VkShaderStageFlagBits
1622 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1623 {
1624 return (1 << mesa_stage);
1625 }
1626
1627 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1628
1629 #define radv_foreach_stage(stage, stage_bits) \
1630 for (gl_shader_stage stage, \
1631 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1632 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1633 __tmp &= ~(1 << (stage)))
1634
1635 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1636 unsigned radv_format_meta_fs_key(VkFormat format);
1637
1638 struct radv_multisample_state {
1639 uint32_t db_eqaa;
1640 uint32_t pa_sc_mode_cntl_0;
1641 uint32_t pa_sc_mode_cntl_1;
1642 uint32_t pa_sc_aa_config;
1643 uint32_t pa_sc_aa_mask[2];
1644 unsigned num_samples;
1645 };
1646
1647 struct radv_prim_vertex_count {
1648 uint8_t min;
1649 uint8_t incr;
1650 };
1651
1652 struct radv_ia_multi_vgt_param_helpers {
1653 uint32_t base;
1654 bool partial_es_wave;
1655 uint8_t primgroup_size;
1656 bool ia_switch_on_eoi;
1657 bool partial_vs_wave;
1658 };
1659
1660 struct radv_binning_state {
1661 uint32_t pa_sc_binner_cntl_0;
1662 uint32_t db_dfsm_control;
1663 };
1664
1665 #define SI_GS_PER_ES 128
1666
1667 struct radv_pipeline {
1668 struct vk_object_base base;
1669 struct radv_device * device;
1670 struct radv_dynamic_state dynamic_state;
1671
1672 struct radv_pipeline_layout * layout;
1673
1674 bool need_indirect_descriptor_sets;
1675 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1676 struct radv_shader_variant *gs_copy_shader;
1677 VkShaderStageFlags active_stages;
1678
1679 struct radeon_cmdbuf cs;
1680 uint32_t ctx_cs_hash;
1681 struct radeon_cmdbuf ctx_cs;
1682
1683 uint32_t binding_stride[MAX_VBS];
1684 uint8_t num_vertex_bindings;
1685
1686 uint32_t user_data_0[MESA_SHADER_STAGES];
1687 union {
1688 struct {
1689 struct radv_multisample_state ms;
1690 struct radv_binning_state binning;
1691 uint32_t spi_baryc_cntl;
1692 bool prim_restart_enable;
1693 unsigned esgs_ring_size;
1694 unsigned gsvs_ring_size;
1695 uint32_t vtx_base_sgpr;
1696 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1697 uint8_t vtx_emit_num;
1698 bool can_use_guardband;
1699 uint32_t needed_dynamic_state;
1700 bool disable_out_of_order_rast_for_occlusion;
1701 unsigned tess_patch_control_points;
1702 unsigned pa_su_sc_mode_cntl;
1703 unsigned db_depth_control;
1704 bool uses_dynamic_stride;
1705
1706 /* Used for rbplus */
1707 uint32_t col_format;
1708 uint32_t cb_target_mask;
1709 } graphics;
1710 };
1711
1712 unsigned max_waves;
1713 unsigned scratch_bytes_per_wave;
1714
1715 /* Not NULL if graphics pipeline uses streamout. */
1716 struct radv_shader_variant *streamout_shader;
1717 };
1718
1719 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1720 {
1721 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1722 }
1723
1724 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1725 {
1726 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1727 }
1728
1729 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1730
1731 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1732
1733 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1734
1735 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1736 gl_shader_stage stage,
1737 int idx);
1738
1739 struct radv_shader_variant *radv_get_shader(const struct radv_pipeline *pipeline,
1740 gl_shader_stage stage);
1741
1742 struct radv_graphics_pipeline_create_info {
1743 bool use_rectlist;
1744 bool db_depth_clear;
1745 bool db_stencil_clear;
1746 bool db_depth_disable_expclear;
1747 bool db_stencil_disable_expclear;
1748 bool depth_compress_disable;
1749 bool stencil_compress_disable;
1750 bool resummarize_enable;
1751 uint32_t custom_blend_mode;
1752 };
1753
1754 VkResult
1755 radv_graphics_pipeline_create(VkDevice device,
1756 VkPipelineCache cache,
1757 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1758 const struct radv_graphics_pipeline_create_info *extra,
1759 const VkAllocationCallbacks *alloc,
1760 VkPipeline *pPipeline);
1761
1762 struct radv_binning_settings {
1763 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1764 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1765 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1766 };
1767
1768 struct radv_binning_settings
1769 radv_get_binning_settings(const struct radv_physical_device *pdev);
1770
1771 struct vk_format_description;
1772 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1773 int first_non_void);
1774 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1775 int first_non_void);
1776 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1777 uint32_t radv_translate_colorformat(VkFormat format);
1778 uint32_t radv_translate_color_numformat(VkFormat format,
1779 const struct vk_format_description *desc,
1780 int first_non_void);
1781 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1782 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1783 uint32_t radv_translate_dbformat(VkFormat format);
1784 uint32_t radv_translate_tex_dataformat(VkFormat format,
1785 const struct vk_format_description *desc,
1786 int first_non_void);
1787 uint32_t radv_translate_tex_numformat(VkFormat format,
1788 const struct vk_format_description *desc,
1789 int first_non_void);
1790 bool radv_format_pack_clear_color(VkFormat format,
1791 uint32_t clear_vals[2],
1792 VkClearColorValue *value);
1793 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1794 bool radv_dcc_formats_compatible(VkFormat format1,
1795 VkFormat format2);
1796 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1797
1798 struct radv_image_plane {
1799 VkFormat format;
1800 struct radeon_surf surface;
1801 uint64_t offset;
1802 };
1803
1804 struct radv_image {
1805 struct vk_object_base base;
1806 VkImageType type;
1807 /* The original VkFormat provided by the client. This may not match any
1808 * of the actual surface formats.
1809 */
1810 VkFormat vk_format;
1811 VkImageAspectFlags aspects;
1812 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1813 struct ac_surf_info info;
1814 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1815 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1816
1817 VkDeviceSize size;
1818 uint32_t alignment;
1819
1820 unsigned queue_family_mask;
1821 bool exclusive;
1822 bool shareable;
1823
1824 /* Set when bound */
1825 struct radeon_winsys_bo *bo;
1826 VkDeviceSize offset;
1827 bool tc_compatible_htile;
1828 bool tc_compatible_cmask;
1829
1830 uint64_t clear_value_offset;
1831 uint64_t fce_pred_offset;
1832 uint64_t dcc_pred_offset;
1833
1834 /*
1835 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1836 * stored at this offset is UINT_MAX, the driver will emit
1837 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1838 * SET_CONTEXT_REG packet.
1839 */
1840 uint64_t tc_compat_zrange_offset;
1841
1842 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1843 VkDeviceMemory owned_memory;
1844
1845 unsigned plane_count;
1846 struct radv_image_plane planes[0];
1847 };
1848
1849 /* Whether the image has a htile that is known consistent with the contents of
1850 * the image and is allowed to be in compressed form.
1851 *
1852 * If this is false reads that don't use the htile should be able to return
1853 * correct results.
1854 */
1855 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1856 VkImageLayout layout,
1857 bool in_render_loop,
1858 unsigned queue_mask);
1859
1860 bool radv_layout_can_fast_clear(const struct radv_image *image,
1861 VkImageLayout layout,
1862 bool in_render_loop,
1863 unsigned queue_mask);
1864
1865 bool radv_layout_dcc_compressed(const struct radv_device *device,
1866 const struct radv_image *image,
1867 VkImageLayout layout,
1868 bool in_render_loop,
1869 unsigned queue_mask);
1870
1871 /**
1872 * Return whether the image has CMASK metadata for color surfaces.
1873 */
1874 static inline bool
1875 radv_image_has_cmask(const struct radv_image *image)
1876 {
1877 return image->planes[0].surface.cmask_offset;
1878 }
1879
1880 /**
1881 * Return whether the image has FMASK metadata for color surfaces.
1882 */
1883 static inline bool
1884 radv_image_has_fmask(const struct radv_image *image)
1885 {
1886 return image->planes[0].surface.fmask_offset;
1887 }
1888
1889 /**
1890 * Return whether the image has DCC metadata for color surfaces.
1891 */
1892 static inline bool
1893 radv_image_has_dcc(const struct radv_image *image)
1894 {
1895 return image->planes[0].surface.dcc_size;
1896 }
1897
1898 /**
1899 * Return whether the image is TC-compatible CMASK.
1900 */
1901 static inline bool
1902 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1903 {
1904 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1905 }
1906
1907 /**
1908 * Return whether DCC metadata is enabled for a level.
1909 */
1910 static inline bool
1911 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1912 {
1913 return radv_image_has_dcc(image) &&
1914 level < image->planes[0].surface.num_dcc_levels;
1915 }
1916
1917 /**
1918 * Return whether the image has CB metadata.
1919 */
1920 static inline bool
1921 radv_image_has_CB_metadata(const struct radv_image *image)
1922 {
1923 return radv_image_has_cmask(image) ||
1924 radv_image_has_fmask(image) ||
1925 radv_image_has_dcc(image);
1926 }
1927
1928 /**
1929 * Return whether the image has HTILE metadata for depth surfaces.
1930 */
1931 static inline bool
1932 radv_image_has_htile(const struct radv_image *image)
1933 {
1934 return image->planes[0].surface.htile_size;
1935 }
1936
1937 /**
1938 * Return whether HTILE metadata is enabled for a level.
1939 */
1940 static inline bool
1941 radv_htile_enabled(const struct radv_image *image, unsigned level)
1942 {
1943 return radv_image_has_htile(image) && level == 0;
1944 }
1945
1946 /**
1947 * Return whether the image is TC-compatible HTILE.
1948 */
1949 static inline bool
1950 radv_image_is_tc_compat_htile(const struct radv_image *image)
1951 {
1952 return radv_image_has_htile(image) && image->tc_compatible_htile;
1953 }
1954
1955 static inline uint64_t
1956 radv_image_get_fast_clear_va(const struct radv_image *image,
1957 uint32_t base_level)
1958 {
1959 uint64_t va = radv_buffer_get_va(image->bo);
1960 va += image->offset + image->clear_value_offset + base_level * 8;
1961 return va;
1962 }
1963
1964 static inline uint64_t
1965 radv_image_get_fce_pred_va(const struct radv_image *image,
1966 uint32_t base_level)
1967 {
1968 uint64_t va = radv_buffer_get_va(image->bo);
1969 va += image->offset + image->fce_pred_offset + base_level * 8;
1970 return va;
1971 }
1972
1973 static inline uint64_t
1974 radv_image_get_dcc_pred_va(const struct radv_image *image,
1975 uint32_t base_level)
1976 {
1977 uint64_t va = radv_buffer_get_va(image->bo);
1978 va += image->offset + image->dcc_pred_offset + base_level * 8;
1979 return va;
1980 }
1981
1982 static inline uint64_t
1983 radv_get_tc_compat_zrange_va(const struct radv_image *image,
1984 uint32_t base_level)
1985 {
1986 uint64_t va = radv_buffer_get_va(image->bo);
1987 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
1988 return va;
1989 }
1990
1991 static inline uint64_t
1992 radv_get_ds_clear_value_va(const struct radv_image *image,
1993 uint32_t base_level)
1994 {
1995 uint64_t va = radv_buffer_get_va(image->bo);
1996 va += image->offset + image->clear_value_offset + base_level * 8;
1997 return va;
1998 }
1999
2000 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
2001
2002 static inline uint32_t
2003 radv_get_layerCount(const struct radv_image *image,
2004 const VkImageSubresourceRange *range)
2005 {
2006 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
2007 image->info.array_size - range->baseArrayLayer : range->layerCount;
2008 }
2009
2010 static inline uint32_t
2011 radv_get_levelCount(const struct radv_image *image,
2012 const VkImageSubresourceRange *range)
2013 {
2014 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2015 image->info.levels - range->baseMipLevel : range->levelCount;
2016 }
2017
2018 struct radeon_bo_metadata;
2019 void
2020 radv_init_metadata(struct radv_device *device,
2021 struct radv_image *image,
2022 struct radeon_bo_metadata *metadata);
2023
2024 void
2025 radv_image_override_offset_stride(struct radv_device *device,
2026 struct radv_image *image,
2027 uint64_t offset, uint32_t stride);
2028
2029 union radv_descriptor {
2030 struct {
2031 uint32_t plane0_descriptor[8];
2032 uint32_t fmask_descriptor[8];
2033 };
2034 struct {
2035 uint32_t plane_descriptors[3][8];
2036 };
2037 };
2038
2039 struct radv_image_view {
2040 struct vk_object_base base;
2041 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2042 struct radeon_winsys_bo *bo;
2043
2044 VkImageViewType type;
2045 VkImageAspectFlags aspect_mask;
2046 VkFormat vk_format;
2047 unsigned plane_id;
2048 bool multiple_planes;
2049 uint32_t base_layer;
2050 uint32_t layer_count;
2051 uint32_t base_mip;
2052 uint32_t level_count;
2053 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2054
2055 union radv_descriptor descriptor;
2056
2057 /* Descriptor for use as a storage image as opposed to a sampled image.
2058 * This has a few differences for cube maps (e.g. type).
2059 */
2060 union radv_descriptor storage_descriptor;
2061 };
2062
2063 struct radv_image_create_info {
2064 const VkImageCreateInfo *vk_info;
2065 bool scanout;
2066 bool no_metadata_planes;
2067 const struct radeon_bo_metadata *bo_metadata;
2068 };
2069
2070 VkResult
2071 radv_image_create_layout(struct radv_device *device,
2072 struct radv_image_create_info create_info,
2073 struct radv_image *image);
2074
2075 VkResult radv_image_create(VkDevice _device,
2076 const struct radv_image_create_info *info,
2077 const VkAllocationCallbacks* alloc,
2078 VkImage *pImage);
2079
2080 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2081
2082 VkResult
2083 radv_image_from_gralloc(VkDevice device_h,
2084 const VkImageCreateInfo *base_info,
2085 const VkNativeBufferANDROID *gralloc_info,
2086 const VkAllocationCallbacks *alloc,
2087 VkImage *out_image_h);
2088 uint64_t
2089 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2090 const VkImageUsageFlags vk_usage);
2091 VkResult
2092 radv_import_ahb_memory(struct radv_device *device,
2093 struct radv_device_memory *mem,
2094 unsigned priority,
2095 const VkImportAndroidHardwareBufferInfoANDROID *info);
2096 VkResult
2097 radv_create_ahb_memory(struct radv_device *device,
2098 struct radv_device_memory *mem,
2099 unsigned priority,
2100 const VkMemoryAllocateInfo *pAllocateInfo);
2101
2102 VkFormat
2103 radv_select_android_external_format(const void *next, VkFormat default_format);
2104
2105 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2106
2107 struct radv_image_view_extra_create_info {
2108 bool disable_compression;
2109 };
2110
2111 void radv_image_view_init(struct radv_image_view *view,
2112 struct radv_device *device,
2113 const VkImageViewCreateInfo *pCreateInfo,
2114 const struct radv_image_view_extra_create_info* extra_create_info);
2115
2116 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2117
2118 struct radv_sampler_ycbcr_conversion {
2119 struct vk_object_base base;
2120 VkFormat format;
2121 VkSamplerYcbcrModelConversion ycbcr_model;
2122 VkSamplerYcbcrRange ycbcr_range;
2123 VkComponentMapping components;
2124 VkChromaLocation chroma_offsets[2];
2125 VkFilter chroma_filter;
2126 };
2127
2128 struct radv_buffer_view {
2129 struct vk_object_base base;
2130 struct radeon_winsys_bo *bo;
2131 VkFormat vk_format;
2132 uint64_t range; /**< VkBufferViewCreateInfo::range */
2133 uint32_t state[4];
2134 };
2135 void radv_buffer_view_init(struct radv_buffer_view *view,
2136 struct radv_device *device,
2137 const VkBufferViewCreateInfo* pCreateInfo);
2138
2139 static inline struct VkExtent3D
2140 radv_sanitize_image_extent(const VkImageType imageType,
2141 const struct VkExtent3D imageExtent)
2142 {
2143 switch (imageType) {
2144 case VK_IMAGE_TYPE_1D:
2145 return (VkExtent3D) { imageExtent.width, 1, 1 };
2146 case VK_IMAGE_TYPE_2D:
2147 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2148 case VK_IMAGE_TYPE_3D:
2149 return imageExtent;
2150 default:
2151 unreachable("invalid image type");
2152 }
2153 }
2154
2155 static inline struct VkOffset3D
2156 radv_sanitize_image_offset(const VkImageType imageType,
2157 const struct VkOffset3D imageOffset)
2158 {
2159 switch (imageType) {
2160 case VK_IMAGE_TYPE_1D:
2161 return (VkOffset3D) { imageOffset.x, 0, 0 };
2162 case VK_IMAGE_TYPE_2D:
2163 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2164 case VK_IMAGE_TYPE_3D:
2165 return imageOffset;
2166 default:
2167 unreachable("invalid image type");
2168 }
2169 }
2170
2171 static inline bool
2172 radv_image_extent_compare(const struct radv_image *image,
2173 const VkExtent3D *extent)
2174 {
2175 if (extent->width != image->info.width ||
2176 extent->height != image->info.height ||
2177 extent->depth != image->info.depth)
2178 return false;
2179 return true;
2180 }
2181
2182 struct radv_sampler {
2183 struct vk_object_base base;
2184 uint32_t state[4];
2185 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2186 uint32_t border_color_slot;
2187 };
2188
2189 struct radv_framebuffer {
2190 struct vk_object_base base;
2191 uint32_t width;
2192 uint32_t height;
2193 uint32_t layers;
2194
2195 uint32_t attachment_count;
2196 struct radv_image_view *attachments[0];
2197 };
2198
2199 struct radv_subpass_barrier {
2200 VkPipelineStageFlags src_stage_mask;
2201 VkAccessFlags src_access_mask;
2202 VkAccessFlags dst_access_mask;
2203 };
2204
2205 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2206 const struct radv_subpass_barrier *barrier);
2207
2208 struct radv_subpass_attachment {
2209 uint32_t attachment;
2210 VkImageLayout layout;
2211 VkImageLayout stencil_layout;
2212 bool in_render_loop;
2213 };
2214
2215 struct radv_subpass {
2216 uint32_t attachment_count;
2217 struct radv_subpass_attachment * attachments;
2218
2219 uint32_t input_count;
2220 uint32_t color_count;
2221 struct radv_subpass_attachment * input_attachments;
2222 struct radv_subpass_attachment * color_attachments;
2223 struct radv_subpass_attachment * resolve_attachments;
2224 struct radv_subpass_attachment * depth_stencil_attachment;
2225 struct radv_subpass_attachment * ds_resolve_attachment;
2226 VkResolveModeFlagBits depth_resolve_mode;
2227 VkResolveModeFlagBits stencil_resolve_mode;
2228
2229 /** Subpass has at least one color resolve attachment */
2230 bool has_color_resolve;
2231
2232 /** Subpass has at least one color attachment */
2233 bool has_color_att;
2234
2235 struct radv_subpass_barrier start_barrier;
2236
2237 uint32_t view_mask;
2238
2239 VkSampleCountFlagBits color_sample_count;
2240 VkSampleCountFlagBits depth_sample_count;
2241 VkSampleCountFlagBits max_sample_count;
2242 };
2243
2244 uint32_t
2245 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2246
2247 struct radv_render_pass_attachment {
2248 VkFormat format;
2249 uint32_t samples;
2250 VkAttachmentLoadOp load_op;
2251 VkAttachmentLoadOp stencil_load_op;
2252 VkImageLayout initial_layout;
2253 VkImageLayout final_layout;
2254 VkImageLayout stencil_initial_layout;
2255 VkImageLayout stencil_final_layout;
2256
2257 /* The subpass id in which the attachment will be used first/last. */
2258 uint32_t first_subpass_idx;
2259 uint32_t last_subpass_idx;
2260 };
2261
2262 struct radv_render_pass {
2263 struct vk_object_base base;
2264 uint32_t attachment_count;
2265 uint32_t subpass_count;
2266 struct radv_subpass_attachment * subpass_attachments;
2267 struct radv_render_pass_attachment * attachments;
2268 struct radv_subpass_barrier end_barrier;
2269 struct radv_subpass subpasses[0];
2270 };
2271
2272 VkResult radv_device_init_meta(struct radv_device *device);
2273 void radv_device_finish_meta(struct radv_device *device);
2274
2275 struct radv_query_pool {
2276 struct vk_object_base base;
2277 struct radeon_winsys_bo *bo;
2278 uint32_t stride;
2279 uint32_t availability_offset;
2280 uint64_t size;
2281 char *ptr;
2282 VkQueryType type;
2283 uint32_t pipeline_stats_mask;
2284 };
2285
2286 typedef enum {
2287 RADV_SEMAPHORE_NONE,
2288 RADV_SEMAPHORE_WINSYS,
2289 RADV_SEMAPHORE_SYNCOBJ,
2290 RADV_SEMAPHORE_TIMELINE_SYNCOBJ,
2291 RADV_SEMAPHORE_TIMELINE,
2292 } radv_semaphore_kind;
2293
2294 struct radv_deferred_queue_submission;
2295
2296 struct radv_timeline_waiter {
2297 struct list_head list;
2298 struct radv_deferred_queue_submission *submission;
2299 uint64_t value;
2300 };
2301
2302 struct radv_timeline_point {
2303 struct list_head list;
2304
2305 uint64_t value;
2306 uint32_t syncobj;
2307
2308 /* Separate from the list to accomodate CPU wait being async, as well
2309 * as prevent point deletion during submission. */
2310 unsigned wait_count;
2311 };
2312
2313 struct radv_timeline {
2314 /* Using a pthread mutex to be compatible with condition variables. */
2315 pthread_mutex_t mutex;
2316
2317 uint64_t highest_signaled;
2318 uint64_t highest_submitted;
2319
2320 struct list_head points;
2321
2322 /* Keep free points on hand so we do not have to recreate syncobjs all
2323 * the time. */
2324 struct list_head free_points;
2325
2326 /* Submissions that are deferred waiting for a specific value to be
2327 * submitted. */
2328 struct list_head waiters;
2329 };
2330
2331 struct radv_timeline_syncobj {
2332 /* Keep syncobj first, so common-code can just handle this as
2333 * non-timeline syncobj. */
2334 uint32_t syncobj;
2335 uint64_t max_point; /* max submitted point. */
2336 };
2337
2338 struct radv_semaphore_part {
2339 radv_semaphore_kind kind;
2340 union {
2341 uint32_t syncobj;
2342 struct radeon_winsys_sem *ws_sem;
2343 struct radv_timeline timeline;
2344 struct radv_timeline_syncobj timeline_syncobj;
2345 };
2346 };
2347
2348 struct radv_semaphore {
2349 struct vk_object_base base;
2350 struct radv_semaphore_part permanent;
2351 struct radv_semaphore_part temporary;
2352 };
2353
2354 bool radv_queue_internal_submit(struct radv_queue *queue,
2355 struct radeon_cmdbuf *cs);
2356
2357 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2358 VkPipelineBindPoint bind_point,
2359 struct radv_descriptor_set *set,
2360 unsigned idx);
2361
2362 void
2363 radv_update_descriptor_sets(struct radv_device *device,
2364 struct radv_cmd_buffer *cmd_buffer,
2365 VkDescriptorSet overrideSet,
2366 uint32_t descriptorWriteCount,
2367 const VkWriteDescriptorSet *pDescriptorWrites,
2368 uint32_t descriptorCopyCount,
2369 const VkCopyDescriptorSet *pDescriptorCopies);
2370
2371 void
2372 radv_update_descriptor_set_with_template(struct radv_device *device,
2373 struct radv_cmd_buffer *cmd_buffer,
2374 struct radv_descriptor_set *set,
2375 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2376 const void *pData);
2377
2378 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2379 VkPipelineBindPoint pipelineBindPoint,
2380 VkPipelineLayout _layout,
2381 uint32_t set,
2382 uint32_t descriptorWriteCount,
2383 const VkWriteDescriptorSet *pDescriptorWrites);
2384
2385 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2386 struct radv_image *image,
2387 const VkImageSubresourceRange *range, uint32_t value);
2388
2389 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2390 struct radv_image *image,
2391 const VkImageSubresourceRange *range);
2392
2393 typedef enum {
2394 RADV_FENCE_NONE,
2395 RADV_FENCE_WINSYS,
2396 RADV_FENCE_SYNCOBJ,
2397 RADV_FENCE_WSI,
2398 } radv_fence_kind;
2399
2400 struct radv_fence_part {
2401 radv_fence_kind kind;
2402
2403 union {
2404 /* AMDGPU winsys fence. */
2405 struct radeon_winsys_fence *fence;
2406
2407 /* DRM syncobj handle for syncobj-based fences. */
2408 uint32_t syncobj;
2409
2410 /* WSI fence. */
2411 struct wsi_fence *fence_wsi;
2412 };
2413 };
2414
2415 struct radv_fence {
2416 struct vk_object_base base;
2417 struct radv_fence_part permanent;
2418 struct radv_fence_part temporary;
2419 };
2420
2421 /* radv_nir_to_llvm.c */
2422 struct radv_shader_args;
2423
2424 void llvm_compile_shader(struct radv_device *device,
2425 unsigned shader_count,
2426 struct nir_shader *const *shaders,
2427 struct radv_shader_binary **binary,
2428 struct radv_shader_args *args);
2429
2430 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2431 gl_shader_stage stage,
2432 const struct nir_shader *nir);
2433
2434 /* radv_shader_info.h */
2435 struct radv_shader_info;
2436 struct radv_shader_variant_key;
2437
2438 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2439 const struct radv_pipeline_layout *layout,
2440 const struct radv_shader_variant_key *key,
2441 struct radv_shader_info *info,
2442 bool use_llvm);
2443
2444 void radv_nir_shader_info_init(struct radv_shader_info *info);
2445
2446 /* radv_sqtt.c */
2447 struct radv_thread_trace_info {
2448 uint32_t cur_offset;
2449 uint32_t trace_status;
2450 union {
2451 uint32_t gfx9_write_counter;
2452 uint32_t gfx10_dropped_cntr;
2453 };
2454 };
2455
2456 struct radv_thread_trace_se {
2457 struct radv_thread_trace_info info;
2458 void *data_ptr;
2459 uint32_t shader_engine;
2460 uint32_t compute_unit;
2461 };
2462
2463 struct radv_thread_trace {
2464 uint32_t num_traces;
2465 struct radv_thread_trace_se traces[4];
2466 };
2467
2468 bool radv_thread_trace_init(struct radv_device *device);
2469 void radv_thread_trace_finish(struct radv_device *device);
2470 bool radv_begin_thread_trace(struct radv_queue *queue);
2471 bool radv_end_thread_trace(struct radv_queue *queue);
2472 bool radv_get_thread_trace(struct radv_queue *queue,
2473 struct radv_thread_trace *thread_trace);
2474 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2475 const void *data, uint32_t num_dwords);
2476
2477 /* radv_rgp.c */
2478 int radv_dump_thread_trace(struct radv_device *device,
2479 const struct radv_thread_trace *trace);
2480
2481 /* radv_sqtt_layer_.c */
2482 struct radv_barrier_data {
2483 union {
2484 struct {
2485 uint16_t depth_stencil_expand : 1;
2486 uint16_t htile_hiz_range_expand : 1;
2487 uint16_t depth_stencil_resummarize : 1;
2488 uint16_t dcc_decompress : 1;
2489 uint16_t fmask_decompress : 1;
2490 uint16_t fast_clear_eliminate : 1;
2491 uint16_t fmask_color_expand : 1;
2492 uint16_t init_mask_ram : 1;
2493 uint16_t reserved : 8;
2494 };
2495 uint16_t all;
2496 } layout_transitions;
2497 };
2498
2499 /**
2500 * Value for the reason field of an RGP barrier start marker originating from
2501 * the Vulkan client (does not include PAL-defined values). (Table 15)
2502 */
2503 enum rgp_barrier_reason {
2504 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2505
2506 /* External app-generated barrier reasons, i.e. API synchronization
2507 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2508 */
2509 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2510 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2511 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2512
2513 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2514 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2515 */
2516 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2517 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2518 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2519 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2520 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2521 };
2522
2523 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2524 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2525 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2526 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2527 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2528 VkImageAspectFlagBits aspects);
2529 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2530 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2531 enum rgp_barrier_reason reason);
2532 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2533 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2534 const struct radv_barrier_data *barrier);
2535
2536 struct radeon_winsys_sem;
2537
2538 uint64_t radv_get_current_time(void);
2539
2540 static inline uint32_t
2541 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2542 {
2543 switch (gl_prim) {
2544 case 0: /* GL_POINTS */
2545 return 1;
2546 case 1: /* GL_LINES */
2547 case 3: /* GL_LINE_STRIP */
2548 return 2;
2549 case 4: /* GL_TRIANGLES */
2550 case 5: /* GL_TRIANGLE_STRIP */
2551 return 3;
2552 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2553 return 4;
2554 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2555 return 6;
2556 case 7: /* GL_QUADS */
2557 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2558 default:
2559 assert(0);
2560 return 0;
2561 }
2562 }
2563
2564 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2565 const VkRenderPassBeginInfo *pRenderPassBegin);
2566 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2567
2568 static inline uint32_t si_translate_prim(unsigned topology)
2569 {
2570 switch (topology) {
2571 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2572 return V_008958_DI_PT_POINTLIST;
2573 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2574 return V_008958_DI_PT_LINELIST;
2575 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2576 return V_008958_DI_PT_LINESTRIP;
2577 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2578 return V_008958_DI_PT_TRILIST;
2579 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2580 return V_008958_DI_PT_TRISTRIP;
2581 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2582 return V_008958_DI_PT_TRIFAN;
2583 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2584 return V_008958_DI_PT_LINELIST_ADJ;
2585 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2586 return V_008958_DI_PT_LINESTRIP_ADJ;
2587 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2588 return V_008958_DI_PT_TRILIST_ADJ;
2589 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2590 return V_008958_DI_PT_TRISTRIP_ADJ;
2591 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2592 return V_008958_DI_PT_PATCH;
2593 default:
2594 assert(0);
2595 return 0;
2596 }
2597 }
2598
2599 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2600 {
2601 switch (op) {
2602 case VK_STENCIL_OP_KEEP:
2603 return V_02842C_STENCIL_KEEP;
2604 case VK_STENCIL_OP_ZERO:
2605 return V_02842C_STENCIL_ZERO;
2606 case VK_STENCIL_OP_REPLACE:
2607 return V_02842C_STENCIL_REPLACE_TEST;
2608 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2609 return V_02842C_STENCIL_ADD_CLAMP;
2610 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2611 return V_02842C_STENCIL_SUB_CLAMP;
2612 case VK_STENCIL_OP_INVERT:
2613 return V_02842C_STENCIL_INVERT;
2614 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2615 return V_02842C_STENCIL_ADD_WRAP;
2616 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2617 return V_02842C_STENCIL_SUB_WRAP;
2618 default:
2619 return 0;
2620 }
2621 }
2622
2623 /**
2624 * Helper used for debugging compiler issues by enabling/disabling LLVM for a
2625 * specific shader stage (developers only).
2626 */
2627 static inline bool
2628 radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage)
2629 {
2630 return device->physical_device->use_llvm;
2631 }
2632
2633 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2634 \
2635 static inline struct __radv_type * \
2636 __radv_type ## _from_handle(__VkType _handle) \
2637 { \
2638 return (struct __radv_type *) _handle; \
2639 } \
2640 \
2641 static inline __VkType \
2642 __radv_type ## _to_handle(struct __radv_type *_obj) \
2643 { \
2644 return (__VkType) _obj; \
2645 }
2646
2647 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2648 \
2649 static inline struct __radv_type * \
2650 __radv_type ## _from_handle(__VkType _handle) \
2651 { \
2652 return (struct __radv_type *)(uintptr_t) _handle; \
2653 } \
2654 \
2655 static inline __VkType \
2656 __radv_type ## _to_handle(struct __radv_type *_obj) \
2657 { \
2658 return (__VkType)(uintptr_t) _obj; \
2659 }
2660
2661 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2662 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2663
2664 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2665 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2666 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2667 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2668 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2669
2670 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2671 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2672 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2673 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2674 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2675 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2676 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2677 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2678 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2679 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2680 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2681 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2682 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2683 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2684 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2685 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2686 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2687 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2688 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2689 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2690 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2691 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2692
2693 #endif /* RADV_PRIVATE_H */