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radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 13
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
104
105 /*
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
108 */
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
110
111 enum radv_mem_heap {
112 RADV_MEM_HEAP_VRAM,
113 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
114 RADV_MEM_HEAP_GTT,
115 RADV_MEM_HEAP_COUNT
116 };
117
118 enum radv_mem_type {
119 RADV_MEM_TYPE_VRAM,
120 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
121 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
122 RADV_MEM_TYPE_GTT_CACHED,
123 RADV_MEM_TYPE_COUNT
124 };
125
126 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
127
128 static inline uint32_t
129 align_u32(uint32_t v, uint32_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline uint32_t
136 align_u32_npot(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a * a;
139 }
140
141 static inline uint64_t
142 align_u64(uint64_t v, uint64_t a)
143 {
144 assert(a != 0 && a == (a & -a));
145 return (v + a - 1) & ~(a - 1);
146 }
147
148 static inline int32_t
149 align_i32(int32_t v, int32_t a)
150 {
151 assert(a != 0 && a == (a & -a));
152 return (v + a - 1) & ~(a - 1);
153 }
154
155 /** Alignment must be a power of 2. */
156 static inline bool
157 radv_is_aligned(uintmax_t n, uintmax_t a)
158 {
159 assert(a == (a & -a));
160 return (n & (a - 1)) == 0;
161 }
162
163 static inline uint32_t
164 round_up_u32(uint32_t v, uint32_t a)
165 {
166 return (v + a - 1) / a;
167 }
168
169 static inline uint64_t
170 round_up_u64(uint64_t v, uint64_t a)
171 {
172 return (v + a - 1) / a;
173 }
174
175 static inline uint32_t
176 radv_minify(uint32_t n, uint32_t levels)
177 {
178 if (unlikely(n == 0))
179 return 0;
180 else
181 return MAX2(n >> levels, 1);
182 }
183 static inline float
184 radv_clamp_f(float f, float min, float max)
185 {
186 assert(min < max);
187
188 if (f > max)
189 return max;
190 else if (f < min)
191 return min;
192 else
193 return f;
194 }
195
196 static inline bool
197 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
198 {
199 if (*inout_mask & clear_mask) {
200 *inout_mask &= ~clear_mask;
201 return true;
202 } else {
203 return false;
204 }
205 }
206
207 #define for_each_bit(b, dword) \
208 for (uint32_t __dword = (dword); \
209 (b) = __builtin_ffs(__dword) - 1, __dword; \
210 __dword &= ~(1 << (b)))
211
212 #define typed_memcpy(dest, src, count) ({ \
213 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
214 memcpy((dest), (src), (count) * sizeof(*(src))); \
215 })
216
217 /* Whenever we generate an error, pass it through this function. Useful for
218 * debugging, where we can break on it. Only call at error site, not when
219 * propagating errors. Might be useful to plug in a stack trace here.
220 */
221
222 struct radv_instance;
223
224 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
225
226 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
227 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
228
229 void __radv_finishme(const char *file, int line, const char *format, ...)
230 radv_printflike(3, 4);
231 void radv_loge(const char *format, ...) radv_printflike(1, 2);
232 void radv_loge_v(const char *format, va_list va);
233 void radv_logi(const char *format, ...) radv_printflike(1, 2);
234 void radv_logi_v(const char *format, va_list va);
235
236 /**
237 * Print a FINISHME message, including its source location.
238 */
239 #define radv_finishme(format, ...) \
240 do { \
241 static bool reported = false; \
242 if (!reported) { \
243 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 reported = true; \
245 } \
246 } while (0)
247
248 /* A non-fatal assert. Useful for debugging. */
249 #ifdef DEBUG
250 #define radv_assert(x) ({ \
251 if (unlikely(!(x))) \
252 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
253 })
254 #else
255 #define radv_assert(x)
256 #endif
257
258 #define stub_return(v) \
259 do { \
260 radv_finishme("stub %s", __func__); \
261 return (v); \
262 } while (0)
263
264 #define stub() \
265 do { \
266 radv_finishme("stub %s", __func__); \
267 return; \
268 } while (0)
269
270 void *radv_lookup_entrypoint_unchecked(const char *name);
271 void *radv_lookup_entrypoint_checked(const char *name,
272 uint32_t core_version,
273 const struct radv_instance_extension_table *instance,
274 const struct radv_device_extension_table *device);
275
276 struct radv_physical_device {
277 VK_LOADER_DATA _loader_data;
278
279 struct radv_instance * instance;
280
281 struct radeon_winsys *ws;
282 struct radeon_info rad_info;
283 char path[20];
284 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
285 uint8_t driver_uuid[VK_UUID_SIZE];
286 uint8_t device_uuid[VK_UUID_SIZE];
287 uint8_t cache_uuid[VK_UUID_SIZE];
288
289 int local_fd;
290 int master_fd;
291 struct wsi_device wsi_device;
292
293 bool has_rbplus; /* if RB+ register exist */
294 bool rbplus_allowed; /* if RB+ is allowed */
295 bool has_clear_state;
296 bool cpdma_prefetch_writes_memory;
297 bool has_scissor_bug;
298
299 bool has_out_of_order_rast;
300 bool out_of_order_rast_allowed;
301
302 /* Whether DCC should be enabled for MSAA textures. */
303 bool dcc_msaa_allowed;
304
305 /* This is the drivers on-disk cache used as a fallback as opposed to
306 * the pipeline cache defined by apps.
307 */
308 struct disk_cache * disk_cache;
309
310 VkPhysicalDeviceMemoryProperties memory_properties;
311 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
312
313 struct radv_device_extension_table supported_extensions;
314 };
315
316 struct radv_instance {
317 VK_LOADER_DATA _loader_data;
318
319 VkAllocationCallbacks alloc;
320
321 uint32_t apiVersion;
322 int physicalDeviceCount;
323 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
324
325 uint64_t debug_flags;
326 uint64_t perftest_flags;
327
328 struct vk_debug_report_instance debug_report_callbacks;
329
330 struct radv_instance_extension_table enabled_extensions;
331 };
332
333 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
334 void radv_finish_wsi(struct radv_physical_device *physical_device);
335
336 bool radv_instance_extension_supported(const char *name);
337 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
338 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
339 const char *name);
340
341 struct cache_entry;
342
343 struct radv_pipeline_cache {
344 struct radv_device * device;
345 pthread_mutex_t mutex;
346
347 uint32_t total_size;
348 uint32_t table_size;
349 uint32_t kernel_count;
350 struct cache_entry ** hash_table;
351 bool modified;
352
353 VkAllocationCallbacks alloc;
354 };
355
356 struct radv_pipeline_key {
357 uint32_t instance_rate_inputs;
358 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
359 uint64_t vertex_alpha_adjust;
360 unsigned tess_input_vertices;
361 uint32_t col_format;
362 uint32_t is_int8;
363 uint32_t is_int10;
364 uint8_t log2_ps_iter_samples;
365 uint8_t num_samples;
366 uint32_t has_multiview_view_index : 1;
367 uint32_t optimisations_disabled : 1;
368 };
369
370 void
371 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
372 struct radv_device *device);
373 void
374 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
375 void
376 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
377 const void *data, size_t size);
378
379 struct radv_shader_variant;
380
381 bool
382 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
383 struct radv_pipeline_cache *cache,
384 const unsigned char *sha1,
385 struct radv_shader_variant **variants);
386
387 void
388 radv_pipeline_cache_insert_shaders(struct radv_device *device,
389 struct radv_pipeline_cache *cache,
390 const unsigned char *sha1,
391 struct radv_shader_variant **variants,
392 const void *const *codes,
393 const unsigned *code_sizes);
394
395 enum radv_blit_ds_layout {
396 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
397 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
398 RADV_BLIT_DS_LAYOUT_COUNT,
399 };
400
401 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
402 {
403 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
404 }
405
406 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
407 {
408 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
409 }
410
411 enum radv_meta_dst_layout {
412 RADV_META_DST_LAYOUT_GENERAL,
413 RADV_META_DST_LAYOUT_OPTIMAL,
414 RADV_META_DST_LAYOUT_COUNT,
415 };
416
417 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
418 {
419 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
420 }
421
422 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
423 {
424 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
425 }
426
427 struct radv_meta_state {
428 VkAllocationCallbacks alloc;
429
430 struct radv_pipeline_cache cache;
431
432 /**
433 * Use array element `i` for images with `2^i` samples.
434 */
435 struct {
436 VkRenderPass render_pass[NUM_META_FS_KEYS];
437 VkPipeline color_pipelines[NUM_META_FS_KEYS];
438
439 VkRenderPass depthstencil_rp;
440 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
441 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
442 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
443 } clear[1 + MAX_SAMPLES_LOG2];
444
445 VkPipelineLayout clear_color_p_layout;
446 VkPipelineLayout clear_depth_p_layout;
447 struct {
448 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
449
450 /** Pipeline that blits from a 1D image. */
451 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
452
453 /** Pipeline that blits from a 2D image. */
454 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
455
456 /** Pipeline that blits from a 3D image. */
457 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
458
459 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
460 VkPipeline depth_only_1d_pipeline;
461 VkPipeline depth_only_2d_pipeline;
462 VkPipeline depth_only_3d_pipeline;
463
464 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
465 VkPipeline stencil_only_1d_pipeline;
466 VkPipeline stencil_only_2d_pipeline;
467 VkPipeline stencil_only_3d_pipeline;
468 VkPipelineLayout pipeline_layout;
469 VkDescriptorSetLayout ds_layout;
470 } blit;
471
472 struct {
473 VkPipelineLayout p_layouts[5];
474 VkDescriptorSetLayout ds_layouts[5];
475 VkPipeline pipelines[5][NUM_META_FS_KEYS];
476
477 VkPipeline depth_only_pipeline[5];
478
479 VkPipeline stencil_only_pipeline[5];
480 } blit2d[1 + MAX_SAMPLES_LOG2];
481
482 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
483 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
484 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
485
486 struct {
487 VkPipelineLayout img_p_layout;
488 VkDescriptorSetLayout img_ds_layout;
489 VkPipeline pipeline;
490 VkPipeline pipeline_3d;
491 } itob;
492 struct {
493 VkPipelineLayout img_p_layout;
494 VkDescriptorSetLayout img_ds_layout;
495 VkPipeline pipeline;
496 VkPipeline pipeline_3d;
497 } btoi;
498 struct {
499 VkPipelineLayout img_p_layout;
500 VkDescriptorSetLayout img_ds_layout;
501 VkPipeline pipeline;
502 VkPipeline pipeline_3d;
503 } itoi;
504 struct {
505 VkPipelineLayout img_p_layout;
506 VkDescriptorSetLayout img_ds_layout;
507 VkPipeline pipeline;
508 VkPipeline pipeline_3d;
509 } cleari;
510
511 struct {
512 VkPipelineLayout p_layout;
513 VkPipeline pipeline[NUM_META_FS_KEYS];
514 VkRenderPass pass[NUM_META_FS_KEYS];
515 } resolve;
516
517 struct {
518 VkDescriptorSetLayout ds_layout;
519 VkPipelineLayout p_layout;
520 struct {
521 VkPipeline pipeline;
522 VkPipeline i_pipeline;
523 VkPipeline srgb_pipeline;
524 } rc[MAX_SAMPLES_LOG2];
525 } resolve_compute;
526
527 struct {
528 VkDescriptorSetLayout ds_layout;
529 VkPipelineLayout p_layout;
530
531 struct {
532 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
533 VkPipeline pipeline[NUM_META_FS_KEYS];
534 } rc[MAX_SAMPLES_LOG2];
535 } resolve_fragment;
536
537 struct {
538 VkPipelineLayout p_layout;
539 VkPipeline decompress_pipeline;
540 VkPipeline resummarize_pipeline;
541 VkRenderPass pass;
542 } depth_decomp[1 + MAX_SAMPLES_LOG2];
543
544 struct {
545 VkPipelineLayout p_layout;
546 VkPipeline cmask_eliminate_pipeline;
547 VkPipeline fmask_decompress_pipeline;
548 VkPipeline dcc_decompress_pipeline;
549 VkRenderPass pass;
550
551 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
552 VkPipelineLayout dcc_decompress_compute_p_layout;
553 VkPipeline dcc_decompress_compute_pipeline;
554 } fast_clear_flush;
555
556 struct {
557 VkPipelineLayout fill_p_layout;
558 VkPipelineLayout copy_p_layout;
559 VkDescriptorSetLayout fill_ds_layout;
560 VkDescriptorSetLayout copy_ds_layout;
561 VkPipeline fill_pipeline;
562 VkPipeline copy_pipeline;
563 } buffer;
564
565 struct {
566 VkDescriptorSetLayout ds_layout;
567 VkPipelineLayout p_layout;
568 VkPipeline occlusion_query_pipeline;
569 VkPipeline pipeline_statistics_query_pipeline;
570 } query;
571 };
572
573 /* queue types */
574 #define RADV_QUEUE_GENERAL 0
575 #define RADV_QUEUE_COMPUTE 1
576 #define RADV_QUEUE_TRANSFER 2
577
578 #define RADV_MAX_QUEUE_FAMILIES 3
579
580 enum ring_type radv_queue_family_to_ring(int f);
581
582 struct radv_queue {
583 VK_LOADER_DATA _loader_data;
584 struct radv_device * device;
585 struct radeon_winsys_ctx *hw_ctx;
586 enum radeon_ctx_priority priority;
587 uint32_t queue_family_index;
588 int queue_idx;
589 VkDeviceQueueCreateFlags flags;
590
591 uint32_t scratch_size;
592 uint32_t compute_scratch_size;
593 uint32_t esgs_ring_size;
594 uint32_t gsvs_ring_size;
595 bool has_tess_rings;
596 bool has_sample_positions;
597
598 struct radeon_winsys_bo *scratch_bo;
599 struct radeon_winsys_bo *descriptor_bo;
600 struct radeon_winsys_bo *compute_scratch_bo;
601 struct radeon_winsys_bo *esgs_ring_bo;
602 struct radeon_winsys_bo *gsvs_ring_bo;
603 struct radeon_winsys_bo *tess_rings_bo;
604 struct radeon_cmdbuf *initial_preamble_cs;
605 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
606 struct radeon_cmdbuf *continue_preamble_cs;
607 };
608
609 struct radv_bo_list {
610 struct radv_winsys_bo_list list;
611 unsigned capacity;
612 pthread_mutex_t mutex;
613 };
614
615 struct radv_device {
616 VK_LOADER_DATA _loader_data;
617
618 VkAllocationCallbacks alloc;
619
620 struct radv_instance * instance;
621 struct radeon_winsys *ws;
622
623 struct radv_meta_state meta_state;
624
625 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
626 int queue_count[RADV_MAX_QUEUE_FAMILIES];
627 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
628
629 bool always_use_syncobj;
630 bool has_distributed_tess;
631 bool pbb_allowed;
632 bool dfsm_allowed;
633 uint32_t tess_offchip_block_dw_size;
634 uint32_t scratch_waves;
635 uint32_t dispatch_initiator;
636
637 uint32_t gs_table_depth;
638
639 /* MSAA sample locations.
640 * The first index is the sample index.
641 * The second index is the coordinate: X, Y. */
642 float sample_locations_1x[1][2];
643 float sample_locations_2x[2][2];
644 float sample_locations_4x[4][2];
645 float sample_locations_8x[8][2];
646 float sample_locations_16x[16][2];
647
648 /* CIK and later */
649 uint32_t gfx_init_size_dw;
650 struct radeon_winsys_bo *gfx_init;
651
652 struct radeon_winsys_bo *trace_bo;
653 uint32_t *trace_id_ptr;
654
655 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
656 bool keep_shader_info;
657
658 struct radv_physical_device *physical_device;
659
660 /* Backup in-memory cache to be used if the app doesn't provide one */
661 struct radv_pipeline_cache * mem_cache;
662
663 /*
664 * use different counters so MSAA MRTs get consecutive surface indices,
665 * even if MASK is allocated in between.
666 */
667 uint32_t image_mrt_offset_counter;
668 uint32_t fmask_mrt_offset_counter;
669 struct list_head shader_slabs;
670 mtx_t shader_slab_mutex;
671
672 /* For detecting VM faults reported by dmesg. */
673 uint64_t dmesg_timestamp;
674
675 struct radv_device_extension_table enabled_extensions;
676
677 /* Whether the driver uses a global BO list. */
678 bool use_global_bo_list;
679
680 struct radv_bo_list bo_list;
681 };
682
683 struct radv_device_memory {
684 struct radeon_winsys_bo *bo;
685 /* for dedicated allocations */
686 struct radv_image *image;
687 struct radv_buffer *buffer;
688 uint32_t type_index;
689 VkDeviceSize map_size;
690 void * map;
691 void * user_ptr;
692 };
693
694
695 struct radv_descriptor_range {
696 uint64_t va;
697 uint32_t size;
698 };
699
700 struct radv_descriptor_set {
701 const struct radv_descriptor_set_layout *layout;
702 uint32_t size;
703
704 struct radeon_winsys_bo *bo;
705 uint64_t va;
706 uint32_t *mapped_ptr;
707 struct radv_descriptor_range *dynamic_descriptors;
708
709 struct radeon_winsys_bo *descriptors[0];
710 };
711
712 struct radv_push_descriptor_set
713 {
714 struct radv_descriptor_set set;
715 uint32_t capacity;
716 };
717
718 struct radv_descriptor_pool_entry {
719 uint32_t offset;
720 uint32_t size;
721 struct radv_descriptor_set *set;
722 };
723
724 struct radv_descriptor_pool {
725 struct radeon_winsys_bo *bo;
726 uint8_t *mapped_ptr;
727 uint64_t current_offset;
728 uint64_t size;
729
730 uint8_t *host_memory_base;
731 uint8_t *host_memory_ptr;
732 uint8_t *host_memory_end;
733
734 uint32_t entry_count;
735 uint32_t max_entry_count;
736 struct radv_descriptor_pool_entry entries[0];
737 };
738
739 struct radv_descriptor_update_template_entry {
740 VkDescriptorType descriptor_type;
741
742 /* The number of descriptors to update */
743 uint32_t descriptor_count;
744
745 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
746 uint32_t dst_offset;
747
748 /* In dwords. Not valid/used for dynamic descriptors */
749 uint32_t dst_stride;
750
751 uint32_t buffer_offset;
752
753 /* Only valid for combined image samplers and samplers */
754 uint16_t has_sampler;
755
756 /* In bytes */
757 size_t src_offset;
758 size_t src_stride;
759
760 /* For push descriptors */
761 const uint32_t *immutable_samplers;
762 };
763
764 struct radv_descriptor_update_template {
765 uint32_t entry_count;
766 VkPipelineBindPoint bind_point;
767 struct radv_descriptor_update_template_entry entry[0];
768 };
769
770 struct radv_buffer {
771 VkDeviceSize size;
772
773 VkBufferUsageFlags usage;
774 VkBufferCreateFlags flags;
775
776 /* Set when bound */
777 struct radeon_winsys_bo * bo;
778 VkDeviceSize offset;
779
780 bool shareable;
781 };
782
783 enum radv_dynamic_state_bits {
784 RADV_DYNAMIC_VIEWPORT = 1 << 0,
785 RADV_DYNAMIC_SCISSOR = 1 << 1,
786 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
787 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
788 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
789 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
790 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
791 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
792 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
793 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
794 RADV_DYNAMIC_ALL = (1 << 10) - 1,
795 };
796
797 enum radv_cmd_dirty_bits {
798 /* Keep the dynamic state dirty bits in sync with
799 * enum radv_dynamic_state_bits */
800 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
801 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
802 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
803 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
804 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
805 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
807 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
808 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
809 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
810 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
811 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
812 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
813 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
814 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
815 };
816
817 enum radv_cmd_flush_bits {
818 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
819 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
820 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
821 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
822 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
823 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
824 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
825 /* Same as above, but only writes back and doesn't invalidate */
826 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
827 /* Framebuffer caches */
828 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
829 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
830 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
831 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
832 /* Engine synchronization. */
833 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
834 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
835 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
836 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
837 /* Pipeline query controls. */
838 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
839 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
840
841 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
842 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
843 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
844 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
845 };
846
847 struct radv_vertex_binding {
848 struct radv_buffer * buffer;
849 VkDeviceSize offset;
850 };
851
852 struct radv_viewport_state {
853 uint32_t count;
854 VkViewport viewports[MAX_VIEWPORTS];
855 };
856
857 struct radv_scissor_state {
858 uint32_t count;
859 VkRect2D scissors[MAX_SCISSORS];
860 };
861
862 struct radv_discard_rectangle_state {
863 uint32_t count;
864 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
865 };
866
867 struct radv_dynamic_state {
868 /**
869 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
870 * Defines the set of saved dynamic state.
871 */
872 uint32_t mask;
873
874 struct radv_viewport_state viewport;
875
876 struct radv_scissor_state scissor;
877
878 float line_width;
879
880 struct {
881 float bias;
882 float clamp;
883 float slope;
884 } depth_bias;
885
886 float blend_constants[4];
887
888 struct {
889 float min;
890 float max;
891 } depth_bounds;
892
893 struct {
894 uint32_t front;
895 uint32_t back;
896 } stencil_compare_mask;
897
898 struct {
899 uint32_t front;
900 uint32_t back;
901 } stencil_write_mask;
902
903 struct {
904 uint32_t front;
905 uint32_t back;
906 } stencil_reference;
907
908 struct radv_discard_rectangle_state discard_rectangle;
909 };
910
911 extern const struct radv_dynamic_state default_dynamic_state;
912
913 const char *
914 radv_get_debug_option_name(int id);
915
916 const char *
917 radv_get_perftest_option_name(int id);
918
919 /**
920 * Attachment state when recording a renderpass instance.
921 *
922 * The clear value is valid only if there exists a pending clear.
923 */
924 struct radv_attachment_state {
925 VkImageAspectFlags pending_clear_aspects;
926 uint32_t cleared_views;
927 VkClearValue clear_value;
928 VkImageLayout current_layout;
929 };
930
931 struct radv_descriptor_state {
932 struct radv_descriptor_set *sets[MAX_SETS];
933 uint32_t dirty;
934 uint32_t valid;
935 struct radv_push_descriptor_set push_set;
936 bool push_dirty;
937 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
938 };
939
940 struct radv_cmd_state {
941 /* Vertex descriptors */
942 uint64_t vb_va;
943 unsigned vb_size;
944
945 bool predicating;
946 uint32_t dirty;
947
948 uint32_t prefetch_L2_mask;
949
950 struct radv_pipeline * pipeline;
951 struct radv_pipeline * emitted_pipeline;
952 struct radv_pipeline * compute_pipeline;
953 struct radv_pipeline * emitted_compute_pipeline;
954 struct radv_framebuffer * framebuffer;
955 struct radv_render_pass * pass;
956 const struct radv_subpass * subpass;
957 struct radv_dynamic_state dynamic;
958 struct radv_attachment_state * attachments;
959 VkRect2D render_area;
960
961 /* Index buffer */
962 struct radv_buffer *index_buffer;
963 uint64_t index_offset;
964 uint32_t index_type;
965 uint32_t max_index_count;
966 uint64_t index_va;
967 int32_t last_index_type;
968
969 int32_t last_primitive_reset_en;
970 uint32_t last_primitive_reset_index;
971 enum radv_cmd_flush_bits flush_bits;
972 unsigned active_occlusion_queries;
973 bool perfect_occlusion_queries_enabled;
974 unsigned active_pipeline_queries;
975 float offset_scale;
976 uint32_t trace_id;
977 uint32_t last_ia_multi_vgt_param;
978
979 uint32_t last_num_instances;
980 uint32_t last_first_instance;
981 uint32_t last_vertex_offset;
982
983 /* Whether CP DMA is busy/idle. */
984 bool dma_is_busy;
985 };
986
987 struct radv_cmd_pool {
988 VkAllocationCallbacks alloc;
989 struct list_head cmd_buffers;
990 struct list_head free_cmd_buffers;
991 uint32_t queue_family_index;
992 };
993
994 struct radv_cmd_buffer_upload {
995 uint8_t *map;
996 unsigned offset;
997 uint64_t size;
998 struct radeon_winsys_bo *upload_bo;
999 struct list_head list;
1000 };
1001
1002 enum radv_cmd_buffer_status {
1003 RADV_CMD_BUFFER_STATUS_INVALID,
1004 RADV_CMD_BUFFER_STATUS_INITIAL,
1005 RADV_CMD_BUFFER_STATUS_RECORDING,
1006 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1007 RADV_CMD_BUFFER_STATUS_PENDING,
1008 };
1009
1010 struct radv_cmd_buffer {
1011 VK_LOADER_DATA _loader_data;
1012
1013 struct radv_device * device;
1014
1015 struct radv_cmd_pool * pool;
1016 struct list_head pool_link;
1017
1018 VkCommandBufferUsageFlags usage_flags;
1019 VkCommandBufferLevel level;
1020 enum radv_cmd_buffer_status status;
1021 struct radeon_cmdbuf *cs;
1022 struct radv_cmd_state state;
1023 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1024 uint32_t queue_family_index;
1025
1026 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1027 VkShaderStageFlags push_constant_stages;
1028 struct radv_descriptor_set meta_push_descriptors;
1029
1030 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1031
1032 struct radv_cmd_buffer_upload upload;
1033
1034 uint32_t scratch_size_needed;
1035 uint32_t compute_scratch_size_needed;
1036 uint32_t esgs_ring_size_needed;
1037 uint32_t gsvs_ring_size_needed;
1038 bool tess_rings_needed;
1039 bool sample_positions_needed;
1040
1041 VkResult record_result;
1042
1043 int ring_offsets_idx; /* just used for verification */
1044 uint32_t gfx9_fence_offset;
1045 struct radeon_winsys_bo *gfx9_fence_bo;
1046 uint32_t gfx9_fence_idx;
1047 uint64_t gfx9_eop_bug_va;
1048
1049 /**
1050 * Whether a query pool has been resetted and we have to flush caches.
1051 */
1052 bool pending_reset_query;
1053 };
1054
1055 struct radv_image;
1056
1057 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1058
1059 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1060 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1061
1062 void cik_create_gfx_config(struct radv_device *device);
1063
1064 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1065 int count, const VkViewport *viewports);
1066 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1067 int count, const VkRect2D *scissors,
1068 const VkViewport *viewports, bool can_use_guardband);
1069 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1070 bool instanced_draw, bool indirect_draw,
1071 uint32_t draw_vertex_count);
1072 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1073 enum chip_class chip_class,
1074 bool is_mec,
1075 unsigned event, unsigned event_flags,
1076 unsigned data_sel,
1077 uint64_t va,
1078 uint32_t old_fence,
1079 uint32_t new_fence,
1080 uint64_t gfx9_eop_bug_va);
1081
1082 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1083 uint64_t va, uint32_t ref,
1084 uint32_t mask);
1085 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1086 enum chip_class chip_class,
1087 uint32_t *fence_ptr, uint64_t va,
1088 bool is_mec,
1089 enum radv_cmd_flush_bits flush_bits,
1090 uint64_t gfx9_eop_bug_va);
1091 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1092 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1093 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1094 uint64_t src_va, uint64_t dest_va,
1095 uint64_t size);
1096 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1097 unsigned size);
1098 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1099 uint64_t size, unsigned value);
1100 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1101
1102 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1103 bool
1104 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1105 unsigned size,
1106 unsigned alignment,
1107 unsigned *out_offset,
1108 void **ptr);
1109 void
1110 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1111 const struct radv_subpass *subpass,
1112 bool transitions);
1113 bool
1114 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1115 unsigned size, unsigned alignmnet,
1116 const void *data, unsigned *out_offset);
1117
1118 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1119 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1120 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1121 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1122 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1123 unsigned radv_cayman_get_maxdist(int log_samples);
1124 void radv_device_init_msaa(struct radv_device *device);
1125
1126 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1127 struct radv_image *image,
1128 VkClearDepthStencilValue ds_clear_value,
1129 VkImageAspectFlags aspects);
1130
1131 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1132 struct radv_image *image,
1133 int cb_idx,
1134 uint32_t color_values[2]);
1135
1136 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1137 struct radv_image *image,
1138 bool value);
1139 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1140 struct radeon_winsys_bo *bo,
1141 uint64_t offset, uint64_t size, uint32_t value);
1142 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1143 bool radv_get_memory_fd(struct radv_device *device,
1144 struct radv_device_memory *memory,
1145 int *pFD);
1146
1147 static inline void
1148 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1149 unsigned sh_offset, unsigned pointer_count,
1150 bool use_32bit_pointers)
1151 {
1152 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1153 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1154 }
1155
1156 static inline void
1157 radv_emit_shader_pointer_body(struct radv_device *device,
1158 struct radeon_cmdbuf *cs,
1159 uint64_t va, bool use_32bit_pointers)
1160 {
1161 radeon_emit(cs, va);
1162
1163 if (use_32bit_pointers) {
1164 assert(va == 0 ||
1165 (va >> 32) == device->physical_device->rad_info.address32_hi);
1166 } else {
1167 radeon_emit(cs, va >> 32);
1168 }
1169 }
1170
1171 static inline void
1172 radv_emit_shader_pointer(struct radv_device *device,
1173 struct radeon_cmdbuf *cs,
1174 uint32_t sh_offset, uint64_t va, bool global)
1175 {
1176 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1177
1178 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1179 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1180 }
1181
1182 static inline struct radv_descriptor_state *
1183 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1184 VkPipelineBindPoint bind_point)
1185 {
1186 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1187 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1188 return &cmd_buffer->descriptors[bind_point];
1189 }
1190
1191 /*
1192 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1193 *
1194 * Limitations: Can't call normal dispatch functions without binding or rebinding
1195 * the compute pipeline.
1196 */
1197 void radv_unaligned_dispatch(
1198 struct radv_cmd_buffer *cmd_buffer,
1199 uint32_t x,
1200 uint32_t y,
1201 uint32_t z);
1202
1203 struct radv_event {
1204 struct radeon_winsys_bo *bo;
1205 uint64_t *map;
1206 };
1207
1208 struct radv_shader_module;
1209
1210 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1211 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1212 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1213 void
1214 radv_hash_shaders(unsigned char *hash,
1215 const VkPipelineShaderStageCreateInfo **stages,
1216 const struct radv_pipeline_layout *layout,
1217 const struct radv_pipeline_key *key,
1218 uint32_t flags);
1219
1220 static inline gl_shader_stage
1221 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1222 {
1223 assert(__builtin_popcount(vk_stage) == 1);
1224 return ffs(vk_stage) - 1;
1225 }
1226
1227 static inline VkShaderStageFlagBits
1228 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1229 {
1230 return (1 << mesa_stage);
1231 }
1232
1233 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1234
1235 #define radv_foreach_stage(stage, stage_bits) \
1236 for (gl_shader_stage stage, \
1237 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1238 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1239 __tmp &= ~(1 << (stage)))
1240
1241 unsigned radv_format_meta_fs_key(VkFormat format);
1242
1243 struct radv_multisample_state {
1244 uint32_t db_eqaa;
1245 uint32_t pa_sc_line_cntl;
1246 uint32_t pa_sc_mode_cntl_0;
1247 uint32_t pa_sc_mode_cntl_1;
1248 uint32_t pa_sc_aa_config;
1249 uint32_t pa_sc_aa_mask[2];
1250 unsigned num_samples;
1251 };
1252
1253 struct radv_prim_vertex_count {
1254 uint8_t min;
1255 uint8_t incr;
1256 };
1257
1258 struct radv_vertex_elements_info {
1259 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1260 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1261 uint32_t binding[MAX_VERTEX_ATTRIBS];
1262 uint32_t offset[MAX_VERTEX_ATTRIBS];
1263 uint32_t count;
1264 };
1265
1266 struct radv_ia_multi_vgt_param_helpers {
1267 uint32_t base;
1268 bool partial_es_wave;
1269 uint8_t primgroup_size;
1270 bool wd_switch_on_eop;
1271 bool ia_switch_on_eoi;
1272 bool partial_vs_wave;
1273 };
1274
1275 #define SI_GS_PER_ES 128
1276
1277 struct radv_pipeline {
1278 struct radv_device * device;
1279 struct radv_dynamic_state dynamic_state;
1280
1281 struct radv_pipeline_layout * layout;
1282
1283 bool need_indirect_descriptor_sets;
1284 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1285 struct radv_shader_variant *gs_copy_shader;
1286 VkShaderStageFlags active_stages;
1287
1288 struct radeon_cmdbuf cs;
1289
1290 struct radv_vertex_elements_info vertex_elements;
1291
1292 uint32_t binding_stride[MAX_VBS];
1293
1294 uint32_t user_data_0[MESA_SHADER_STAGES];
1295 union {
1296 struct {
1297 struct radv_multisample_state ms;
1298 uint32_t spi_baryc_cntl;
1299 bool prim_restart_enable;
1300 unsigned esgs_ring_size;
1301 unsigned gsvs_ring_size;
1302 uint32_t vtx_base_sgpr;
1303 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1304 uint8_t vtx_emit_num;
1305 struct radv_prim_vertex_count prim_vertex_count;
1306 bool can_use_guardband;
1307 uint32_t needed_dynamic_state;
1308 bool disable_out_of_order_rast_for_occlusion;
1309
1310 /* Used for rbplus */
1311 uint32_t col_format;
1312 uint32_t cb_target_mask;
1313 } graphics;
1314 };
1315
1316 unsigned max_waves;
1317 unsigned scratch_bytes_per_wave;
1318 };
1319
1320 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1321 {
1322 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1323 }
1324
1325 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1326 {
1327 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1328 }
1329
1330 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1331 gl_shader_stage stage,
1332 int idx);
1333
1334 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1335 gl_shader_stage stage);
1336
1337 struct radv_graphics_pipeline_create_info {
1338 bool use_rectlist;
1339 bool db_depth_clear;
1340 bool db_stencil_clear;
1341 bool db_depth_disable_expclear;
1342 bool db_stencil_disable_expclear;
1343 bool db_flush_depth_inplace;
1344 bool db_flush_stencil_inplace;
1345 bool db_resummarize;
1346 uint32_t custom_blend_mode;
1347 };
1348
1349 VkResult
1350 radv_graphics_pipeline_create(VkDevice device,
1351 VkPipelineCache cache,
1352 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1353 const struct radv_graphics_pipeline_create_info *extra,
1354 const VkAllocationCallbacks *alloc,
1355 VkPipeline *pPipeline);
1356
1357 struct vk_format_description;
1358 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1359 int first_non_void);
1360 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1361 int first_non_void);
1362 uint32_t radv_translate_colorformat(VkFormat format);
1363 uint32_t radv_translate_color_numformat(VkFormat format,
1364 const struct vk_format_description *desc,
1365 int first_non_void);
1366 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1367 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1368 uint32_t radv_translate_dbformat(VkFormat format);
1369 uint32_t radv_translate_tex_dataformat(VkFormat format,
1370 const struct vk_format_description *desc,
1371 int first_non_void);
1372 uint32_t radv_translate_tex_numformat(VkFormat format,
1373 const struct vk_format_description *desc,
1374 int first_non_void);
1375 bool radv_format_pack_clear_color(VkFormat format,
1376 uint32_t clear_vals[2],
1377 VkClearColorValue *value);
1378 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1379 bool radv_dcc_formats_compatible(VkFormat format1,
1380 VkFormat format2);
1381
1382 struct radv_fmask_info {
1383 uint64_t offset;
1384 uint64_t size;
1385 unsigned alignment;
1386 unsigned pitch_in_pixels;
1387 unsigned bank_height;
1388 unsigned slice_tile_max;
1389 unsigned tile_mode_index;
1390 unsigned tile_swizzle;
1391 };
1392
1393 struct radv_cmask_info {
1394 uint64_t offset;
1395 uint64_t size;
1396 unsigned alignment;
1397 unsigned slice_tile_max;
1398 };
1399
1400 struct radv_image {
1401 VkImageType type;
1402 /* The original VkFormat provided by the client. This may not match any
1403 * of the actual surface formats.
1404 */
1405 VkFormat vk_format;
1406 VkImageAspectFlags aspects;
1407 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1408 struct ac_surf_info info;
1409 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1410 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1411
1412 VkDeviceSize size;
1413 uint32_t alignment;
1414
1415 unsigned queue_family_mask;
1416 bool exclusive;
1417 bool shareable;
1418
1419 /* Set when bound */
1420 struct radeon_winsys_bo *bo;
1421 VkDeviceSize offset;
1422 uint64_t dcc_offset;
1423 uint64_t htile_offset;
1424 bool tc_compatible_htile;
1425 struct radeon_surf surface;
1426
1427 struct radv_fmask_info fmask;
1428 struct radv_cmask_info cmask;
1429 uint64_t clear_value_offset;
1430 uint64_t dcc_pred_offset;
1431
1432 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1433 VkDeviceMemory owned_memory;
1434 };
1435
1436 /* Whether the image has a htile that is known consistent with the contents of
1437 * the image. */
1438 bool radv_layout_has_htile(const struct radv_image *image,
1439 VkImageLayout layout,
1440 unsigned queue_mask);
1441
1442 /* Whether the image has a htile that is known consistent with the contents of
1443 * the image and is allowed to be in compressed form.
1444 *
1445 * If this is false reads that don't use the htile should be able to return
1446 * correct results.
1447 */
1448 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1449 VkImageLayout layout,
1450 unsigned queue_mask);
1451
1452 bool radv_layout_can_fast_clear(const struct radv_image *image,
1453 VkImageLayout layout,
1454 unsigned queue_mask);
1455
1456 bool radv_layout_dcc_compressed(const struct radv_image *image,
1457 VkImageLayout layout,
1458 unsigned queue_mask);
1459
1460 /**
1461 * Return whether the image has CMASK metadata for color surfaces.
1462 */
1463 static inline bool
1464 radv_image_has_cmask(const struct radv_image *image)
1465 {
1466 return image->cmask.size;
1467 }
1468
1469 /**
1470 * Return whether the image has FMASK metadata for color surfaces.
1471 */
1472 static inline bool
1473 radv_image_has_fmask(const struct radv_image *image)
1474 {
1475 return image->fmask.size;
1476 }
1477
1478 /**
1479 * Return whether the image has DCC metadata for color surfaces.
1480 */
1481 static inline bool
1482 radv_image_has_dcc(const struct radv_image *image)
1483 {
1484 return image->surface.dcc_size;
1485 }
1486
1487 /**
1488 * Return whether DCC metadata is enabled for a level.
1489 */
1490 static inline bool
1491 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1492 {
1493 return radv_image_has_dcc(image) &&
1494 level < image->surface.num_dcc_levels;
1495 }
1496
1497 /**
1498 * Return whether the image has CB metadata.
1499 */
1500 static inline bool
1501 radv_image_has_CB_metadata(const struct radv_image *image)
1502 {
1503 return radv_image_has_cmask(image) ||
1504 radv_image_has_fmask(image) ||
1505 radv_image_has_dcc(image);
1506 }
1507
1508 /**
1509 * Return whether the image has HTILE metadata for depth surfaces.
1510 */
1511 static inline bool
1512 radv_image_has_htile(const struct radv_image *image)
1513 {
1514 return image->surface.htile_size;
1515 }
1516
1517 /**
1518 * Return whether HTILE metadata is enabled for a level.
1519 */
1520 static inline bool
1521 radv_htile_enabled(const struct radv_image *image, unsigned level)
1522 {
1523 return radv_image_has_htile(image) && level == 0;
1524 }
1525
1526 /**
1527 * Return whether the image is TC-compatible HTILE.
1528 */
1529 static inline bool
1530 radv_image_is_tc_compat_htile(const struct radv_image *image)
1531 {
1532 return radv_image_has_htile(image) && image->tc_compatible_htile;
1533 }
1534
1535 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1536
1537 static inline uint32_t
1538 radv_get_layerCount(const struct radv_image *image,
1539 const VkImageSubresourceRange *range)
1540 {
1541 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1542 image->info.array_size - range->baseArrayLayer : range->layerCount;
1543 }
1544
1545 static inline uint32_t
1546 radv_get_levelCount(const struct radv_image *image,
1547 const VkImageSubresourceRange *range)
1548 {
1549 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1550 image->info.levels - range->baseMipLevel : range->levelCount;
1551 }
1552
1553 struct radeon_bo_metadata;
1554 void
1555 radv_init_metadata(struct radv_device *device,
1556 struct radv_image *image,
1557 struct radeon_bo_metadata *metadata);
1558
1559 struct radv_image_view {
1560 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1561 struct radeon_winsys_bo *bo;
1562
1563 VkImageViewType type;
1564 VkImageAspectFlags aspect_mask;
1565 VkFormat vk_format;
1566 uint32_t base_layer;
1567 uint32_t layer_count;
1568 uint32_t base_mip;
1569 uint32_t level_count;
1570 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1571
1572 uint32_t descriptor[16];
1573
1574 /* Descriptor for use as a storage image as opposed to a sampled image.
1575 * This has a few differences for cube maps (e.g. type).
1576 */
1577 uint32_t storage_descriptor[16];
1578 };
1579
1580 struct radv_image_create_info {
1581 const VkImageCreateInfo *vk_info;
1582 bool scanout;
1583 bool no_metadata_planes;
1584 };
1585
1586 VkResult radv_image_create(VkDevice _device,
1587 const struct radv_image_create_info *info,
1588 const VkAllocationCallbacks* alloc,
1589 VkImage *pImage);
1590
1591 VkResult
1592 radv_image_from_gralloc(VkDevice device_h,
1593 const VkImageCreateInfo *base_info,
1594 const VkNativeBufferANDROID *gralloc_info,
1595 const VkAllocationCallbacks *alloc,
1596 VkImage *out_image_h);
1597
1598 void radv_image_view_init(struct radv_image_view *view,
1599 struct radv_device *device,
1600 const VkImageViewCreateInfo* pCreateInfo);
1601
1602 struct radv_buffer_view {
1603 struct radeon_winsys_bo *bo;
1604 VkFormat vk_format;
1605 uint64_t range; /**< VkBufferViewCreateInfo::range */
1606 uint32_t state[4];
1607 };
1608 void radv_buffer_view_init(struct radv_buffer_view *view,
1609 struct radv_device *device,
1610 const VkBufferViewCreateInfo* pCreateInfo);
1611
1612 static inline struct VkExtent3D
1613 radv_sanitize_image_extent(const VkImageType imageType,
1614 const struct VkExtent3D imageExtent)
1615 {
1616 switch (imageType) {
1617 case VK_IMAGE_TYPE_1D:
1618 return (VkExtent3D) { imageExtent.width, 1, 1 };
1619 case VK_IMAGE_TYPE_2D:
1620 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1621 case VK_IMAGE_TYPE_3D:
1622 return imageExtent;
1623 default:
1624 unreachable("invalid image type");
1625 }
1626 }
1627
1628 static inline struct VkOffset3D
1629 radv_sanitize_image_offset(const VkImageType imageType,
1630 const struct VkOffset3D imageOffset)
1631 {
1632 switch (imageType) {
1633 case VK_IMAGE_TYPE_1D:
1634 return (VkOffset3D) { imageOffset.x, 0, 0 };
1635 case VK_IMAGE_TYPE_2D:
1636 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1637 case VK_IMAGE_TYPE_3D:
1638 return imageOffset;
1639 default:
1640 unreachable("invalid image type");
1641 }
1642 }
1643
1644 static inline bool
1645 radv_image_extent_compare(const struct radv_image *image,
1646 const VkExtent3D *extent)
1647 {
1648 if (extent->width != image->info.width ||
1649 extent->height != image->info.height ||
1650 extent->depth != image->info.depth)
1651 return false;
1652 return true;
1653 }
1654
1655 struct radv_sampler {
1656 uint32_t state[4];
1657 };
1658
1659 struct radv_color_buffer_info {
1660 uint64_t cb_color_base;
1661 uint64_t cb_color_cmask;
1662 uint64_t cb_color_fmask;
1663 uint64_t cb_dcc_base;
1664 uint32_t cb_color_pitch;
1665 uint32_t cb_color_slice;
1666 uint32_t cb_color_view;
1667 uint32_t cb_color_info;
1668 uint32_t cb_color_attrib;
1669 uint32_t cb_color_attrib2;
1670 uint32_t cb_dcc_control;
1671 uint32_t cb_color_cmask_slice;
1672 uint32_t cb_color_fmask_slice;
1673 };
1674
1675 struct radv_ds_buffer_info {
1676 uint64_t db_z_read_base;
1677 uint64_t db_stencil_read_base;
1678 uint64_t db_z_write_base;
1679 uint64_t db_stencil_write_base;
1680 uint64_t db_htile_data_base;
1681 uint32_t db_depth_info;
1682 uint32_t db_z_info;
1683 uint32_t db_stencil_info;
1684 uint32_t db_depth_view;
1685 uint32_t db_depth_size;
1686 uint32_t db_depth_slice;
1687 uint32_t db_htile_surface;
1688 uint32_t pa_su_poly_offset_db_fmt_cntl;
1689 uint32_t db_z_info2;
1690 uint32_t db_stencil_info2;
1691 float offset_scale;
1692 };
1693
1694 struct radv_attachment_info {
1695 union {
1696 struct radv_color_buffer_info cb;
1697 struct radv_ds_buffer_info ds;
1698 };
1699 struct radv_image_view *attachment;
1700 };
1701
1702 struct radv_framebuffer {
1703 uint32_t width;
1704 uint32_t height;
1705 uint32_t layers;
1706
1707 uint32_t attachment_count;
1708 struct radv_attachment_info attachments[0];
1709 };
1710
1711 struct radv_subpass_barrier {
1712 VkPipelineStageFlags src_stage_mask;
1713 VkAccessFlags src_access_mask;
1714 VkAccessFlags dst_access_mask;
1715 };
1716
1717 struct radv_subpass_attachment {
1718 uint32_t attachment;
1719 VkImageLayout layout;
1720 };
1721
1722 struct radv_subpass {
1723 uint32_t input_count;
1724 uint32_t color_count;
1725 struct radv_subpass_attachment * input_attachments;
1726 struct radv_subpass_attachment * color_attachments;
1727 struct radv_subpass_attachment * resolve_attachments;
1728 struct radv_subpass_attachment depth_stencil_attachment;
1729
1730 /** Subpass has at least one resolve attachment */
1731 bool has_resolve;
1732
1733 struct radv_subpass_barrier start_barrier;
1734
1735 uint32_t view_mask;
1736 VkSampleCountFlagBits max_sample_count;
1737 };
1738
1739 struct radv_render_pass_attachment {
1740 VkFormat format;
1741 uint32_t samples;
1742 VkAttachmentLoadOp load_op;
1743 VkAttachmentLoadOp stencil_load_op;
1744 VkImageLayout initial_layout;
1745 VkImageLayout final_layout;
1746 uint32_t view_mask;
1747 };
1748
1749 struct radv_render_pass {
1750 uint32_t attachment_count;
1751 uint32_t subpass_count;
1752 struct radv_subpass_attachment * subpass_attachments;
1753 struct radv_render_pass_attachment * attachments;
1754 struct radv_subpass_barrier end_barrier;
1755 struct radv_subpass subpasses[0];
1756 };
1757
1758 VkResult radv_device_init_meta(struct radv_device *device);
1759 void radv_device_finish_meta(struct radv_device *device);
1760
1761 struct radv_query_pool {
1762 struct radeon_winsys_bo *bo;
1763 uint32_t stride;
1764 uint32_t availability_offset;
1765 uint64_t size;
1766 char *ptr;
1767 VkQueryType type;
1768 uint32_t pipeline_stats_mask;
1769 };
1770
1771 struct radv_semaphore {
1772 /* use a winsys sem for non-exportable */
1773 struct radeon_winsys_sem *sem;
1774 uint32_t syncobj;
1775 uint32_t temp_syncobj;
1776 };
1777
1778 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1779 VkPipelineBindPoint bind_point,
1780 struct radv_descriptor_set *set,
1781 unsigned idx);
1782
1783 void
1784 radv_update_descriptor_sets(struct radv_device *device,
1785 struct radv_cmd_buffer *cmd_buffer,
1786 VkDescriptorSet overrideSet,
1787 uint32_t descriptorWriteCount,
1788 const VkWriteDescriptorSet *pDescriptorWrites,
1789 uint32_t descriptorCopyCount,
1790 const VkCopyDescriptorSet *pDescriptorCopies);
1791
1792 void
1793 radv_update_descriptor_set_with_template(struct radv_device *device,
1794 struct radv_cmd_buffer *cmd_buffer,
1795 struct radv_descriptor_set *set,
1796 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1797 const void *pData);
1798
1799 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1800 VkPipelineBindPoint pipelineBindPoint,
1801 VkPipelineLayout _layout,
1802 uint32_t set,
1803 uint32_t descriptorWriteCount,
1804 const VkWriteDescriptorSet *pDescriptorWrites);
1805
1806 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1807 struct radv_image *image, uint32_t value);
1808
1809 struct radv_fence {
1810 struct radeon_winsys_fence *fence;
1811 struct wsi_fence *fence_wsi;
1812 bool submitted;
1813 bool signalled;
1814
1815 uint32_t syncobj;
1816 uint32_t temp_syncobj;
1817 };
1818
1819 /* radv_nir_to_llvm.c */
1820 struct radv_shader_variant_info;
1821 struct radv_nir_compiler_options;
1822
1823 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1824 struct nir_shader *geom_shader,
1825 struct ac_shader_binary *binary,
1826 struct ac_shader_config *config,
1827 struct radv_shader_variant_info *shader_info,
1828 const struct radv_nir_compiler_options *option);
1829
1830 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1831 struct ac_shader_binary *binary,
1832 struct ac_shader_config *config,
1833 struct radv_shader_variant_info *shader_info,
1834 struct nir_shader *const *nir,
1835 int nir_count,
1836 const struct radv_nir_compiler_options *options);
1837
1838 /* radv_shader_info.h */
1839 struct radv_shader_info;
1840
1841 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1842 const struct radv_nir_compiler_options *options,
1843 struct radv_shader_info *info);
1844
1845 struct radeon_winsys_sem;
1846
1847 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1848 \
1849 static inline struct __radv_type * \
1850 __radv_type ## _from_handle(__VkType _handle) \
1851 { \
1852 return (struct __radv_type *) _handle; \
1853 } \
1854 \
1855 static inline __VkType \
1856 __radv_type ## _to_handle(struct __radv_type *_obj) \
1857 { \
1858 return (__VkType) _obj; \
1859 }
1860
1861 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1862 \
1863 static inline struct __radv_type * \
1864 __radv_type ## _from_handle(__VkType _handle) \
1865 { \
1866 return (struct __radv_type *)(uintptr_t) _handle; \
1867 } \
1868 \
1869 static inline __VkType \
1870 __radv_type ## _to_handle(struct __radv_type *_obj) \
1871 { \
1872 return (__VkType)(uintptr_t) _obj; \
1873 }
1874
1875 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1876 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1877
1878 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1879 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1880 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1881 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1882 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1883
1884 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1885 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1886 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1887 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1888 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1889 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1890 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1891 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1892 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1893 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1894 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1895 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1896 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1897 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1898 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1899 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1900 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1901 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1902 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1903 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1904 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1905
1906 #endif /* RADV_PRIVATE_H */