bb58fa700feade9ccac1c6352f46e807fa31d1ec
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorv(struct radv_instance *instance, const void *object,
198 VkDebugReportObjectTypeEXT type, VkResult error,
199 const char *file, int line, const char *format,
200 va_list args);
201
202 VkResult __vk_errorf(struct radv_instance *instance, const void *object,
203 VkDebugReportObjectTypeEXT type, VkResult error,
204 const char *file, int line, const char *format, ...)
205 radv_printflike(7, 8);
206
207 #define vk_error(instance, error) \
208 __vk_errorf(instance, NULL, \
209 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
210 error, __FILE__, __LINE__, NULL);
211 #define vk_errorf(instance, error, format, ...) \
212 __vk_errorf(instance, NULL, \
213 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT, \
214 error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220 void radv_logi(const char *format, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x) do {} while(0)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 int radv_get_instance_entrypoint_index(const char *name);
258 int radv_get_device_entrypoint_index(const char *name);
259 int radv_get_physical_device_entrypoint_index(const char *name);
260
261 const char *radv_get_instance_entry_name(int index);
262 const char *radv_get_physical_device_entry_name(int index);
263 const char *radv_get_device_entry_name(int index);
264
265 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
266 const struct radv_instance_extension_table *instance);
267 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
268 const struct radv_instance_extension_table *instance);
269 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
272
273 void *radv_lookup_entrypoint(const char *name);
274
275 struct radv_physical_device {
276 VK_LOADER_DATA _loader_data;
277
278 /* Link in radv_instance::physical_devices */
279 struct list_head link;
280
281 struct radv_instance * instance;
282
283 struct radeon_winsys *ws;
284 struct radeon_info rad_info;
285 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
286 uint8_t driver_uuid[VK_UUID_SIZE];
287 uint8_t device_uuid[VK_UUID_SIZE];
288 uint8_t cache_uuid[VK_UUID_SIZE];
289
290 int local_fd;
291 int master_fd;
292 struct wsi_device wsi_device;
293
294 bool out_of_order_rast_allowed;
295
296 /* Whether DCC should be enabled for MSAA textures. */
297 bool dcc_msaa_allowed;
298
299 /* Whether to enable NGG. */
300 bool use_ngg;
301
302 /* Whether to enable NGG GS. */
303 bool use_ngg_gs;
304
305 /* Whether to enable NGG streamout. */
306 bool use_ngg_streamout;
307
308 /* Number of threads per wave. */
309 uint8_t ps_wave_size;
310 uint8_t cs_wave_size;
311 uint8_t ge_wave_size;
312
313 /* Whether to use the LLVM compiler backend */
314 bool use_llvm;
315
316 /* This is the drivers on-disk cache used as a fallback as opposed to
317 * the pipeline cache defined by apps.
318 */
319 struct disk_cache * disk_cache;
320
321 VkPhysicalDeviceMemoryProperties memory_properties;
322 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
323 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
324
325 drmPciBusInfo bus_info;
326
327 struct radv_device_extension_table supported_extensions;
328 };
329
330 struct radv_instance {
331 struct vk_object_base base;
332
333 VkAllocationCallbacks alloc;
334
335 uint32_t apiVersion;
336
337 char * applicationName;
338 uint32_t applicationVersion;
339 char * engineName;
340 uint32_t engineVersion;
341
342 uint64_t debug_flags;
343 uint64_t perftest_flags;
344
345 struct vk_debug_report_instance debug_report_callbacks;
346
347 struct radv_instance_extension_table enabled_extensions;
348 struct radv_instance_dispatch_table dispatch;
349 struct radv_physical_device_dispatch_table physical_device_dispatch;
350 struct radv_device_dispatch_table device_dispatch;
351
352 bool physical_devices_enumerated;
353 struct list_head physical_devices;
354
355 struct driOptionCache dri_options;
356 struct driOptionCache available_dri_options;
357
358 /**
359 * Workarounds for game bugs.
360 */
361 bool enable_mrt_output_nan_fixup;
362 };
363
364 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
365 void radv_finish_wsi(struct radv_physical_device *physical_device);
366
367 bool radv_instance_extension_supported(const char *name);
368 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
369 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
370 const char *name);
371
372 struct cache_entry;
373
374 struct radv_pipeline_cache {
375 struct vk_object_base base;
376 struct radv_device * device;
377 pthread_mutex_t mutex;
378 VkPipelineCacheCreateFlags flags;
379
380 uint32_t total_size;
381 uint32_t table_size;
382 uint32_t kernel_count;
383 struct cache_entry ** hash_table;
384 bool modified;
385
386 VkAllocationCallbacks alloc;
387 };
388
389 struct radv_pipeline_key {
390 uint32_t instance_rate_inputs;
391 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
392 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
393 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
394 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
395 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
396 uint64_t vertex_alpha_adjust;
397 uint32_t vertex_post_shuffle;
398 unsigned tess_input_vertices;
399 uint32_t col_format;
400 uint32_t is_int8;
401 uint32_t is_int10;
402 uint8_t log2_ps_iter_samples;
403 uint8_t num_samples;
404 bool is_dual_src;
405 uint32_t has_multiview_view_index : 1;
406 uint32_t optimisations_disabled : 1;
407 uint8_t topology;
408
409 /* Non-zero if a required subgroup size is specified via
410 * VK_EXT_subgroup_size_control.
411 */
412 uint8_t compute_subgroup_size;
413 };
414
415 struct radv_shader_binary;
416 struct radv_shader_variant;
417
418 void
419 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
420 struct radv_device *device);
421 void
422 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
423 bool
424 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
425 const void *data, size_t size);
426
427 bool
428 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
429 struct radv_pipeline_cache *cache,
430 const unsigned char *sha1,
431 struct radv_shader_variant **variants,
432 bool *found_in_application_cache);
433
434 void
435 radv_pipeline_cache_insert_shaders(struct radv_device *device,
436 struct radv_pipeline_cache *cache,
437 const unsigned char *sha1,
438 struct radv_shader_variant **variants,
439 struct radv_shader_binary *const *binaries);
440
441 enum radv_blit_ds_layout {
442 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
443 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
444 RADV_BLIT_DS_LAYOUT_COUNT,
445 };
446
447 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
448 {
449 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
450 }
451
452 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
453 {
454 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
455 }
456
457 enum radv_meta_dst_layout {
458 RADV_META_DST_LAYOUT_GENERAL,
459 RADV_META_DST_LAYOUT_OPTIMAL,
460 RADV_META_DST_LAYOUT_COUNT,
461 };
462
463 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
464 {
465 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
466 }
467
468 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
469 {
470 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
471 }
472
473 struct radv_meta_state {
474 VkAllocationCallbacks alloc;
475
476 struct radv_pipeline_cache cache;
477
478 /*
479 * For on-demand pipeline creation, makes sure that
480 * only one thread tries to build a pipeline at the same time.
481 */
482 mtx_t mtx;
483
484 /**
485 * Use array element `i` for images with `2^i` samples.
486 */
487 struct {
488 VkRenderPass render_pass[NUM_META_FS_KEYS];
489 VkPipeline color_pipelines[NUM_META_FS_KEYS];
490
491 VkRenderPass depthstencil_rp;
492 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
493 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
494 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
495
496 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
497 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
498 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
499 } clear[MAX_SAMPLES_LOG2];
500
501 VkPipelineLayout clear_color_p_layout;
502 VkPipelineLayout clear_depth_p_layout;
503 VkPipelineLayout clear_depth_unrestricted_p_layout;
504
505 /* Optimized compute fast HTILE clear for stencil or depth only. */
506 VkPipeline clear_htile_mask_pipeline;
507 VkPipelineLayout clear_htile_mask_p_layout;
508 VkDescriptorSetLayout clear_htile_mask_ds_layout;
509
510 struct {
511 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
512
513 /** Pipeline that blits from a 1D image. */
514 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
515
516 /** Pipeline that blits from a 2D image. */
517 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
518
519 /** Pipeline that blits from a 3D image. */
520 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
521
522 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
523 VkPipeline depth_only_1d_pipeline;
524 VkPipeline depth_only_2d_pipeline;
525 VkPipeline depth_only_3d_pipeline;
526
527 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
528 VkPipeline stencil_only_1d_pipeline;
529 VkPipeline stencil_only_2d_pipeline;
530 VkPipeline stencil_only_3d_pipeline;
531 VkPipelineLayout pipeline_layout;
532 VkDescriptorSetLayout ds_layout;
533 } blit;
534
535 struct {
536 VkPipelineLayout p_layouts[5];
537 VkDescriptorSetLayout ds_layouts[5];
538 VkPipeline pipelines[5][NUM_META_FS_KEYS];
539
540 VkPipeline depth_only_pipeline[5];
541
542 VkPipeline stencil_only_pipeline[5];
543 } blit2d[MAX_SAMPLES_LOG2];
544
545 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
546 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
547 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
548
549 struct {
550 VkPipelineLayout img_p_layout;
551 VkDescriptorSetLayout img_ds_layout;
552 VkPipeline pipeline;
553 VkPipeline pipeline_3d;
554 } itob;
555 struct {
556 VkPipelineLayout img_p_layout;
557 VkDescriptorSetLayout img_ds_layout;
558 VkPipeline pipeline;
559 VkPipeline pipeline_3d;
560 } btoi;
561 struct {
562 VkPipelineLayout img_p_layout;
563 VkDescriptorSetLayout img_ds_layout;
564 VkPipeline pipeline;
565 } btoi_r32g32b32;
566 struct {
567 VkPipelineLayout img_p_layout;
568 VkDescriptorSetLayout img_ds_layout;
569 VkPipeline pipeline;
570 VkPipeline pipeline_3d;
571 } itoi;
572 struct {
573 VkPipelineLayout img_p_layout;
574 VkDescriptorSetLayout img_ds_layout;
575 VkPipeline pipeline;
576 } itoi_r32g32b32;
577 struct {
578 VkPipelineLayout img_p_layout;
579 VkDescriptorSetLayout img_ds_layout;
580 VkPipeline pipeline;
581 VkPipeline pipeline_3d;
582 } cleari;
583 struct {
584 VkPipelineLayout img_p_layout;
585 VkDescriptorSetLayout img_ds_layout;
586 VkPipeline pipeline;
587 } cleari_r32g32b32;
588
589 struct {
590 VkPipelineLayout p_layout;
591 VkPipeline pipeline[NUM_META_FS_KEYS];
592 VkRenderPass pass[NUM_META_FS_KEYS];
593 } resolve;
594
595 struct {
596 VkDescriptorSetLayout ds_layout;
597 VkPipelineLayout p_layout;
598 struct {
599 VkPipeline pipeline;
600 VkPipeline i_pipeline;
601 VkPipeline srgb_pipeline;
602 } rc[MAX_SAMPLES_LOG2];
603
604 VkPipeline depth_zero_pipeline;
605 struct {
606 VkPipeline average_pipeline;
607 VkPipeline max_pipeline;
608 VkPipeline min_pipeline;
609 } depth[MAX_SAMPLES_LOG2];
610
611 VkPipeline stencil_zero_pipeline;
612 struct {
613 VkPipeline max_pipeline;
614 VkPipeline min_pipeline;
615 } stencil[MAX_SAMPLES_LOG2];
616 } resolve_compute;
617
618 struct {
619 VkDescriptorSetLayout ds_layout;
620 VkPipelineLayout p_layout;
621
622 struct {
623 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
624 VkPipeline pipeline[NUM_META_FS_KEYS];
625 } rc[MAX_SAMPLES_LOG2];
626
627 VkRenderPass depth_render_pass;
628 VkPipeline depth_zero_pipeline;
629 struct {
630 VkPipeline average_pipeline;
631 VkPipeline max_pipeline;
632 VkPipeline min_pipeline;
633 } depth[MAX_SAMPLES_LOG2];
634
635 VkRenderPass stencil_render_pass;
636 VkPipeline stencil_zero_pipeline;
637 struct {
638 VkPipeline max_pipeline;
639 VkPipeline min_pipeline;
640 } stencil[MAX_SAMPLES_LOG2];
641 } resolve_fragment;
642
643 struct {
644 VkPipelineLayout p_layout;
645 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
646 VkPipeline resummarize_pipeline;
647 VkRenderPass pass;
648 } depth_decomp[MAX_SAMPLES_LOG2];
649
650 struct {
651 VkPipelineLayout p_layout;
652 VkPipeline cmask_eliminate_pipeline;
653 VkPipeline fmask_decompress_pipeline;
654 VkPipeline dcc_decompress_pipeline;
655 VkRenderPass pass;
656
657 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
658 VkPipelineLayout dcc_decompress_compute_p_layout;
659 VkPipeline dcc_decompress_compute_pipeline;
660 } fast_clear_flush;
661
662 struct {
663 VkPipelineLayout fill_p_layout;
664 VkPipelineLayout copy_p_layout;
665 VkDescriptorSetLayout fill_ds_layout;
666 VkDescriptorSetLayout copy_ds_layout;
667 VkPipeline fill_pipeline;
668 VkPipeline copy_pipeline;
669 } buffer;
670
671 struct {
672 VkDescriptorSetLayout ds_layout;
673 VkPipelineLayout p_layout;
674 VkPipeline occlusion_query_pipeline;
675 VkPipeline pipeline_statistics_query_pipeline;
676 VkPipeline tfb_query_pipeline;
677 VkPipeline timestamp_query_pipeline;
678 } query;
679
680 struct {
681 VkDescriptorSetLayout ds_layout;
682 VkPipelineLayout p_layout;
683 VkPipeline pipeline[MAX_SAMPLES_LOG2];
684 } fmask_expand;
685 };
686
687 /* queue types */
688 #define RADV_QUEUE_GENERAL 0
689 #define RADV_QUEUE_COMPUTE 1
690 #define RADV_QUEUE_TRANSFER 2
691
692 #define RADV_MAX_QUEUE_FAMILIES 3
693
694 struct radv_deferred_queue_submission;
695
696 enum ring_type radv_queue_family_to_ring(int f);
697
698 struct radv_queue {
699 VK_LOADER_DATA _loader_data;
700 struct radv_device * device;
701 struct radeon_winsys_ctx *hw_ctx;
702 enum radeon_ctx_priority priority;
703 uint32_t queue_family_index;
704 int queue_idx;
705 VkDeviceQueueCreateFlags flags;
706
707 uint32_t scratch_size_per_wave;
708 uint32_t scratch_waves;
709 uint32_t compute_scratch_size_per_wave;
710 uint32_t compute_scratch_waves;
711 uint32_t esgs_ring_size;
712 uint32_t gsvs_ring_size;
713 bool has_tess_rings;
714 bool has_gds;
715 bool has_gds_oa;
716 bool has_sample_positions;
717
718 struct radeon_winsys_bo *scratch_bo;
719 struct radeon_winsys_bo *descriptor_bo;
720 struct radeon_winsys_bo *compute_scratch_bo;
721 struct radeon_winsys_bo *esgs_ring_bo;
722 struct radeon_winsys_bo *gsvs_ring_bo;
723 struct radeon_winsys_bo *tess_rings_bo;
724 struct radeon_winsys_bo *gds_bo;
725 struct radeon_winsys_bo *gds_oa_bo;
726 struct radeon_cmdbuf *initial_preamble_cs;
727 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
728 struct radeon_cmdbuf *continue_preamble_cs;
729
730 struct list_head pending_submissions;
731 pthread_mutex_t pending_mutex;
732
733 pthread_mutex_t thread_mutex;
734 pthread_cond_t thread_cond;
735 struct radv_deferred_queue_submission *thread_submission;
736 pthread_t submission_thread;
737 bool thread_exit;
738 bool thread_running;
739 };
740
741 struct radv_bo_list {
742 struct radv_winsys_bo_list list;
743 unsigned capacity;
744 pthread_mutex_t mutex;
745 };
746
747 VkResult radv_bo_list_add(struct radv_device *device,
748 struct radeon_winsys_bo *bo);
749 void radv_bo_list_remove(struct radv_device *device,
750 struct radeon_winsys_bo *bo);
751
752 #define RADV_BORDER_COLOR_COUNT 4096
753 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
754
755 struct radv_device_border_color_data {
756 bool used[RADV_BORDER_COLOR_COUNT];
757
758 struct radeon_winsys_bo *bo;
759 VkClearColorValue *colors_gpu_ptr;
760
761 /* Mutex is required to guarantee vkCreateSampler thread safety
762 * given that we are writing to a buffer and checking color occupation */
763 pthread_mutex_t mutex;
764 };
765
766 struct radv_device {
767 struct vk_device vk;
768
769 struct radv_instance * instance;
770 struct radeon_winsys *ws;
771
772 struct radv_meta_state meta_state;
773
774 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
775 int queue_count[RADV_MAX_QUEUE_FAMILIES];
776 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
777
778 bool always_use_syncobj;
779 bool pbb_allowed;
780 bool dfsm_allowed;
781 uint32_t tess_offchip_block_dw_size;
782 uint32_t scratch_waves;
783 uint32_t dispatch_initiator;
784
785 uint32_t gs_table_depth;
786
787 /* MSAA sample locations.
788 * The first index is the sample index.
789 * The second index is the coordinate: X, Y. */
790 float sample_locations_1x[1][2];
791 float sample_locations_2x[2][2];
792 float sample_locations_4x[4][2];
793 float sample_locations_8x[8][2];
794
795 /* GFX7 and later */
796 uint32_t gfx_init_size_dw;
797 struct radeon_winsys_bo *gfx_init;
798
799 struct radeon_winsys_bo *trace_bo;
800 uint32_t *trace_id_ptr;
801
802 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
803 bool keep_shader_info;
804
805 struct radv_physical_device *physical_device;
806
807 /* Backup in-memory cache to be used if the app doesn't provide one */
808 struct radv_pipeline_cache * mem_cache;
809
810 /*
811 * use different counters so MSAA MRTs get consecutive surface indices,
812 * even if MASK is allocated in between.
813 */
814 uint32_t image_mrt_offset_counter;
815 uint32_t fmask_mrt_offset_counter;
816 struct list_head shader_slabs;
817 mtx_t shader_slab_mutex;
818
819 /* For detecting VM faults reported by dmesg. */
820 uint64_t dmesg_timestamp;
821
822 struct radv_device_extension_table enabled_extensions;
823 struct radv_device_dispatch_table dispatch;
824
825 /* Whether the app has enabled the robustBufferAccess feature. */
826 bool robust_buffer_access;
827
828 /* Whether the driver uses a global BO list. */
829 bool use_global_bo_list;
830
831 struct radv_bo_list bo_list;
832
833 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
834 int force_aniso;
835
836 struct radv_device_border_color_data border_color_data;
837
838 /* Condition variable for legacy timelines, to notify waiters when a
839 * new point gets submitted. */
840 pthread_cond_t timeline_cond;
841
842 /* Thread trace. */
843 struct radeon_cmdbuf *thread_trace_start_cs[2];
844 struct radeon_cmdbuf *thread_trace_stop_cs[2];
845 struct radeon_winsys_bo *thread_trace_bo;
846 void *thread_trace_ptr;
847 uint32_t thread_trace_buffer_size;
848 int thread_trace_start_frame;
849 char *thread_trace_trigger_file;
850
851 /* Trap handler. */
852 struct radv_shader_variant *trap_handler_shader;
853 struct radeon_winsys_bo *tma_bo; /* Trap Memory Address */
854 uint32_t *tma_ptr;
855
856 /* Overallocation. */
857 bool overallocation_disallowed;
858 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
859 mtx_t overallocation_mutex;
860
861 /* Track the number of device loss occurs. */
862 int lost;
863 };
864
865 VkResult _radv_device_set_lost(struct radv_device *device,
866 const char *file, int line,
867 const char *msg, ...)
868 radv_printflike(4, 5);
869
870 #define radv_device_set_lost(dev, ...) \
871 _radv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
872
873 static inline bool
874 radv_device_is_lost(const struct radv_device *device)
875 {
876 return unlikely(p_atomic_read(&device->lost));
877 }
878
879 struct radv_device_memory {
880 struct vk_object_base base;
881 struct radeon_winsys_bo *bo;
882 /* for dedicated allocations */
883 struct radv_image *image;
884 struct radv_buffer *buffer;
885 uint32_t heap_index;
886 uint64_t alloc_size;
887 void * map;
888 void * user_ptr;
889
890 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
891 struct AHardwareBuffer * android_hardware_buffer;
892 #endif
893 };
894
895
896 struct radv_descriptor_range {
897 uint64_t va;
898 uint32_t size;
899 };
900
901 struct radv_descriptor_set {
902 struct vk_object_base base;
903 const struct radv_descriptor_set_layout *layout;
904 uint32_t size;
905 uint32_t buffer_count;
906
907 struct radeon_winsys_bo *bo;
908 uint64_t va;
909 uint32_t *mapped_ptr;
910 struct radv_descriptor_range *dynamic_descriptors;
911
912 struct radeon_winsys_bo *descriptors[0];
913 };
914
915 struct radv_push_descriptor_set
916 {
917 struct radv_descriptor_set set;
918 uint32_t capacity;
919 };
920
921 struct radv_descriptor_pool_entry {
922 uint32_t offset;
923 uint32_t size;
924 struct radv_descriptor_set *set;
925 };
926
927 struct radv_descriptor_pool {
928 struct vk_object_base base;
929 struct radeon_winsys_bo *bo;
930 uint8_t *mapped_ptr;
931 uint64_t current_offset;
932 uint64_t size;
933
934 uint8_t *host_memory_base;
935 uint8_t *host_memory_ptr;
936 uint8_t *host_memory_end;
937
938 uint32_t entry_count;
939 uint32_t max_entry_count;
940 struct radv_descriptor_pool_entry entries[0];
941 };
942
943 struct radv_descriptor_update_template_entry {
944 VkDescriptorType descriptor_type;
945
946 /* The number of descriptors to update */
947 uint32_t descriptor_count;
948
949 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
950 uint32_t dst_offset;
951
952 /* In dwords. Not valid/used for dynamic descriptors */
953 uint32_t dst_stride;
954
955 uint32_t buffer_offset;
956
957 /* Only valid for combined image samplers and samplers */
958 uint8_t has_sampler;
959 uint8_t sampler_offset;
960
961 /* In bytes */
962 size_t src_offset;
963 size_t src_stride;
964
965 /* For push descriptors */
966 const uint32_t *immutable_samplers;
967 };
968
969 struct radv_descriptor_update_template {
970 struct vk_object_base base;
971 uint32_t entry_count;
972 VkPipelineBindPoint bind_point;
973 struct radv_descriptor_update_template_entry entry[0];
974 };
975
976 struct radv_buffer {
977 struct vk_object_base base;
978 VkDeviceSize size;
979
980 VkBufferUsageFlags usage;
981 VkBufferCreateFlags flags;
982
983 /* Set when bound */
984 struct radeon_winsys_bo * bo;
985 VkDeviceSize offset;
986
987 bool shareable;
988 };
989
990 enum radv_dynamic_state_bits {
991 RADV_DYNAMIC_VIEWPORT = 1 << 0,
992 RADV_DYNAMIC_SCISSOR = 1 << 1,
993 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
994 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
995 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
996 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
997 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
998 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
999 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
1000 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
1001 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
1002 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
1003 RADV_DYNAMIC_CULL_MODE = 1 << 12,
1004 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
1005 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
1006 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
1007 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
1008 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
1009 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
1010 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1011 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
1012 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1013 RADV_DYNAMIC_ALL = (1 << 22) - 1,
1014 };
1015
1016 enum radv_cmd_dirty_bits {
1017 /* Keep the dynamic state dirty bits in sync with
1018 * enum radv_dynamic_state_bits */
1019 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
1020 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
1021 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
1022 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
1023 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
1024 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
1025 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
1026 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
1027 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
1028 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
1029 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
1030 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
1031 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
1032 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
1033 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
1034 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
1035 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
1036 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
1037 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
1038 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1039 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
1040 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1041 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
1042 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
1043 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
1044 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
1045 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
1046 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
1047 };
1048
1049 enum radv_cmd_flush_bits {
1050 /* Instruction cache. */
1051 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1052 /* Scalar L1 cache. */
1053 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1054 /* Vector L1 cache. */
1055 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1056 /* L2 cache + L2 metadata cache writeback & invalidate.
1057 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1058 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1059 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1060 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1061 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1062 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1063 /* Framebuffer caches */
1064 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1065 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1066 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1067 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1068 /* Engine synchronization. */
1069 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1070 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1071 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1072 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1073 /* Pipeline query controls. */
1074 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1075 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1076 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1077
1078 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1079 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1080 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1081 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1082 };
1083
1084 struct radv_vertex_binding {
1085 struct radv_buffer * buffer;
1086 VkDeviceSize offset;
1087 VkDeviceSize size;
1088 VkDeviceSize stride;
1089 };
1090
1091 struct radv_streamout_binding {
1092 struct radv_buffer *buffer;
1093 VkDeviceSize offset;
1094 VkDeviceSize size;
1095 };
1096
1097 struct radv_streamout_state {
1098 /* Mask of bound streamout buffers. */
1099 uint8_t enabled_mask;
1100
1101 /* External state that comes from the last vertex stage, it must be
1102 * set explicitely when binding a new graphics pipeline.
1103 */
1104 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1105 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1106
1107 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1108 uint32_t hw_enabled_mask;
1109
1110 /* State of VGT_STRMOUT_(CONFIG|EN) */
1111 bool streamout_enabled;
1112 };
1113
1114 struct radv_viewport_state {
1115 uint32_t count;
1116 VkViewport viewports[MAX_VIEWPORTS];
1117 };
1118
1119 struct radv_scissor_state {
1120 uint32_t count;
1121 VkRect2D scissors[MAX_SCISSORS];
1122 };
1123
1124 struct radv_discard_rectangle_state {
1125 uint32_t count;
1126 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1127 };
1128
1129 struct radv_sample_locations_state {
1130 VkSampleCountFlagBits per_pixel;
1131 VkExtent2D grid_size;
1132 uint32_t count;
1133 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1134 };
1135
1136 struct radv_dynamic_state {
1137 /**
1138 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1139 * Defines the set of saved dynamic state.
1140 */
1141 uint32_t mask;
1142
1143 struct radv_viewport_state viewport;
1144
1145 struct radv_scissor_state scissor;
1146
1147 float line_width;
1148
1149 struct {
1150 float bias;
1151 float clamp;
1152 float slope;
1153 } depth_bias;
1154
1155 float blend_constants[4];
1156
1157 struct {
1158 float min;
1159 float max;
1160 } depth_bounds;
1161
1162 struct {
1163 uint32_t front;
1164 uint32_t back;
1165 } stencil_compare_mask;
1166
1167 struct {
1168 uint32_t front;
1169 uint32_t back;
1170 } stencil_write_mask;
1171
1172 struct {
1173 struct {
1174 VkStencilOp fail_op;
1175 VkStencilOp pass_op;
1176 VkStencilOp depth_fail_op;
1177 VkCompareOp compare_op;
1178 } front;
1179
1180 struct {
1181 VkStencilOp fail_op;
1182 VkStencilOp pass_op;
1183 VkStencilOp depth_fail_op;
1184 VkCompareOp compare_op;
1185 } back;
1186 } stencil_op;
1187
1188 struct {
1189 uint32_t front;
1190 uint32_t back;
1191 } stencil_reference;
1192
1193 struct radv_discard_rectangle_state discard_rectangle;
1194
1195 struct radv_sample_locations_state sample_location;
1196
1197 struct {
1198 uint32_t factor;
1199 uint16_t pattern;
1200 } line_stipple;
1201
1202 VkCullModeFlags cull_mode;
1203 VkFrontFace front_face;
1204 unsigned primitive_topology;
1205
1206 bool depth_test_enable;
1207 bool depth_write_enable;
1208 VkCompareOp depth_compare_op;
1209 bool depth_bounds_test_enable;
1210 bool stencil_test_enable;
1211 };
1212
1213 extern const struct radv_dynamic_state default_dynamic_state;
1214
1215 const char *
1216 radv_get_debug_option_name(int id);
1217
1218 const char *
1219 radv_get_perftest_option_name(int id);
1220
1221 struct radv_color_buffer_info {
1222 uint64_t cb_color_base;
1223 uint64_t cb_color_cmask;
1224 uint64_t cb_color_fmask;
1225 uint64_t cb_dcc_base;
1226 uint32_t cb_color_slice;
1227 uint32_t cb_color_view;
1228 uint32_t cb_color_info;
1229 uint32_t cb_color_attrib;
1230 uint32_t cb_color_attrib2; /* GFX9 and later */
1231 uint32_t cb_color_attrib3; /* GFX10 and later */
1232 uint32_t cb_dcc_control;
1233 uint32_t cb_color_cmask_slice;
1234 uint32_t cb_color_fmask_slice;
1235 union {
1236 uint32_t cb_color_pitch; // GFX6-GFX8
1237 uint32_t cb_mrt_epitch; // GFX9+
1238 };
1239 };
1240
1241 struct radv_ds_buffer_info {
1242 uint64_t db_z_read_base;
1243 uint64_t db_stencil_read_base;
1244 uint64_t db_z_write_base;
1245 uint64_t db_stencil_write_base;
1246 uint64_t db_htile_data_base;
1247 uint32_t db_depth_info;
1248 uint32_t db_z_info;
1249 uint32_t db_stencil_info;
1250 uint32_t db_depth_view;
1251 uint32_t db_depth_size;
1252 uint32_t db_depth_slice;
1253 uint32_t db_htile_surface;
1254 uint32_t pa_su_poly_offset_db_fmt_cntl;
1255 uint32_t db_z_info2; /* GFX9 only */
1256 uint32_t db_stencil_info2; /* GFX9 only */
1257 float offset_scale;
1258 };
1259
1260 void
1261 radv_initialise_color_surface(struct radv_device *device,
1262 struct radv_color_buffer_info *cb,
1263 struct radv_image_view *iview);
1264 void
1265 radv_initialise_ds_surface(struct radv_device *device,
1266 struct radv_ds_buffer_info *ds,
1267 struct radv_image_view *iview);
1268
1269 /**
1270 * Attachment state when recording a renderpass instance.
1271 *
1272 * The clear value is valid only if there exists a pending clear.
1273 */
1274 struct radv_attachment_state {
1275 VkImageAspectFlags pending_clear_aspects;
1276 uint32_t cleared_views;
1277 VkClearValue clear_value;
1278 VkImageLayout current_layout;
1279 VkImageLayout current_stencil_layout;
1280 bool current_in_render_loop;
1281 struct radv_sample_locations_state sample_location;
1282
1283 union {
1284 struct radv_color_buffer_info cb;
1285 struct radv_ds_buffer_info ds;
1286 };
1287 struct radv_image_view *iview;
1288 };
1289
1290 struct radv_descriptor_state {
1291 struct radv_descriptor_set *sets[MAX_SETS];
1292 uint32_t dirty;
1293 uint32_t valid;
1294 struct radv_push_descriptor_set push_set;
1295 bool push_dirty;
1296 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1297 };
1298
1299 struct radv_subpass_sample_locs_state {
1300 uint32_t subpass_idx;
1301 struct radv_sample_locations_state sample_location;
1302 };
1303
1304 struct radv_cmd_state {
1305 /* Vertex descriptors */
1306 uint64_t vb_va;
1307 unsigned vb_size;
1308
1309 bool predicating;
1310 uint32_t dirty;
1311
1312 uint32_t prefetch_L2_mask;
1313
1314 struct radv_pipeline * pipeline;
1315 struct radv_pipeline * emitted_pipeline;
1316 struct radv_pipeline * compute_pipeline;
1317 struct radv_pipeline * emitted_compute_pipeline;
1318 struct radv_framebuffer * framebuffer;
1319 struct radv_render_pass * pass;
1320 const struct radv_subpass * subpass;
1321 struct radv_dynamic_state dynamic;
1322 struct radv_attachment_state * attachments;
1323 struct radv_streamout_state streamout;
1324 VkRect2D render_area;
1325
1326 uint32_t num_subpass_sample_locs;
1327 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1328
1329 /* Index buffer */
1330 struct radv_buffer *index_buffer;
1331 uint64_t index_offset;
1332 uint32_t index_type;
1333 uint32_t max_index_count;
1334 uint64_t index_va;
1335 int32_t last_index_type;
1336
1337 int32_t last_primitive_reset_en;
1338 uint32_t last_primitive_reset_index;
1339 enum radv_cmd_flush_bits flush_bits;
1340 unsigned active_occlusion_queries;
1341 bool perfect_occlusion_queries_enabled;
1342 unsigned active_pipeline_queries;
1343 unsigned active_pipeline_gds_queries;
1344 float offset_scale;
1345 uint32_t trace_id;
1346 uint32_t last_ia_multi_vgt_param;
1347
1348 uint32_t last_num_instances;
1349 uint32_t last_first_instance;
1350 uint32_t last_vertex_offset;
1351
1352 uint32_t last_sx_ps_downconvert;
1353 uint32_t last_sx_blend_opt_epsilon;
1354 uint32_t last_sx_blend_opt_control;
1355
1356 /* Whether CP DMA is busy/idle. */
1357 bool dma_is_busy;
1358
1359 /* Conditional rendering info. */
1360 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1361 uint64_t predication_va;
1362
1363 /* Inheritance info. */
1364 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1365
1366 bool context_roll_without_scissor_emitted;
1367
1368 /* SQTT related state. */
1369 uint32_t current_event_type;
1370 uint32_t num_events;
1371 uint32_t num_layout_transitions;
1372 };
1373
1374 struct radv_cmd_pool {
1375 struct vk_object_base base;
1376 VkAllocationCallbacks alloc;
1377 struct list_head cmd_buffers;
1378 struct list_head free_cmd_buffers;
1379 uint32_t queue_family_index;
1380 };
1381
1382 struct radv_cmd_buffer_upload {
1383 uint8_t *map;
1384 unsigned offset;
1385 uint64_t size;
1386 struct radeon_winsys_bo *upload_bo;
1387 struct list_head list;
1388 };
1389
1390 enum radv_cmd_buffer_status {
1391 RADV_CMD_BUFFER_STATUS_INVALID,
1392 RADV_CMD_BUFFER_STATUS_INITIAL,
1393 RADV_CMD_BUFFER_STATUS_RECORDING,
1394 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1395 RADV_CMD_BUFFER_STATUS_PENDING,
1396 };
1397
1398 struct radv_cmd_buffer {
1399 struct vk_object_base base;
1400
1401 struct radv_device * device;
1402
1403 struct radv_cmd_pool * pool;
1404 struct list_head pool_link;
1405
1406 VkCommandBufferUsageFlags usage_flags;
1407 VkCommandBufferLevel level;
1408 enum radv_cmd_buffer_status status;
1409 struct radeon_cmdbuf *cs;
1410 struct radv_cmd_state state;
1411 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1412 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1413 uint32_t queue_family_index;
1414
1415 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1416 VkShaderStageFlags push_constant_stages;
1417 struct radv_descriptor_set meta_push_descriptors;
1418
1419 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1420
1421 struct radv_cmd_buffer_upload upload;
1422
1423 uint32_t scratch_size_per_wave_needed;
1424 uint32_t scratch_waves_wanted;
1425 uint32_t compute_scratch_size_per_wave_needed;
1426 uint32_t compute_scratch_waves_wanted;
1427 uint32_t esgs_ring_size_needed;
1428 uint32_t gsvs_ring_size_needed;
1429 bool tess_rings_needed;
1430 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1431 bool gds_oa_needed; /* for GFX10 streamout */
1432 bool sample_positions_needed;
1433
1434 VkResult record_result;
1435
1436 uint64_t gfx9_fence_va;
1437 uint32_t gfx9_fence_idx;
1438 uint64_t gfx9_eop_bug_va;
1439
1440 /**
1441 * Whether a query pool has been resetted and we have to flush caches.
1442 */
1443 bool pending_reset_query;
1444
1445 /**
1446 * Bitmask of pending active query flushes.
1447 */
1448 enum radv_cmd_flush_bits active_query_flush_bits;
1449 };
1450
1451 struct radv_image;
1452 struct radv_image_view;
1453
1454 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1455
1456 void si_emit_graphics(struct radv_device *device,
1457 struct radeon_cmdbuf *cs);
1458 void si_emit_compute(struct radv_device *device,
1459 struct radeon_cmdbuf *cs);
1460
1461 void cik_create_gfx_config(struct radv_device *device);
1462
1463 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1464 int count, const VkViewport *viewports);
1465 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1466 int count, const VkRect2D *scissors,
1467 const VkViewport *viewports, bool can_use_guardband);
1468 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1469 bool instanced_draw, bool indirect_draw,
1470 bool count_from_stream_output,
1471 uint32_t draw_vertex_count,
1472 unsigned topology);
1473 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1474 enum chip_class chip_class,
1475 bool is_mec,
1476 unsigned event, unsigned event_flags,
1477 unsigned dst_sel, unsigned data_sel,
1478 uint64_t va,
1479 uint32_t new_fence,
1480 uint64_t gfx9_eop_bug_va);
1481
1482 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1483 uint32_t ref, uint32_t mask);
1484 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1485 enum chip_class chip_class,
1486 uint32_t *fence_ptr, uint64_t va,
1487 bool is_mec,
1488 enum radv_cmd_flush_bits flush_bits,
1489 uint64_t gfx9_eop_bug_va);
1490 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1491 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1492 bool inverted, uint64_t va);
1493 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1494 uint64_t src_va, uint64_t dest_va,
1495 uint64_t size);
1496 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1497 unsigned size);
1498 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1499 uint64_t size, unsigned value);
1500 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1501
1502 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1503 bool
1504 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1505 unsigned size,
1506 unsigned alignment,
1507 unsigned *out_offset,
1508 void **ptr);
1509 void
1510 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1511 const struct radv_subpass *subpass);
1512 bool
1513 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1514 unsigned size, unsigned alignmnet,
1515 const void *data, unsigned *out_offset);
1516
1517 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1518 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1519 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1520 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1521 VkImageAspectFlags aspects,
1522 VkResolveModeFlagBits resolve_mode);
1523 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1524 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1525 VkImageAspectFlags aspects,
1526 VkResolveModeFlagBits resolve_mode);
1527 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1528 unsigned radv_get_default_max_sample_dist(int log_samples);
1529 void radv_device_init_msaa(struct radv_device *device);
1530
1531 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1532 const struct radv_image_view *iview,
1533 VkClearDepthStencilValue ds_clear_value,
1534 VkImageAspectFlags aspects);
1535
1536 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1537 const struct radv_image_view *iview,
1538 int cb_idx,
1539 uint32_t color_values[2]);
1540
1541 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1542 struct radv_image *image,
1543 const VkImageSubresourceRange *range, bool value);
1544
1545 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1546 struct radv_image *image,
1547 const VkImageSubresourceRange *range, bool value);
1548
1549 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1550 struct radeon_winsys_bo *bo,
1551 uint64_t offset, uint64_t size, uint32_t value);
1552 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1553 bool radv_get_memory_fd(struct radv_device *device,
1554 struct radv_device_memory *memory,
1555 int *pFD);
1556 void radv_free_memory(struct radv_device *device,
1557 const VkAllocationCallbacks* pAllocator,
1558 struct radv_device_memory *mem);
1559
1560 static inline void
1561 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1562 unsigned sh_offset, unsigned pointer_count,
1563 bool use_32bit_pointers)
1564 {
1565 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1566 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1567 }
1568
1569 static inline void
1570 radv_emit_shader_pointer_body(struct radv_device *device,
1571 struct radeon_cmdbuf *cs,
1572 uint64_t va, bool use_32bit_pointers)
1573 {
1574 radeon_emit(cs, va);
1575
1576 if (use_32bit_pointers) {
1577 assert(va == 0 ||
1578 (va >> 32) == device->physical_device->rad_info.address32_hi);
1579 } else {
1580 radeon_emit(cs, va >> 32);
1581 }
1582 }
1583
1584 static inline void
1585 radv_emit_shader_pointer(struct radv_device *device,
1586 struct radeon_cmdbuf *cs,
1587 uint32_t sh_offset, uint64_t va, bool global)
1588 {
1589 bool use_32bit_pointers = !global;
1590
1591 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1592 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1593 }
1594
1595 static inline struct radv_descriptor_state *
1596 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1597 VkPipelineBindPoint bind_point)
1598 {
1599 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1600 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1601 return &cmd_buffer->descriptors[bind_point];
1602 }
1603
1604 /*
1605 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1606 *
1607 * Limitations: Can't call normal dispatch functions without binding or rebinding
1608 * the compute pipeline.
1609 */
1610 void radv_unaligned_dispatch(
1611 struct radv_cmd_buffer *cmd_buffer,
1612 uint32_t x,
1613 uint32_t y,
1614 uint32_t z);
1615
1616 struct radv_event {
1617 struct vk_object_base base;
1618 struct radeon_winsys_bo *bo;
1619 uint64_t *map;
1620 };
1621
1622 struct radv_shader_module;
1623
1624 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1625 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1626 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1627 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1628 #define RADV_HASH_SHADER_LLVM (1 << 4)
1629
1630 void
1631 radv_hash_shaders(unsigned char *hash,
1632 const VkPipelineShaderStageCreateInfo **stages,
1633 const struct radv_pipeline_layout *layout,
1634 const struct radv_pipeline_key *key,
1635 uint32_t flags);
1636
1637 static inline gl_shader_stage
1638 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1639 {
1640 assert(__builtin_popcount(vk_stage) == 1);
1641 return ffs(vk_stage) - 1;
1642 }
1643
1644 static inline VkShaderStageFlagBits
1645 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1646 {
1647 return (1 << mesa_stage);
1648 }
1649
1650 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1651
1652 #define radv_foreach_stage(stage, stage_bits) \
1653 for (gl_shader_stage stage, \
1654 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1655 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1656 __tmp &= ~(1 << (stage)))
1657
1658 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1659 unsigned radv_format_meta_fs_key(VkFormat format);
1660
1661 struct radv_multisample_state {
1662 uint32_t db_eqaa;
1663 uint32_t pa_sc_mode_cntl_0;
1664 uint32_t pa_sc_mode_cntl_1;
1665 uint32_t pa_sc_aa_config;
1666 uint32_t pa_sc_aa_mask[2];
1667 unsigned num_samples;
1668 };
1669
1670 struct radv_prim_vertex_count {
1671 uint8_t min;
1672 uint8_t incr;
1673 };
1674
1675 struct radv_ia_multi_vgt_param_helpers {
1676 uint32_t base;
1677 bool partial_es_wave;
1678 uint8_t primgroup_size;
1679 bool ia_switch_on_eoi;
1680 bool partial_vs_wave;
1681 };
1682
1683 struct radv_binning_state {
1684 uint32_t pa_sc_binner_cntl_0;
1685 uint32_t db_dfsm_control;
1686 };
1687
1688 #define SI_GS_PER_ES 128
1689
1690 struct radv_pipeline {
1691 struct vk_object_base base;
1692 struct radv_device * device;
1693 struct radv_dynamic_state dynamic_state;
1694
1695 struct radv_pipeline_layout * layout;
1696
1697 bool need_indirect_descriptor_sets;
1698 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1699 struct radv_shader_variant *gs_copy_shader;
1700 VkShaderStageFlags active_stages;
1701
1702 struct radeon_cmdbuf cs;
1703 uint32_t ctx_cs_hash;
1704 struct radeon_cmdbuf ctx_cs;
1705
1706 uint32_t binding_stride[MAX_VBS];
1707 uint8_t num_vertex_bindings;
1708
1709 uint32_t user_data_0[MESA_SHADER_STAGES];
1710 union {
1711 struct {
1712 struct radv_multisample_state ms;
1713 struct radv_binning_state binning;
1714 uint32_t spi_baryc_cntl;
1715 bool prim_restart_enable;
1716 unsigned esgs_ring_size;
1717 unsigned gsvs_ring_size;
1718 uint32_t vtx_base_sgpr;
1719 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1720 uint8_t vtx_emit_num;
1721 bool can_use_guardband;
1722 uint32_t needed_dynamic_state;
1723 bool disable_out_of_order_rast_for_occlusion;
1724 unsigned tess_patch_control_points;
1725 unsigned pa_su_sc_mode_cntl;
1726 unsigned db_depth_control;
1727 bool uses_dynamic_stride;
1728
1729 /* Used for rbplus */
1730 uint32_t col_format;
1731 uint32_t cb_target_mask;
1732 } graphics;
1733 };
1734
1735 unsigned max_waves;
1736 unsigned scratch_bytes_per_wave;
1737
1738 /* Not NULL if graphics pipeline uses streamout. */
1739 struct radv_shader_variant *streamout_shader;
1740 };
1741
1742 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1743 {
1744 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1745 }
1746
1747 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1748 {
1749 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1750 }
1751
1752 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1753
1754 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1755
1756 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1757
1758 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1759 gl_shader_stage stage,
1760 int idx);
1761
1762 struct radv_shader_variant *radv_get_shader(const struct radv_pipeline *pipeline,
1763 gl_shader_stage stage);
1764
1765 struct radv_graphics_pipeline_create_info {
1766 bool use_rectlist;
1767 bool db_depth_clear;
1768 bool db_stencil_clear;
1769 bool db_depth_disable_expclear;
1770 bool db_stencil_disable_expclear;
1771 bool depth_compress_disable;
1772 bool stencil_compress_disable;
1773 bool resummarize_enable;
1774 uint32_t custom_blend_mode;
1775 };
1776
1777 VkResult
1778 radv_graphics_pipeline_create(VkDevice device,
1779 VkPipelineCache cache,
1780 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1781 const struct radv_graphics_pipeline_create_info *extra,
1782 const VkAllocationCallbacks *alloc,
1783 VkPipeline *pPipeline);
1784
1785 struct radv_binning_settings {
1786 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1787 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1788 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1789 };
1790
1791 struct radv_binning_settings
1792 radv_get_binning_settings(const struct radv_physical_device *pdev);
1793
1794 struct vk_format_description;
1795 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1796 int first_non_void);
1797 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1798 int first_non_void);
1799 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1800 uint32_t radv_translate_colorformat(VkFormat format);
1801 uint32_t radv_translate_color_numformat(VkFormat format,
1802 const struct vk_format_description *desc,
1803 int first_non_void);
1804 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1805 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1806 uint32_t radv_translate_dbformat(VkFormat format);
1807 uint32_t radv_translate_tex_dataformat(VkFormat format,
1808 const struct vk_format_description *desc,
1809 int first_non_void);
1810 uint32_t radv_translate_tex_numformat(VkFormat format,
1811 const struct vk_format_description *desc,
1812 int first_non_void);
1813 bool radv_format_pack_clear_color(VkFormat format,
1814 uint32_t clear_vals[2],
1815 VkClearColorValue *value);
1816 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1817 bool radv_dcc_formats_compatible(VkFormat format1,
1818 VkFormat format2);
1819 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1820
1821 struct radv_image_plane {
1822 VkFormat format;
1823 struct radeon_surf surface;
1824 uint64_t offset;
1825 };
1826
1827 struct radv_image {
1828 struct vk_object_base base;
1829 VkImageType type;
1830 /* The original VkFormat provided by the client. This may not match any
1831 * of the actual surface formats.
1832 */
1833 VkFormat vk_format;
1834 VkImageAspectFlags aspects;
1835 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1836 struct ac_surf_info info;
1837 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1838 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1839
1840 VkDeviceSize size;
1841 uint32_t alignment;
1842
1843 unsigned queue_family_mask;
1844 bool exclusive;
1845 bool shareable;
1846
1847 /* Set when bound */
1848 struct radeon_winsys_bo *bo;
1849 VkDeviceSize offset;
1850 bool tc_compatible_htile;
1851 bool tc_compatible_cmask;
1852
1853 uint64_t clear_value_offset;
1854 uint64_t fce_pred_offset;
1855 uint64_t dcc_pred_offset;
1856
1857 /*
1858 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1859 * stored at this offset is UINT_MAX, the driver will emit
1860 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1861 * SET_CONTEXT_REG packet.
1862 */
1863 uint64_t tc_compat_zrange_offset;
1864
1865 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1866 VkDeviceMemory owned_memory;
1867
1868 unsigned plane_count;
1869 struct radv_image_plane planes[0];
1870 };
1871
1872 /* Whether the image has a htile that is known consistent with the contents of
1873 * the image and is allowed to be in compressed form.
1874 *
1875 * If this is false reads that don't use the htile should be able to return
1876 * correct results.
1877 */
1878 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1879 VkImageLayout layout,
1880 bool in_render_loop,
1881 unsigned queue_mask);
1882
1883 bool radv_layout_can_fast_clear(const struct radv_image *image,
1884 VkImageLayout layout,
1885 bool in_render_loop,
1886 unsigned queue_mask);
1887
1888 bool radv_layout_dcc_compressed(const struct radv_device *device,
1889 const struct radv_image *image,
1890 VkImageLayout layout,
1891 bool in_render_loop,
1892 unsigned queue_mask);
1893
1894 /**
1895 * Return whether the image has CMASK metadata for color surfaces.
1896 */
1897 static inline bool
1898 radv_image_has_cmask(const struct radv_image *image)
1899 {
1900 return image->planes[0].surface.cmask_offset;
1901 }
1902
1903 /**
1904 * Return whether the image has FMASK metadata for color surfaces.
1905 */
1906 static inline bool
1907 radv_image_has_fmask(const struct radv_image *image)
1908 {
1909 return image->planes[0].surface.fmask_offset;
1910 }
1911
1912 /**
1913 * Return whether the image has DCC metadata for color surfaces.
1914 */
1915 static inline bool
1916 radv_image_has_dcc(const struct radv_image *image)
1917 {
1918 return image->planes[0].surface.dcc_size;
1919 }
1920
1921 /**
1922 * Return whether the image is TC-compatible CMASK.
1923 */
1924 static inline bool
1925 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1926 {
1927 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1928 }
1929
1930 /**
1931 * Return whether DCC metadata is enabled for a level.
1932 */
1933 static inline bool
1934 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1935 {
1936 return radv_image_has_dcc(image) &&
1937 level < image->planes[0].surface.num_dcc_levels;
1938 }
1939
1940 /**
1941 * Return whether the image has CB metadata.
1942 */
1943 static inline bool
1944 radv_image_has_CB_metadata(const struct radv_image *image)
1945 {
1946 return radv_image_has_cmask(image) ||
1947 radv_image_has_fmask(image) ||
1948 radv_image_has_dcc(image);
1949 }
1950
1951 /**
1952 * Return whether the image has HTILE metadata for depth surfaces.
1953 */
1954 static inline bool
1955 radv_image_has_htile(const struct radv_image *image)
1956 {
1957 return image->planes[0].surface.htile_size;
1958 }
1959
1960 /**
1961 * Return whether HTILE metadata is enabled for a level.
1962 */
1963 static inline bool
1964 radv_htile_enabled(const struct radv_image *image, unsigned level)
1965 {
1966 return radv_image_has_htile(image) && level == 0;
1967 }
1968
1969 /**
1970 * Return whether the image is TC-compatible HTILE.
1971 */
1972 static inline bool
1973 radv_image_is_tc_compat_htile(const struct radv_image *image)
1974 {
1975 return radv_image_has_htile(image) && image->tc_compatible_htile;
1976 }
1977
1978 static inline uint64_t
1979 radv_image_get_fast_clear_va(const struct radv_image *image,
1980 uint32_t base_level)
1981 {
1982 uint64_t va = radv_buffer_get_va(image->bo);
1983 va += image->offset + image->clear_value_offset + base_level * 8;
1984 return va;
1985 }
1986
1987 static inline uint64_t
1988 radv_image_get_fce_pred_va(const struct radv_image *image,
1989 uint32_t base_level)
1990 {
1991 uint64_t va = radv_buffer_get_va(image->bo);
1992 va += image->offset + image->fce_pred_offset + base_level * 8;
1993 return va;
1994 }
1995
1996 static inline uint64_t
1997 radv_image_get_dcc_pred_va(const struct radv_image *image,
1998 uint32_t base_level)
1999 {
2000 uint64_t va = radv_buffer_get_va(image->bo);
2001 va += image->offset + image->dcc_pred_offset + base_level * 8;
2002 return va;
2003 }
2004
2005 static inline uint64_t
2006 radv_get_tc_compat_zrange_va(const struct radv_image *image,
2007 uint32_t base_level)
2008 {
2009 uint64_t va = radv_buffer_get_va(image->bo);
2010 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
2011 return va;
2012 }
2013
2014 static inline uint64_t
2015 radv_get_ds_clear_value_va(const struct radv_image *image,
2016 uint32_t base_level)
2017 {
2018 uint64_t va = radv_buffer_get_va(image->bo);
2019 va += image->offset + image->clear_value_offset + base_level * 8;
2020 return va;
2021 }
2022
2023 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
2024
2025 static inline uint32_t
2026 radv_get_layerCount(const struct radv_image *image,
2027 const VkImageSubresourceRange *range)
2028 {
2029 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
2030 image->info.array_size - range->baseArrayLayer : range->layerCount;
2031 }
2032
2033 static inline uint32_t
2034 radv_get_levelCount(const struct radv_image *image,
2035 const VkImageSubresourceRange *range)
2036 {
2037 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2038 image->info.levels - range->baseMipLevel : range->levelCount;
2039 }
2040
2041 struct radeon_bo_metadata;
2042 void
2043 radv_init_metadata(struct radv_device *device,
2044 struct radv_image *image,
2045 struct radeon_bo_metadata *metadata);
2046
2047 void
2048 radv_image_override_offset_stride(struct radv_device *device,
2049 struct radv_image *image,
2050 uint64_t offset, uint32_t stride);
2051
2052 union radv_descriptor {
2053 struct {
2054 uint32_t plane0_descriptor[8];
2055 uint32_t fmask_descriptor[8];
2056 };
2057 struct {
2058 uint32_t plane_descriptors[3][8];
2059 };
2060 };
2061
2062 struct radv_image_view {
2063 struct vk_object_base base;
2064 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2065 struct radeon_winsys_bo *bo;
2066
2067 VkImageViewType type;
2068 VkImageAspectFlags aspect_mask;
2069 VkFormat vk_format;
2070 unsigned plane_id;
2071 bool multiple_planes;
2072 uint32_t base_layer;
2073 uint32_t layer_count;
2074 uint32_t base_mip;
2075 uint32_t level_count;
2076 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2077
2078 union radv_descriptor descriptor;
2079
2080 /* Descriptor for use as a storage image as opposed to a sampled image.
2081 * This has a few differences for cube maps (e.g. type).
2082 */
2083 union radv_descriptor storage_descriptor;
2084 };
2085
2086 struct radv_image_create_info {
2087 const VkImageCreateInfo *vk_info;
2088 bool scanout;
2089 bool no_metadata_planes;
2090 const struct radeon_bo_metadata *bo_metadata;
2091 };
2092
2093 VkResult
2094 radv_image_create_layout(struct radv_device *device,
2095 struct radv_image_create_info create_info,
2096 struct radv_image *image);
2097
2098 VkResult radv_image_create(VkDevice _device,
2099 const struct radv_image_create_info *info,
2100 const VkAllocationCallbacks* alloc,
2101 VkImage *pImage);
2102
2103 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2104
2105 VkResult
2106 radv_image_from_gralloc(VkDevice device_h,
2107 const VkImageCreateInfo *base_info,
2108 const VkNativeBufferANDROID *gralloc_info,
2109 const VkAllocationCallbacks *alloc,
2110 VkImage *out_image_h);
2111 uint64_t
2112 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2113 const VkImageUsageFlags vk_usage);
2114 VkResult
2115 radv_import_ahb_memory(struct radv_device *device,
2116 struct radv_device_memory *mem,
2117 unsigned priority,
2118 const VkImportAndroidHardwareBufferInfoANDROID *info);
2119 VkResult
2120 radv_create_ahb_memory(struct radv_device *device,
2121 struct radv_device_memory *mem,
2122 unsigned priority,
2123 const VkMemoryAllocateInfo *pAllocateInfo);
2124
2125 VkFormat
2126 radv_select_android_external_format(const void *next, VkFormat default_format);
2127
2128 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2129
2130 struct radv_image_view_extra_create_info {
2131 bool disable_compression;
2132 };
2133
2134 void radv_image_view_init(struct radv_image_view *view,
2135 struct radv_device *device,
2136 const VkImageViewCreateInfo *pCreateInfo,
2137 const struct radv_image_view_extra_create_info* extra_create_info);
2138
2139 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2140
2141 struct radv_sampler_ycbcr_conversion {
2142 struct vk_object_base base;
2143 VkFormat format;
2144 VkSamplerYcbcrModelConversion ycbcr_model;
2145 VkSamplerYcbcrRange ycbcr_range;
2146 VkComponentMapping components;
2147 VkChromaLocation chroma_offsets[2];
2148 VkFilter chroma_filter;
2149 };
2150
2151 struct radv_buffer_view {
2152 struct vk_object_base base;
2153 struct radeon_winsys_bo *bo;
2154 VkFormat vk_format;
2155 uint64_t range; /**< VkBufferViewCreateInfo::range */
2156 uint32_t state[4];
2157 };
2158 void radv_buffer_view_init(struct radv_buffer_view *view,
2159 struct radv_device *device,
2160 const VkBufferViewCreateInfo* pCreateInfo);
2161
2162 static inline struct VkExtent3D
2163 radv_sanitize_image_extent(const VkImageType imageType,
2164 const struct VkExtent3D imageExtent)
2165 {
2166 switch (imageType) {
2167 case VK_IMAGE_TYPE_1D:
2168 return (VkExtent3D) { imageExtent.width, 1, 1 };
2169 case VK_IMAGE_TYPE_2D:
2170 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2171 case VK_IMAGE_TYPE_3D:
2172 return imageExtent;
2173 default:
2174 unreachable("invalid image type");
2175 }
2176 }
2177
2178 static inline struct VkOffset3D
2179 radv_sanitize_image_offset(const VkImageType imageType,
2180 const struct VkOffset3D imageOffset)
2181 {
2182 switch (imageType) {
2183 case VK_IMAGE_TYPE_1D:
2184 return (VkOffset3D) { imageOffset.x, 0, 0 };
2185 case VK_IMAGE_TYPE_2D:
2186 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2187 case VK_IMAGE_TYPE_3D:
2188 return imageOffset;
2189 default:
2190 unreachable("invalid image type");
2191 }
2192 }
2193
2194 static inline bool
2195 radv_image_extent_compare(const struct radv_image *image,
2196 const VkExtent3D *extent)
2197 {
2198 if (extent->width != image->info.width ||
2199 extent->height != image->info.height ||
2200 extent->depth != image->info.depth)
2201 return false;
2202 return true;
2203 }
2204
2205 struct radv_sampler {
2206 struct vk_object_base base;
2207 uint32_t state[4];
2208 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2209 uint32_t border_color_slot;
2210 };
2211
2212 struct radv_framebuffer {
2213 struct vk_object_base base;
2214 uint32_t width;
2215 uint32_t height;
2216 uint32_t layers;
2217
2218 uint32_t attachment_count;
2219 struct radv_image_view *attachments[0];
2220 };
2221
2222 struct radv_subpass_barrier {
2223 VkPipelineStageFlags src_stage_mask;
2224 VkAccessFlags src_access_mask;
2225 VkAccessFlags dst_access_mask;
2226 };
2227
2228 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2229 const struct radv_subpass_barrier *barrier);
2230
2231 struct radv_subpass_attachment {
2232 uint32_t attachment;
2233 VkImageLayout layout;
2234 VkImageLayout stencil_layout;
2235 bool in_render_loop;
2236 };
2237
2238 struct radv_subpass {
2239 uint32_t attachment_count;
2240 struct radv_subpass_attachment * attachments;
2241
2242 uint32_t input_count;
2243 uint32_t color_count;
2244 struct radv_subpass_attachment * input_attachments;
2245 struct radv_subpass_attachment * color_attachments;
2246 struct radv_subpass_attachment * resolve_attachments;
2247 struct radv_subpass_attachment * depth_stencil_attachment;
2248 struct radv_subpass_attachment * ds_resolve_attachment;
2249 VkResolveModeFlagBits depth_resolve_mode;
2250 VkResolveModeFlagBits stencil_resolve_mode;
2251
2252 /** Subpass has at least one color resolve attachment */
2253 bool has_color_resolve;
2254
2255 /** Subpass has at least one color attachment */
2256 bool has_color_att;
2257
2258 struct radv_subpass_barrier start_barrier;
2259
2260 uint32_t view_mask;
2261
2262 VkSampleCountFlagBits color_sample_count;
2263 VkSampleCountFlagBits depth_sample_count;
2264 VkSampleCountFlagBits max_sample_count;
2265 };
2266
2267 uint32_t
2268 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2269
2270 struct radv_render_pass_attachment {
2271 VkFormat format;
2272 uint32_t samples;
2273 VkAttachmentLoadOp load_op;
2274 VkAttachmentLoadOp stencil_load_op;
2275 VkImageLayout initial_layout;
2276 VkImageLayout final_layout;
2277 VkImageLayout stencil_initial_layout;
2278 VkImageLayout stencil_final_layout;
2279
2280 /* The subpass id in which the attachment will be used first/last. */
2281 uint32_t first_subpass_idx;
2282 uint32_t last_subpass_idx;
2283 };
2284
2285 struct radv_render_pass {
2286 struct vk_object_base base;
2287 uint32_t attachment_count;
2288 uint32_t subpass_count;
2289 struct radv_subpass_attachment * subpass_attachments;
2290 struct radv_render_pass_attachment * attachments;
2291 struct radv_subpass_barrier end_barrier;
2292 struct radv_subpass subpasses[0];
2293 };
2294
2295 VkResult radv_device_init_meta(struct radv_device *device);
2296 void radv_device_finish_meta(struct radv_device *device);
2297
2298 struct radv_query_pool {
2299 struct vk_object_base base;
2300 struct radeon_winsys_bo *bo;
2301 uint32_t stride;
2302 uint32_t availability_offset;
2303 uint64_t size;
2304 char *ptr;
2305 VkQueryType type;
2306 uint32_t pipeline_stats_mask;
2307 };
2308
2309 typedef enum {
2310 RADV_SEMAPHORE_NONE,
2311 RADV_SEMAPHORE_WINSYS,
2312 RADV_SEMAPHORE_SYNCOBJ,
2313 RADV_SEMAPHORE_TIMELINE_SYNCOBJ,
2314 RADV_SEMAPHORE_TIMELINE,
2315 } radv_semaphore_kind;
2316
2317 struct radv_deferred_queue_submission;
2318
2319 struct radv_timeline_waiter {
2320 struct list_head list;
2321 struct radv_deferred_queue_submission *submission;
2322 uint64_t value;
2323 };
2324
2325 struct radv_timeline_point {
2326 struct list_head list;
2327
2328 uint64_t value;
2329 uint32_t syncobj;
2330
2331 /* Separate from the list to accomodate CPU wait being async, as well
2332 * as prevent point deletion during submission. */
2333 unsigned wait_count;
2334 };
2335
2336 struct radv_timeline {
2337 /* Using a pthread mutex to be compatible with condition variables. */
2338 pthread_mutex_t mutex;
2339
2340 uint64_t highest_signaled;
2341 uint64_t highest_submitted;
2342
2343 struct list_head points;
2344
2345 /* Keep free points on hand so we do not have to recreate syncobjs all
2346 * the time. */
2347 struct list_head free_points;
2348
2349 /* Submissions that are deferred waiting for a specific value to be
2350 * submitted. */
2351 struct list_head waiters;
2352 };
2353
2354 struct radv_timeline_syncobj {
2355 /* Keep syncobj first, so common-code can just handle this as
2356 * non-timeline syncobj. */
2357 uint32_t syncobj;
2358 uint64_t max_point; /* max submitted point. */
2359 };
2360
2361 struct radv_semaphore_part {
2362 radv_semaphore_kind kind;
2363 union {
2364 uint32_t syncobj;
2365 struct radeon_winsys_sem *ws_sem;
2366 struct radv_timeline timeline;
2367 struct radv_timeline_syncobj timeline_syncobj;
2368 };
2369 };
2370
2371 struct radv_semaphore {
2372 struct vk_object_base base;
2373 struct radv_semaphore_part permanent;
2374 struct radv_semaphore_part temporary;
2375 };
2376
2377 bool radv_queue_internal_submit(struct radv_queue *queue,
2378 struct radeon_cmdbuf *cs);
2379
2380 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2381 VkPipelineBindPoint bind_point,
2382 struct radv_descriptor_set *set,
2383 unsigned idx);
2384
2385 void
2386 radv_update_descriptor_sets(struct radv_device *device,
2387 struct radv_cmd_buffer *cmd_buffer,
2388 VkDescriptorSet overrideSet,
2389 uint32_t descriptorWriteCount,
2390 const VkWriteDescriptorSet *pDescriptorWrites,
2391 uint32_t descriptorCopyCount,
2392 const VkCopyDescriptorSet *pDescriptorCopies);
2393
2394 void
2395 radv_update_descriptor_set_with_template(struct radv_device *device,
2396 struct radv_cmd_buffer *cmd_buffer,
2397 struct radv_descriptor_set *set,
2398 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2399 const void *pData);
2400
2401 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2402 VkPipelineBindPoint pipelineBindPoint,
2403 VkPipelineLayout _layout,
2404 uint32_t set,
2405 uint32_t descriptorWriteCount,
2406 const VkWriteDescriptorSet *pDescriptorWrites);
2407
2408 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2409 struct radv_image *image,
2410 const VkImageSubresourceRange *range, uint32_t value);
2411
2412 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2413 struct radv_image *image,
2414 const VkImageSubresourceRange *range);
2415
2416 typedef enum {
2417 RADV_FENCE_NONE,
2418 RADV_FENCE_WINSYS,
2419 RADV_FENCE_SYNCOBJ,
2420 RADV_FENCE_WSI,
2421 } radv_fence_kind;
2422
2423 struct radv_fence_part {
2424 radv_fence_kind kind;
2425
2426 union {
2427 /* AMDGPU winsys fence. */
2428 struct radeon_winsys_fence *fence;
2429
2430 /* DRM syncobj handle for syncobj-based fences. */
2431 uint32_t syncobj;
2432
2433 /* WSI fence. */
2434 struct wsi_fence *fence_wsi;
2435 };
2436 };
2437
2438 struct radv_fence {
2439 struct vk_object_base base;
2440 struct radv_fence_part permanent;
2441 struct radv_fence_part temporary;
2442 };
2443
2444 /* radv_nir_to_llvm.c */
2445 struct radv_shader_args;
2446
2447 void llvm_compile_shader(struct radv_device *device,
2448 unsigned shader_count,
2449 struct nir_shader *const *shaders,
2450 struct radv_shader_binary **binary,
2451 struct radv_shader_args *args);
2452
2453 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2454 gl_shader_stage stage,
2455 const struct nir_shader *nir);
2456
2457 /* radv_shader_info.h */
2458 struct radv_shader_info;
2459 struct radv_shader_variant_key;
2460
2461 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2462 const struct radv_pipeline_layout *layout,
2463 const struct radv_shader_variant_key *key,
2464 struct radv_shader_info *info,
2465 bool use_llvm);
2466
2467 void radv_nir_shader_info_init(struct radv_shader_info *info);
2468
2469 /* radv_sqtt.c */
2470 struct radv_thread_trace_info {
2471 uint32_t cur_offset;
2472 uint32_t trace_status;
2473 union {
2474 uint32_t gfx9_write_counter;
2475 uint32_t gfx10_dropped_cntr;
2476 };
2477 };
2478
2479 struct radv_thread_trace_se {
2480 struct radv_thread_trace_info info;
2481 void *data_ptr;
2482 uint32_t shader_engine;
2483 uint32_t compute_unit;
2484 };
2485
2486 struct radv_thread_trace {
2487 uint32_t num_traces;
2488 struct radv_thread_trace_se traces[4];
2489 };
2490
2491 bool radv_thread_trace_init(struct radv_device *device);
2492 void radv_thread_trace_finish(struct radv_device *device);
2493 bool radv_begin_thread_trace(struct radv_queue *queue);
2494 bool radv_end_thread_trace(struct radv_queue *queue);
2495 bool radv_get_thread_trace(struct radv_queue *queue,
2496 struct radv_thread_trace *thread_trace);
2497 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2498 const void *data, uint32_t num_dwords);
2499
2500 /* radv_rgp.c */
2501 int radv_dump_thread_trace(struct radv_device *device,
2502 const struct radv_thread_trace *trace);
2503
2504 /* radv_sqtt_layer_.c */
2505 struct radv_barrier_data {
2506 union {
2507 struct {
2508 uint16_t depth_stencil_expand : 1;
2509 uint16_t htile_hiz_range_expand : 1;
2510 uint16_t depth_stencil_resummarize : 1;
2511 uint16_t dcc_decompress : 1;
2512 uint16_t fmask_decompress : 1;
2513 uint16_t fast_clear_eliminate : 1;
2514 uint16_t fmask_color_expand : 1;
2515 uint16_t init_mask_ram : 1;
2516 uint16_t reserved : 8;
2517 };
2518 uint16_t all;
2519 } layout_transitions;
2520 };
2521
2522 /**
2523 * Value for the reason field of an RGP barrier start marker originating from
2524 * the Vulkan client (does not include PAL-defined values). (Table 15)
2525 */
2526 enum rgp_barrier_reason {
2527 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2528
2529 /* External app-generated barrier reasons, i.e. API synchronization
2530 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2531 */
2532 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2533 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2534 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2535
2536 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2537 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2538 */
2539 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2540 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2541 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2542 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2543 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2544 };
2545
2546 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2547 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2548 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2549 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2550 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2551 VkImageAspectFlagBits aspects);
2552 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2553 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2554 enum rgp_barrier_reason reason);
2555 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2556 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2557 const struct radv_barrier_data *barrier);
2558
2559 struct radeon_winsys_sem;
2560
2561 uint64_t radv_get_current_time(void);
2562
2563 static inline uint32_t
2564 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2565 {
2566 switch (gl_prim) {
2567 case 0: /* GL_POINTS */
2568 return 1;
2569 case 1: /* GL_LINES */
2570 case 3: /* GL_LINE_STRIP */
2571 return 2;
2572 case 4: /* GL_TRIANGLES */
2573 case 5: /* GL_TRIANGLE_STRIP */
2574 return 3;
2575 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2576 return 4;
2577 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2578 return 6;
2579 case 7: /* GL_QUADS */
2580 return V_028A6C_TRISTRIP;
2581 default:
2582 assert(0);
2583 return 0;
2584 }
2585 }
2586
2587 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2588 const VkRenderPassBeginInfo *pRenderPassBegin);
2589 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2590
2591 static inline uint32_t si_translate_prim(unsigned topology)
2592 {
2593 switch (topology) {
2594 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2595 return V_008958_DI_PT_POINTLIST;
2596 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2597 return V_008958_DI_PT_LINELIST;
2598 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2599 return V_008958_DI_PT_LINESTRIP;
2600 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2601 return V_008958_DI_PT_TRILIST;
2602 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2603 return V_008958_DI_PT_TRISTRIP;
2604 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2605 return V_008958_DI_PT_TRIFAN;
2606 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2607 return V_008958_DI_PT_LINELIST_ADJ;
2608 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2609 return V_008958_DI_PT_LINESTRIP_ADJ;
2610 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2611 return V_008958_DI_PT_TRILIST_ADJ;
2612 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2613 return V_008958_DI_PT_TRISTRIP_ADJ;
2614 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2615 return V_008958_DI_PT_PATCH;
2616 default:
2617 assert(0);
2618 return 0;
2619 }
2620 }
2621
2622 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2623 {
2624 switch (op) {
2625 case VK_STENCIL_OP_KEEP:
2626 return V_02842C_STENCIL_KEEP;
2627 case VK_STENCIL_OP_ZERO:
2628 return V_02842C_STENCIL_ZERO;
2629 case VK_STENCIL_OP_REPLACE:
2630 return V_02842C_STENCIL_REPLACE_TEST;
2631 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2632 return V_02842C_STENCIL_ADD_CLAMP;
2633 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2634 return V_02842C_STENCIL_SUB_CLAMP;
2635 case VK_STENCIL_OP_INVERT:
2636 return V_02842C_STENCIL_INVERT;
2637 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2638 return V_02842C_STENCIL_ADD_WRAP;
2639 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2640 return V_02842C_STENCIL_SUB_WRAP;
2641 default:
2642 return 0;
2643 }
2644 }
2645
2646 /**
2647 * Helper used for debugging compiler issues by enabling/disabling LLVM for a
2648 * specific shader stage (developers only).
2649 */
2650 static inline bool
2651 radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage)
2652 {
2653 return device->physical_device->use_llvm;
2654 }
2655
2656 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2657 \
2658 static inline struct __radv_type * \
2659 __radv_type ## _from_handle(__VkType _handle) \
2660 { \
2661 return (struct __radv_type *) _handle; \
2662 } \
2663 \
2664 static inline __VkType \
2665 __radv_type ## _to_handle(struct __radv_type *_obj) \
2666 { \
2667 return (__VkType) _obj; \
2668 }
2669
2670 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2671 \
2672 static inline struct __radv_type * \
2673 __radv_type ## _from_handle(__VkType _handle) \
2674 { \
2675 return (struct __radv_type *)(uintptr_t) _handle; \
2676 } \
2677 \
2678 static inline __VkType \
2679 __radv_type ## _to_handle(struct __radv_type *_obj) \
2680 { \
2681 return (__VkType)(uintptr_t) _obj; \
2682 }
2683
2684 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2685 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2686
2687 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2688 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2689 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2690 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2691 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2692
2693 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2694 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2695 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2696 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2697 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2698 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2715
2716 #endif /* RADV_PRIVATE_H */