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[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
61
62 #include <llvm-c/TargetMachine.h>
63
64 /* Pre-declarations needed for WSI entrypoints */
65 struct wl_surface;
66 struct wl_display;
67 typedef struct xcb_connection_t xcb_connection_t;
68 typedef uint32_t xcb_visualid_t;
69 typedef uint32_t xcb_window_t;
70
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
75
76 #include "radv_entrypoints.h"
77
78 #include "wsi_common.h"
79
80 #define ATI_VENDOR_ID 0x1002
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
91 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
92 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define RADV_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97
98 #define NUM_DEPTH_CLEAR_PIPELINES 3
99
100 /*
101 * This is the point we switch from using CP to compute shader
102 * for certain buffer operations.
103 */
104 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
105
106 enum radv_mem_heap {
107 RADV_MEM_HEAP_VRAM,
108 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
109 RADV_MEM_HEAP_GTT,
110 RADV_MEM_HEAP_COUNT
111 };
112
113 enum radv_mem_type {
114 RADV_MEM_TYPE_VRAM,
115 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
116 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
117 RADV_MEM_TYPE_GTT_CACHED,
118 RADV_MEM_TYPE_COUNT
119 };
120
121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
122
123 static inline uint32_t
124 align_u32(uint32_t v, uint32_t a)
125 {
126 assert(a != 0 && a == (a & -a));
127 return (v + a - 1) & ~(a - 1);
128 }
129
130 static inline uint32_t
131 align_u32_npot(uint32_t v, uint32_t a)
132 {
133 return (v + a - 1) / a * a;
134 }
135
136 static inline uint64_t
137 align_u64(uint64_t v, uint64_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 static inline int32_t
144 align_i32(int32_t v, int32_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 /** Alignment must be a power of 2. */
151 static inline bool
152 radv_is_aligned(uintmax_t n, uintmax_t a)
153 {
154 assert(a == (a & -a));
155 return (n & (a - 1)) == 0;
156 }
157
158 static inline uint32_t
159 round_up_u32(uint32_t v, uint32_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint64_t
165 round_up_u64(uint64_t v, uint64_t a)
166 {
167 return (v + a - 1) / a;
168 }
169
170 static inline uint32_t
171 radv_minify(uint32_t n, uint32_t levels)
172 {
173 if (unlikely(n == 0))
174 return 0;
175 else
176 return MAX2(n >> levels, 1);
177 }
178 static inline float
179 radv_clamp_f(float f, float min, float max)
180 {
181 assert(min < max);
182
183 if (f > max)
184 return max;
185 else if (f < min)
186 return min;
187 else
188 return f;
189 }
190
191 static inline bool
192 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
193 {
194 if (*inout_mask & clear_mask) {
195 *inout_mask &= ~clear_mask;
196 return true;
197 } else {
198 return false;
199 }
200 }
201
202 #define for_each_bit(b, dword) \
203 for (uint32_t __dword = (dword); \
204 (b) = __builtin_ffs(__dword) - 1, __dword; \
205 __dword &= ~(1 << (b)))
206
207 #define typed_memcpy(dest, src, count) ({ \
208 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
209 memcpy((dest), (src), (count) * sizeof(*(src))); \
210 })
211
212 /* Whenever we generate an error, pass it through this function. Useful for
213 * debugging, where we can break on it. Only call at error site, not when
214 * propagating errors. Might be useful to plug in a stack trace here.
215 */
216
217 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
218
219 #ifdef DEBUG
220 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
221 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
222 #else
223 #define vk_error(error) error
224 #define vk_errorf(error, format, ...) error
225 #endif
226
227 void __radv_finishme(const char *file, int line, const char *format, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format, va_list va);
231
232 /**
233 * Print a FINISHME message, including its source location.
234 */
235 #define radv_finishme(format, ...) \
236 do { \
237 static bool reported = false; \
238 if (!reported) { \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
240 reported = true; \
241 } \
242 } while (0)
243
244 /* A non-fatal assert. Useful for debugging. */
245 #ifdef DEBUG
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
249 })
250 #else
251 #define radv_assert(x)
252 #endif
253
254 #define stub_return(v) \
255 do { \
256 radv_finishme("stub %s", __func__); \
257 return (v); \
258 } while (0)
259
260 #define stub() \
261 do { \
262 radv_finishme("stub %s", __func__); \
263 return; \
264 } while (0)
265
266 void *radv_lookup_entrypoint_unchecked(const char *name);
267 void *radv_lookup_entrypoint_checked(const char *name,
268 uint32_t core_version,
269 const struct radv_instance_extension_table *instance,
270 const struct radv_device_extension_table *device);
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
281 uint8_t driver_uuid[VK_UUID_SIZE];
282 uint8_t device_uuid[VK_UUID_SIZE];
283 uint8_t cache_uuid[VK_UUID_SIZE];
284
285 int local_fd;
286 struct wsi_device wsi_device;
287
288 bool has_rbplus; /* if RB+ register exist */
289 bool rbplus_allowed; /* if RB+ is allowed */
290 bool has_clear_state;
291 bool cpdma_prefetch_writes_memory;
292 bool has_scissor_bug;
293
294 bool has_out_of_order_rast;
295 bool out_of_order_rast_allowed;
296
297 /* This is the drivers on-disk cache used as a fallback as opposed to
298 * the pipeline cache defined by apps.
299 */
300 struct disk_cache * disk_cache;
301
302 VkPhysicalDeviceMemoryProperties memory_properties;
303 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
304
305 struct radv_device_extension_table supported_extensions;
306 };
307
308 struct radv_instance {
309 VK_LOADER_DATA _loader_data;
310
311 VkAllocationCallbacks alloc;
312
313 uint32_t apiVersion;
314 int physicalDeviceCount;
315 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
316
317 uint64_t debug_flags;
318 uint64_t perftest_flags;
319
320 struct vk_debug_report_instance debug_report_callbacks;
321
322 struct radv_instance_extension_table enabled_extensions;
323 };
324
325 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
326 void radv_finish_wsi(struct radv_physical_device *physical_device);
327
328 bool radv_instance_extension_supported(const char *name);
329 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
330 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
331 const char *name);
332
333 struct cache_entry;
334
335 struct radv_pipeline_cache {
336 struct radv_device * device;
337 pthread_mutex_t mutex;
338
339 uint32_t total_size;
340 uint32_t table_size;
341 uint32_t kernel_count;
342 struct cache_entry ** hash_table;
343 bool modified;
344
345 VkAllocationCallbacks alloc;
346 };
347
348 struct radv_pipeline_key {
349 uint32_t instance_rate_inputs;
350 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
351 unsigned tess_input_vertices;
352 uint32_t col_format;
353 uint32_t is_int8;
354 uint32_t is_int10;
355 uint8_t log2_ps_iter_samples;
356 uint8_t log2_num_samples;
357 uint32_t multisample : 1;
358 uint32_t has_multiview_view_index : 1;
359 };
360
361 void
362 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
363 struct radv_device *device);
364 void
365 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
366 void
367 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
368 const void *data, size_t size);
369
370 struct radv_shader_variant;
371
372 bool
373 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
374 struct radv_pipeline_cache *cache,
375 const unsigned char *sha1,
376 struct radv_shader_variant **variants);
377
378 void
379 radv_pipeline_cache_insert_shaders(struct radv_device *device,
380 struct radv_pipeline_cache *cache,
381 const unsigned char *sha1,
382 struct radv_shader_variant **variants,
383 const void *const *codes,
384 const unsigned *code_sizes);
385
386 enum radv_blit_ds_layout {
387 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
388 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
389 RADV_BLIT_DS_LAYOUT_COUNT,
390 };
391
392 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
393 {
394 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
395 }
396
397 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
398 {
399 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
400 }
401
402 enum radv_meta_dst_layout {
403 RADV_META_DST_LAYOUT_GENERAL,
404 RADV_META_DST_LAYOUT_OPTIMAL,
405 RADV_META_DST_LAYOUT_COUNT,
406 };
407
408 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
409 {
410 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
411 }
412
413 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
414 {
415 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
416 }
417
418 struct radv_meta_state {
419 VkAllocationCallbacks alloc;
420
421 struct radv_pipeline_cache cache;
422
423 /**
424 * Use array element `i` for images with `2^i` samples.
425 */
426 struct {
427 VkRenderPass render_pass[NUM_META_FS_KEYS];
428 VkPipeline color_pipelines[NUM_META_FS_KEYS];
429
430 VkRenderPass depthstencil_rp;
431 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
432 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
433 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
434 } clear[1 + MAX_SAMPLES_LOG2];
435
436 VkPipelineLayout clear_color_p_layout;
437 VkPipelineLayout clear_depth_p_layout;
438 struct {
439 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
440
441 /** Pipeline that blits from a 1D image. */
442 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
443
444 /** Pipeline that blits from a 2D image. */
445 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
446
447 /** Pipeline that blits from a 3D image. */
448 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
449
450 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
451 VkPipeline depth_only_1d_pipeline;
452 VkPipeline depth_only_2d_pipeline;
453 VkPipeline depth_only_3d_pipeline;
454
455 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
456 VkPipeline stencil_only_1d_pipeline;
457 VkPipeline stencil_only_2d_pipeline;
458 VkPipeline stencil_only_3d_pipeline;
459 VkPipelineLayout pipeline_layout;
460 VkDescriptorSetLayout ds_layout;
461 } blit;
462
463 struct {
464 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
465
466 VkPipelineLayout p_layouts[3];
467 VkDescriptorSetLayout ds_layouts[3];
468 VkPipeline pipelines[3][NUM_META_FS_KEYS];
469
470 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
471 VkPipeline depth_only_pipeline[3];
472
473 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
474 VkPipeline stencil_only_pipeline[3];
475 } blit2d;
476
477 struct {
478 VkPipelineLayout img_p_layout;
479 VkDescriptorSetLayout img_ds_layout;
480 VkPipeline pipeline;
481 VkPipeline pipeline_3d;
482 } itob;
483 struct {
484 VkPipelineLayout img_p_layout;
485 VkDescriptorSetLayout img_ds_layout;
486 VkPipeline pipeline;
487 VkPipeline pipeline_3d;
488 } btoi;
489 struct {
490 VkPipelineLayout img_p_layout;
491 VkDescriptorSetLayout img_ds_layout;
492 VkPipeline pipeline;
493 VkPipeline pipeline_3d;
494 } itoi;
495 struct {
496 VkPipelineLayout img_p_layout;
497 VkDescriptorSetLayout img_ds_layout;
498 VkPipeline pipeline;
499 VkPipeline pipeline_3d;
500 } cleari;
501
502 struct {
503 VkPipelineLayout p_layout;
504 VkPipeline pipeline[NUM_META_FS_KEYS];
505 VkRenderPass pass[NUM_META_FS_KEYS];
506 } resolve;
507
508 struct {
509 VkDescriptorSetLayout ds_layout;
510 VkPipelineLayout p_layout;
511 struct {
512 VkPipeline pipeline;
513 VkPipeline i_pipeline;
514 VkPipeline srgb_pipeline;
515 } rc[MAX_SAMPLES_LOG2];
516 } resolve_compute;
517
518 struct {
519 VkDescriptorSetLayout ds_layout;
520 VkPipelineLayout p_layout;
521
522 struct {
523 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
524 VkPipeline pipeline[NUM_META_FS_KEYS];
525 } rc[MAX_SAMPLES_LOG2];
526 } resolve_fragment;
527
528 struct {
529 VkPipelineLayout p_layout;
530 VkPipeline decompress_pipeline;
531 VkPipeline resummarize_pipeline;
532 VkRenderPass pass;
533 } depth_decomp[1 + MAX_SAMPLES_LOG2];
534
535 struct {
536 VkPipelineLayout p_layout;
537 VkPipeline cmask_eliminate_pipeline;
538 VkPipeline fmask_decompress_pipeline;
539 VkPipeline dcc_decompress_pipeline;
540 VkRenderPass pass;
541
542 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
543 VkPipelineLayout dcc_decompress_compute_p_layout;
544 VkPipeline dcc_decompress_compute_pipeline;
545 } fast_clear_flush;
546
547 struct {
548 VkPipelineLayout fill_p_layout;
549 VkPipelineLayout copy_p_layout;
550 VkDescriptorSetLayout fill_ds_layout;
551 VkDescriptorSetLayout copy_ds_layout;
552 VkPipeline fill_pipeline;
553 VkPipeline copy_pipeline;
554 } buffer;
555
556 struct {
557 VkDescriptorSetLayout ds_layout;
558 VkPipelineLayout p_layout;
559 VkPipeline occlusion_query_pipeline;
560 VkPipeline pipeline_statistics_query_pipeline;
561 } query;
562 };
563
564 /* queue types */
565 #define RADV_QUEUE_GENERAL 0
566 #define RADV_QUEUE_COMPUTE 1
567 #define RADV_QUEUE_TRANSFER 2
568
569 #define RADV_MAX_QUEUE_FAMILIES 3
570
571 enum ring_type radv_queue_family_to_ring(int f);
572
573 struct radv_queue {
574 VK_LOADER_DATA _loader_data;
575 struct radv_device * device;
576 struct radeon_winsys_ctx *hw_ctx;
577 enum radeon_ctx_priority priority;
578 uint32_t queue_family_index;
579 int queue_idx;
580 VkDeviceQueueCreateFlags flags;
581
582 uint32_t scratch_size;
583 uint32_t compute_scratch_size;
584 uint32_t esgs_ring_size;
585 uint32_t gsvs_ring_size;
586 bool has_tess_rings;
587 bool has_sample_positions;
588
589 struct radeon_winsys_bo *scratch_bo;
590 struct radeon_winsys_bo *descriptor_bo;
591 struct radeon_winsys_bo *compute_scratch_bo;
592 struct radeon_winsys_bo *esgs_ring_bo;
593 struct radeon_winsys_bo *gsvs_ring_bo;
594 struct radeon_winsys_bo *tess_rings_bo;
595 struct radeon_winsys_cs *initial_preamble_cs;
596 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
597 struct radeon_winsys_cs *continue_preamble_cs;
598 };
599
600 struct radv_device {
601 VK_LOADER_DATA _loader_data;
602
603 VkAllocationCallbacks alloc;
604
605 struct radv_instance * instance;
606 struct radeon_winsys *ws;
607
608 struct radv_meta_state meta_state;
609
610 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
611 int queue_count[RADV_MAX_QUEUE_FAMILIES];
612 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
613
614 bool always_use_syncobj;
615 bool llvm_supports_spill;
616 bool has_distributed_tess;
617 bool pbb_allowed;
618 bool dfsm_allowed;
619 uint32_t tess_offchip_block_dw_size;
620 uint32_t scratch_waves;
621 uint32_t dispatch_initiator;
622
623 uint32_t gs_table_depth;
624
625 /* MSAA sample locations.
626 * The first index is the sample index.
627 * The second index is the coordinate: X, Y. */
628 float sample_locations_1x[1][2];
629 float sample_locations_2x[2][2];
630 float sample_locations_4x[4][2];
631 float sample_locations_8x[8][2];
632 float sample_locations_16x[16][2];
633
634 /* CIK and later */
635 uint32_t gfx_init_size_dw;
636 struct radeon_winsys_bo *gfx_init;
637
638 struct radeon_winsys_bo *trace_bo;
639 uint32_t *trace_id_ptr;
640
641 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
642 bool keep_shader_info;
643
644 struct radv_physical_device *physical_device;
645
646 /* Backup in-memory cache to be used if the app doesn't provide one */
647 struct radv_pipeline_cache * mem_cache;
648
649 /*
650 * use different counters so MSAA MRTs get consecutive surface indices,
651 * even if MASK is allocated in between.
652 */
653 uint32_t image_mrt_offset_counter;
654 uint32_t fmask_mrt_offset_counter;
655 struct list_head shader_slabs;
656 mtx_t shader_slab_mutex;
657
658 /* For detecting VM faults reported by dmesg. */
659 uint64_t dmesg_timestamp;
660
661 struct radv_device_extension_table enabled_extensions;
662 };
663
664 struct radv_device_memory {
665 struct radeon_winsys_bo *bo;
666 /* for dedicated allocations */
667 struct radv_image *image;
668 struct radv_buffer *buffer;
669 uint32_t type_index;
670 VkDeviceSize map_size;
671 void * map;
672 void * user_ptr;
673 };
674
675
676 struct radv_descriptor_range {
677 uint64_t va;
678 uint32_t size;
679 };
680
681 struct radv_descriptor_set {
682 const struct radv_descriptor_set_layout *layout;
683 uint32_t size;
684
685 struct radeon_winsys_bo *bo;
686 uint64_t va;
687 uint32_t *mapped_ptr;
688 struct radv_descriptor_range *dynamic_descriptors;
689
690 struct radeon_winsys_bo *descriptors[0];
691 };
692
693 struct radv_push_descriptor_set
694 {
695 struct radv_descriptor_set set;
696 uint32_t capacity;
697 };
698
699 struct radv_descriptor_pool_entry {
700 uint32_t offset;
701 uint32_t size;
702 struct radv_descriptor_set *set;
703 };
704
705 struct radv_descriptor_pool {
706 struct radeon_winsys_bo *bo;
707 uint8_t *mapped_ptr;
708 uint64_t current_offset;
709 uint64_t size;
710
711 uint8_t *host_memory_base;
712 uint8_t *host_memory_ptr;
713 uint8_t *host_memory_end;
714
715 uint32_t entry_count;
716 uint32_t max_entry_count;
717 struct radv_descriptor_pool_entry entries[0];
718 };
719
720 struct radv_descriptor_update_template_entry {
721 VkDescriptorType descriptor_type;
722
723 /* The number of descriptors to update */
724 uint32_t descriptor_count;
725
726 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
727 uint32_t dst_offset;
728
729 /* In dwords. Not valid/used for dynamic descriptors */
730 uint32_t dst_stride;
731
732 uint32_t buffer_offset;
733
734 /* Only valid for combined image samplers and samplers */
735 uint16_t has_sampler;
736
737 /* In bytes */
738 size_t src_offset;
739 size_t src_stride;
740
741 /* For push descriptors */
742 const uint32_t *immutable_samplers;
743 };
744
745 struct radv_descriptor_update_template {
746 uint32_t entry_count;
747 VkPipelineBindPoint bind_point;
748 struct radv_descriptor_update_template_entry entry[0];
749 };
750
751 struct radv_buffer {
752 VkDeviceSize size;
753
754 VkBufferUsageFlags usage;
755 VkBufferCreateFlags flags;
756
757 /* Set when bound */
758 struct radeon_winsys_bo * bo;
759 VkDeviceSize offset;
760
761 bool shareable;
762 };
763
764 enum radv_dynamic_state_bits {
765 RADV_DYNAMIC_VIEWPORT = 1 << 0,
766 RADV_DYNAMIC_SCISSOR = 1 << 1,
767 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
768 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
769 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
770 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
771 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
772 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
773 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
774 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
775 RADV_DYNAMIC_ALL = (1 << 10) - 1,
776 };
777
778 enum radv_cmd_dirty_bits {
779 /* Keep the dynamic state dirty bits in sync with
780 * enum radv_dynamic_state_bits */
781 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
782 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
783 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
784 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
785 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
786 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
787 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
788 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
789 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
790 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
791 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
792 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
793 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
794 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
795 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
796 };
797
798 enum radv_cmd_flush_bits {
799 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
800 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
801 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
802 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
803 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
804 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
805 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
806 /* Same as above, but only writes back and doesn't invalidate */
807 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
808 /* Framebuffer caches */
809 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
810 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
811 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
812 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
813 /* Engine synchronization. */
814 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
815 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
816 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
817 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
818
819 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
820 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
821 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
822 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
823 };
824
825 struct radv_vertex_binding {
826 struct radv_buffer * buffer;
827 VkDeviceSize offset;
828 };
829
830 struct radv_viewport_state {
831 uint32_t count;
832 VkViewport viewports[MAX_VIEWPORTS];
833 };
834
835 struct radv_scissor_state {
836 uint32_t count;
837 VkRect2D scissors[MAX_SCISSORS];
838 };
839
840 struct radv_discard_rectangle_state {
841 uint32_t count;
842 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
843 };
844
845 struct radv_dynamic_state {
846 /**
847 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
848 * Defines the set of saved dynamic state.
849 */
850 uint32_t mask;
851
852 struct radv_viewport_state viewport;
853
854 struct radv_scissor_state scissor;
855
856 float line_width;
857
858 struct {
859 float bias;
860 float clamp;
861 float slope;
862 } depth_bias;
863
864 float blend_constants[4];
865
866 struct {
867 float min;
868 float max;
869 } depth_bounds;
870
871 struct {
872 uint32_t front;
873 uint32_t back;
874 } stencil_compare_mask;
875
876 struct {
877 uint32_t front;
878 uint32_t back;
879 } stencil_write_mask;
880
881 struct {
882 uint32_t front;
883 uint32_t back;
884 } stencil_reference;
885
886 struct radv_discard_rectangle_state discard_rectangle;
887 };
888
889 extern const struct radv_dynamic_state default_dynamic_state;
890
891 const char *
892 radv_get_debug_option_name(int id);
893
894 const char *
895 radv_get_perftest_option_name(int id);
896
897 /**
898 * Attachment state when recording a renderpass instance.
899 *
900 * The clear value is valid only if there exists a pending clear.
901 */
902 struct radv_attachment_state {
903 VkImageAspectFlags pending_clear_aspects;
904 uint32_t cleared_views;
905 VkClearValue clear_value;
906 VkImageLayout current_layout;
907 };
908
909 struct radv_descriptor_state {
910 struct radv_descriptor_set *sets[MAX_SETS];
911 uint32_t dirty;
912 uint32_t valid;
913 struct radv_push_descriptor_set push_set;
914 bool push_dirty;
915 };
916
917 struct radv_cmd_state {
918 /* Vertex descriptors */
919 uint64_t vb_va;
920 unsigned vb_size;
921
922 bool predicating;
923 uint32_t dirty;
924
925 uint32_t prefetch_L2_mask;
926
927 struct radv_pipeline * pipeline;
928 struct radv_pipeline * emitted_pipeline;
929 struct radv_pipeline * compute_pipeline;
930 struct radv_pipeline * emitted_compute_pipeline;
931 struct radv_framebuffer * framebuffer;
932 struct radv_render_pass * pass;
933 const struct radv_subpass * subpass;
934 struct radv_dynamic_state dynamic;
935 struct radv_attachment_state * attachments;
936 VkRect2D render_area;
937
938 /* Index buffer */
939 struct radv_buffer *index_buffer;
940 uint64_t index_offset;
941 uint32_t index_type;
942 uint32_t max_index_count;
943 uint64_t index_va;
944 int32_t last_index_type;
945
946 int32_t last_primitive_reset_en;
947 uint32_t last_primitive_reset_index;
948 enum radv_cmd_flush_bits flush_bits;
949 unsigned active_occlusion_queries;
950 bool perfect_occlusion_queries_enabled;
951 float offset_scale;
952 uint32_t trace_id;
953 uint32_t last_ia_multi_vgt_param;
954
955 uint32_t last_num_instances;
956 uint32_t last_first_instance;
957 uint32_t last_vertex_offset;
958 };
959
960 struct radv_cmd_pool {
961 VkAllocationCallbacks alloc;
962 struct list_head cmd_buffers;
963 struct list_head free_cmd_buffers;
964 uint32_t queue_family_index;
965 };
966
967 struct radv_cmd_buffer_upload {
968 uint8_t *map;
969 unsigned offset;
970 uint64_t size;
971 struct radeon_winsys_bo *upload_bo;
972 struct list_head list;
973 };
974
975 enum radv_cmd_buffer_status {
976 RADV_CMD_BUFFER_STATUS_INVALID,
977 RADV_CMD_BUFFER_STATUS_INITIAL,
978 RADV_CMD_BUFFER_STATUS_RECORDING,
979 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
980 RADV_CMD_BUFFER_STATUS_PENDING,
981 };
982
983 struct radv_cmd_buffer {
984 VK_LOADER_DATA _loader_data;
985
986 struct radv_device * device;
987
988 struct radv_cmd_pool * pool;
989 struct list_head pool_link;
990
991 VkCommandBufferUsageFlags usage_flags;
992 VkCommandBufferLevel level;
993 enum radv_cmd_buffer_status status;
994 struct radeon_winsys_cs *cs;
995 struct radv_cmd_state state;
996 struct radv_vertex_binding vertex_bindings[MAX_VBS];
997 uint32_t queue_family_index;
998
999 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1000 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1001 VkShaderStageFlags push_constant_stages;
1002 struct radv_descriptor_set meta_push_descriptors;
1003
1004 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1005
1006 struct radv_cmd_buffer_upload upload;
1007
1008 uint32_t scratch_size_needed;
1009 uint32_t compute_scratch_size_needed;
1010 uint32_t esgs_ring_size_needed;
1011 uint32_t gsvs_ring_size_needed;
1012 bool tess_rings_needed;
1013 bool sample_positions_needed;
1014
1015 VkResult record_result;
1016
1017 int ring_offsets_idx; /* just used for verification */
1018 uint32_t gfx9_fence_offset;
1019 struct radeon_winsys_bo *gfx9_fence_bo;
1020 uint32_t gfx9_fence_idx;
1021
1022 /**
1023 * Whether a query pool has been resetted and we have to flush caches.
1024 */
1025 bool pending_reset_query;
1026 };
1027
1028 struct radv_image;
1029
1030 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1031
1032 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1033 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1034
1035 void cik_create_gfx_config(struct radv_device *device);
1036
1037 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1038 int count, const VkViewport *viewports);
1039 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1040 int count, const VkRect2D *scissors,
1041 const VkViewport *viewports, bool can_use_guardband);
1042 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1043 bool instanced_draw, bool indirect_draw,
1044 uint32_t draw_vertex_count);
1045 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1046 bool predicated,
1047 enum chip_class chip_class,
1048 bool is_mec,
1049 unsigned event, unsigned event_flags,
1050 unsigned data_sel,
1051 uint64_t va,
1052 uint32_t old_fence,
1053 uint32_t new_fence);
1054
1055 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1056 bool predicated,
1057 uint64_t va, uint32_t ref,
1058 uint32_t mask);
1059 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1060 enum chip_class chip_class,
1061 uint32_t *fence_ptr, uint64_t va,
1062 bool is_mec,
1063 enum radv_cmd_flush_bits flush_bits);
1064 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1065 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1066 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1067 uint64_t src_va, uint64_t dest_va,
1068 uint64_t size);
1069 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1070 unsigned size);
1071 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1072 uint64_t size, unsigned value);
1073 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1074 bool
1075 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1076 unsigned size,
1077 unsigned alignment,
1078 unsigned *out_offset,
1079 void **ptr);
1080 void
1081 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1082 const struct radv_subpass *subpass,
1083 bool transitions);
1084 bool
1085 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1086 unsigned size, unsigned alignmnet,
1087 const void *data, unsigned *out_offset);
1088
1089 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1090 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1091 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1092 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1093 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1094 unsigned radv_cayman_get_maxdist(int log_samples);
1095 void radv_device_init_msaa(struct radv_device *device);
1096 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1097 struct radv_image *image,
1098 VkClearDepthStencilValue ds_clear_value,
1099 VkImageAspectFlags aspects);
1100 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1101 struct radv_image *image,
1102 int idx,
1103 uint32_t color_values[2]);
1104 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1105 struct radv_image *image,
1106 bool value);
1107 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1108 struct radeon_winsys_bo *bo,
1109 uint64_t offset, uint64_t size, uint32_t value);
1110 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1111 bool radv_get_memory_fd(struct radv_device *device,
1112 struct radv_device_memory *memory,
1113 int *pFD);
1114
1115 static inline struct radv_descriptor_state *
1116 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1117 VkPipelineBindPoint bind_point)
1118 {
1119 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1120 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1121 return &cmd_buffer->descriptors[bind_point];
1122 }
1123
1124 /*
1125 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1126 *
1127 * Limitations: Can't call normal dispatch functions without binding or rebinding
1128 * the compute pipeline.
1129 */
1130 void radv_unaligned_dispatch(
1131 struct radv_cmd_buffer *cmd_buffer,
1132 uint32_t x,
1133 uint32_t y,
1134 uint32_t z);
1135
1136 struct radv_event {
1137 struct radeon_winsys_bo *bo;
1138 uint64_t *map;
1139 };
1140
1141 struct radv_shader_module;
1142
1143 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1144 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1145 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1146 void
1147 radv_hash_shaders(unsigned char *hash,
1148 const VkPipelineShaderStageCreateInfo **stages,
1149 const struct radv_pipeline_layout *layout,
1150 const struct radv_pipeline_key *key,
1151 uint32_t flags);
1152
1153 static inline gl_shader_stage
1154 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1155 {
1156 assert(__builtin_popcount(vk_stage) == 1);
1157 return ffs(vk_stage) - 1;
1158 }
1159
1160 static inline VkShaderStageFlagBits
1161 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1162 {
1163 return (1 << mesa_stage);
1164 }
1165
1166 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1167
1168 #define radv_foreach_stage(stage, stage_bits) \
1169 for (gl_shader_stage stage, \
1170 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1171 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1172 __tmp &= ~(1 << (stage)))
1173
1174 unsigned radv_format_meta_fs_key(VkFormat format);
1175
1176 struct radv_multisample_state {
1177 uint32_t db_eqaa;
1178 uint32_t pa_sc_line_cntl;
1179 uint32_t pa_sc_mode_cntl_0;
1180 uint32_t pa_sc_mode_cntl_1;
1181 uint32_t pa_sc_aa_config;
1182 uint32_t pa_sc_aa_mask[2];
1183 unsigned num_samples;
1184 };
1185
1186 struct radv_prim_vertex_count {
1187 uint8_t min;
1188 uint8_t incr;
1189 };
1190
1191 struct radv_vertex_elements_info {
1192 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1193 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1194 uint32_t binding[MAX_VERTEX_ATTRIBS];
1195 uint32_t offset[MAX_VERTEX_ATTRIBS];
1196 uint32_t count;
1197 };
1198
1199 struct radv_ia_multi_vgt_param_helpers {
1200 uint32_t base;
1201 bool partial_es_wave;
1202 uint8_t primgroup_size;
1203 bool wd_switch_on_eop;
1204 bool ia_switch_on_eoi;
1205 bool partial_vs_wave;
1206 };
1207
1208 #define SI_GS_PER_ES 128
1209
1210 struct radv_pipeline {
1211 struct radv_device * device;
1212 struct radv_dynamic_state dynamic_state;
1213
1214 struct radv_pipeline_layout * layout;
1215
1216 bool need_indirect_descriptor_sets;
1217 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1218 struct radv_shader_variant *gs_copy_shader;
1219 VkShaderStageFlags active_stages;
1220
1221 struct radeon_winsys_cs cs;
1222
1223 struct radv_vertex_elements_info vertex_elements;
1224
1225 uint32_t binding_stride[MAX_VBS];
1226
1227 uint32_t user_data_0[MESA_SHADER_STAGES];
1228 union {
1229 struct {
1230 struct radv_multisample_state ms;
1231 uint32_t spi_baryc_cntl;
1232 bool prim_restart_enable;
1233 unsigned esgs_ring_size;
1234 unsigned gsvs_ring_size;
1235 uint32_t vtx_base_sgpr;
1236 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1237 uint8_t vtx_emit_num;
1238 struct radv_prim_vertex_count prim_vertex_count;
1239 bool can_use_guardband;
1240 uint32_t needed_dynamic_state;
1241 bool disable_out_of_order_rast_for_occlusion;
1242
1243 /* Used for rbplus */
1244 uint32_t col_format;
1245 uint32_t cb_target_mask;
1246 } graphics;
1247 };
1248
1249 unsigned max_waves;
1250 unsigned scratch_bytes_per_wave;
1251 };
1252
1253 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1254 {
1255 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1256 }
1257
1258 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1259 {
1260 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1261 }
1262
1263 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1264 gl_shader_stage stage,
1265 int idx);
1266
1267 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1268
1269 struct radv_graphics_pipeline_create_info {
1270 bool use_rectlist;
1271 bool db_depth_clear;
1272 bool db_stencil_clear;
1273 bool db_depth_disable_expclear;
1274 bool db_stencil_disable_expclear;
1275 bool db_flush_depth_inplace;
1276 bool db_flush_stencil_inplace;
1277 bool db_resummarize;
1278 uint32_t custom_blend_mode;
1279 };
1280
1281 VkResult
1282 radv_graphics_pipeline_create(VkDevice device,
1283 VkPipelineCache cache,
1284 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1285 const struct radv_graphics_pipeline_create_info *extra,
1286 const VkAllocationCallbacks *alloc,
1287 VkPipeline *pPipeline);
1288
1289 struct vk_format_description;
1290 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1291 int first_non_void);
1292 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1293 int first_non_void);
1294 uint32_t radv_translate_colorformat(VkFormat format);
1295 uint32_t radv_translate_color_numformat(VkFormat format,
1296 const struct vk_format_description *desc,
1297 int first_non_void);
1298 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1299 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1300 uint32_t radv_translate_dbformat(VkFormat format);
1301 uint32_t radv_translate_tex_dataformat(VkFormat format,
1302 const struct vk_format_description *desc,
1303 int first_non_void);
1304 uint32_t radv_translate_tex_numformat(VkFormat format,
1305 const struct vk_format_description *desc,
1306 int first_non_void);
1307 bool radv_format_pack_clear_color(VkFormat format,
1308 uint32_t clear_vals[2],
1309 VkClearColorValue *value);
1310 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1311 bool radv_dcc_formats_compatible(VkFormat format1,
1312 VkFormat format2);
1313
1314 struct radv_fmask_info {
1315 uint64_t offset;
1316 uint64_t size;
1317 unsigned alignment;
1318 unsigned pitch_in_pixels;
1319 unsigned bank_height;
1320 unsigned slice_tile_max;
1321 unsigned tile_mode_index;
1322 unsigned tile_swizzle;
1323 };
1324
1325 struct radv_cmask_info {
1326 uint64_t offset;
1327 uint64_t size;
1328 unsigned alignment;
1329 unsigned slice_tile_max;
1330 };
1331
1332 struct radv_image {
1333 VkImageType type;
1334 /* The original VkFormat provided by the client. This may not match any
1335 * of the actual surface formats.
1336 */
1337 VkFormat vk_format;
1338 VkImageAspectFlags aspects;
1339 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1340 struct ac_surf_info info;
1341 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1342 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1343
1344 VkDeviceSize size;
1345 uint32_t alignment;
1346
1347 unsigned queue_family_mask;
1348 bool exclusive;
1349 bool shareable;
1350
1351 /* Set when bound */
1352 struct radeon_winsys_bo *bo;
1353 VkDeviceSize offset;
1354 uint64_t dcc_offset;
1355 uint64_t htile_offset;
1356 bool tc_compatible_htile;
1357 struct radeon_surf surface;
1358
1359 struct radv_fmask_info fmask;
1360 struct radv_cmask_info cmask;
1361 uint64_t clear_value_offset;
1362 uint64_t dcc_pred_offset;
1363
1364 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1365 VkDeviceMemory owned_memory;
1366 };
1367
1368 /* Whether the image has a htile that is known consistent with the contents of
1369 * the image. */
1370 bool radv_layout_has_htile(const struct radv_image *image,
1371 VkImageLayout layout,
1372 unsigned queue_mask);
1373
1374 /* Whether the image has a htile that is known consistent with the contents of
1375 * the image and is allowed to be in compressed form.
1376 *
1377 * If this is false reads that don't use the htile should be able to return
1378 * correct results.
1379 */
1380 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1381 VkImageLayout layout,
1382 unsigned queue_mask);
1383
1384 bool radv_layout_can_fast_clear(const struct radv_image *image,
1385 VkImageLayout layout,
1386 unsigned queue_mask);
1387
1388 bool radv_layout_dcc_compressed(const struct radv_image *image,
1389 VkImageLayout layout,
1390 unsigned queue_mask);
1391
1392 /**
1393 * Return whether the image has CMASK metadata for color surfaces.
1394 */
1395 static inline bool
1396 radv_image_has_cmask(const struct radv_image *image)
1397 {
1398 return image->cmask.size;
1399 }
1400
1401 /**
1402 * Return whether the image has FMASK metadata for color surfaces.
1403 */
1404 static inline bool
1405 radv_image_has_fmask(const struct radv_image *image)
1406 {
1407 return image->fmask.size;
1408 }
1409
1410 /**
1411 * Return whether the image has DCC metadata for color surfaces.
1412 */
1413 static inline bool
1414 radv_image_has_dcc(const struct radv_image *image)
1415 {
1416 return image->surface.dcc_size;
1417 }
1418
1419 /**
1420 * Return whether DCC metadata is enabled for a level.
1421 */
1422 static inline bool
1423 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1424 {
1425 return radv_image_has_dcc(image) &&
1426 level < image->surface.num_dcc_levels;
1427 }
1428
1429 /**
1430 * Return whether the image has HTILE metadata for depth surfaces.
1431 */
1432 static inline bool
1433 radv_image_has_htile(const struct radv_image *image)
1434 {
1435 return image->surface.htile_size;
1436 }
1437
1438 /**
1439 * Return whether HTILE metadata is enabled for a level.
1440 */
1441 static inline bool
1442 radv_htile_enabled(const struct radv_image *image, unsigned level)
1443 {
1444 return radv_image_has_htile(image) && level == 0;
1445 }
1446
1447 /**
1448 * Return whether the image is TC-compatible HTILE.
1449 */
1450 static inline bool
1451 radv_image_is_tc_compat_htile(const struct radv_image *image)
1452 {
1453 return radv_image_has_htile(image) && image->tc_compatible_htile;
1454 }
1455
1456 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1457
1458 static inline uint32_t
1459 radv_get_layerCount(const struct radv_image *image,
1460 const VkImageSubresourceRange *range)
1461 {
1462 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1463 image->info.array_size - range->baseArrayLayer : range->layerCount;
1464 }
1465
1466 static inline uint32_t
1467 radv_get_levelCount(const struct radv_image *image,
1468 const VkImageSubresourceRange *range)
1469 {
1470 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1471 image->info.levels - range->baseMipLevel : range->levelCount;
1472 }
1473
1474 struct radeon_bo_metadata;
1475 void
1476 radv_init_metadata(struct radv_device *device,
1477 struct radv_image *image,
1478 struct radeon_bo_metadata *metadata);
1479
1480 struct radv_image_view {
1481 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1482 struct radeon_winsys_bo *bo;
1483
1484 VkImageViewType type;
1485 VkImageAspectFlags aspect_mask;
1486 VkFormat vk_format;
1487 uint32_t base_layer;
1488 uint32_t layer_count;
1489 uint32_t base_mip;
1490 uint32_t level_count;
1491 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1492
1493 uint32_t descriptor[16];
1494
1495 /* Descriptor for use as a storage image as opposed to a sampled image.
1496 * This has a few differences for cube maps (e.g. type).
1497 */
1498 uint32_t storage_descriptor[16];
1499 };
1500
1501 struct radv_image_create_info {
1502 const VkImageCreateInfo *vk_info;
1503 bool scanout;
1504 bool no_metadata_planes;
1505 };
1506
1507 VkResult radv_image_create(VkDevice _device,
1508 const struct radv_image_create_info *info,
1509 const VkAllocationCallbacks* alloc,
1510 VkImage *pImage);
1511
1512 VkResult
1513 radv_image_from_gralloc(VkDevice device_h,
1514 const VkImageCreateInfo *base_info,
1515 const VkNativeBufferANDROID *gralloc_info,
1516 const VkAllocationCallbacks *alloc,
1517 VkImage *out_image_h);
1518
1519 void radv_image_view_init(struct radv_image_view *view,
1520 struct radv_device *device,
1521 const VkImageViewCreateInfo* pCreateInfo);
1522
1523 struct radv_buffer_view {
1524 struct radeon_winsys_bo *bo;
1525 VkFormat vk_format;
1526 uint64_t range; /**< VkBufferViewCreateInfo::range */
1527 uint32_t state[4];
1528 };
1529 void radv_buffer_view_init(struct radv_buffer_view *view,
1530 struct radv_device *device,
1531 const VkBufferViewCreateInfo* pCreateInfo);
1532
1533 static inline struct VkExtent3D
1534 radv_sanitize_image_extent(const VkImageType imageType,
1535 const struct VkExtent3D imageExtent)
1536 {
1537 switch (imageType) {
1538 case VK_IMAGE_TYPE_1D:
1539 return (VkExtent3D) { imageExtent.width, 1, 1 };
1540 case VK_IMAGE_TYPE_2D:
1541 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1542 case VK_IMAGE_TYPE_3D:
1543 return imageExtent;
1544 default:
1545 unreachable("invalid image type");
1546 }
1547 }
1548
1549 static inline struct VkOffset3D
1550 radv_sanitize_image_offset(const VkImageType imageType,
1551 const struct VkOffset3D imageOffset)
1552 {
1553 switch (imageType) {
1554 case VK_IMAGE_TYPE_1D:
1555 return (VkOffset3D) { imageOffset.x, 0, 0 };
1556 case VK_IMAGE_TYPE_2D:
1557 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1558 case VK_IMAGE_TYPE_3D:
1559 return imageOffset;
1560 default:
1561 unreachable("invalid image type");
1562 }
1563 }
1564
1565 static inline bool
1566 radv_image_extent_compare(const struct radv_image *image,
1567 const VkExtent3D *extent)
1568 {
1569 if (extent->width != image->info.width ||
1570 extent->height != image->info.height ||
1571 extent->depth != image->info.depth)
1572 return false;
1573 return true;
1574 }
1575
1576 struct radv_sampler {
1577 uint32_t state[4];
1578 };
1579
1580 struct radv_color_buffer_info {
1581 uint64_t cb_color_base;
1582 uint64_t cb_color_cmask;
1583 uint64_t cb_color_fmask;
1584 uint64_t cb_dcc_base;
1585 uint32_t cb_color_pitch;
1586 uint32_t cb_color_slice;
1587 uint32_t cb_color_view;
1588 uint32_t cb_color_info;
1589 uint32_t cb_color_attrib;
1590 uint32_t cb_color_attrib2;
1591 uint32_t cb_dcc_control;
1592 uint32_t cb_color_cmask_slice;
1593 uint32_t cb_color_fmask_slice;
1594 };
1595
1596 struct radv_ds_buffer_info {
1597 uint64_t db_z_read_base;
1598 uint64_t db_stencil_read_base;
1599 uint64_t db_z_write_base;
1600 uint64_t db_stencil_write_base;
1601 uint64_t db_htile_data_base;
1602 uint32_t db_depth_info;
1603 uint32_t db_z_info;
1604 uint32_t db_stencil_info;
1605 uint32_t db_depth_view;
1606 uint32_t db_depth_size;
1607 uint32_t db_depth_slice;
1608 uint32_t db_htile_surface;
1609 uint32_t pa_su_poly_offset_db_fmt_cntl;
1610 uint32_t db_z_info2;
1611 uint32_t db_stencil_info2;
1612 float offset_scale;
1613 };
1614
1615 struct radv_attachment_info {
1616 union {
1617 struct radv_color_buffer_info cb;
1618 struct radv_ds_buffer_info ds;
1619 };
1620 struct radv_image_view *attachment;
1621 };
1622
1623 struct radv_framebuffer {
1624 uint32_t width;
1625 uint32_t height;
1626 uint32_t layers;
1627
1628 uint32_t attachment_count;
1629 struct radv_attachment_info attachments[0];
1630 };
1631
1632 struct radv_subpass_barrier {
1633 VkPipelineStageFlags src_stage_mask;
1634 VkAccessFlags src_access_mask;
1635 VkAccessFlags dst_access_mask;
1636 };
1637
1638 struct radv_subpass {
1639 uint32_t input_count;
1640 uint32_t color_count;
1641 VkAttachmentReference * input_attachments;
1642 VkAttachmentReference * color_attachments;
1643 VkAttachmentReference * resolve_attachments;
1644 VkAttachmentReference depth_stencil_attachment;
1645
1646 /** Subpass has at least one resolve attachment */
1647 bool has_resolve;
1648
1649 struct radv_subpass_barrier start_barrier;
1650
1651 uint32_t view_mask;
1652 VkSampleCountFlagBits max_sample_count;
1653 };
1654
1655 struct radv_render_pass_attachment {
1656 VkFormat format;
1657 uint32_t samples;
1658 VkAttachmentLoadOp load_op;
1659 VkAttachmentLoadOp stencil_load_op;
1660 VkImageLayout initial_layout;
1661 VkImageLayout final_layout;
1662 uint32_t view_mask;
1663 };
1664
1665 struct radv_render_pass {
1666 uint32_t attachment_count;
1667 uint32_t subpass_count;
1668 VkAttachmentReference * subpass_attachments;
1669 struct radv_render_pass_attachment * attachments;
1670 struct radv_subpass_barrier end_barrier;
1671 struct radv_subpass subpasses[0];
1672 };
1673
1674 VkResult radv_device_init_meta(struct radv_device *device);
1675 void radv_device_finish_meta(struct radv_device *device);
1676
1677 struct radv_query_pool {
1678 struct radeon_winsys_bo *bo;
1679 uint32_t stride;
1680 uint32_t availability_offset;
1681 uint64_t size;
1682 char *ptr;
1683 VkQueryType type;
1684 uint32_t pipeline_stats_mask;
1685 };
1686
1687 struct radv_semaphore {
1688 /* use a winsys sem for non-exportable */
1689 struct radeon_winsys_sem *sem;
1690 uint32_t syncobj;
1691 uint32_t temp_syncobj;
1692 };
1693
1694 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1695 int num_wait_sems,
1696 const VkSemaphore *wait_sems,
1697 int num_signal_sems,
1698 const VkSemaphore *signal_sems,
1699 VkFence fence);
1700 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1701
1702 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1703 VkPipelineBindPoint bind_point,
1704 struct radv_descriptor_set *set,
1705 unsigned idx);
1706
1707 void
1708 radv_update_descriptor_sets(struct radv_device *device,
1709 struct radv_cmd_buffer *cmd_buffer,
1710 VkDescriptorSet overrideSet,
1711 uint32_t descriptorWriteCount,
1712 const VkWriteDescriptorSet *pDescriptorWrites,
1713 uint32_t descriptorCopyCount,
1714 const VkCopyDescriptorSet *pDescriptorCopies);
1715
1716 void
1717 radv_update_descriptor_set_with_template(struct radv_device *device,
1718 struct radv_cmd_buffer *cmd_buffer,
1719 struct radv_descriptor_set *set,
1720 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1721 const void *pData);
1722
1723 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1724 VkPipelineBindPoint pipelineBindPoint,
1725 VkPipelineLayout _layout,
1726 uint32_t set,
1727 uint32_t descriptorWriteCount,
1728 const VkWriteDescriptorSet *pDescriptorWrites);
1729
1730 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1731 struct radv_image *image, uint32_t value);
1732 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1733 struct radv_image *image, uint32_t value);
1734
1735 struct radv_fence {
1736 struct radeon_winsys_fence *fence;
1737 bool submitted;
1738 bool signalled;
1739
1740 uint32_t syncobj;
1741 uint32_t temp_syncobj;
1742 };
1743
1744 /* radv_nir_to_llvm.c */
1745 struct radv_shader_variant_info;
1746 struct radv_nir_compiler_options;
1747
1748 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1749 struct nir_shader *geom_shader,
1750 struct ac_shader_binary *binary,
1751 struct ac_shader_config *config,
1752 struct radv_shader_variant_info *shader_info,
1753 const struct radv_nir_compiler_options *option);
1754
1755 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1756 struct ac_shader_binary *binary,
1757 struct ac_shader_config *config,
1758 struct radv_shader_variant_info *shader_info,
1759 struct nir_shader *const *nir,
1760 int nir_count,
1761 const struct radv_nir_compiler_options *options);
1762
1763 /* radv_shader_info.h */
1764 struct radv_shader_info;
1765
1766 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1767 const struct radv_nir_compiler_options *options,
1768 struct radv_shader_info *info);
1769
1770 struct radeon_winsys_sem;
1771
1772 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1773 \
1774 static inline struct __radv_type * \
1775 __radv_type ## _from_handle(__VkType _handle) \
1776 { \
1777 return (struct __radv_type *) _handle; \
1778 } \
1779 \
1780 static inline __VkType \
1781 __radv_type ## _to_handle(struct __radv_type *_obj) \
1782 { \
1783 return (__VkType) _obj; \
1784 }
1785
1786 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1787 \
1788 static inline struct __radv_type * \
1789 __radv_type ## _from_handle(__VkType _handle) \
1790 { \
1791 return (struct __radv_type *)(uintptr_t) _handle; \
1792 } \
1793 \
1794 static inline __VkType \
1795 __radv_type ## _to_handle(struct __radv_type *_obj) \
1796 { \
1797 return (__VkType)(uintptr_t) _obj; \
1798 }
1799
1800 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1801 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1802
1803 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1804 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1805 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1806 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1807 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1808
1809 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1810 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1811 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1812 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1813 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1814 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1815 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1816 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1817 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1818 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1819 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1820 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1821 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1822 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1823 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1829 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1830
1831 #endif /* RADV_PRIVATE_H */