2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_constants.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vulkan_android.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
80 #include "radv_entrypoints.h"
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
85 /* Helper to determine if we should compile
86 * any of the Android AHB support.
88 * To actually enable the ext we also need
89 * the necessary kernel support.
91 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
92 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
99 unsigned img_format
:9;
101 /* Various formats are only supported with workarounds for vertex fetch,
102 * and some 32_32_32 formats are supported natively, but only for buffers
103 * (possibly with some image support, actually, but no filtering). */
107 #include "gfx10_format_table.h"
111 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
118 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
119 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
120 RADV_MEM_TYPE_GTT_CACHED
,
121 RADV_MEM_TYPE_VRAM_UNCACHED
,
122 RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
,
123 RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
,
124 RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
,
128 enum radv_secure_compile_type
{
129 RADV_SC_TYPE_INIT_SUCCESS
,
130 RADV_SC_TYPE_INIT_FAILURE
,
131 RADV_SC_TYPE_COMPILE_PIPELINE
,
132 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
133 RADV_SC_TYPE_READ_DISK_CACHE
,
134 RADV_SC_TYPE_WRITE_DISK_CACHE
,
135 RADV_SC_TYPE_FORK_DEVICE
,
136 RADV_SC_TYPE_DESTROY_DEVICE
,
140 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
142 static inline uint32_t
143 align_u32(uint32_t v
, uint32_t a
)
145 assert(a
!= 0 && a
== (a
& -a
));
146 return (v
+ a
- 1) & ~(a
- 1);
149 static inline uint32_t
150 align_u32_npot(uint32_t v
, uint32_t a
)
152 return (v
+ a
- 1) / a
* a
;
155 static inline uint64_t
156 align_u64(uint64_t v
, uint64_t a
)
158 assert(a
!= 0 && a
== (a
& -a
));
159 return (v
+ a
- 1) & ~(a
- 1);
162 static inline int32_t
163 align_i32(int32_t v
, int32_t a
)
165 assert(a
!= 0 && a
== (a
& -a
));
166 return (v
+ a
- 1) & ~(a
- 1);
169 /** Alignment must be a power of 2. */
171 radv_is_aligned(uintmax_t n
, uintmax_t a
)
173 assert(a
== (a
& -a
));
174 return (n
& (a
- 1)) == 0;
177 static inline uint32_t
178 round_up_u32(uint32_t v
, uint32_t a
)
180 return (v
+ a
- 1) / a
;
183 static inline uint64_t
184 round_up_u64(uint64_t v
, uint64_t a
)
186 return (v
+ a
- 1) / a
;
189 static inline uint32_t
190 radv_minify(uint32_t n
, uint32_t levels
)
192 if (unlikely(n
== 0))
195 return MAX2(n
>> levels
, 1);
198 radv_clamp_f(float f
, float min
, float max
)
211 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
213 if (*inout_mask
& clear_mask
) {
214 *inout_mask
&= ~clear_mask
;
221 #define for_each_bit(b, dword) \
222 for (uint32_t __dword = (dword); \
223 (b) = __builtin_ffs(__dword) - 1, __dword; \
224 __dword &= ~(1 << (b)))
226 #define typed_memcpy(dest, src, count) ({ \
227 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
228 memcpy((dest), (src), (count) * sizeof(*(src))); \
231 /* Whenever we generate an error, pass it through this function. Useful for
232 * debugging, where we can break on it. Only call at error site, not when
233 * propagating errors. Might be useful to plug in a stack trace here.
236 struct radv_image_view
;
237 struct radv_instance
;
239 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
241 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
242 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
244 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
245 radv_printflike(3, 4);
246 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
247 void radv_loge_v(const char *format
, va_list va
);
248 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
249 void radv_logi_v(const char *format
, va_list va
);
252 * Print a FINISHME message, including its source location.
254 #define radv_finishme(format, ...) \
256 static bool reported = false; \
258 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
263 /* A non-fatal assert. Useful for debugging. */
265 #define radv_assert(x) ({ \
266 if (unlikely(!(x))) \
267 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
270 #define radv_assert(x) do {} while(0)
273 #define stub_return(v) \
275 radv_finishme("stub %s", __func__); \
281 radv_finishme("stub %s", __func__); \
285 int radv_get_instance_entrypoint_index(const char *name
);
286 int radv_get_device_entrypoint_index(const char *name
);
287 int radv_get_physical_device_entrypoint_index(const char *name
);
289 const char *radv_get_instance_entry_name(int index
);
290 const char *radv_get_physical_device_entry_name(int index
);
291 const char *radv_get_device_entry_name(int index
);
293 bool radv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
294 const struct radv_instance_extension_table
*instance
);
295 bool radv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
296 const struct radv_instance_extension_table
*instance
);
297 bool radv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
298 const struct radv_instance_extension_table
*instance
,
299 const struct radv_device_extension_table
*device
);
301 void *radv_lookup_entrypoint(const char *name
);
303 struct radv_physical_device
{
304 VK_LOADER_DATA _loader_data
;
306 struct radv_instance
* instance
;
308 struct radeon_winsys
*ws
;
309 struct radeon_info rad_info
;
310 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
311 uint8_t driver_uuid
[VK_UUID_SIZE
];
312 uint8_t device_uuid
[VK_UUID_SIZE
];
313 uint8_t cache_uuid
[VK_UUID_SIZE
];
317 struct wsi_device wsi_device
;
319 bool out_of_order_rast_allowed
;
321 /* Whether DCC should be enabled for MSAA textures. */
322 bool dcc_msaa_allowed
;
324 /* Whether to enable the AMD_shader_ballot extension */
325 bool use_shader_ballot
;
327 /* Whether to enable NGG. */
330 /* Whether to enable NGG GS. */
333 /* Whether to enable NGG streamout. */
334 bool use_ngg_streamout
;
336 /* Number of threads per wave. */
337 uint8_t ps_wave_size
;
338 uint8_t cs_wave_size
;
339 uint8_t ge_wave_size
;
341 /* Whether to use the experimental compiler backend */
344 /* This is the drivers on-disk cache used as a fallback as opposed to
345 * the pipeline cache defined by apps.
347 struct disk_cache
* disk_cache
;
349 VkPhysicalDeviceMemoryProperties memory_properties
;
350 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
352 drmPciBusInfo bus_info
;
354 struct radv_device_extension_table supported_extensions
;
357 struct radv_instance
{
358 VK_LOADER_DATA _loader_data
;
360 VkAllocationCallbacks alloc
;
363 int physicalDeviceCount
;
364 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
367 uint32_t engineVersion
;
369 uint64_t debug_flags
;
370 uint64_t perftest_flags
;
371 uint8_t num_sc_threads
;
373 struct vk_debug_report_instance debug_report_callbacks
;
375 struct radv_instance_extension_table enabled_extensions
;
376 struct radv_instance_dispatch_table dispatch
;
377 struct radv_physical_device_dispatch_table physical_device_dispatch
;
378 struct radv_device_dispatch_table device_dispatch
;
380 struct driOptionCache dri_options
;
381 struct driOptionCache available_dri_options
;
385 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
387 return instance
->num_sc_threads
;
390 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
391 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
393 bool radv_instance_extension_supported(const char *name
);
394 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
395 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
400 struct radv_pipeline_cache
{
401 struct radv_device
* device
;
402 pthread_mutex_t mutex
;
406 uint32_t kernel_count
;
407 struct cache_entry
** hash_table
;
410 VkAllocationCallbacks alloc
;
413 struct radv_pipeline_key
{
414 uint32_t instance_rate_inputs
;
415 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
416 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
417 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
418 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
419 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
420 uint64_t vertex_alpha_adjust
;
421 uint32_t vertex_post_shuffle
;
422 unsigned tess_input_vertices
;
426 uint8_t log2_ps_iter_samples
;
428 uint32_t has_multiview_view_index
: 1;
429 uint32_t optimisations_disabled
: 1;
432 /* Non-zero if a required subgroup size is specified via
433 * VK_EXT_subgroup_size_control.
435 uint8_t compute_subgroup_size
;
438 struct radv_shader_binary
;
439 struct radv_shader_variant
;
442 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
443 struct radv_device
*device
);
445 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
447 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
448 const void *data
, size_t size
);
451 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
452 struct radv_pipeline_cache
*cache
,
453 const unsigned char *sha1
,
454 struct radv_shader_variant
**variants
,
455 bool *found_in_application_cache
);
458 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
459 struct radv_pipeline_cache
*cache
,
460 const unsigned char *sha1
,
461 struct radv_shader_variant
**variants
,
462 struct radv_shader_binary
*const *binaries
);
464 enum radv_blit_ds_layout
{
465 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
466 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
467 RADV_BLIT_DS_LAYOUT_COUNT
,
470 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
472 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
475 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
477 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
480 enum radv_meta_dst_layout
{
481 RADV_META_DST_LAYOUT_GENERAL
,
482 RADV_META_DST_LAYOUT_OPTIMAL
,
483 RADV_META_DST_LAYOUT_COUNT
,
486 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
488 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
491 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
493 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
496 struct radv_meta_state
{
497 VkAllocationCallbacks alloc
;
499 struct radv_pipeline_cache cache
;
502 * For on-demand pipeline creation, makes sure that
503 * only one thread tries to build a pipeline at the same time.
508 * Use array element `i` for images with `2^i` samples.
511 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
512 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
514 VkRenderPass depthstencil_rp
;
515 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
516 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
517 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
519 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
520 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
521 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
522 } clear
[MAX_SAMPLES_LOG2
];
524 VkPipelineLayout clear_color_p_layout
;
525 VkPipelineLayout clear_depth_p_layout
;
526 VkPipelineLayout clear_depth_unrestricted_p_layout
;
528 /* Optimized compute fast HTILE clear for stencil or depth only. */
529 VkPipeline clear_htile_mask_pipeline
;
530 VkPipelineLayout clear_htile_mask_p_layout
;
531 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
534 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
536 /** Pipeline that blits from a 1D image. */
537 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
539 /** Pipeline that blits from a 2D image. */
540 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
542 /** Pipeline that blits from a 3D image. */
543 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
545 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
546 VkPipeline depth_only_1d_pipeline
;
547 VkPipeline depth_only_2d_pipeline
;
548 VkPipeline depth_only_3d_pipeline
;
550 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
551 VkPipeline stencil_only_1d_pipeline
;
552 VkPipeline stencil_only_2d_pipeline
;
553 VkPipeline stencil_only_3d_pipeline
;
554 VkPipelineLayout pipeline_layout
;
555 VkDescriptorSetLayout ds_layout
;
559 VkPipelineLayout p_layouts
[5];
560 VkDescriptorSetLayout ds_layouts
[5];
561 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
563 VkPipeline depth_only_pipeline
[5];
565 VkPipeline stencil_only_pipeline
[5];
566 } blit2d
[MAX_SAMPLES_LOG2
];
568 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
569 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
570 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
573 VkPipelineLayout img_p_layout
;
574 VkDescriptorSetLayout img_ds_layout
;
576 VkPipeline pipeline_3d
;
579 VkPipelineLayout img_p_layout
;
580 VkDescriptorSetLayout img_ds_layout
;
582 VkPipeline pipeline_3d
;
585 VkPipelineLayout img_p_layout
;
586 VkDescriptorSetLayout img_ds_layout
;
590 VkPipelineLayout img_p_layout
;
591 VkDescriptorSetLayout img_ds_layout
;
593 VkPipeline pipeline_3d
;
596 VkPipelineLayout img_p_layout
;
597 VkDescriptorSetLayout img_ds_layout
;
601 VkPipelineLayout img_p_layout
;
602 VkDescriptorSetLayout img_ds_layout
;
604 VkPipeline pipeline_3d
;
607 VkPipelineLayout img_p_layout
;
608 VkDescriptorSetLayout img_ds_layout
;
613 VkPipelineLayout p_layout
;
614 VkPipeline pipeline
[NUM_META_FS_KEYS
];
615 VkRenderPass pass
[NUM_META_FS_KEYS
];
619 VkDescriptorSetLayout ds_layout
;
620 VkPipelineLayout p_layout
;
623 VkPipeline i_pipeline
;
624 VkPipeline srgb_pipeline
;
625 } rc
[MAX_SAMPLES_LOG2
];
627 VkPipeline depth_zero_pipeline
;
629 VkPipeline average_pipeline
;
630 VkPipeline max_pipeline
;
631 VkPipeline min_pipeline
;
632 } depth
[MAX_SAMPLES_LOG2
];
634 VkPipeline stencil_zero_pipeline
;
636 VkPipeline max_pipeline
;
637 VkPipeline min_pipeline
;
638 } stencil
[MAX_SAMPLES_LOG2
];
642 VkDescriptorSetLayout ds_layout
;
643 VkPipelineLayout p_layout
;
646 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
647 VkPipeline pipeline
[NUM_META_FS_KEYS
];
648 } rc
[MAX_SAMPLES_LOG2
];
650 VkRenderPass depth_render_pass
;
651 VkPipeline depth_zero_pipeline
;
653 VkPipeline average_pipeline
;
654 VkPipeline max_pipeline
;
655 VkPipeline min_pipeline
;
656 } depth
[MAX_SAMPLES_LOG2
];
658 VkRenderPass stencil_render_pass
;
659 VkPipeline stencil_zero_pipeline
;
661 VkPipeline max_pipeline
;
662 VkPipeline min_pipeline
;
663 } stencil
[MAX_SAMPLES_LOG2
];
667 VkPipelineLayout p_layout
;
668 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
669 VkPipeline resummarize_pipeline
;
671 } depth_decomp
[MAX_SAMPLES_LOG2
];
674 VkPipelineLayout p_layout
;
675 VkPipeline cmask_eliminate_pipeline
;
676 VkPipeline fmask_decompress_pipeline
;
677 VkPipeline dcc_decompress_pipeline
;
680 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
681 VkPipelineLayout dcc_decompress_compute_p_layout
;
682 VkPipeline dcc_decompress_compute_pipeline
;
686 VkPipelineLayout fill_p_layout
;
687 VkPipelineLayout copy_p_layout
;
688 VkDescriptorSetLayout fill_ds_layout
;
689 VkDescriptorSetLayout copy_ds_layout
;
690 VkPipeline fill_pipeline
;
691 VkPipeline copy_pipeline
;
695 VkDescriptorSetLayout ds_layout
;
696 VkPipelineLayout p_layout
;
697 VkPipeline occlusion_query_pipeline
;
698 VkPipeline pipeline_statistics_query_pipeline
;
699 VkPipeline tfb_query_pipeline
;
700 VkPipeline timestamp_query_pipeline
;
704 VkDescriptorSetLayout ds_layout
;
705 VkPipelineLayout p_layout
;
706 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
711 #define RADV_QUEUE_GENERAL 0
712 #define RADV_QUEUE_COMPUTE 1
713 #define RADV_QUEUE_TRANSFER 2
715 #define RADV_MAX_QUEUE_FAMILIES 3
717 enum ring_type
radv_queue_family_to_ring(int f
);
720 VK_LOADER_DATA _loader_data
;
721 struct radv_device
* device
;
722 struct radeon_winsys_ctx
*hw_ctx
;
723 enum radeon_ctx_priority priority
;
724 uint32_t queue_family_index
;
726 VkDeviceQueueCreateFlags flags
;
728 uint32_t scratch_size_per_wave
;
729 uint32_t scratch_waves
;
730 uint32_t compute_scratch_size_per_wave
;
731 uint32_t compute_scratch_waves
;
732 uint32_t esgs_ring_size
;
733 uint32_t gsvs_ring_size
;
737 bool has_sample_positions
;
739 struct radeon_winsys_bo
*scratch_bo
;
740 struct radeon_winsys_bo
*descriptor_bo
;
741 struct radeon_winsys_bo
*compute_scratch_bo
;
742 struct radeon_winsys_bo
*esgs_ring_bo
;
743 struct radeon_winsys_bo
*gsvs_ring_bo
;
744 struct radeon_winsys_bo
*tess_rings_bo
;
745 struct radeon_winsys_bo
*gds_bo
;
746 struct radeon_winsys_bo
*gds_oa_bo
;
747 struct radeon_cmdbuf
*initial_preamble_cs
;
748 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
749 struct radeon_cmdbuf
*continue_preamble_cs
;
751 struct list_head pending_submissions
;
752 pthread_mutex_t pending_mutex
;
755 struct radv_bo_list
{
756 struct radv_winsys_bo_list list
;
758 pthread_mutex_t mutex
;
761 struct radv_secure_compile_process
{
762 /* Secure process file descriptors. Used to communicate between the
763 * user facing device and the idle forked device used to fork a clean
764 * process for each new pipeline compile.
767 int fd_secure_output
;
769 /* FIFO file descriptors used to communicate between the user facing
770 * device and the secure process that does the actual secure compile.
775 /* Secure compile process id */
778 /* Is the secure compile process currently in use by a thread */
782 struct radv_secure_compile_state
{
783 struct radv_secure_compile_process
*secure_compile_processes
;
784 uint32_t secure_compile_thread_counter
;
785 mtx_t secure_compile_mutex
;
787 /* Unique process ID used to build name for FIFO file descriptor */
792 VK_LOADER_DATA _loader_data
;
794 VkAllocationCallbacks alloc
;
796 struct radv_instance
* instance
;
797 struct radeon_winsys
*ws
;
799 struct radv_meta_state meta_state
;
801 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
802 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
803 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
805 bool always_use_syncobj
;
808 uint32_t tess_offchip_block_dw_size
;
809 uint32_t scratch_waves
;
810 uint32_t dispatch_initiator
;
812 uint32_t gs_table_depth
;
814 /* MSAA sample locations.
815 * The first index is the sample index.
816 * The second index is the coordinate: X, Y. */
817 float sample_locations_1x
[1][2];
818 float sample_locations_2x
[2][2];
819 float sample_locations_4x
[4][2];
820 float sample_locations_8x
[8][2];
823 uint32_t gfx_init_size_dw
;
824 struct radeon_winsys_bo
*gfx_init
;
826 struct radeon_winsys_bo
*trace_bo
;
827 uint32_t *trace_id_ptr
;
829 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
830 bool keep_shader_info
;
832 struct radv_physical_device
*physical_device
;
834 /* Backup in-memory cache to be used if the app doesn't provide one */
835 struct radv_pipeline_cache
* mem_cache
;
838 * use different counters so MSAA MRTs get consecutive surface indices,
839 * even if MASK is allocated in between.
841 uint32_t image_mrt_offset_counter
;
842 uint32_t fmask_mrt_offset_counter
;
843 struct list_head shader_slabs
;
844 mtx_t shader_slab_mutex
;
846 /* For detecting VM faults reported by dmesg. */
847 uint64_t dmesg_timestamp
;
849 struct radv_device_extension_table enabled_extensions
;
850 struct radv_device_dispatch_table dispatch
;
852 /* Whether the app has enabled the robustBufferAccess feature. */
853 bool robust_buffer_access
;
855 /* Whether the driver uses a global BO list. */
856 bool use_global_bo_list
;
858 struct radv_bo_list bo_list
;
860 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
863 struct radv_secure_compile_state
*sc_state
;
865 /* Condition variable for legacy timelines, to notify waiters when a
866 * new point gets submitted. */
867 pthread_cond_t timeline_cond
;
870 struct radeon_cmdbuf
*thread_trace_start_cs
[2];
871 struct radeon_cmdbuf
*thread_trace_stop_cs
[2];
872 struct radeon_winsys_bo
*thread_trace_bo
;
873 void *thread_trace_ptr
;
874 uint32_t thread_trace_buffer_size
;
875 int thread_trace_start_frame
;
878 struct radv_device_memory
{
879 struct radeon_winsys_bo
*bo
;
880 /* for dedicated allocations */
881 struct radv_image
*image
;
882 struct radv_buffer
*buffer
;
884 VkDeviceSize map_size
;
888 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
889 struct AHardwareBuffer
* android_hardware_buffer
;
894 struct radv_descriptor_range
{
899 struct radv_descriptor_set
{
900 const struct radv_descriptor_set_layout
*layout
;
902 uint32_t buffer_count
;
904 struct radeon_winsys_bo
*bo
;
906 uint32_t *mapped_ptr
;
907 struct radv_descriptor_range
*dynamic_descriptors
;
909 struct radeon_winsys_bo
*descriptors
[0];
912 struct radv_push_descriptor_set
914 struct radv_descriptor_set set
;
918 struct radv_descriptor_pool_entry
{
921 struct radv_descriptor_set
*set
;
924 struct radv_descriptor_pool
{
925 struct radeon_winsys_bo
*bo
;
927 uint64_t current_offset
;
930 uint8_t *host_memory_base
;
931 uint8_t *host_memory_ptr
;
932 uint8_t *host_memory_end
;
934 uint32_t entry_count
;
935 uint32_t max_entry_count
;
936 struct radv_descriptor_pool_entry entries
[0];
939 struct radv_descriptor_update_template_entry
{
940 VkDescriptorType descriptor_type
;
942 /* The number of descriptors to update */
943 uint32_t descriptor_count
;
945 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
948 /* In dwords. Not valid/used for dynamic descriptors */
951 uint32_t buffer_offset
;
953 /* Only valid for combined image samplers and samplers */
955 uint8_t sampler_offset
;
961 /* For push descriptors */
962 const uint32_t *immutable_samplers
;
965 struct radv_descriptor_update_template
{
966 uint32_t entry_count
;
967 VkPipelineBindPoint bind_point
;
968 struct radv_descriptor_update_template_entry entry
[0];
974 VkBufferUsageFlags usage
;
975 VkBufferCreateFlags flags
;
978 struct radeon_winsys_bo
* bo
;
984 enum radv_dynamic_state_bits
{
985 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
986 RADV_DYNAMIC_SCISSOR
= 1 << 1,
987 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
988 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
989 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
990 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
991 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
992 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
993 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
994 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
995 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
996 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
997 RADV_DYNAMIC_ALL
= (1 << 12) - 1,
1000 enum radv_cmd_dirty_bits
{
1001 /* Keep the dynamic state dirty bits in sync with
1002 * enum radv_dynamic_state_bits */
1003 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
1004 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
1005 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
1006 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
1007 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
1008 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
1009 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
1010 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
1011 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
1012 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
1013 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
1014 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
1015 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 12) - 1,
1016 RADV_CMD_DIRTY_PIPELINE
= 1 << 12,
1017 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 13,
1018 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 14,
1019 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 15,
1020 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 16,
1023 enum radv_cmd_flush_bits
{
1024 /* Instruction cache. */
1025 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1026 /* Scalar L1 cache. */
1027 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1028 /* Vector L1 cache. */
1029 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1030 /* L2 cache + L2 metadata cache writeback & invalidate.
1031 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1032 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1033 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1034 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1035 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1036 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1037 /* Framebuffer caches */
1038 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1039 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1040 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1041 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1042 /* Engine synchronization. */
1043 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1044 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1045 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1046 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1047 /* Pipeline query controls. */
1048 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1049 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1050 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1052 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1053 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1054 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1055 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1058 struct radv_vertex_binding
{
1059 struct radv_buffer
* buffer
;
1060 VkDeviceSize offset
;
1063 struct radv_streamout_binding
{
1064 struct radv_buffer
*buffer
;
1065 VkDeviceSize offset
;
1069 struct radv_streamout_state
{
1070 /* Mask of bound streamout buffers. */
1071 uint8_t enabled_mask
;
1073 /* External state that comes from the last vertex stage, it must be
1074 * set explicitely when binding a new graphics pipeline.
1076 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1077 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1079 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1080 uint32_t hw_enabled_mask
;
1082 /* State of VGT_STRMOUT_(CONFIG|EN) */
1083 bool streamout_enabled
;
1086 struct radv_viewport_state
{
1088 VkViewport viewports
[MAX_VIEWPORTS
];
1091 struct radv_scissor_state
{
1093 VkRect2D scissors
[MAX_SCISSORS
];
1096 struct radv_discard_rectangle_state
{
1098 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1101 struct radv_sample_locations_state
{
1102 VkSampleCountFlagBits per_pixel
;
1103 VkExtent2D grid_size
;
1105 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1108 struct radv_dynamic_state
{
1110 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1111 * Defines the set of saved dynamic state.
1115 struct radv_viewport_state viewport
;
1117 struct radv_scissor_state scissor
;
1127 float blend_constants
[4];
1137 } stencil_compare_mask
;
1142 } stencil_write_mask
;
1147 } stencil_reference
;
1149 struct radv_discard_rectangle_state discard_rectangle
;
1151 struct radv_sample_locations_state sample_location
;
1159 extern const struct radv_dynamic_state default_dynamic_state
;
1162 radv_get_debug_option_name(int id
);
1165 radv_get_perftest_option_name(int id
);
1167 struct radv_color_buffer_info
{
1168 uint64_t cb_color_base
;
1169 uint64_t cb_color_cmask
;
1170 uint64_t cb_color_fmask
;
1171 uint64_t cb_dcc_base
;
1172 uint32_t cb_color_slice
;
1173 uint32_t cb_color_view
;
1174 uint32_t cb_color_info
;
1175 uint32_t cb_color_attrib
;
1176 uint32_t cb_color_attrib2
; /* GFX9 and later */
1177 uint32_t cb_color_attrib3
; /* GFX10 and later */
1178 uint32_t cb_dcc_control
;
1179 uint32_t cb_color_cmask_slice
;
1180 uint32_t cb_color_fmask_slice
;
1182 uint32_t cb_color_pitch
; // GFX6-GFX8
1183 uint32_t cb_mrt_epitch
; // GFX9+
1187 struct radv_ds_buffer_info
{
1188 uint64_t db_z_read_base
;
1189 uint64_t db_stencil_read_base
;
1190 uint64_t db_z_write_base
;
1191 uint64_t db_stencil_write_base
;
1192 uint64_t db_htile_data_base
;
1193 uint32_t db_depth_info
;
1195 uint32_t db_stencil_info
;
1196 uint32_t db_depth_view
;
1197 uint32_t db_depth_size
;
1198 uint32_t db_depth_slice
;
1199 uint32_t db_htile_surface
;
1200 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1201 uint32_t db_z_info2
; /* GFX9 only */
1202 uint32_t db_stencil_info2
; /* GFX9 only */
1207 radv_initialise_color_surface(struct radv_device
*device
,
1208 struct radv_color_buffer_info
*cb
,
1209 struct radv_image_view
*iview
);
1211 radv_initialise_ds_surface(struct radv_device
*device
,
1212 struct radv_ds_buffer_info
*ds
,
1213 struct radv_image_view
*iview
);
1216 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1219 * Attachment state when recording a renderpass instance.
1221 * The clear value is valid only if there exists a pending clear.
1223 struct radv_attachment_state
{
1224 VkImageAspectFlags pending_clear_aspects
;
1225 uint32_t cleared_views
;
1226 VkClearValue clear_value
;
1227 VkImageLayout current_layout
;
1228 VkImageLayout current_stencil_layout
;
1229 bool current_in_render_loop
;
1230 struct radv_sample_locations_state sample_location
;
1233 struct radv_color_buffer_info cb
;
1234 struct radv_ds_buffer_info ds
;
1236 struct radv_image_view
*iview
;
1239 struct radv_descriptor_state
{
1240 struct radv_descriptor_set
*sets
[MAX_SETS
];
1243 struct radv_push_descriptor_set push_set
;
1245 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1248 struct radv_subpass_sample_locs_state
{
1249 uint32_t subpass_idx
;
1250 struct radv_sample_locations_state sample_location
;
1253 struct radv_cmd_state
{
1254 /* Vertex descriptors */
1261 uint32_t prefetch_L2_mask
;
1263 struct radv_pipeline
* pipeline
;
1264 struct radv_pipeline
* emitted_pipeline
;
1265 struct radv_pipeline
* compute_pipeline
;
1266 struct radv_pipeline
* emitted_compute_pipeline
;
1267 struct radv_framebuffer
* framebuffer
;
1268 struct radv_render_pass
* pass
;
1269 const struct radv_subpass
* subpass
;
1270 struct radv_dynamic_state dynamic
;
1271 struct radv_attachment_state
* attachments
;
1272 struct radv_streamout_state streamout
;
1273 VkRect2D render_area
;
1275 uint32_t num_subpass_sample_locs
;
1276 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1279 struct radv_buffer
*index_buffer
;
1280 uint64_t index_offset
;
1281 uint32_t index_type
;
1282 uint32_t max_index_count
;
1284 int32_t last_index_type
;
1286 int32_t last_primitive_reset_en
;
1287 uint32_t last_primitive_reset_index
;
1288 enum radv_cmd_flush_bits flush_bits
;
1289 unsigned active_occlusion_queries
;
1290 bool perfect_occlusion_queries_enabled
;
1291 unsigned active_pipeline_queries
;
1292 unsigned active_pipeline_gds_queries
;
1295 uint32_t last_ia_multi_vgt_param
;
1297 uint32_t last_num_instances
;
1298 uint32_t last_first_instance
;
1299 uint32_t last_vertex_offset
;
1301 uint32_t last_sx_ps_downconvert
;
1302 uint32_t last_sx_blend_opt_epsilon
;
1303 uint32_t last_sx_blend_opt_control
;
1305 /* Whether CP DMA is busy/idle. */
1308 /* Conditional rendering info. */
1309 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1310 uint64_t predication_va
;
1312 /* Inheritance info. */
1313 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1315 bool context_roll_without_scissor_emitted
;
1317 /* SQTT related state. */
1318 uint32_t current_event_type
;
1319 uint32_t num_events
;
1320 uint32_t num_layout_transitions
;
1323 struct radv_cmd_pool
{
1324 VkAllocationCallbacks alloc
;
1325 struct list_head cmd_buffers
;
1326 struct list_head free_cmd_buffers
;
1327 uint32_t queue_family_index
;
1330 struct radv_cmd_buffer_upload
{
1334 struct radeon_winsys_bo
*upload_bo
;
1335 struct list_head list
;
1338 enum radv_cmd_buffer_status
{
1339 RADV_CMD_BUFFER_STATUS_INVALID
,
1340 RADV_CMD_BUFFER_STATUS_INITIAL
,
1341 RADV_CMD_BUFFER_STATUS_RECORDING
,
1342 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1343 RADV_CMD_BUFFER_STATUS_PENDING
,
1346 struct radv_cmd_buffer
{
1347 VK_LOADER_DATA _loader_data
;
1349 struct radv_device
* device
;
1351 struct radv_cmd_pool
* pool
;
1352 struct list_head pool_link
;
1354 VkCommandBufferUsageFlags usage_flags
;
1355 VkCommandBufferLevel level
;
1356 enum radv_cmd_buffer_status status
;
1357 struct radeon_cmdbuf
*cs
;
1358 struct radv_cmd_state state
;
1359 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1360 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1361 uint32_t queue_family_index
;
1363 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1364 VkShaderStageFlags push_constant_stages
;
1365 struct radv_descriptor_set meta_push_descriptors
;
1367 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1369 struct radv_cmd_buffer_upload upload
;
1371 uint32_t scratch_size_per_wave_needed
;
1372 uint32_t scratch_waves_wanted
;
1373 uint32_t compute_scratch_size_per_wave_needed
;
1374 uint32_t compute_scratch_waves_wanted
;
1375 uint32_t esgs_ring_size_needed
;
1376 uint32_t gsvs_ring_size_needed
;
1377 bool tess_rings_needed
;
1378 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1379 bool gds_oa_needed
; /* for GFX10 streamout */
1380 bool sample_positions_needed
;
1382 VkResult record_result
;
1384 uint64_t gfx9_fence_va
;
1385 uint32_t gfx9_fence_idx
;
1386 uint64_t gfx9_eop_bug_va
;
1389 * Whether a query pool has been resetted and we have to flush caches.
1391 bool pending_reset_query
;
1394 * Bitmask of pending active query flushes.
1396 enum radv_cmd_flush_bits active_query_flush_bits
;
1400 struct radv_image_view
;
1402 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1404 void si_emit_graphics(struct radv_device
*device
,
1405 struct radeon_cmdbuf
*cs
);
1406 void si_emit_compute(struct radv_physical_device
*physical_device
,
1407 struct radeon_cmdbuf
*cs
);
1409 void cik_create_gfx_config(struct radv_device
*device
);
1411 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1412 int count
, const VkViewport
*viewports
);
1413 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1414 int count
, const VkRect2D
*scissors
,
1415 const VkViewport
*viewports
, bool can_use_guardband
);
1416 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1417 bool instanced_draw
, bool indirect_draw
,
1418 bool count_from_stream_output
,
1419 uint32_t draw_vertex_count
);
1420 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1421 enum chip_class chip_class
,
1423 unsigned event
, unsigned event_flags
,
1424 unsigned dst_sel
, unsigned data_sel
,
1427 uint64_t gfx9_eop_bug_va
);
1429 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1430 uint32_t ref
, uint32_t mask
);
1431 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1432 enum chip_class chip_class
,
1433 uint32_t *fence_ptr
, uint64_t va
,
1435 enum radv_cmd_flush_bits flush_bits
,
1436 uint64_t gfx9_eop_bug_va
);
1437 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1438 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1439 bool inverted
, uint64_t va
);
1440 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1441 uint64_t src_va
, uint64_t dest_va
,
1443 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1445 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1446 uint64_t size
, unsigned value
);
1447 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1449 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1451 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1454 unsigned *out_offset
,
1457 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1458 const struct radv_subpass
*subpass
);
1460 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1461 unsigned size
, unsigned alignmnet
,
1462 const void *data
, unsigned *out_offset
);
1464 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1465 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1466 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1467 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1468 VkImageAspectFlags aspects
,
1469 VkResolveModeFlagBits resolve_mode
);
1470 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1471 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1472 VkImageAspectFlags aspects
,
1473 VkResolveModeFlagBits resolve_mode
);
1474 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1475 unsigned radv_get_default_max_sample_dist(int log_samples
);
1476 void radv_device_init_msaa(struct radv_device
*device
);
1478 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1479 const struct radv_image_view
*iview
,
1480 VkClearDepthStencilValue ds_clear_value
,
1481 VkImageAspectFlags aspects
);
1483 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1484 const struct radv_image_view
*iview
,
1486 uint32_t color_values
[2]);
1488 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1489 struct radv_image
*image
,
1490 const VkImageSubresourceRange
*range
, bool value
);
1492 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1493 struct radv_image
*image
,
1494 const VkImageSubresourceRange
*range
, bool value
);
1496 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1497 struct radeon_winsys_bo
*bo
,
1498 uint64_t offset
, uint64_t size
, uint32_t value
);
1499 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1500 bool radv_get_memory_fd(struct radv_device
*device
,
1501 struct radv_device_memory
*memory
,
1505 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1506 unsigned sh_offset
, unsigned pointer_count
,
1507 bool use_32bit_pointers
)
1509 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1510 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1514 radv_emit_shader_pointer_body(struct radv_device
*device
,
1515 struct radeon_cmdbuf
*cs
,
1516 uint64_t va
, bool use_32bit_pointers
)
1518 radeon_emit(cs
, va
);
1520 if (use_32bit_pointers
) {
1522 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1524 radeon_emit(cs
, va
>> 32);
1529 radv_emit_shader_pointer(struct radv_device
*device
,
1530 struct radeon_cmdbuf
*cs
,
1531 uint32_t sh_offset
, uint64_t va
, bool global
)
1533 bool use_32bit_pointers
= !global
;
1535 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1536 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1539 static inline struct radv_descriptor_state
*
1540 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1541 VkPipelineBindPoint bind_point
)
1543 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1544 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1545 return &cmd_buffer
->descriptors
[bind_point
];
1549 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1551 * Limitations: Can't call normal dispatch functions without binding or rebinding
1552 * the compute pipeline.
1554 void radv_unaligned_dispatch(
1555 struct radv_cmd_buffer
*cmd_buffer
,
1561 struct radeon_winsys_bo
*bo
;
1565 struct radv_shader_module
;
1567 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1568 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1569 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1570 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1571 #define RADV_HASH_SHADER_ACO (1 << 4)
1574 radv_hash_shaders(unsigned char *hash
,
1575 const VkPipelineShaderStageCreateInfo
**stages
,
1576 const struct radv_pipeline_layout
*layout
,
1577 const struct radv_pipeline_key
*key
,
1580 static inline gl_shader_stage
1581 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1583 assert(__builtin_popcount(vk_stage
) == 1);
1584 return ffs(vk_stage
) - 1;
1587 static inline VkShaderStageFlagBits
1588 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1590 return (1 << mesa_stage
);
1593 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1595 #define radv_foreach_stage(stage, stage_bits) \
1596 for (gl_shader_stage stage, \
1597 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1598 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1599 __tmp &= ~(1 << (stage)))
1601 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1602 unsigned radv_format_meta_fs_key(VkFormat format
);
1604 struct radv_multisample_state
{
1606 uint32_t pa_sc_line_cntl
;
1607 uint32_t pa_sc_mode_cntl_0
;
1608 uint32_t pa_sc_mode_cntl_1
;
1609 uint32_t pa_sc_aa_config
;
1610 uint32_t pa_sc_aa_mask
[2];
1611 unsigned num_samples
;
1614 struct radv_prim_vertex_count
{
1619 struct radv_vertex_elements_info
{
1620 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1623 struct radv_ia_multi_vgt_param_helpers
{
1625 bool partial_es_wave
;
1626 uint8_t primgroup_size
;
1627 bool wd_switch_on_eop
;
1628 bool ia_switch_on_eoi
;
1629 bool partial_vs_wave
;
1632 struct radv_binning_state
{
1633 uint32_t pa_sc_binner_cntl_0
;
1634 uint32_t db_dfsm_control
;
1637 #define SI_GS_PER_ES 128
1639 struct radv_pipeline
{
1640 struct radv_device
* device
;
1641 struct radv_dynamic_state dynamic_state
;
1643 struct radv_pipeline_layout
* layout
;
1645 bool need_indirect_descriptor_sets
;
1646 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1647 struct radv_shader_variant
*gs_copy_shader
;
1648 VkShaderStageFlags active_stages
;
1650 struct radeon_cmdbuf cs
;
1651 uint32_t ctx_cs_hash
;
1652 struct radeon_cmdbuf ctx_cs
;
1654 struct radv_vertex_elements_info vertex_elements
;
1656 uint32_t binding_stride
[MAX_VBS
];
1657 uint8_t num_vertex_bindings
;
1659 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1662 struct radv_multisample_state ms
;
1663 struct radv_binning_state binning
;
1664 uint32_t spi_baryc_cntl
;
1665 bool prim_restart_enable
;
1666 unsigned esgs_ring_size
;
1667 unsigned gsvs_ring_size
;
1668 uint32_t vtx_base_sgpr
;
1669 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1670 uint8_t vtx_emit_num
;
1671 struct radv_prim_vertex_count prim_vertex_count
;
1672 bool can_use_guardband
;
1673 uint32_t needed_dynamic_state
;
1674 bool disable_out_of_order_rast_for_occlusion
;
1677 /* Used for rbplus */
1678 uint32_t col_format
;
1679 uint32_t cb_target_mask
;
1684 unsigned scratch_bytes_per_wave
;
1686 /* Not NULL if graphics pipeline uses streamout. */
1687 struct radv_shader_variant
*streamout_shader
;
1690 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1692 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1695 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1697 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1700 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1702 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1704 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1706 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1707 gl_shader_stage stage
,
1710 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1711 gl_shader_stage stage
);
1713 struct radv_graphics_pipeline_create_info
{
1715 bool db_depth_clear
;
1716 bool db_stencil_clear
;
1717 bool db_depth_disable_expclear
;
1718 bool db_stencil_disable_expclear
;
1719 bool depth_compress_disable
;
1720 bool stencil_compress_disable
;
1721 bool resummarize_enable
;
1722 uint32_t custom_blend_mode
;
1726 radv_graphics_pipeline_create(VkDevice device
,
1727 VkPipelineCache cache
,
1728 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1729 const struct radv_graphics_pipeline_create_info
*extra
,
1730 const VkAllocationCallbacks
*alloc
,
1731 VkPipeline
*pPipeline
);
1733 struct radv_binning_settings
{
1734 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1735 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1736 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1739 struct radv_binning_settings
1740 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1742 struct vk_format_description
;
1743 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1744 int first_non_void
);
1745 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1746 int first_non_void
);
1747 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1748 uint32_t radv_translate_colorformat(VkFormat format
);
1749 uint32_t radv_translate_color_numformat(VkFormat format
,
1750 const struct vk_format_description
*desc
,
1751 int first_non_void
);
1752 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1753 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1754 uint32_t radv_translate_dbformat(VkFormat format
);
1755 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1756 const struct vk_format_description
*desc
,
1757 int first_non_void
);
1758 uint32_t radv_translate_tex_numformat(VkFormat format
,
1759 const struct vk_format_description
*desc
,
1760 int first_non_void
);
1761 bool radv_format_pack_clear_color(VkFormat format
,
1762 uint32_t clear_vals
[2],
1763 VkClearColorValue
*value
);
1764 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1765 bool radv_dcc_formats_compatible(VkFormat format1
,
1767 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1769 struct radv_image_plane
{
1771 struct radeon_surf surface
;
1777 /* The original VkFormat provided by the client. This may not match any
1778 * of the actual surface formats.
1781 VkImageAspectFlags aspects
;
1782 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1783 struct ac_surf_info info
;
1784 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1785 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1790 unsigned queue_family_mask
;
1794 /* Set when bound */
1795 struct radeon_winsys_bo
*bo
;
1796 VkDeviceSize offset
;
1797 uint64_t dcc_offset
;
1798 uint64_t htile_offset
;
1799 bool tc_compatible_htile
;
1800 bool tc_compatible_cmask
;
1802 uint64_t cmask_offset
;
1803 uint64_t fmask_offset
;
1804 uint64_t clear_value_offset
;
1805 uint64_t fce_pred_offset
;
1806 uint64_t dcc_pred_offset
;
1809 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1810 * stored at this offset is UINT_MAX, the driver will emit
1811 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1812 * SET_CONTEXT_REG packet.
1814 uint64_t tc_compat_zrange_offset
;
1816 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1817 VkDeviceMemory owned_memory
;
1819 unsigned plane_count
;
1820 struct radv_image_plane planes
[0];
1823 /* Whether the image has a htile that is known consistent with the contents of
1824 * the image and is allowed to be in compressed form.
1826 * If this is false reads that don't use the htile should be able to return
1829 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1830 VkImageLayout layout
,
1831 bool in_render_loop
,
1832 unsigned queue_mask
);
1834 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1835 VkImageLayout layout
,
1836 bool in_render_loop
,
1837 unsigned queue_mask
);
1839 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1840 const struct radv_image
*image
,
1841 VkImageLayout layout
,
1842 bool in_render_loop
,
1843 unsigned queue_mask
);
1846 * Return whether the image has CMASK metadata for color surfaces.
1849 radv_image_has_cmask(const struct radv_image
*image
)
1851 return image
->cmask_offset
;
1855 * Return whether the image has FMASK metadata for color surfaces.
1858 radv_image_has_fmask(const struct radv_image
*image
)
1860 return image
->fmask_offset
;
1864 * Return whether the image has DCC metadata for color surfaces.
1867 radv_image_has_dcc(const struct radv_image
*image
)
1869 return image
->planes
[0].surface
.dcc_size
;
1873 * Return whether the image is TC-compatible CMASK.
1876 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1878 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1882 * Return whether DCC metadata is enabled for a level.
1885 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1887 return radv_image_has_dcc(image
) &&
1888 level
< image
->planes
[0].surface
.num_dcc_levels
;
1892 * Return whether the image has CB metadata.
1895 radv_image_has_CB_metadata(const struct radv_image
*image
)
1897 return radv_image_has_cmask(image
) ||
1898 radv_image_has_fmask(image
) ||
1899 radv_image_has_dcc(image
);
1903 * Return whether the image has HTILE metadata for depth surfaces.
1906 radv_image_has_htile(const struct radv_image
*image
)
1908 return image
->planes
[0].surface
.htile_size
;
1912 * Return whether HTILE metadata is enabled for a level.
1915 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1917 return radv_image_has_htile(image
) && level
== 0;
1921 * Return whether the image is TC-compatible HTILE.
1924 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1926 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1929 static inline uint64_t
1930 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1931 uint32_t base_level
)
1933 uint64_t va
= radv_buffer_get_va(image
->bo
);
1934 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1938 static inline uint64_t
1939 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1940 uint32_t base_level
)
1942 uint64_t va
= radv_buffer_get_va(image
->bo
);
1943 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1947 static inline uint64_t
1948 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1949 uint32_t base_level
)
1951 uint64_t va
= radv_buffer_get_va(image
->bo
);
1952 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1956 static inline uint64_t
1957 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1958 uint32_t base_level
)
1960 uint64_t va
= radv_buffer_get_va(image
->bo
);
1961 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1965 static inline uint64_t
1966 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1967 uint32_t base_level
)
1969 uint64_t va
= radv_buffer_get_va(image
->bo
);
1970 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1974 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1976 static inline uint32_t
1977 radv_get_layerCount(const struct radv_image
*image
,
1978 const VkImageSubresourceRange
*range
)
1980 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1981 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1984 static inline uint32_t
1985 radv_get_levelCount(const struct radv_image
*image
,
1986 const VkImageSubresourceRange
*range
)
1988 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1989 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1992 struct radeon_bo_metadata
;
1994 radv_init_metadata(struct radv_device
*device
,
1995 struct radv_image
*image
,
1996 struct radeon_bo_metadata
*metadata
);
1999 radv_image_override_offset_stride(struct radv_device
*device
,
2000 struct radv_image
*image
,
2001 uint64_t offset
, uint32_t stride
);
2003 union radv_descriptor
{
2005 uint32_t plane0_descriptor
[8];
2006 uint32_t fmask_descriptor
[8];
2009 uint32_t plane_descriptors
[3][8];
2013 struct radv_image_view
{
2014 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
2015 struct radeon_winsys_bo
*bo
;
2017 VkImageViewType type
;
2018 VkImageAspectFlags aspect_mask
;
2021 bool multiple_planes
;
2022 uint32_t base_layer
;
2023 uint32_t layer_count
;
2025 uint32_t level_count
;
2026 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2028 union radv_descriptor descriptor
;
2030 /* Descriptor for use as a storage image as opposed to a sampled image.
2031 * This has a few differences for cube maps (e.g. type).
2033 union radv_descriptor storage_descriptor
;
2036 struct radv_image_create_info
{
2037 const VkImageCreateInfo
*vk_info
;
2039 bool no_metadata_planes
;
2040 const struct radeon_bo_metadata
*bo_metadata
;
2044 radv_image_create_layout(struct radv_device
*device
,
2045 struct radv_image_create_info create_info
,
2046 struct radv_image
*image
);
2048 VkResult
radv_image_create(VkDevice _device
,
2049 const struct radv_image_create_info
*info
,
2050 const VkAllocationCallbacks
* alloc
,
2053 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2056 radv_image_from_gralloc(VkDevice device_h
,
2057 const VkImageCreateInfo
*base_info
,
2058 const VkNativeBufferANDROID
*gralloc_info
,
2059 const VkAllocationCallbacks
*alloc
,
2060 VkImage
*out_image_h
);
2062 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2063 const VkImageUsageFlags vk_usage
);
2065 radv_import_ahb_memory(struct radv_device
*device
,
2066 struct radv_device_memory
*mem
,
2068 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2070 radv_create_ahb_memory(struct radv_device
*device
,
2071 struct radv_device_memory
*mem
,
2073 const VkMemoryAllocateInfo
*pAllocateInfo
);
2076 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2078 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2080 struct radv_image_view_extra_create_info
{
2081 bool disable_compression
;
2084 void radv_image_view_init(struct radv_image_view
*view
,
2085 struct radv_device
*device
,
2086 const VkImageViewCreateInfo
*pCreateInfo
,
2087 const struct radv_image_view_extra_create_info
* extra_create_info
);
2089 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2091 struct radv_sampler_ycbcr_conversion
{
2093 VkSamplerYcbcrModelConversion ycbcr_model
;
2094 VkSamplerYcbcrRange ycbcr_range
;
2095 VkComponentMapping components
;
2096 VkChromaLocation chroma_offsets
[2];
2097 VkFilter chroma_filter
;
2100 struct radv_buffer_view
{
2101 struct radeon_winsys_bo
*bo
;
2103 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2106 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2107 struct radv_device
*device
,
2108 const VkBufferViewCreateInfo
* pCreateInfo
);
2110 static inline struct VkExtent3D
2111 radv_sanitize_image_extent(const VkImageType imageType
,
2112 const struct VkExtent3D imageExtent
)
2114 switch (imageType
) {
2115 case VK_IMAGE_TYPE_1D
:
2116 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2117 case VK_IMAGE_TYPE_2D
:
2118 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2119 case VK_IMAGE_TYPE_3D
:
2122 unreachable("invalid image type");
2126 static inline struct VkOffset3D
2127 radv_sanitize_image_offset(const VkImageType imageType
,
2128 const struct VkOffset3D imageOffset
)
2130 switch (imageType
) {
2131 case VK_IMAGE_TYPE_1D
:
2132 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2133 case VK_IMAGE_TYPE_2D
:
2134 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2135 case VK_IMAGE_TYPE_3D
:
2138 unreachable("invalid image type");
2143 radv_image_extent_compare(const struct radv_image
*image
,
2144 const VkExtent3D
*extent
)
2146 if (extent
->width
!= image
->info
.width
||
2147 extent
->height
!= image
->info
.height
||
2148 extent
->depth
!= image
->info
.depth
)
2153 struct radv_sampler
{
2155 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2158 struct radv_framebuffer
{
2163 uint32_t attachment_count
;
2164 struct radv_image_view
*attachments
[0];
2167 struct radv_subpass_barrier
{
2168 VkPipelineStageFlags src_stage_mask
;
2169 VkAccessFlags src_access_mask
;
2170 VkAccessFlags dst_access_mask
;
2173 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2174 const struct radv_subpass_barrier
*barrier
);
2176 struct radv_subpass_attachment
{
2177 uint32_t attachment
;
2178 VkImageLayout layout
;
2179 VkImageLayout stencil_layout
;
2180 bool in_render_loop
;
2183 struct radv_subpass
{
2184 uint32_t attachment_count
;
2185 struct radv_subpass_attachment
* attachments
;
2187 uint32_t input_count
;
2188 uint32_t color_count
;
2189 struct radv_subpass_attachment
* input_attachments
;
2190 struct radv_subpass_attachment
* color_attachments
;
2191 struct radv_subpass_attachment
* resolve_attachments
;
2192 struct radv_subpass_attachment
* depth_stencil_attachment
;
2193 struct radv_subpass_attachment
* ds_resolve_attachment
;
2194 VkResolveModeFlagBits depth_resolve_mode
;
2195 VkResolveModeFlagBits stencil_resolve_mode
;
2197 /** Subpass has at least one color resolve attachment */
2198 bool has_color_resolve
;
2200 /** Subpass has at least one color attachment */
2203 struct radv_subpass_barrier start_barrier
;
2207 VkSampleCountFlagBits color_sample_count
;
2208 VkSampleCountFlagBits depth_sample_count
;
2209 VkSampleCountFlagBits max_sample_count
;
2213 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2215 struct radv_render_pass_attachment
{
2218 VkAttachmentLoadOp load_op
;
2219 VkAttachmentLoadOp stencil_load_op
;
2220 VkImageLayout initial_layout
;
2221 VkImageLayout final_layout
;
2222 VkImageLayout stencil_initial_layout
;
2223 VkImageLayout stencil_final_layout
;
2225 /* The subpass id in which the attachment will be used first/last. */
2226 uint32_t first_subpass_idx
;
2227 uint32_t last_subpass_idx
;
2230 struct radv_render_pass
{
2231 uint32_t attachment_count
;
2232 uint32_t subpass_count
;
2233 struct radv_subpass_attachment
* subpass_attachments
;
2234 struct radv_render_pass_attachment
* attachments
;
2235 struct radv_subpass_barrier end_barrier
;
2236 struct radv_subpass subpasses
[0];
2239 VkResult
radv_device_init_meta(struct radv_device
*device
);
2240 void radv_device_finish_meta(struct radv_device
*device
);
2242 struct radv_query_pool
{
2243 struct radeon_winsys_bo
*bo
;
2245 uint32_t availability_offset
;
2249 uint32_t pipeline_stats_mask
;
2253 RADV_SEMAPHORE_NONE
,
2254 RADV_SEMAPHORE_WINSYS
,
2255 RADV_SEMAPHORE_SYNCOBJ
,
2256 RADV_SEMAPHORE_TIMELINE
,
2257 } radv_semaphore_kind
;
2259 struct radv_deferred_queue_submission
;
2261 struct radv_timeline_waiter
{
2262 struct list_head list
;
2263 struct radv_deferred_queue_submission
*submission
;
2267 struct radv_timeline_point
{
2268 struct list_head list
;
2273 /* Separate from the list to accomodate CPU wait being async, as well
2274 * as prevent point deletion during submission. */
2275 unsigned wait_count
;
2278 struct radv_timeline
{
2279 /* Using a pthread mutex to be compatible with condition variables. */
2280 pthread_mutex_t mutex
;
2282 uint64_t highest_signaled
;
2283 uint64_t highest_submitted
;
2285 struct list_head points
;
2287 /* Keep free points on hand so we do not have to recreate syncobjs all
2289 struct list_head free_points
;
2291 /* Submissions that are deferred waiting for a specific value to be
2293 struct list_head waiters
;
2296 struct radv_semaphore_part
{
2297 radv_semaphore_kind kind
;
2300 struct radeon_winsys_sem
*ws_sem
;
2301 struct radv_timeline timeline
;
2305 struct radv_semaphore
{
2306 struct radv_semaphore_part permanent
;
2307 struct radv_semaphore_part temporary
;
2310 bool radv_queue_internal_submit(struct radv_queue
*queue
,
2311 struct radeon_cmdbuf
*cs
);
2313 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2314 VkPipelineBindPoint bind_point
,
2315 struct radv_descriptor_set
*set
,
2319 radv_update_descriptor_sets(struct radv_device
*device
,
2320 struct radv_cmd_buffer
*cmd_buffer
,
2321 VkDescriptorSet overrideSet
,
2322 uint32_t descriptorWriteCount
,
2323 const VkWriteDescriptorSet
*pDescriptorWrites
,
2324 uint32_t descriptorCopyCount
,
2325 const VkCopyDescriptorSet
*pDescriptorCopies
);
2328 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2329 struct radv_cmd_buffer
*cmd_buffer
,
2330 struct radv_descriptor_set
*set
,
2331 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2334 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2335 VkPipelineBindPoint pipelineBindPoint
,
2336 VkPipelineLayout _layout
,
2338 uint32_t descriptorWriteCount
,
2339 const VkWriteDescriptorSet
*pDescriptorWrites
);
2341 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2342 struct radv_image
*image
,
2343 const VkImageSubresourceRange
*range
, uint32_t value
);
2345 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2346 struct radv_image
*image
,
2347 const VkImageSubresourceRange
*range
);
2350 struct radeon_winsys_fence
*fence
;
2351 struct wsi_fence
*fence_wsi
;
2354 uint32_t temp_syncobj
;
2357 /* radv_nir_to_llvm.c */
2358 struct radv_shader_args
;
2360 void llvm_compile_shader(struct radv_device
*device
,
2361 unsigned shader_count
,
2362 struct nir_shader
*const *shaders
,
2363 struct radv_shader_binary
**binary
,
2364 struct radv_shader_args
*args
);
2366 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2367 gl_shader_stage stage
,
2368 const struct nir_shader
*nir
);
2370 /* radv_shader_info.h */
2371 struct radv_shader_info
;
2372 struct radv_shader_variant_key
;
2374 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2375 const struct radv_pipeline_layout
*layout
,
2376 const struct radv_shader_variant_key
*key
,
2377 struct radv_shader_info
*info
);
2379 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2382 struct radv_thread_trace_info
{
2383 uint32_t cur_offset
;
2384 uint32_t trace_status
;
2386 uint32_t gfx9_write_counter
;
2387 uint32_t gfx10_dropped_cntr
;
2391 struct radv_thread_trace_se
{
2392 struct radv_thread_trace_info info
;
2394 uint32_t shader_engine
;
2395 uint32_t compute_unit
;
2398 struct radv_thread_trace
{
2399 uint32_t num_traces
;
2400 struct radv_thread_trace_se traces
[4];
2403 bool radv_thread_trace_init(struct radv_device
*device
);
2404 void radv_thread_trace_finish(struct radv_device
*device
);
2405 bool radv_begin_thread_trace(struct radv_queue
*queue
);
2406 bool radv_end_thread_trace(struct radv_queue
*queue
);
2407 bool radv_get_thread_trace(struct radv_queue
*queue
,
2408 struct radv_thread_trace
*thread_trace
);
2409 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf
*cs
,
2410 const void *data
, uint32_t num_dwords
);
2413 int radv_dump_thread_trace(struct radv_device
*device
,
2414 const struct radv_thread_trace
*trace
);
2416 /* radv_sqtt_layer_.c */
2417 struct radv_barrier_data
{
2420 uint16_t depth_stencil_expand
: 1;
2421 uint16_t htile_hiz_range_expand
: 1;
2422 uint16_t depth_stencil_resummarize
: 1;
2423 uint16_t dcc_decompress
: 1;
2424 uint16_t fmask_decompress
: 1;
2425 uint16_t fast_clear_eliminate
: 1;
2426 uint16_t fmask_color_expand
: 1;
2427 uint16_t init_mask_ram
: 1;
2428 uint16_t reserved
: 8;
2431 } layout_transitions
;
2435 * Value for the reason field of an RGP barrier start marker originating from
2436 * the Vulkan client (does not include PAL-defined values). (Table 15)
2438 enum rgp_barrier_reason
{
2439 RGP_BARRIER_UNKNOWN_REASON
= 0xFFFFFFFF,
2441 /* External app-generated barrier reasons, i.e. API synchronization
2442 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2444 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
= 0x00000001,
2445 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
= 0x00000002,
2446 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
= 0x00000003,
2448 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2449 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2451 RGP_BARRIER_INTERNAL_BASE
= 0xC0000000,
2452 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 0,
2453 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 1,
2454 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL
= RGP_BARRIER_INTERNAL_BASE
+ 2,
2455 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 3
2458 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2459 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2460 void radv_describe_draw(struct radv_cmd_buffer
*cmd_buffer
);
2461 void radv_describe_dispatch(struct radv_cmd_buffer
*cmd_buffer
, int x
, int y
, int z
);
2462 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
,
2463 VkImageAspectFlagBits aspects
);
2464 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
);
2465 void radv_describe_barrier_start(struct radv_cmd_buffer
*cmd_buffer
,
2466 enum rgp_barrier_reason reason
);
2467 void radv_describe_barrier_end(struct radv_cmd_buffer
*cmd_buffer
);
2468 void radv_describe_layout_transition(struct radv_cmd_buffer
*cmd_buffer
,
2469 const struct radv_barrier_data
*barrier
);
2471 struct radeon_winsys_sem
;
2473 uint64_t radv_get_current_time(void);
2475 static inline uint32_t
2476 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2479 case 0: /* GL_POINTS */
2481 case 1: /* GL_LINES */
2482 case 3: /* GL_LINE_STRIP */
2484 case 4: /* GL_TRIANGLES */
2485 case 5: /* GL_TRIANGLE_STRIP */
2487 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2489 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2491 case 7: /* GL_QUADS */
2492 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2499 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
2500 const VkRenderPassBeginInfo
*pRenderPassBegin
);
2501 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
);
2503 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2505 static inline struct __radv_type * \
2506 __radv_type ## _from_handle(__VkType _handle) \
2508 return (struct __radv_type *) _handle; \
2511 static inline __VkType \
2512 __radv_type ## _to_handle(struct __radv_type *_obj) \
2514 return (__VkType) _obj; \
2517 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2519 static inline struct __radv_type * \
2520 __radv_type ## _from_handle(__VkType _handle) \
2522 return (struct __radv_type *)(uintptr_t) _handle; \
2525 static inline __VkType \
2526 __radv_type ## _to_handle(struct __radv_type *_obj) \
2528 return (__VkType)(uintptr_t) _obj; \
2531 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2532 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2534 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2535 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2536 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2537 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2538 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2540 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2541 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2542 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2543 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2544 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2545 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2546 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2547 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2548 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2549 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2550 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2551 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2552 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2553 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2554 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2555 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2556 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2557 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2558 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2559 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2560 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2561 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2563 #endif /* RADV_PRIVATE_H */