2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vulkan_android.h>
80 #include <vulkan/vk_icd.h>
81 #include <vulkan/vk_android_native_buffer.h>
83 #include "radv_entrypoints.h"
85 #include "wsi_common.h"
86 #include "wsi_common_display.h"
88 /* Helper to determine if we should compile
89 * any of the Android AHB support.
91 * To actually enable the ext we also need
92 * the necessary kernel support.
94 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
97 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
101 struct gfx10_format
{
102 unsigned img_format
:9;
104 /* Various formats are only supported with workarounds for vertex fetch,
105 * and some 32_32_32 formats are supported natively, but only for buffers
106 * (possibly with some image support, actually, but no filtering). */
110 #include "gfx10_format_table.h"
114 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
121 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
122 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
123 RADV_MEM_TYPE_GTT_CACHED
,
124 RADV_MEM_TYPE_VRAM_UNCACHED
,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED
,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED
,
127 RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED
,
131 enum radv_secure_compile_type
{
132 RADV_SC_TYPE_INIT_SUCCESS
,
133 RADV_SC_TYPE_INIT_FAILURE
,
134 RADV_SC_TYPE_COMPILE_PIPELINE
,
135 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
136 RADV_SC_TYPE_READ_DISK_CACHE
,
137 RADV_SC_TYPE_WRITE_DISK_CACHE
,
138 RADV_SC_TYPE_DESTROY_DEVICE
,
142 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
144 static inline uint32_t
145 align_u32(uint32_t v
, uint32_t a
)
147 assert(a
!= 0 && a
== (a
& -a
));
148 return (v
+ a
- 1) & ~(a
- 1);
151 static inline uint32_t
152 align_u32_npot(uint32_t v
, uint32_t a
)
154 return (v
+ a
- 1) / a
* a
;
157 static inline uint64_t
158 align_u64(uint64_t v
, uint64_t a
)
160 assert(a
!= 0 && a
== (a
& -a
));
161 return (v
+ a
- 1) & ~(a
- 1);
164 static inline int32_t
165 align_i32(int32_t v
, int32_t a
)
167 assert(a
!= 0 && a
== (a
& -a
));
168 return (v
+ a
- 1) & ~(a
- 1);
171 /** Alignment must be a power of 2. */
173 radv_is_aligned(uintmax_t n
, uintmax_t a
)
175 assert(a
== (a
& -a
));
176 return (n
& (a
- 1)) == 0;
179 static inline uint32_t
180 round_up_u32(uint32_t v
, uint32_t a
)
182 return (v
+ a
- 1) / a
;
185 static inline uint64_t
186 round_up_u64(uint64_t v
, uint64_t a
)
188 return (v
+ a
- 1) / a
;
191 static inline uint32_t
192 radv_minify(uint32_t n
, uint32_t levels
)
194 if (unlikely(n
== 0))
197 return MAX2(n
>> levels
, 1);
200 radv_clamp_f(float f
, float min
, float max
)
213 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
215 if (*inout_mask
& clear_mask
) {
216 *inout_mask
&= ~clear_mask
;
223 #define for_each_bit(b, dword) \
224 for (uint32_t __dword = (dword); \
225 (b) = __builtin_ffs(__dword) - 1, __dword; \
226 __dword &= ~(1 << (b)))
228 #define typed_memcpy(dest, src, count) ({ \
229 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
230 memcpy((dest), (src), (count) * sizeof(*(src))); \
233 /* Whenever we generate an error, pass it through this function. Useful for
234 * debugging, where we can break on it. Only call at error site, not when
235 * propagating errors. Might be useful to plug in a stack trace here.
238 struct radv_image_view
;
239 struct radv_instance
;
241 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
243 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
244 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
246 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
247 radv_printflike(3, 4);
248 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
249 void radv_loge_v(const char *format
, va_list va
);
250 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
251 void radv_logi_v(const char *format
, va_list va
);
254 * Print a FINISHME message, including its source location.
256 #define radv_finishme(format, ...) \
258 static bool reported = false; \
260 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
265 /* A non-fatal assert. Useful for debugging. */
267 #define radv_assert(x) ({ \
268 if (unlikely(!(x))) \
269 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
272 #define radv_assert(x)
275 #define stub_return(v) \
277 radv_finishme("stub %s", __func__); \
283 radv_finishme("stub %s", __func__); \
287 void *radv_lookup_entrypoint_unchecked(const char *name
);
288 void *radv_lookup_entrypoint_checked(const char *name
,
289 uint32_t core_version
,
290 const struct radv_instance_extension_table
*instance
,
291 const struct radv_device_extension_table
*device
);
292 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
293 uint32_t core_version
,
294 const struct radv_instance_extension_table
*instance
);
296 struct radv_physical_device
{
297 VK_LOADER_DATA _loader_data
;
299 struct radv_instance
* instance
;
301 struct radeon_winsys
*ws
;
302 struct radeon_info rad_info
;
303 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
304 uint8_t driver_uuid
[VK_UUID_SIZE
];
305 uint8_t device_uuid
[VK_UUID_SIZE
];
306 uint8_t cache_uuid
[VK_UUID_SIZE
];
310 struct wsi_device wsi_device
;
312 bool out_of_order_rast_allowed
;
314 /* Whether DCC should be enabled for MSAA textures. */
315 bool dcc_msaa_allowed
;
317 /* Whether to enable the AMD_shader_ballot extension */
318 bool use_shader_ballot
;
320 /* Whether to enable NGG. */
323 /* Whether to enable NGG streamout. */
324 bool use_ngg_streamout
;
326 /* Number of threads per wave. */
327 uint8_t ps_wave_size
;
328 uint8_t cs_wave_size
;
329 uint8_t ge_wave_size
;
331 /* Whether to use the experimental compiler backend */
334 /* This is the drivers on-disk cache used as a fallback as opposed to
335 * the pipeline cache defined by apps.
337 struct disk_cache
* disk_cache
;
339 VkPhysicalDeviceMemoryProperties memory_properties
;
340 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
342 drmPciBusInfo bus_info
;
344 struct radv_device_extension_table supported_extensions
;
347 struct radv_instance
{
348 VK_LOADER_DATA _loader_data
;
350 VkAllocationCallbacks alloc
;
353 int physicalDeviceCount
;
354 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
357 uint32_t engineVersion
;
359 uint64_t debug_flags
;
360 uint64_t perftest_flags
;
361 uint8_t num_sc_threads
;
363 struct vk_debug_report_instance debug_report_callbacks
;
365 struct radv_instance_extension_table enabled_extensions
;
367 struct driOptionCache dri_options
;
368 struct driOptionCache available_dri_options
;
372 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
374 return instance
->num_sc_threads
;
377 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
378 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
380 bool radv_instance_extension_supported(const char *name
);
381 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
382 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
387 struct radv_pipeline_cache
{
388 struct radv_device
* device
;
389 pthread_mutex_t mutex
;
393 uint32_t kernel_count
;
394 struct cache_entry
** hash_table
;
397 VkAllocationCallbacks alloc
;
400 struct radv_pipeline_key
{
401 uint32_t instance_rate_inputs
;
402 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
403 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
404 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
405 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
406 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
407 uint64_t vertex_alpha_adjust
;
408 uint32_t vertex_post_shuffle
;
409 unsigned tess_input_vertices
;
413 uint8_t log2_ps_iter_samples
;
415 uint32_t has_multiview_view_index
: 1;
416 uint32_t optimisations_disabled
: 1;
419 /* Non-zero if a required subgroup size is specified via
420 * VK_EXT_subgroup_size_control.
422 uint8_t compute_subgroup_size
;
425 struct radv_shader_binary
;
426 struct radv_shader_variant
;
429 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
430 struct radv_device
*device
);
432 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
434 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
435 const void *data
, size_t size
);
438 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
439 struct radv_pipeline_cache
*cache
,
440 const unsigned char *sha1
,
441 struct radv_shader_variant
**variants
,
442 bool *found_in_application_cache
);
445 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
446 struct radv_pipeline_cache
*cache
,
447 const unsigned char *sha1
,
448 struct radv_shader_variant
**variants
,
449 struct radv_shader_binary
*const *binaries
);
451 enum radv_blit_ds_layout
{
452 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
453 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
454 RADV_BLIT_DS_LAYOUT_COUNT
,
457 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
459 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
462 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
464 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
467 enum radv_meta_dst_layout
{
468 RADV_META_DST_LAYOUT_GENERAL
,
469 RADV_META_DST_LAYOUT_OPTIMAL
,
470 RADV_META_DST_LAYOUT_COUNT
,
473 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
475 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
478 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
480 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
483 struct radv_meta_state
{
484 VkAllocationCallbacks alloc
;
486 struct radv_pipeline_cache cache
;
489 * For on-demand pipeline creation, makes sure that
490 * only one thread tries to build a pipeline at the same time.
495 * Use array element `i` for images with `2^i` samples.
498 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
499 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
501 VkRenderPass depthstencil_rp
;
502 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
503 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
504 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
506 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
507 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
508 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
509 } clear
[MAX_SAMPLES_LOG2
];
511 VkPipelineLayout clear_color_p_layout
;
512 VkPipelineLayout clear_depth_p_layout
;
513 VkPipelineLayout clear_depth_unrestricted_p_layout
;
515 /* Optimized compute fast HTILE clear for stencil or depth only. */
516 VkPipeline clear_htile_mask_pipeline
;
517 VkPipelineLayout clear_htile_mask_p_layout
;
518 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
521 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
523 /** Pipeline that blits from a 1D image. */
524 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
526 /** Pipeline that blits from a 2D image. */
527 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
529 /** Pipeline that blits from a 3D image. */
530 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
532 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
533 VkPipeline depth_only_1d_pipeline
;
534 VkPipeline depth_only_2d_pipeline
;
535 VkPipeline depth_only_3d_pipeline
;
537 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
538 VkPipeline stencil_only_1d_pipeline
;
539 VkPipeline stencil_only_2d_pipeline
;
540 VkPipeline stencil_only_3d_pipeline
;
541 VkPipelineLayout pipeline_layout
;
542 VkDescriptorSetLayout ds_layout
;
546 VkPipelineLayout p_layouts
[5];
547 VkDescriptorSetLayout ds_layouts
[5];
548 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
550 VkPipeline depth_only_pipeline
[5];
552 VkPipeline stencil_only_pipeline
[5];
553 } blit2d
[MAX_SAMPLES_LOG2
];
555 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
556 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
557 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
560 VkPipelineLayout img_p_layout
;
561 VkDescriptorSetLayout img_ds_layout
;
563 VkPipeline pipeline_3d
;
566 VkPipelineLayout img_p_layout
;
567 VkDescriptorSetLayout img_ds_layout
;
569 VkPipeline pipeline_3d
;
572 VkPipelineLayout img_p_layout
;
573 VkDescriptorSetLayout img_ds_layout
;
577 VkPipelineLayout img_p_layout
;
578 VkDescriptorSetLayout img_ds_layout
;
580 VkPipeline pipeline_3d
;
583 VkPipelineLayout img_p_layout
;
584 VkDescriptorSetLayout img_ds_layout
;
588 VkPipelineLayout img_p_layout
;
589 VkDescriptorSetLayout img_ds_layout
;
591 VkPipeline pipeline_3d
;
594 VkPipelineLayout img_p_layout
;
595 VkDescriptorSetLayout img_ds_layout
;
600 VkPipelineLayout p_layout
;
601 VkPipeline pipeline
[NUM_META_FS_KEYS
];
602 VkRenderPass pass
[NUM_META_FS_KEYS
];
606 VkDescriptorSetLayout ds_layout
;
607 VkPipelineLayout p_layout
;
610 VkPipeline i_pipeline
;
611 VkPipeline srgb_pipeline
;
612 } rc
[MAX_SAMPLES_LOG2
];
614 VkPipeline depth_zero_pipeline
;
616 VkPipeline average_pipeline
;
617 VkPipeline max_pipeline
;
618 VkPipeline min_pipeline
;
619 } depth
[MAX_SAMPLES_LOG2
];
621 VkPipeline stencil_zero_pipeline
;
623 VkPipeline max_pipeline
;
624 VkPipeline min_pipeline
;
625 } stencil
[MAX_SAMPLES_LOG2
];
629 VkDescriptorSetLayout ds_layout
;
630 VkPipelineLayout p_layout
;
633 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
634 VkPipeline pipeline
[NUM_META_FS_KEYS
];
635 } rc
[MAX_SAMPLES_LOG2
];
637 VkRenderPass depth_render_pass
;
638 VkPipeline depth_zero_pipeline
;
640 VkPipeline average_pipeline
;
641 VkPipeline max_pipeline
;
642 VkPipeline min_pipeline
;
643 } depth
[MAX_SAMPLES_LOG2
];
645 VkRenderPass stencil_render_pass
;
646 VkPipeline stencil_zero_pipeline
;
648 VkPipeline max_pipeline
;
649 VkPipeline min_pipeline
;
650 } stencil
[MAX_SAMPLES_LOG2
];
654 VkPipelineLayout p_layout
;
655 VkPipeline decompress_pipeline
;
656 VkPipeline resummarize_pipeline
;
658 } depth_decomp
[MAX_SAMPLES_LOG2
];
661 VkPipelineLayout p_layout
;
662 VkPipeline cmask_eliminate_pipeline
;
663 VkPipeline fmask_decompress_pipeline
;
664 VkPipeline dcc_decompress_pipeline
;
667 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
668 VkPipelineLayout dcc_decompress_compute_p_layout
;
669 VkPipeline dcc_decompress_compute_pipeline
;
673 VkPipelineLayout fill_p_layout
;
674 VkPipelineLayout copy_p_layout
;
675 VkDescriptorSetLayout fill_ds_layout
;
676 VkDescriptorSetLayout copy_ds_layout
;
677 VkPipeline fill_pipeline
;
678 VkPipeline copy_pipeline
;
682 VkDescriptorSetLayout ds_layout
;
683 VkPipelineLayout p_layout
;
684 VkPipeline occlusion_query_pipeline
;
685 VkPipeline pipeline_statistics_query_pipeline
;
686 VkPipeline tfb_query_pipeline
;
687 VkPipeline timestamp_query_pipeline
;
691 VkDescriptorSetLayout ds_layout
;
692 VkPipelineLayout p_layout
;
693 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
698 #define RADV_QUEUE_GENERAL 0
699 #define RADV_QUEUE_COMPUTE 1
700 #define RADV_QUEUE_TRANSFER 2
702 #define RADV_MAX_QUEUE_FAMILIES 3
704 enum ring_type
radv_queue_family_to_ring(int f
);
707 VK_LOADER_DATA _loader_data
;
708 struct radv_device
* device
;
709 struct radeon_winsys_ctx
*hw_ctx
;
710 enum radeon_ctx_priority priority
;
711 uint32_t queue_family_index
;
713 VkDeviceQueueCreateFlags flags
;
715 uint32_t scratch_size
;
716 uint32_t compute_scratch_size
;
717 uint32_t esgs_ring_size
;
718 uint32_t gsvs_ring_size
;
721 bool has_sample_positions
;
723 struct radeon_winsys_bo
*scratch_bo
;
724 struct radeon_winsys_bo
*descriptor_bo
;
725 struct radeon_winsys_bo
*compute_scratch_bo
;
726 struct radeon_winsys_bo
*esgs_ring_bo
;
727 struct radeon_winsys_bo
*gsvs_ring_bo
;
728 struct radeon_winsys_bo
*tess_rings_bo
;
729 struct radeon_winsys_bo
*gds_bo
;
730 struct radeon_winsys_bo
*gds_oa_bo
;
731 struct radeon_cmdbuf
*initial_preamble_cs
;
732 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
733 struct radeon_cmdbuf
*continue_preamble_cs
;
735 struct list_head pending_submissions
;
736 pthread_mutex_t pending_mutex
;
739 struct radv_bo_list
{
740 struct radv_winsys_bo_list list
;
742 pthread_mutex_t mutex
;
745 struct radv_secure_compile_process
{
746 /* Secure process file descriptors */
748 int fd_secure_output
;
750 /* Secure compile process id */
753 /* Is the secure compile process currently in use by a thread */
757 struct radv_secure_compile_state
{
758 struct radv_secure_compile_process
*secure_compile_processes
;
759 uint32_t secure_compile_thread_counter
;
760 mtx_t secure_compile_mutex
;
764 VK_LOADER_DATA _loader_data
;
766 VkAllocationCallbacks alloc
;
768 struct radv_instance
* instance
;
769 struct radeon_winsys
*ws
;
771 struct radv_meta_state meta_state
;
773 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
774 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
775 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
777 bool always_use_syncobj
;
780 uint32_t tess_offchip_block_dw_size
;
781 uint32_t scratch_waves
;
782 uint32_t dispatch_initiator
;
784 uint32_t gs_table_depth
;
786 /* MSAA sample locations.
787 * The first index is the sample index.
788 * The second index is the coordinate: X, Y. */
789 float sample_locations_1x
[1][2];
790 float sample_locations_2x
[2][2];
791 float sample_locations_4x
[4][2];
792 float sample_locations_8x
[8][2];
795 uint32_t gfx_init_size_dw
;
796 struct radeon_winsys_bo
*gfx_init
;
798 struct radeon_winsys_bo
*trace_bo
;
799 uint32_t *trace_id_ptr
;
801 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
802 bool keep_shader_info
;
804 struct radv_physical_device
*physical_device
;
806 /* Backup in-memory cache to be used if the app doesn't provide one */
807 struct radv_pipeline_cache
* mem_cache
;
810 * use different counters so MSAA MRTs get consecutive surface indices,
811 * even if MASK is allocated in between.
813 uint32_t image_mrt_offset_counter
;
814 uint32_t fmask_mrt_offset_counter
;
815 struct list_head shader_slabs
;
816 mtx_t shader_slab_mutex
;
818 /* For detecting VM faults reported by dmesg. */
819 uint64_t dmesg_timestamp
;
821 struct radv_device_extension_table enabled_extensions
;
823 /* Whether the app has enabled the robustBufferAccess feature. */
824 bool robust_buffer_access
;
826 /* Whether the driver uses a global BO list. */
827 bool use_global_bo_list
;
829 struct radv_bo_list bo_list
;
831 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
834 struct radv_secure_compile_state
*sc_state
;
836 /* Condition variable for legacy timelines, to notify waiters when a
837 * new point gets submitted. */
838 pthread_cond_t timeline_cond
;
841 struct radv_device_memory
{
842 struct radeon_winsys_bo
*bo
;
843 /* for dedicated allocations */
844 struct radv_image
*image
;
845 struct radv_buffer
*buffer
;
847 VkDeviceSize map_size
;
851 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
852 struct AHardwareBuffer
* android_hardware_buffer
;
857 struct radv_descriptor_range
{
862 struct radv_descriptor_set
{
863 const struct radv_descriptor_set_layout
*layout
;
866 struct radeon_winsys_bo
*bo
;
868 uint32_t *mapped_ptr
;
869 struct radv_descriptor_range
*dynamic_descriptors
;
871 struct radeon_winsys_bo
*descriptors
[0];
874 struct radv_push_descriptor_set
876 struct radv_descriptor_set set
;
880 struct radv_descriptor_pool_entry
{
883 struct radv_descriptor_set
*set
;
886 struct radv_descriptor_pool
{
887 struct radeon_winsys_bo
*bo
;
889 uint64_t current_offset
;
892 uint8_t *host_memory_base
;
893 uint8_t *host_memory_ptr
;
894 uint8_t *host_memory_end
;
896 uint32_t entry_count
;
897 uint32_t max_entry_count
;
898 struct radv_descriptor_pool_entry entries
[0];
901 struct radv_descriptor_update_template_entry
{
902 VkDescriptorType descriptor_type
;
904 /* The number of descriptors to update */
905 uint32_t descriptor_count
;
907 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
910 /* In dwords. Not valid/used for dynamic descriptors */
913 uint32_t buffer_offset
;
915 /* Only valid for combined image samplers and samplers */
917 uint8_t sampler_offset
;
923 /* For push descriptors */
924 const uint32_t *immutable_samplers
;
927 struct radv_descriptor_update_template
{
928 uint32_t entry_count
;
929 VkPipelineBindPoint bind_point
;
930 struct radv_descriptor_update_template_entry entry
[0];
936 VkBufferUsageFlags usage
;
937 VkBufferCreateFlags flags
;
940 struct radeon_winsys_bo
* bo
;
946 enum radv_dynamic_state_bits
{
947 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
948 RADV_DYNAMIC_SCISSOR
= 1 << 1,
949 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
950 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
951 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
952 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
953 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
954 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
955 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
956 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
957 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
958 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
961 enum radv_cmd_dirty_bits
{
962 /* Keep the dynamic state dirty bits in sync with
963 * enum radv_dynamic_state_bits */
964 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
965 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
966 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
967 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
968 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
969 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
970 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
971 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
972 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
973 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
974 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
975 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
976 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
977 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
978 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
979 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
980 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
983 enum radv_cmd_flush_bits
{
984 /* Instruction cache. */
985 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
986 /* Scalar L1 cache. */
987 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
988 /* Vector L1 cache. */
989 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
990 /* L2 cache + L2 metadata cache writeback & invalidate.
991 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
992 RADV_CMD_FLAG_INV_L2
= 1 << 3,
993 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
994 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
995 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
996 RADV_CMD_FLAG_WB_L2
= 1 << 4,
997 /* Framebuffer caches */
998 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
999 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1000 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1001 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1002 /* Engine synchronization. */
1003 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1004 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1005 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1006 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1007 /* Pipeline query controls. */
1008 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1009 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1010 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1012 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1013 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1014 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1015 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1018 struct radv_vertex_binding
{
1019 struct radv_buffer
* buffer
;
1020 VkDeviceSize offset
;
1023 struct radv_streamout_binding
{
1024 struct radv_buffer
*buffer
;
1025 VkDeviceSize offset
;
1029 struct radv_streamout_state
{
1030 /* Mask of bound streamout buffers. */
1031 uint8_t enabled_mask
;
1033 /* External state that comes from the last vertex stage, it must be
1034 * set explicitely when binding a new graphics pipeline.
1036 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1037 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1039 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1040 uint32_t hw_enabled_mask
;
1042 /* State of VGT_STRMOUT_(CONFIG|EN) */
1043 bool streamout_enabled
;
1046 struct radv_viewport_state
{
1048 VkViewport viewports
[MAX_VIEWPORTS
];
1051 struct radv_scissor_state
{
1053 VkRect2D scissors
[MAX_SCISSORS
];
1056 struct radv_discard_rectangle_state
{
1058 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1061 struct radv_sample_locations_state
{
1062 VkSampleCountFlagBits per_pixel
;
1063 VkExtent2D grid_size
;
1065 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1068 struct radv_dynamic_state
{
1070 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1071 * Defines the set of saved dynamic state.
1075 struct radv_viewport_state viewport
;
1077 struct radv_scissor_state scissor
;
1087 float blend_constants
[4];
1097 } stencil_compare_mask
;
1102 } stencil_write_mask
;
1107 } stencil_reference
;
1109 struct radv_discard_rectangle_state discard_rectangle
;
1111 struct radv_sample_locations_state sample_location
;
1114 extern const struct radv_dynamic_state default_dynamic_state
;
1117 radv_get_debug_option_name(int id
);
1120 radv_get_perftest_option_name(int id
);
1122 struct radv_color_buffer_info
{
1123 uint64_t cb_color_base
;
1124 uint64_t cb_color_cmask
;
1125 uint64_t cb_color_fmask
;
1126 uint64_t cb_dcc_base
;
1127 uint32_t cb_color_slice
;
1128 uint32_t cb_color_view
;
1129 uint32_t cb_color_info
;
1130 uint32_t cb_color_attrib
;
1131 uint32_t cb_color_attrib2
; /* GFX9 and later */
1132 uint32_t cb_color_attrib3
; /* GFX10 and later */
1133 uint32_t cb_dcc_control
;
1134 uint32_t cb_color_cmask_slice
;
1135 uint32_t cb_color_fmask_slice
;
1137 uint32_t cb_color_pitch
; // GFX6-GFX8
1138 uint32_t cb_mrt_epitch
; // GFX9+
1142 struct radv_ds_buffer_info
{
1143 uint64_t db_z_read_base
;
1144 uint64_t db_stencil_read_base
;
1145 uint64_t db_z_write_base
;
1146 uint64_t db_stencil_write_base
;
1147 uint64_t db_htile_data_base
;
1148 uint32_t db_depth_info
;
1150 uint32_t db_stencil_info
;
1151 uint32_t db_depth_view
;
1152 uint32_t db_depth_size
;
1153 uint32_t db_depth_slice
;
1154 uint32_t db_htile_surface
;
1155 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1156 uint32_t db_z_info2
; /* GFX9 only */
1157 uint32_t db_stencil_info2
; /* GFX9 only */
1162 radv_initialise_color_surface(struct radv_device
*device
,
1163 struct radv_color_buffer_info
*cb
,
1164 struct radv_image_view
*iview
);
1166 radv_initialise_ds_surface(struct radv_device
*device
,
1167 struct radv_ds_buffer_info
*ds
,
1168 struct radv_image_view
*iview
);
1171 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1174 * Attachment state when recording a renderpass instance.
1176 * The clear value is valid only if there exists a pending clear.
1178 struct radv_attachment_state
{
1179 VkImageAspectFlags pending_clear_aspects
;
1180 uint32_t cleared_views
;
1181 VkClearValue clear_value
;
1182 VkImageLayout current_layout
;
1183 bool current_in_render_loop
;
1184 struct radv_sample_locations_state sample_location
;
1187 struct radv_color_buffer_info cb
;
1188 struct radv_ds_buffer_info ds
;
1190 struct radv_image_view
*iview
;
1193 struct radv_descriptor_state
{
1194 struct radv_descriptor_set
*sets
[MAX_SETS
];
1197 struct radv_push_descriptor_set push_set
;
1199 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1202 struct radv_subpass_sample_locs_state
{
1203 uint32_t subpass_idx
;
1204 struct radv_sample_locations_state sample_location
;
1207 struct radv_cmd_state
{
1208 /* Vertex descriptors */
1215 uint32_t prefetch_L2_mask
;
1217 struct radv_pipeline
* pipeline
;
1218 struct radv_pipeline
* emitted_pipeline
;
1219 struct radv_pipeline
* compute_pipeline
;
1220 struct radv_pipeline
* emitted_compute_pipeline
;
1221 struct radv_framebuffer
* framebuffer
;
1222 struct radv_render_pass
* pass
;
1223 const struct radv_subpass
* subpass
;
1224 struct radv_dynamic_state dynamic
;
1225 struct radv_attachment_state
* attachments
;
1226 struct radv_streamout_state streamout
;
1227 VkRect2D render_area
;
1229 uint32_t num_subpass_sample_locs
;
1230 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1233 struct radv_buffer
*index_buffer
;
1234 uint64_t index_offset
;
1235 uint32_t index_type
;
1236 uint32_t max_index_count
;
1238 int32_t last_index_type
;
1240 int32_t last_primitive_reset_en
;
1241 uint32_t last_primitive_reset_index
;
1242 enum radv_cmd_flush_bits flush_bits
;
1243 unsigned active_occlusion_queries
;
1244 bool perfect_occlusion_queries_enabled
;
1245 unsigned active_pipeline_queries
;
1248 uint32_t last_ia_multi_vgt_param
;
1250 uint32_t last_num_instances
;
1251 uint32_t last_first_instance
;
1252 uint32_t last_vertex_offset
;
1254 /* Whether CP DMA is busy/idle. */
1257 /* Conditional rendering info. */
1258 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1259 uint64_t predication_va
;
1261 bool context_roll_without_scissor_emitted
;
1264 struct radv_cmd_pool
{
1265 VkAllocationCallbacks alloc
;
1266 struct list_head cmd_buffers
;
1267 struct list_head free_cmd_buffers
;
1268 uint32_t queue_family_index
;
1271 struct radv_cmd_buffer_upload
{
1275 struct radeon_winsys_bo
*upload_bo
;
1276 struct list_head list
;
1279 enum radv_cmd_buffer_status
{
1280 RADV_CMD_BUFFER_STATUS_INVALID
,
1281 RADV_CMD_BUFFER_STATUS_INITIAL
,
1282 RADV_CMD_BUFFER_STATUS_RECORDING
,
1283 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1284 RADV_CMD_BUFFER_STATUS_PENDING
,
1287 struct radv_cmd_buffer
{
1288 VK_LOADER_DATA _loader_data
;
1290 struct radv_device
* device
;
1292 struct radv_cmd_pool
* pool
;
1293 struct list_head pool_link
;
1295 VkCommandBufferUsageFlags usage_flags
;
1296 VkCommandBufferLevel level
;
1297 enum radv_cmd_buffer_status status
;
1298 struct radeon_cmdbuf
*cs
;
1299 struct radv_cmd_state state
;
1300 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1301 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1302 uint32_t queue_family_index
;
1304 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1305 VkShaderStageFlags push_constant_stages
;
1306 struct radv_descriptor_set meta_push_descriptors
;
1308 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1310 struct radv_cmd_buffer_upload upload
;
1312 uint32_t scratch_size_needed
;
1313 uint32_t compute_scratch_size_needed
;
1314 uint32_t esgs_ring_size_needed
;
1315 uint32_t gsvs_ring_size_needed
;
1316 bool tess_rings_needed
;
1317 bool gds_needed
; /* for GFX10 streamout */
1318 bool sample_positions_needed
;
1320 VkResult record_result
;
1322 uint64_t gfx9_fence_va
;
1323 uint32_t gfx9_fence_idx
;
1324 uint64_t gfx9_eop_bug_va
;
1327 * Whether a query pool has been resetted and we have to flush caches.
1329 bool pending_reset_query
;
1332 * Bitmask of pending active query flushes.
1334 enum radv_cmd_flush_bits active_query_flush_bits
;
1338 struct radv_image_view
;
1340 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1342 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1343 struct radeon_cmdbuf
*cs
);
1344 void si_emit_compute(struct radv_physical_device
*physical_device
,
1345 struct radeon_cmdbuf
*cs
);
1347 void cik_create_gfx_config(struct radv_device
*device
);
1349 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1350 int count
, const VkViewport
*viewports
);
1351 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1352 int count
, const VkRect2D
*scissors
,
1353 const VkViewport
*viewports
, bool can_use_guardband
);
1354 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1355 bool instanced_draw
, bool indirect_draw
,
1356 bool count_from_stream_output
,
1357 uint32_t draw_vertex_count
);
1358 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1359 enum chip_class chip_class
,
1361 unsigned event
, unsigned event_flags
,
1362 unsigned dst_sel
, unsigned data_sel
,
1365 uint64_t gfx9_eop_bug_va
);
1367 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1368 uint32_t ref
, uint32_t mask
);
1369 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1370 enum chip_class chip_class
,
1371 uint32_t *fence_ptr
, uint64_t va
,
1373 enum radv_cmd_flush_bits flush_bits
,
1374 uint64_t gfx9_eop_bug_va
);
1375 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1376 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1377 bool inverted
, uint64_t va
);
1378 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1379 uint64_t src_va
, uint64_t dest_va
,
1381 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1383 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1384 uint64_t size
, unsigned value
);
1385 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1387 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1389 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1392 unsigned *out_offset
,
1395 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1396 const struct radv_subpass
*subpass
);
1398 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1399 unsigned size
, unsigned alignmnet
,
1400 const void *data
, unsigned *out_offset
);
1402 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1403 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1404 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1405 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1406 VkImageAspectFlags aspects
,
1407 VkResolveModeFlagBitsKHR resolve_mode
);
1408 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1409 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1410 VkImageAspectFlags aspects
,
1411 VkResolveModeFlagBitsKHR resolve_mode
);
1412 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1413 unsigned radv_get_default_max_sample_dist(int log_samples
);
1414 void radv_device_init_msaa(struct radv_device
*device
);
1416 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1417 const struct radv_image_view
*iview
,
1418 VkClearDepthStencilValue ds_clear_value
,
1419 VkImageAspectFlags aspects
);
1421 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1422 const struct radv_image_view
*iview
,
1424 uint32_t color_values
[2]);
1426 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1427 struct radv_image
*image
,
1428 const VkImageSubresourceRange
*range
, bool value
);
1430 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1431 struct radv_image
*image
,
1432 const VkImageSubresourceRange
*range
, bool value
);
1434 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1435 struct radeon_winsys_bo
*bo
,
1436 uint64_t offset
, uint64_t size
, uint32_t value
);
1437 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1438 bool radv_get_memory_fd(struct radv_device
*device
,
1439 struct radv_device_memory
*memory
,
1443 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1444 unsigned sh_offset
, unsigned pointer_count
,
1445 bool use_32bit_pointers
)
1447 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1448 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1452 radv_emit_shader_pointer_body(struct radv_device
*device
,
1453 struct radeon_cmdbuf
*cs
,
1454 uint64_t va
, bool use_32bit_pointers
)
1456 radeon_emit(cs
, va
);
1458 if (use_32bit_pointers
) {
1460 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1462 radeon_emit(cs
, va
>> 32);
1467 radv_emit_shader_pointer(struct radv_device
*device
,
1468 struct radeon_cmdbuf
*cs
,
1469 uint32_t sh_offset
, uint64_t va
, bool global
)
1471 bool use_32bit_pointers
= !global
;
1473 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1474 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1477 static inline struct radv_descriptor_state
*
1478 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1479 VkPipelineBindPoint bind_point
)
1481 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1482 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1483 return &cmd_buffer
->descriptors
[bind_point
];
1487 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1489 * Limitations: Can't call normal dispatch functions without binding or rebinding
1490 * the compute pipeline.
1492 void radv_unaligned_dispatch(
1493 struct radv_cmd_buffer
*cmd_buffer
,
1499 struct radeon_winsys_bo
*bo
;
1503 struct radv_shader_module
;
1505 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1506 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1507 #define RADV_HASH_SHADER_NO_NGG (1 << 2)
1508 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 3)
1509 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 4)
1510 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 5)
1511 #define RADV_HASH_SHADER_ACO (1 << 6)
1514 radv_hash_shaders(unsigned char *hash
,
1515 const VkPipelineShaderStageCreateInfo
**stages
,
1516 const struct radv_pipeline_layout
*layout
,
1517 const struct radv_pipeline_key
*key
,
1520 static inline gl_shader_stage
1521 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1523 assert(__builtin_popcount(vk_stage
) == 1);
1524 return ffs(vk_stage
) - 1;
1527 static inline VkShaderStageFlagBits
1528 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1530 return (1 << mesa_stage
);
1533 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1535 #define radv_foreach_stage(stage, stage_bits) \
1536 for (gl_shader_stage stage, \
1537 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1538 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1539 __tmp &= ~(1 << (stage)))
1541 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1542 unsigned radv_format_meta_fs_key(VkFormat format
);
1544 struct radv_multisample_state
{
1546 uint32_t pa_sc_line_cntl
;
1547 uint32_t pa_sc_mode_cntl_0
;
1548 uint32_t pa_sc_mode_cntl_1
;
1549 uint32_t pa_sc_aa_config
;
1550 uint32_t pa_sc_aa_mask
[2];
1551 unsigned num_samples
;
1554 struct radv_prim_vertex_count
{
1559 struct radv_vertex_elements_info
{
1560 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1563 struct radv_ia_multi_vgt_param_helpers
{
1565 bool partial_es_wave
;
1566 uint8_t primgroup_size
;
1567 bool wd_switch_on_eop
;
1568 bool ia_switch_on_eoi
;
1569 bool partial_vs_wave
;
1572 struct radv_binning_state
{
1573 uint32_t pa_sc_binner_cntl_0
;
1574 uint32_t db_dfsm_control
;
1577 #define SI_GS_PER_ES 128
1579 struct radv_pipeline
{
1580 struct radv_device
* device
;
1581 struct radv_dynamic_state dynamic_state
;
1583 struct radv_pipeline_layout
* layout
;
1585 bool need_indirect_descriptor_sets
;
1586 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1587 struct radv_shader_variant
*gs_copy_shader
;
1588 VkShaderStageFlags active_stages
;
1590 struct radeon_cmdbuf cs
;
1591 uint32_t ctx_cs_hash
;
1592 struct radeon_cmdbuf ctx_cs
;
1594 struct radv_vertex_elements_info vertex_elements
;
1596 uint32_t binding_stride
[MAX_VBS
];
1597 uint8_t num_vertex_bindings
;
1599 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1602 struct radv_multisample_state ms
;
1603 struct radv_binning_state binning
;
1604 uint32_t spi_baryc_cntl
;
1605 bool prim_restart_enable
;
1606 unsigned esgs_ring_size
;
1607 unsigned gsvs_ring_size
;
1608 uint32_t vtx_base_sgpr
;
1609 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1610 uint8_t vtx_emit_num
;
1611 struct radv_prim_vertex_count prim_vertex_count
;
1612 bool can_use_guardband
;
1613 uint32_t needed_dynamic_state
;
1614 bool disable_out_of_order_rast_for_occlusion
;
1616 /* Used for rbplus */
1617 uint32_t col_format
;
1618 uint32_t cb_target_mask
;
1623 unsigned scratch_bytes_per_wave
;
1625 /* Not NULL if graphics pipeline uses streamout. */
1626 struct radv_shader_variant
*streamout_shader
;
1629 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1631 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1634 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1636 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1639 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1641 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1643 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1644 gl_shader_stage stage
,
1647 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1648 gl_shader_stage stage
);
1650 struct radv_graphics_pipeline_create_info
{
1652 bool db_depth_clear
;
1653 bool db_stencil_clear
;
1654 bool db_depth_disable_expclear
;
1655 bool db_stencil_disable_expclear
;
1656 bool db_flush_depth_inplace
;
1657 bool db_flush_stencil_inplace
;
1658 bool db_resummarize
;
1659 uint32_t custom_blend_mode
;
1663 radv_graphics_pipeline_create(VkDevice device
,
1664 VkPipelineCache cache
,
1665 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1666 const struct radv_graphics_pipeline_create_info
*extra
,
1667 const VkAllocationCallbacks
*alloc
,
1668 VkPipeline
*pPipeline
);
1670 struct vk_format_description
;
1671 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1672 int first_non_void
);
1673 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1674 int first_non_void
);
1675 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1676 uint32_t radv_translate_colorformat(VkFormat format
);
1677 uint32_t radv_translate_color_numformat(VkFormat format
,
1678 const struct vk_format_description
*desc
,
1679 int first_non_void
);
1680 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1681 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1682 uint32_t radv_translate_dbformat(VkFormat format
);
1683 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1684 const struct vk_format_description
*desc
,
1685 int first_non_void
);
1686 uint32_t radv_translate_tex_numformat(VkFormat format
,
1687 const struct vk_format_description
*desc
,
1688 int first_non_void
);
1689 bool radv_format_pack_clear_color(VkFormat format
,
1690 uint32_t clear_vals
[2],
1691 VkClearColorValue
*value
);
1692 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1693 bool radv_dcc_formats_compatible(VkFormat format1
,
1695 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1697 struct radv_image_plane
{
1699 struct radeon_surf surface
;
1705 /* The original VkFormat provided by the client. This may not match any
1706 * of the actual surface formats.
1709 VkImageAspectFlags aspects
;
1710 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1711 struct ac_surf_info info
;
1712 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1713 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1718 unsigned queue_family_mask
;
1722 /* Set when bound */
1723 struct radeon_winsys_bo
*bo
;
1724 VkDeviceSize offset
;
1725 uint64_t dcc_offset
;
1726 uint64_t htile_offset
;
1727 bool tc_compatible_htile
;
1728 bool tc_compatible_cmask
;
1730 uint64_t cmask_offset
;
1731 uint64_t fmask_offset
;
1732 uint64_t clear_value_offset
;
1733 uint64_t fce_pred_offset
;
1734 uint64_t dcc_pred_offset
;
1737 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1738 * stored at this offset is UINT_MAX, the driver will emit
1739 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1740 * SET_CONTEXT_REG packet.
1742 uint64_t tc_compat_zrange_offset
;
1744 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1745 VkDeviceMemory owned_memory
;
1747 unsigned plane_count
;
1748 struct radv_image_plane planes
[0];
1751 /* Whether the image has a htile that is known consistent with the contents of
1753 bool radv_layout_has_htile(const struct radv_image
*image
,
1754 VkImageLayout layout
,
1755 bool in_render_loop
,
1756 unsigned queue_mask
);
1758 /* Whether the image has a htile that is known consistent with the contents of
1759 * the image and is allowed to be in compressed form.
1761 * If this is false reads that don't use the htile should be able to return
1764 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1765 VkImageLayout layout
,
1766 bool in_render_loop
,
1767 unsigned queue_mask
);
1769 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1770 VkImageLayout layout
,
1771 bool in_render_loop
,
1772 unsigned queue_mask
);
1774 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1775 const struct radv_image
*image
,
1776 VkImageLayout layout
,
1777 bool in_render_loop
,
1778 unsigned queue_mask
);
1781 * Return whether the image has CMASK metadata for color surfaces.
1784 radv_image_has_cmask(const struct radv_image
*image
)
1786 return image
->cmask_offset
;
1790 * Return whether the image has FMASK metadata for color surfaces.
1793 radv_image_has_fmask(const struct radv_image
*image
)
1795 return image
->fmask_offset
;
1799 * Return whether the image has DCC metadata for color surfaces.
1802 radv_image_has_dcc(const struct radv_image
*image
)
1804 return image
->planes
[0].surface
.dcc_size
;
1808 * Return whether the image is TC-compatible CMASK.
1811 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1813 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1817 * Return whether DCC metadata is enabled for a level.
1820 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1822 return radv_image_has_dcc(image
) &&
1823 level
< image
->planes
[0].surface
.num_dcc_levels
;
1827 * Return whether the image has CB metadata.
1830 radv_image_has_CB_metadata(const struct radv_image
*image
)
1832 return radv_image_has_cmask(image
) ||
1833 radv_image_has_fmask(image
) ||
1834 radv_image_has_dcc(image
);
1838 * Return whether the image has HTILE metadata for depth surfaces.
1841 radv_image_has_htile(const struct radv_image
*image
)
1843 return image
->planes
[0].surface
.htile_size
;
1847 * Return whether HTILE metadata is enabled for a level.
1850 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1852 return radv_image_has_htile(image
) && level
== 0;
1856 * Return whether the image is TC-compatible HTILE.
1859 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1861 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1864 static inline uint64_t
1865 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1866 uint32_t base_level
)
1868 uint64_t va
= radv_buffer_get_va(image
->bo
);
1869 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1873 static inline uint64_t
1874 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1875 uint32_t base_level
)
1877 uint64_t va
= radv_buffer_get_va(image
->bo
);
1878 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1882 static inline uint64_t
1883 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1884 uint32_t base_level
)
1886 uint64_t va
= radv_buffer_get_va(image
->bo
);
1887 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1891 static inline uint64_t
1892 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1893 uint32_t base_level
)
1895 uint64_t va
= radv_buffer_get_va(image
->bo
);
1896 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1900 static inline uint64_t
1901 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1902 uint32_t base_level
)
1904 uint64_t va
= radv_buffer_get_va(image
->bo
);
1905 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1909 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1911 static inline uint32_t
1912 radv_get_layerCount(const struct radv_image
*image
,
1913 const VkImageSubresourceRange
*range
)
1915 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1916 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1919 static inline uint32_t
1920 radv_get_levelCount(const struct radv_image
*image
,
1921 const VkImageSubresourceRange
*range
)
1923 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1924 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1927 struct radeon_bo_metadata
;
1929 radv_init_metadata(struct radv_device
*device
,
1930 struct radv_image
*image
,
1931 struct radeon_bo_metadata
*metadata
);
1934 radv_image_override_offset_stride(struct radv_device
*device
,
1935 struct radv_image
*image
,
1936 uint64_t offset
, uint32_t stride
);
1938 union radv_descriptor
{
1940 uint32_t plane0_descriptor
[8];
1941 uint32_t fmask_descriptor
[8];
1944 uint32_t plane_descriptors
[3][8];
1948 struct radv_image_view
{
1949 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1950 struct radeon_winsys_bo
*bo
;
1952 VkImageViewType type
;
1953 VkImageAspectFlags aspect_mask
;
1956 bool multiple_planes
;
1957 uint32_t base_layer
;
1958 uint32_t layer_count
;
1960 uint32_t level_count
;
1961 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1963 union radv_descriptor descriptor
;
1965 /* Descriptor for use as a storage image as opposed to a sampled image.
1966 * This has a few differences for cube maps (e.g. type).
1968 union radv_descriptor storage_descriptor
;
1971 struct radv_image_create_info
{
1972 const VkImageCreateInfo
*vk_info
;
1974 bool no_metadata_planes
;
1975 const struct radeon_bo_metadata
*bo_metadata
;
1979 radv_image_create_layout(struct radv_device
*device
,
1980 struct radv_image_create_info create_info
,
1981 struct radv_image
*image
);
1983 VkResult
radv_image_create(VkDevice _device
,
1984 const struct radv_image_create_info
*info
,
1985 const VkAllocationCallbacks
* alloc
,
1988 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
1991 radv_image_from_gralloc(VkDevice device_h
,
1992 const VkImageCreateInfo
*base_info
,
1993 const VkNativeBufferANDROID
*gralloc_info
,
1994 const VkAllocationCallbacks
*alloc
,
1995 VkImage
*out_image_h
);
1997 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
1998 const VkImageUsageFlags vk_usage
);
2000 radv_import_ahb_memory(struct radv_device
*device
,
2001 struct radv_device_memory
*mem
,
2003 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2005 radv_create_ahb_memory(struct radv_device
*device
,
2006 struct radv_device_memory
*mem
,
2008 const VkMemoryAllocateInfo
*pAllocateInfo
);
2011 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2013 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2015 struct radv_image_view_extra_create_info
{
2016 bool disable_compression
;
2019 void radv_image_view_init(struct radv_image_view
*view
,
2020 struct radv_device
*device
,
2021 const VkImageViewCreateInfo
*pCreateInfo
,
2022 const struct radv_image_view_extra_create_info
* extra_create_info
);
2024 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2026 struct radv_sampler_ycbcr_conversion
{
2028 VkSamplerYcbcrModelConversion ycbcr_model
;
2029 VkSamplerYcbcrRange ycbcr_range
;
2030 VkComponentMapping components
;
2031 VkChromaLocation chroma_offsets
[2];
2032 VkFilter chroma_filter
;
2035 struct radv_buffer_view
{
2036 struct radeon_winsys_bo
*bo
;
2038 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2041 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2042 struct radv_device
*device
,
2043 const VkBufferViewCreateInfo
* pCreateInfo
);
2045 static inline struct VkExtent3D
2046 radv_sanitize_image_extent(const VkImageType imageType
,
2047 const struct VkExtent3D imageExtent
)
2049 switch (imageType
) {
2050 case VK_IMAGE_TYPE_1D
:
2051 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2052 case VK_IMAGE_TYPE_2D
:
2053 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2054 case VK_IMAGE_TYPE_3D
:
2057 unreachable("invalid image type");
2061 static inline struct VkOffset3D
2062 radv_sanitize_image_offset(const VkImageType imageType
,
2063 const struct VkOffset3D imageOffset
)
2065 switch (imageType
) {
2066 case VK_IMAGE_TYPE_1D
:
2067 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2068 case VK_IMAGE_TYPE_2D
:
2069 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2070 case VK_IMAGE_TYPE_3D
:
2073 unreachable("invalid image type");
2078 radv_image_extent_compare(const struct radv_image
*image
,
2079 const VkExtent3D
*extent
)
2081 if (extent
->width
!= image
->info
.width
||
2082 extent
->height
!= image
->info
.height
||
2083 extent
->depth
!= image
->info
.depth
)
2088 struct radv_sampler
{
2090 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2093 struct radv_framebuffer
{
2098 uint32_t attachment_count
;
2099 struct radv_image_view
*attachments
[0];
2102 struct radv_subpass_barrier
{
2103 VkPipelineStageFlags src_stage_mask
;
2104 VkAccessFlags src_access_mask
;
2105 VkAccessFlags dst_access_mask
;
2108 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2109 const struct radv_subpass_barrier
*barrier
);
2111 struct radv_subpass_attachment
{
2112 uint32_t attachment
;
2113 VkImageLayout layout
;
2114 bool in_render_loop
;
2117 struct radv_subpass
{
2118 uint32_t attachment_count
;
2119 struct radv_subpass_attachment
* attachments
;
2121 uint32_t input_count
;
2122 uint32_t color_count
;
2123 struct radv_subpass_attachment
* input_attachments
;
2124 struct radv_subpass_attachment
* color_attachments
;
2125 struct radv_subpass_attachment
* resolve_attachments
;
2126 struct radv_subpass_attachment
* depth_stencil_attachment
;
2127 struct radv_subpass_attachment
* ds_resolve_attachment
;
2128 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2129 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2131 /** Subpass has at least one color resolve attachment */
2132 bool has_color_resolve
;
2134 /** Subpass has at least one color attachment */
2137 struct radv_subpass_barrier start_barrier
;
2140 VkSampleCountFlagBits max_sample_count
;
2144 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2146 struct radv_render_pass_attachment
{
2149 VkAttachmentLoadOp load_op
;
2150 VkAttachmentLoadOp stencil_load_op
;
2151 VkImageLayout initial_layout
;
2152 VkImageLayout final_layout
;
2154 /* The subpass id in which the attachment will be used first/last. */
2155 uint32_t first_subpass_idx
;
2156 uint32_t last_subpass_idx
;
2159 struct radv_render_pass
{
2160 uint32_t attachment_count
;
2161 uint32_t subpass_count
;
2162 struct radv_subpass_attachment
* subpass_attachments
;
2163 struct radv_render_pass_attachment
* attachments
;
2164 struct radv_subpass_barrier end_barrier
;
2165 struct radv_subpass subpasses
[0];
2168 VkResult
radv_device_init_meta(struct radv_device
*device
);
2169 void radv_device_finish_meta(struct radv_device
*device
);
2171 struct radv_query_pool
{
2172 struct radeon_winsys_bo
*bo
;
2174 uint32_t availability_offset
;
2178 uint32_t pipeline_stats_mask
;
2182 RADV_SEMAPHORE_NONE
,
2183 RADV_SEMAPHORE_WINSYS
,
2184 RADV_SEMAPHORE_SYNCOBJ
,
2185 RADV_SEMAPHORE_TIMELINE
,
2186 } radv_semaphore_kind
;
2188 struct radv_deferred_queue_submission
;
2190 struct radv_timeline_waiter
{
2191 struct list_head list
;
2192 struct radv_deferred_queue_submission
*submission
;
2196 struct radv_timeline_point
{
2197 struct list_head list
;
2202 /* Separate from the list to accomodate CPU wait being async, as well
2203 * as prevent point deletion during submission. */
2204 unsigned wait_count
;
2207 struct radv_timeline
{
2208 /* Using a pthread mutex to be compatible with condition variables. */
2209 pthread_mutex_t mutex
;
2211 uint64_t highest_signaled
;
2212 uint64_t highest_submitted
;
2214 struct list_head points
;
2216 /* Keep free points on hand so we do not have to recreate syncobjs all
2218 struct list_head free_points
;
2220 /* Submissions that are deferred waiting for a specific value to be
2222 struct list_head waiters
;
2225 struct radv_semaphore_part
{
2226 radv_semaphore_kind kind
;
2229 struct radeon_winsys_sem
*ws_sem
;
2230 struct radv_timeline timeline
;
2234 struct radv_semaphore
{
2235 struct radv_semaphore_part permanent
;
2236 struct radv_semaphore_part temporary
;
2239 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2240 VkPipelineBindPoint bind_point
,
2241 struct radv_descriptor_set
*set
,
2245 radv_update_descriptor_sets(struct radv_device
*device
,
2246 struct radv_cmd_buffer
*cmd_buffer
,
2247 VkDescriptorSet overrideSet
,
2248 uint32_t descriptorWriteCount
,
2249 const VkWriteDescriptorSet
*pDescriptorWrites
,
2250 uint32_t descriptorCopyCount
,
2251 const VkCopyDescriptorSet
*pDescriptorCopies
);
2254 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2255 struct radv_cmd_buffer
*cmd_buffer
,
2256 struct radv_descriptor_set
*set
,
2257 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2260 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2261 VkPipelineBindPoint pipelineBindPoint
,
2262 VkPipelineLayout _layout
,
2264 uint32_t descriptorWriteCount
,
2265 const VkWriteDescriptorSet
*pDescriptorWrites
);
2267 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2268 struct radv_image
*image
,
2269 const VkImageSubresourceRange
*range
, uint32_t value
);
2271 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2272 struct radv_image
*image
,
2273 const VkImageSubresourceRange
*range
);
2276 struct radeon_winsys_fence
*fence
;
2277 struct wsi_fence
*fence_wsi
;
2280 uint32_t temp_syncobj
;
2283 /* radv_nir_to_llvm.c */
2284 struct radv_shader_info
;
2285 struct radv_nir_compiler_options
;
2287 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2288 struct nir_shader
*geom_shader
,
2289 struct radv_shader_binary
**rbinary
,
2290 struct radv_shader_info
*info
,
2291 const struct radv_nir_compiler_options
*option
);
2293 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2294 struct radv_shader_binary
**rbinary
,
2295 struct radv_shader_info
*info
,
2296 struct nir_shader
*const *nir
,
2298 const struct radv_nir_compiler_options
*options
);
2300 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2301 gl_shader_stage stage
,
2302 const struct nir_shader
*nir
);
2304 /* radv_shader_info.h */
2305 struct radv_shader_info
;
2306 struct radv_shader_variant_key
;
2308 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2309 const struct radv_pipeline_layout
*layout
,
2310 const struct radv_shader_variant_key
*key
,
2311 struct radv_shader_info
*info
);
2313 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2315 struct radeon_winsys_sem
;
2317 uint64_t radv_get_current_time(void);
2319 static inline uint32_t
2320 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2323 case 0: /* GL_POINTS */
2325 case 1: /* GL_LINES */
2326 case 3: /* GL_LINE_STRIP */
2328 case 4: /* GL_TRIANGLES */
2329 case 5: /* GL_TRIANGLE_STRIP */
2331 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2333 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2335 case 7: /* GL_QUADS */
2336 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2343 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2345 static inline struct __radv_type * \
2346 __radv_type ## _from_handle(__VkType _handle) \
2348 return (struct __radv_type *) _handle; \
2351 static inline __VkType \
2352 __radv_type ## _to_handle(struct __radv_type *_obj) \
2354 return (__VkType) _obj; \
2357 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2359 static inline struct __radv_type * \
2360 __radv_type ## _from_handle(__VkType _handle) \
2362 return (struct __radv_type *)(uintptr_t) _handle; \
2365 static inline __VkType \
2366 __radv_type ## _to_handle(struct __radv_type *_obj) \
2368 return (__VkType)(uintptr_t) _obj; \
2371 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2372 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2374 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2375 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2376 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2377 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2378 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2380 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2381 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2382 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2383 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2384 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2385 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2386 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2387 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2388 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2389 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2390 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2391 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2392 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2393 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2394 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2395 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2396 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2397 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2398 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2399 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2400 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2401 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2403 #endif /* RADV_PRIVATE_H */