2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_constants.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
67 /* Pre-declarations needed for WSI entrypoints */
70 typedef struct xcb_connection_t xcb_connection_t
;
71 typedef uint32_t xcb_visualid_t
;
72 typedef uint32_t xcb_window_t
;
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vulkan_android.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
80 #include "radv_entrypoints.h"
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
85 /* Helper to determine if we should compile
86 * any of the Android AHB support.
88 * To actually enable the ext we also need
89 * the necessary kernel support.
91 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
92 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
99 unsigned img_format
:9;
101 /* Various formats are only supported with workarounds for vertex fetch,
102 * and some 32_32_32 formats are supported natively, but only for buffers
103 * (possibly with some image support, actually, but no filtering). */
107 #include "gfx10_format_table.h"
109 enum radv_secure_compile_type
{
110 RADV_SC_TYPE_INIT_SUCCESS
,
111 RADV_SC_TYPE_INIT_FAILURE
,
112 RADV_SC_TYPE_COMPILE_PIPELINE
,
113 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
114 RADV_SC_TYPE_READ_DISK_CACHE
,
115 RADV_SC_TYPE_WRITE_DISK_CACHE
,
116 RADV_SC_TYPE_FORK_DEVICE
,
117 RADV_SC_TYPE_DESTROY_DEVICE
,
121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
123 static inline uint32_t
124 align_u32(uint32_t v
, uint32_t a
)
126 assert(a
!= 0 && a
== (a
& -a
));
127 return (v
+ a
- 1) & ~(a
- 1);
130 static inline uint32_t
131 align_u32_npot(uint32_t v
, uint32_t a
)
133 return (v
+ a
- 1) / a
* a
;
136 static inline uint64_t
137 align_u64(uint64_t v
, uint64_t a
)
139 assert(a
!= 0 && a
== (a
& -a
));
140 return (v
+ a
- 1) & ~(a
- 1);
143 static inline int32_t
144 align_i32(int32_t v
, int32_t a
)
146 assert(a
!= 0 && a
== (a
& -a
));
147 return (v
+ a
- 1) & ~(a
- 1);
150 /** Alignment must be a power of 2. */
152 radv_is_aligned(uintmax_t n
, uintmax_t a
)
154 assert(a
== (a
& -a
));
155 return (n
& (a
- 1)) == 0;
158 static inline uint32_t
159 round_up_u32(uint32_t v
, uint32_t a
)
161 return (v
+ a
- 1) / a
;
164 static inline uint64_t
165 round_up_u64(uint64_t v
, uint64_t a
)
167 return (v
+ a
- 1) / a
;
170 static inline uint32_t
171 radv_minify(uint32_t n
, uint32_t levels
)
173 if (unlikely(n
== 0))
176 return MAX2(n
>> levels
, 1);
179 radv_clamp_f(float f
, float min
, float max
)
192 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
194 if (*inout_mask
& clear_mask
) {
195 *inout_mask
&= ~clear_mask
;
202 #define for_each_bit(b, dword) \
203 for (uint32_t __dword = (dword); \
204 (b) = __builtin_ffs(__dword) - 1, __dword; \
205 __dword &= ~(1 << (b)))
207 #define typed_memcpy(dest, src, count) ({ \
208 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
209 memcpy((dest), (src), (count) * sizeof(*(src))); \
212 /* Whenever we generate an error, pass it through this function. Useful for
213 * debugging, where we can break on it. Only call at error site, not when
214 * propagating errors. Might be useful to plug in a stack trace here.
217 struct radv_image_view
;
218 struct radv_instance
;
220 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
222 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
223 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
225 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
226 radv_printflike(3, 4);
227 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
228 void radv_loge_v(const char *format
, va_list va
);
229 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
230 void radv_logi_v(const char *format
, va_list va
);
233 * Print a FINISHME message, including its source location.
235 #define radv_finishme(format, ...) \
237 static bool reported = false; \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 /* A non-fatal assert. Useful for debugging. */
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 #define radv_assert(x) do {} while(0)
254 #define stub_return(v) \
256 radv_finishme("stub %s", __func__); \
262 radv_finishme("stub %s", __func__); \
266 int radv_get_instance_entrypoint_index(const char *name
);
267 int radv_get_device_entrypoint_index(const char *name
);
268 int radv_get_physical_device_entrypoint_index(const char *name
);
270 const char *radv_get_instance_entry_name(int index
);
271 const char *radv_get_physical_device_entry_name(int index
);
272 const char *radv_get_device_entry_name(int index
);
274 bool radv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
275 const struct radv_instance_extension_table
*instance
);
276 bool radv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
277 const struct radv_instance_extension_table
*instance
);
278 bool radv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
279 const struct radv_instance_extension_table
*instance
,
280 const struct radv_device_extension_table
*device
);
282 void *radv_lookup_entrypoint(const char *name
);
284 struct radv_physical_device
{
285 VK_LOADER_DATA _loader_data
;
287 struct radv_instance
* instance
;
289 struct radeon_winsys
*ws
;
290 struct radeon_info rad_info
;
291 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
292 uint8_t driver_uuid
[VK_UUID_SIZE
];
293 uint8_t device_uuid
[VK_UUID_SIZE
];
294 uint8_t cache_uuid
[VK_UUID_SIZE
];
298 struct wsi_device wsi_device
;
300 bool out_of_order_rast_allowed
;
302 /* Whether DCC should be enabled for MSAA textures. */
303 bool dcc_msaa_allowed
;
305 /* Whether to enable the AMD_shader_ballot extension */
306 bool use_shader_ballot
;
308 /* Whether to enable NGG. */
311 /* Whether to enable NGG GS. */
314 /* Whether to enable NGG streamout. */
315 bool use_ngg_streamout
;
317 /* Number of threads per wave. */
318 uint8_t ps_wave_size
;
319 uint8_t cs_wave_size
;
320 uint8_t ge_wave_size
;
322 /* Whether to use the experimental compiler backend */
325 /* This is the drivers on-disk cache used as a fallback as opposed to
326 * the pipeline cache defined by apps.
328 struct disk_cache
* disk_cache
;
330 VkPhysicalDeviceMemoryProperties memory_properties
;
331 enum radeon_bo_domain memory_domains
[VK_MAX_MEMORY_TYPES
];
332 enum radeon_bo_flag memory_flags
[VK_MAX_MEMORY_TYPES
];
334 drmPciBusInfo bus_info
;
336 struct radv_device_extension_table supported_extensions
;
339 struct radv_instance
{
340 VK_LOADER_DATA _loader_data
;
342 VkAllocationCallbacks alloc
;
345 int physicalDeviceCount
;
346 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
349 uint32_t engineVersion
;
351 uint64_t debug_flags
;
352 uint64_t perftest_flags
;
353 uint8_t num_sc_threads
;
355 struct vk_debug_report_instance debug_report_callbacks
;
357 struct radv_instance_extension_table enabled_extensions
;
358 struct radv_instance_dispatch_table dispatch
;
359 struct radv_physical_device_dispatch_table physical_device_dispatch
;
360 struct radv_device_dispatch_table device_dispatch
;
362 struct driOptionCache dri_options
;
363 struct driOptionCache available_dri_options
;
367 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
369 return instance
->num_sc_threads
;
372 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
373 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
375 bool radv_instance_extension_supported(const char *name
);
376 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
377 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
382 struct radv_pipeline_cache
{
383 struct radv_device
* device
;
384 pthread_mutex_t mutex
;
388 uint32_t kernel_count
;
389 struct cache_entry
** hash_table
;
392 VkAllocationCallbacks alloc
;
395 struct radv_pipeline_key
{
396 uint32_t instance_rate_inputs
;
397 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
398 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
399 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
400 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
401 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
402 uint64_t vertex_alpha_adjust
;
403 uint32_t vertex_post_shuffle
;
404 unsigned tess_input_vertices
;
408 uint8_t log2_ps_iter_samples
;
410 uint32_t has_multiview_view_index
: 1;
411 uint32_t optimisations_disabled
: 1;
414 /* Non-zero if a required subgroup size is specified via
415 * VK_EXT_subgroup_size_control.
417 uint8_t compute_subgroup_size
;
420 struct radv_shader_binary
;
421 struct radv_shader_variant
;
424 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
425 struct radv_device
*device
);
427 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
429 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
430 const void *data
, size_t size
);
433 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
434 struct radv_pipeline_cache
*cache
,
435 const unsigned char *sha1
,
436 struct radv_shader_variant
**variants
,
437 bool *found_in_application_cache
);
440 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
441 struct radv_pipeline_cache
*cache
,
442 const unsigned char *sha1
,
443 struct radv_shader_variant
**variants
,
444 struct radv_shader_binary
*const *binaries
);
446 enum radv_blit_ds_layout
{
447 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
448 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
449 RADV_BLIT_DS_LAYOUT_COUNT
,
452 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
454 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
457 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
459 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
462 enum radv_meta_dst_layout
{
463 RADV_META_DST_LAYOUT_GENERAL
,
464 RADV_META_DST_LAYOUT_OPTIMAL
,
465 RADV_META_DST_LAYOUT_COUNT
,
468 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
470 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
473 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
475 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
478 struct radv_meta_state
{
479 VkAllocationCallbacks alloc
;
481 struct radv_pipeline_cache cache
;
484 * For on-demand pipeline creation, makes sure that
485 * only one thread tries to build a pipeline at the same time.
490 * Use array element `i` for images with `2^i` samples.
493 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
494 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
496 VkRenderPass depthstencil_rp
;
497 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
498 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
499 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
501 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
502 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
503 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
504 } clear
[MAX_SAMPLES_LOG2
];
506 VkPipelineLayout clear_color_p_layout
;
507 VkPipelineLayout clear_depth_p_layout
;
508 VkPipelineLayout clear_depth_unrestricted_p_layout
;
510 /* Optimized compute fast HTILE clear for stencil or depth only. */
511 VkPipeline clear_htile_mask_pipeline
;
512 VkPipelineLayout clear_htile_mask_p_layout
;
513 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
516 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
518 /** Pipeline that blits from a 1D image. */
519 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
521 /** Pipeline that blits from a 2D image. */
522 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
524 /** Pipeline that blits from a 3D image. */
525 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
527 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
528 VkPipeline depth_only_1d_pipeline
;
529 VkPipeline depth_only_2d_pipeline
;
530 VkPipeline depth_only_3d_pipeline
;
532 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
533 VkPipeline stencil_only_1d_pipeline
;
534 VkPipeline stencil_only_2d_pipeline
;
535 VkPipeline stencil_only_3d_pipeline
;
536 VkPipelineLayout pipeline_layout
;
537 VkDescriptorSetLayout ds_layout
;
541 VkPipelineLayout p_layouts
[5];
542 VkDescriptorSetLayout ds_layouts
[5];
543 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
545 VkPipeline depth_only_pipeline
[5];
547 VkPipeline stencil_only_pipeline
[5];
548 } blit2d
[MAX_SAMPLES_LOG2
];
550 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
551 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
552 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
555 VkPipelineLayout img_p_layout
;
556 VkDescriptorSetLayout img_ds_layout
;
558 VkPipeline pipeline_3d
;
561 VkPipelineLayout img_p_layout
;
562 VkDescriptorSetLayout img_ds_layout
;
564 VkPipeline pipeline_3d
;
567 VkPipelineLayout img_p_layout
;
568 VkDescriptorSetLayout img_ds_layout
;
572 VkPipelineLayout img_p_layout
;
573 VkDescriptorSetLayout img_ds_layout
;
575 VkPipeline pipeline_3d
;
578 VkPipelineLayout img_p_layout
;
579 VkDescriptorSetLayout img_ds_layout
;
583 VkPipelineLayout img_p_layout
;
584 VkDescriptorSetLayout img_ds_layout
;
586 VkPipeline pipeline_3d
;
589 VkPipelineLayout img_p_layout
;
590 VkDescriptorSetLayout img_ds_layout
;
595 VkPipelineLayout p_layout
;
596 VkPipeline pipeline
[NUM_META_FS_KEYS
];
597 VkRenderPass pass
[NUM_META_FS_KEYS
];
601 VkDescriptorSetLayout ds_layout
;
602 VkPipelineLayout p_layout
;
605 VkPipeline i_pipeline
;
606 VkPipeline srgb_pipeline
;
607 } rc
[MAX_SAMPLES_LOG2
];
609 VkPipeline depth_zero_pipeline
;
611 VkPipeline average_pipeline
;
612 VkPipeline max_pipeline
;
613 VkPipeline min_pipeline
;
614 } depth
[MAX_SAMPLES_LOG2
];
616 VkPipeline stencil_zero_pipeline
;
618 VkPipeline max_pipeline
;
619 VkPipeline min_pipeline
;
620 } stencil
[MAX_SAMPLES_LOG2
];
624 VkDescriptorSetLayout ds_layout
;
625 VkPipelineLayout p_layout
;
628 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
629 VkPipeline pipeline
[NUM_META_FS_KEYS
];
630 } rc
[MAX_SAMPLES_LOG2
];
632 VkRenderPass depth_render_pass
;
633 VkPipeline depth_zero_pipeline
;
635 VkPipeline average_pipeline
;
636 VkPipeline max_pipeline
;
637 VkPipeline min_pipeline
;
638 } depth
[MAX_SAMPLES_LOG2
];
640 VkRenderPass stencil_render_pass
;
641 VkPipeline stencil_zero_pipeline
;
643 VkPipeline max_pipeline
;
644 VkPipeline min_pipeline
;
645 } stencil
[MAX_SAMPLES_LOG2
];
649 VkPipelineLayout p_layout
;
650 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
651 VkPipeline resummarize_pipeline
;
653 } depth_decomp
[MAX_SAMPLES_LOG2
];
656 VkPipelineLayout p_layout
;
657 VkPipeline cmask_eliminate_pipeline
;
658 VkPipeline fmask_decompress_pipeline
;
659 VkPipeline dcc_decompress_pipeline
;
662 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
663 VkPipelineLayout dcc_decompress_compute_p_layout
;
664 VkPipeline dcc_decompress_compute_pipeline
;
668 VkPipelineLayout fill_p_layout
;
669 VkPipelineLayout copy_p_layout
;
670 VkDescriptorSetLayout fill_ds_layout
;
671 VkDescriptorSetLayout copy_ds_layout
;
672 VkPipeline fill_pipeline
;
673 VkPipeline copy_pipeline
;
677 VkDescriptorSetLayout ds_layout
;
678 VkPipelineLayout p_layout
;
679 VkPipeline occlusion_query_pipeline
;
680 VkPipeline pipeline_statistics_query_pipeline
;
681 VkPipeline tfb_query_pipeline
;
682 VkPipeline timestamp_query_pipeline
;
686 VkDescriptorSetLayout ds_layout
;
687 VkPipelineLayout p_layout
;
688 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
693 #define RADV_QUEUE_GENERAL 0
694 #define RADV_QUEUE_COMPUTE 1
695 #define RADV_QUEUE_TRANSFER 2
697 #define RADV_MAX_QUEUE_FAMILIES 3
699 enum ring_type
radv_queue_family_to_ring(int f
);
702 VK_LOADER_DATA _loader_data
;
703 struct radv_device
* device
;
704 struct radeon_winsys_ctx
*hw_ctx
;
705 enum radeon_ctx_priority priority
;
706 uint32_t queue_family_index
;
708 VkDeviceQueueCreateFlags flags
;
710 uint32_t scratch_size_per_wave
;
711 uint32_t scratch_waves
;
712 uint32_t compute_scratch_size_per_wave
;
713 uint32_t compute_scratch_waves
;
714 uint32_t esgs_ring_size
;
715 uint32_t gsvs_ring_size
;
719 bool has_sample_positions
;
721 struct radeon_winsys_bo
*scratch_bo
;
722 struct radeon_winsys_bo
*descriptor_bo
;
723 struct radeon_winsys_bo
*compute_scratch_bo
;
724 struct radeon_winsys_bo
*esgs_ring_bo
;
725 struct radeon_winsys_bo
*gsvs_ring_bo
;
726 struct radeon_winsys_bo
*tess_rings_bo
;
727 struct radeon_winsys_bo
*gds_bo
;
728 struct radeon_winsys_bo
*gds_oa_bo
;
729 struct radeon_cmdbuf
*initial_preamble_cs
;
730 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
731 struct radeon_cmdbuf
*continue_preamble_cs
;
733 struct list_head pending_submissions
;
734 pthread_mutex_t pending_mutex
;
737 struct radv_bo_list
{
738 struct radv_winsys_bo_list list
;
740 pthread_mutex_t mutex
;
743 VkResult
radv_bo_list_add(struct radv_device
*device
,
744 struct radeon_winsys_bo
*bo
);
745 void radv_bo_list_remove(struct radv_device
*device
,
746 struct radeon_winsys_bo
*bo
);
748 struct radv_secure_compile_process
{
749 /* Secure process file descriptors. Used to communicate between the
750 * user facing device and the idle forked device used to fork a clean
751 * process for each new pipeline compile.
754 int fd_secure_output
;
756 /* FIFO file descriptors used to communicate between the user facing
757 * device and the secure process that does the actual secure compile.
762 /* Secure compile process id */
765 /* Is the secure compile process currently in use by a thread */
769 struct radv_secure_compile_state
{
770 struct radv_secure_compile_process
*secure_compile_processes
;
771 uint32_t secure_compile_thread_counter
;
772 mtx_t secure_compile_mutex
;
774 /* Unique process ID used to build name for FIFO file descriptor */
779 VK_LOADER_DATA _loader_data
;
781 VkAllocationCallbacks alloc
;
783 struct radv_instance
* instance
;
784 struct radeon_winsys
*ws
;
786 struct radv_meta_state meta_state
;
788 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
789 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
790 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
792 bool always_use_syncobj
;
795 uint32_t tess_offchip_block_dw_size
;
796 uint32_t scratch_waves
;
797 uint32_t dispatch_initiator
;
799 uint32_t gs_table_depth
;
801 /* MSAA sample locations.
802 * The first index is the sample index.
803 * The second index is the coordinate: X, Y. */
804 float sample_locations_1x
[1][2];
805 float sample_locations_2x
[2][2];
806 float sample_locations_4x
[4][2];
807 float sample_locations_8x
[8][2];
810 uint32_t gfx_init_size_dw
;
811 struct radeon_winsys_bo
*gfx_init
;
813 struct radeon_winsys_bo
*trace_bo
;
814 uint32_t *trace_id_ptr
;
816 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
817 bool keep_shader_info
;
819 struct radv_physical_device
*physical_device
;
821 /* Backup in-memory cache to be used if the app doesn't provide one */
822 struct radv_pipeline_cache
* mem_cache
;
825 * use different counters so MSAA MRTs get consecutive surface indices,
826 * even if MASK is allocated in between.
828 uint32_t image_mrt_offset_counter
;
829 uint32_t fmask_mrt_offset_counter
;
830 struct list_head shader_slabs
;
831 mtx_t shader_slab_mutex
;
833 /* For detecting VM faults reported by dmesg. */
834 uint64_t dmesg_timestamp
;
836 struct radv_device_extension_table enabled_extensions
;
837 struct radv_device_dispatch_table dispatch
;
839 /* Whether the app has enabled the robustBufferAccess feature. */
840 bool robust_buffer_access
;
842 /* Whether the driver uses a global BO list. */
843 bool use_global_bo_list
;
845 struct radv_bo_list bo_list
;
847 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
850 struct radv_secure_compile_state
*sc_state
;
852 /* Condition variable for legacy timelines, to notify waiters when a
853 * new point gets submitted. */
854 pthread_cond_t timeline_cond
;
857 struct radeon_cmdbuf
*thread_trace_start_cs
[2];
858 struct radeon_cmdbuf
*thread_trace_stop_cs
[2];
859 struct radeon_winsys_bo
*thread_trace_bo
;
860 void *thread_trace_ptr
;
861 uint32_t thread_trace_buffer_size
;
862 int thread_trace_start_frame
;
865 struct radv_device_memory
{
866 struct radeon_winsys_bo
*bo
;
867 /* for dedicated allocations */
868 struct radv_image
*image
;
869 struct radv_buffer
*buffer
;
873 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
874 struct AHardwareBuffer
* android_hardware_buffer
;
879 struct radv_descriptor_range
{
884 struct radv_descriptor_set
{
885 const struct radv_descriptor_set_layout
*layout
;
887 uint32_t buffer_count
;
889 struct radeon_winsys_bo
*bo
;
891 uint32_t *mapped_ptr
;
892 struct radv_descriptor_range
*dynamic_descriptors
;
894 struct radeon_winsys_bo
*descriptors
[0];
897 struct radv_push_descriptor_set
899 struct radv_descriptor_set set
;
903 struct radv_descriptor_pool_entry
{
906 struct radv_descriptor_set
*set
;
909 struct radv_descriptor_pool
{
910 struct radeon_winsys_bo
*bo
;
912 uint64_t current_offset
;
915 uint8_t *host_memory_base
;
916 uint8_t *host_memory_ptr
;
917 uint8_t *host_memory_end
;
919 uint32_t entry_count
;
920 uint32_t max_entry_count
;
921 struct radv_descriptor_pool_entry entries
[0];
924 struct radv_descriptor_update_template_entry
{
925 VkDescriptorType descriptor_type
;
927 /* The number of descriptors to update */
928 uint32_t descriptor_count
;
930 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
933 /* In dwords. Not valid/used for dynamic descriptors */
936 uint32_t buffer_offset
;
938 /* Only valid for combined image samplers and samplers */
940 uint8_t sampler_offset
;
946 /* For push descriptors */
947 const uint32_t *immutable_samplers
;
950 struct radv_descriptor_update_template
{
951 uint32_t entry_count
;
952 VkPipelineBindPoint bind_point
;
953 struct radv_descriptor_update_template_entry entry
[0];
959 VkBufferUsageFlags usage
;
960 VkBufferCreateFlags flags
;
963 struct radeon_winsys_bo
* bo
;
969 enum radv_dynamic_state_bits
{
970 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
971 RADV_DYNAMIC_SCISSOR
= 1 << 1,
972 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
973 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
974 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
975 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
976 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
977 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
978 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
979 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
980 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
981 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
982 RADV_DYNAMIC_ALL
= (1 << 12) - 1,
985 enum radv_cmd_dirty_bits
{
986 /* Keep the dynamic state dirty bits in sync with
987 * enum radv_dynamic_state_bits */
988 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
989 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
990 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
991 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
992 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
993 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
994 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
995 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
996 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
997 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
998 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
999 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
1000 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 12) - 1,
1001 RADV_CMD_DIRTY_PIPELINE
= 1 << 12,
1002 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 13,
1003 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 14,
1004 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 15,
1005 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 16,
1008 enum radv_cmd_flush_bits
{
1009 /* Instruction cache. */
1010 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1011 /* Scalar L1 cache. */
1012 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1013 /* Vector L1 cache. */
1014 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1015 /* L2 cache + L2 metadata cache writeback & invalidate.
1016 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1017 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1018 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1019 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1020 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1021 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1022 /* Framebuffer caches */
1023 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1024 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1025 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1026 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1027 /* Engine synchronization. */
1028 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1029 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1030 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1031 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1032 /* Pipeline query controls. */
1033 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1034 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1035 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1037 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1038 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1039 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1040 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1043 struct radv_vertex_binding
{
1044 struct radv_buffer
* buffer
;
1045 VkDeviceSize offset
;
1048 struct radv_streamout_binding
{
1049 struct radv_buffer
*buffer
;
1050 VkDeviceSize offset
;
1054 struct radv_streamout_state
{
1055 /* Mask of bound streamout buffers. */
1056 uint8_t enabled_mask
;
1058 /* External state that comes from the last vertex stage, it must be
1059 * set explicitely when binding a new graphics pipeline.
1061 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1062 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1064 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1065 uint32_t hw_enabled_mask
;
1067 /* State of VGT_STRMOUT_(CONFIG|EN) */
1068 bool streamout_enabled
;
1071 struct radv_viewport_state
{
1073 VkViewport viewports
[MAX_VIEWPORTS
];
1076 struct radv_scissor_state
{
1078 VkRect2D scissors
[MAX_SCISSORS
];
1081 struct radv_discard_rectangle_state
{
1083 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1086 struct radv_sample_locations_state
{
1087 VkSampleCountFlagBits per_pixel
;
1088 VkExtent2D grid_size
;
1090 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1093 struct radv_dynamic_state
{
1095 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1096 * Defines the set of saved dynamic state.
1100 struct radv_viewport_state viewport
;
1102 struct radv_scissor_state scissor
;
1112 float blend_constants
[4];
1122 } stencil_compare_mask
;
1127 } stencil_write_mask
;
1132 } stencil_reference
;
1134 struct radv_discard_rectangle_state discard_rectangle
;
1136 struct radv_sample_locations_state sample_location
;
1144 extern const struct radv_dynamic_state default_dynamic_state
;
1147 radv_get_debug_option_name(int id
);
1150 radv_get_perftest_option_name(int id
);
1152 struct radv_color_buffer_info
{
1153 uint64_t cb_color_base
;
1154 uint64_t cb_color_cmask
;
1155 uint64_t cb_color_fmask
;
1156 uint64_t cb_dcc_base
;
1157 uint32_t cb_color_slice
;
1158 uint32_t cb_color_view
;
1159 uint32_t cb_color_info
;
1160 uint32_t cb_color_attrib
;
1161 uint32_t cb_color_attrib2
; /* GFX9 and later */
1162 uint32_t cb_color_attrib3
; /* GFX10 and later */
1163 uint32_t cb_dcc_control
;
1164 uint32_t cb_color_cmask_slice
;
1165 uint32_t cb_color_fmask_slice
;
1167 uint32_t cb_color_pitch
; // GFX6-GFX8
1168 uint32_t cb_mrt_epitch
; // GFX9+
1172 struct radv_ds_buffer_info
{
1173 uint64_t db_z_read_base
;
1174 uint64_t db_stencil_read_base
;
1175 uint64_t db_z_write_base
;
1176 uint64_t db_stencil_write_base
;
1177 uint64_t db_htile_data_base
;
1178 uint32_t db_depth_info
;
1180 uint32_t db_stencil_info
;
1181 uint32_t db_depth_view
;
1182 uint32_t db_depth_size
;
1183 uint32_t db_depth_slice
;
1184 uint32_t db_htile_surface
;
1185 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1186 uint32_t db_z_info2
; /* GFX9 only */
1187 uint32_t db_stencil_info2
; /* GFX9 only */
1192 radv_initialise_color_surface(struct radv_device
*device
,
1193 struct radv_color_buffer_info
*cb
,
1194 struct radv_image_view
*iview
);
1196 radv_initialise_ds_surface(struct radv_device
*device
,
1197 struct radv_ds_buffer_info
*ds
,
1198 struct radv_image_view
*iview
);
1201 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1204 * Attachment state when recording a renderpass instance.
1206 * The clear value is valid only if there exists a pending clear.
1208 struct radv_attachment_state
{
1209 VkImageAspectFlags pending_clear_aspects
;
1210 uint32_t cleared_views
;
1211 VkClearValue clear_value
;
1212 VkImageLayout current_layout
;
1213 VkImageLayout current_stencil_layout
;
1214 bool current_in_render_loop
;
1215 struct radv_sample_locations_state sample_location
;
1218 struct radv_color_buffer_info cb
;
1219 struct radv_ds_buffer_info ds
;
1221 struct radv_image_view
*iview
;
1224 struct radv_descriptor_state
{
1225 struct radv_descriptor_set
*sets
[MAX_SETS
];
1228 struct radv_push_descriptor_set push_set
;
1230 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1233 struct radv_subpass_sample_locs_state
{
1234 uint32_t subpass_idx
;
1235 struct radv_sample_locations_state sample_location
;
1238 struct radv_cmd_state
{
1239 /* Vertex descriptors */
1246 uint32_t prefetch_L2_mask
;
1248 struct radv_pipeline
* pipeline
;
1249 struct radv_pipeline
* emitted_pipeline
;
1250 struct radv_pipeline
* compute_pipeline
;
1251 struct radv_pipeline
* emitted_compute_pipeline
;
1252 struct radv_framebuffer
* framebuffer
;
1253 struct radv_render_pass
* pass
;
1254 const struct radv_subpass
* subpass
;
1255 struct radv_dynamic_state dynamic
;
1256 struct radv_attachment_state
* attachments
;
1257 struct radv_streamout_state streamout
;
1258 VkRect2D render_area
;
1260 uint32_t num_subpass_sample_locs
;
1261 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1264 struct radv_buffer
*index_buffer
;
1265 uint64_t index_offset
;
1266 uint32_t index_type
;
1267 uint32_t max_index_count
;
1269 int32_t last_index_type
;
1271 int32_t last_primitive_reset_en
;
1272 uint32_t last_primitive_reset_index
;
1273 enum radv_cmd_flush_bits flush_bits
;
1274 unsigned active_occlusion_queries
;
1275 bool perfect_occlusion_queries_enabled
;
1276 unsigned active_pipeline_queries
;
1277 unsigned active_pipeline_gds_queries
;
1280 uint32_t last_ia_multi_vgt_param
;
1282 uint32_t last_num_instances
;
1283 uint32_t last_first_instance
;
1284 uint32_t last_vertex_offset
;
1286 uint32_t last_sx_ps_downconvert
;
1287 uint32_t last_sx_blend_opt_epsilon
;
1288 uint32_t last_sx_blend_opt_control
;
1290 /* Whether CP DMA is busy/idle. */
1293 /* Conditional rendering info. */
1294 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1295 uint64_t predication_va
;
1297 /* Inheritance info. */
1298 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1300 bool context_roll_without_scissor_emitted
;
1302 /* SQTT related state. */
1303 uint32_t current_event_type
;
1304 uint32_t num_events
;
1305 uint32_t num_layout_transitions
;
1308 struct radv_cmd_pool
{
1309 VkAllocationCallbacks alloc
;
1310 struct list_head cmd_buffers
;
1311 struct list_head free_cmd_buffers
;
1312 uint32_t queue_family_index
;
1315 struct radv_cmd_buffer_upload
{
1319 struct radeon_winsys_bo
*upload_bo
;
1320 struct list_head list
;
1323 enum radv_cmd_buffer_status
{
1324 RADV_CMD_BUFFER_STATUS_INVALID
,
1325 RADV_CMD_BUFFER_STATUS_INITIAL
,
1326 RADV_CMD_BUFFER_STATUS_RECORDING
,
1327 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1328 RADV_CMD_BUFFER_STATUS_PENDING
,
1331 struct radv_cmd_buffer
{
1332 VK_LOADER_DATA _loader_data
;
1334 struct radv_device
* device
;
1336 struct radv_cmd_pool
* pool
;
1337 struct list_head pool_link
;
1339 VkCommandBufferUsageFlags usage_flags
;
1340 VkCommandBufferLevel level
;
1341 enum radv_cmd_buffer_status status
;
1342 struct radeon_cmdbuf
*cs
;
1343 struct radv_cmd_state state
;
1344 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1345 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1346 uint32_t queue_family_index
;
1348 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1349 VkShaderStageFlags push_constant_stages
;
1350 struct radv_descriptor_set meta_push_descriptors
;
1352 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1354 struct radv_cmd_buffer_upload upload
;
1356 uint32_t scratch_size_per_wave_needed
;
1357 uint32_t scratch_waves_wanted
;
1358 uint32_t compute_scratch_size_per_wave_needed
;
1359 uint32_t compute_scratch_waves_wanted
;
1360 uint32_t esgs_ring_size_needed
;
1361 uint32_t gsvs_ring_size_needed
;
1362 bool tess_rings_needed
;
1363 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1364 bool gds_oa_needed
; /* for GFX10 streamout */
1365 bool sample_positions_needed
;
1367 VkResult record_result
;
1369 uint64_t gfx9_fence_va
;
1370 uint32_t gfx9_fence_idx
;
1371 uint64_t gfx9_eop_bug_va
;
1374 * Whether a query pool has been resetted and we have to flush caches.
1376 bool pending_reset_query
;
1379 * Bitmask of pending active query flushes.
1381 enum radv_cmd_flush_bits active_query_flush_bits
;
1385 struct radv_image_view
;
1387 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1389 void si_emit_graphics(struct radv_device
*device
,
1390 struct radeon_cmdbuf
*cs
);
1391 void si_emit_compute(struct radv_physical_device
*physical_device
,
1392 struct radeon_cmdbuf
*cs
);
1394 void cik_create_gfx_config(struct radv_device
*device
);
1396 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1397 int count
, const VkViewport
*viewports
);
1398 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1399 int count
, const VkRect2D
*scissors
,
1400 const VkViewport
*viewports
, bool can_use_guardband
);
1401 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1402 bool instanced_draw
, bool indirect_draw
,
1403 bool count_from_stream_output
,
1404 uint32_t draw_vertex_count
);
1405 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1406 enum chip_class chip_class
,
1408 unsigned event
, unsigned event_flags
,
1409 unsigned dst_sel
, unsigned data_sel
,
1412 uint64_t gfx9_eop_bug_va
);
1414 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1415 uint32_t ref
, uint32_t mask
);
1416 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1417 enum chip_class chip_class
,
1418 uint32_t *fence_ptr
, uint64_t va
,
1420 enum radv_cmd_flush_bits flush_bits
,
1421 uint64_t gfx9_eop_bug_va
);
1422 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1423 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1424 bool inverted
, uint64_t va
);
1425 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1426 uint64_t src_va
, uint64_t dest_va
,
1428 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1430 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1431 uint64_t size
, unsigned value
);
1432 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1434 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1436 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1439 unsigned *out_offset
,
1442 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1443 const struct radv_subpass
*subpass
);
1445 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1446 unsigned size
, unsigned alignmnet
,
1447 const void *data
, unsigned *out_offset
);
1449 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1450 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1451 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1452 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1453 VkImageAspectFlags aspects
,
1454 VkResolveModeFlagBits resolve_mode
);
1455 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1456 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1457 VkImageAspectFlags aspects
,
1458 VkResolveModeFlagBits resolve_mode
);
1459 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1460 unsigned radv_get_default_max_sample_dist(int log_samples
);
1461 void radv_device_init_msaa(struct radv_device
*device
);
1463 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1464 const struct radv_image_view
*iview
,
1465 VkClearDepthStencilValue ds_clear_value
,
1466 VkImageAspectFlags aspects
);
1468 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1469 const struct radv_image_view
*iview
,
1471 uint32_t color_values
[2]);
1473 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1474 struct radv_image
*image
,
1475 const VkImageSubresourceRange
*range
, bool value
);
1477 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1478 struct radv_image
*image
,
1479 const VkImageSubresourceRange
*range
, bool value
);
1481 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1482 struct radeon_winsys_bo
*bo
,
1483 uint64_t offset
, uint64_t size
, uint32_t value
);
1484 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1485 bool radv_get_memory_fd(struct radv_device
*device
,
1486 struct radv_device_memory
*memory
,
1490 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1491 unsigned sh_offset
, unsigned pointer_count
,
1492 bool use_32bit_pointers
)
1494 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1495 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1499 radv_emit_shader_pointer_body(struct radv_device
*device
,
1500 struct radeon_cmdbuf
*cs
,
1501 uint64_t va
, bool use_32bit_pointers
)
1503 radeon_emit(cs
, va
);
1505 if (use_32bit_pointers
) {
1507 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1509 radeon_emit(cs
, va
>> 32);
1514 radv_emit_shader_pointer(struct radv_device
*device
,
1515 struct radeon_cmdbuf
*cs
,
1516 uint32_t sh_offset
, uint64_t va
, bool global
)
1518 bool use_32bit_pointers
= !global
;
1520 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1521 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1524 static inline struct radv_descriptor_state
*
1525 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1526 VkPipelineBindPoint bind_point
)
1528 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1529 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1530 return &cmd_buffer
->descriptors
[bind_point
];
1534 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1536 * Limitations: Can't call normal dispatch functions without binding or rebinding
1537 * the compute pipeline.
1539 void radv_unaligned_dispatch(
1540 struct radv_cmd_buffer
*cmd_buffer
,
1546 struct radeon_winsys_bo
*bo
;
1550 struct radv_shader_module
;
1552 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1553 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1554 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1555 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1556 #define RADV_HASH_SHADER_ACO (1 << 4)
1559 radv_hash_shaders(unsigned char *hash
,
1560 const VkPipelineShaderStageCreateInfo
**stages
,
1561 const struct radv_pipeline_layout
*layout
,
1562 const struct radv_pipeline_key
*key
,
1565 static inline gl_shader_stage
1566 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1568 assert(__builtin_popcount(vk_stage
) == 1);
1569 return ffs(vk_stage
) - 1;
1572 static inline VkShaderStageFlagBits
1573 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1575 return (1 << mesa_stage
);
1578 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1580 #define radv_foreach_stage(stage, stage_bits) \
1581 for (gl_shader_stage stage, \
1582 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1583 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1584 __tmp &= ~(1 << (stage)))
1586 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1587 unsigned radv_format_meta_fs_key(VkFormat format
);
1589 struct radv_multisample_state
{
1591 uint32_t pa_sc_line_cntl
;
1592 uint32_t pa_sc_mode_cntl_0
;
1593 uint32_t pa_sc_mode_cntl_1
;
1594 uint32_t pa_sc_aa_config
;
1595 uint32_t pa_sc_aa_mask
[2];
1596 unsigned num_samples
;
1599 struct radv_prim_vertex_count
{
1604 struct radv_vertex_elements_info
{
1605 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1608 struct radv_ia_multi_vgt_param_helpers
{
1610 bool partial_es_wave
;
1611 uint8_t primgroup_size
;
1612 bool wd_switch_on_eop
;
1613 bool ia_switch_on_eoi
;
1614 bool partial_vs_wave
;
1617 struct radv_binning_state
{
1618 uint32_t pa_sc_binner_cntl_0
;
1619 uint32_t db_dfsm_control
;
1622 #define SI_GS_PER_ES 128
1624 struct radv_pipeline
{
1625 struct radv_device
* device
;
1626 struct radv_dynamic_state dynamic_state
;
1628 struct radv_pipeline_layout
* layout
;
1630 bool need_indirect_descriptor_sets
;
1631 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1632 struct radv_shader_variant
*gs_copy_shader
;
1633 VkShaderStageFlags active_stages
;
1635 struct radeon_cmdbuf cs
;
1636 uint32_t ctx_cs_hash
;
1637 struct radeon_cmdbuf ctx_cs
;
1639 struct radv_vertex_elements_info vertex_elements
;
1641 uint32_t binding_stride
[MAX_VBS
];
1642 uint8_t num_vertex_bindings
;
1644 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1647 struct radv_multisample_state ms
;
1648 struct radv_binning_state binning
;
1649 uint32_t spi_baryc_cntl
;
1650 bool prim_restart_enable
;
1651 unsigned esgs_ring_size
;
1652 unsigned gsvs_ring_size
;
1653 uint32_t vtx_base_sgpr
;
1654 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1655 uint8_t vtx_emit_num
;
1656 struct radv_prim_vertex_count prim_vertex_count
;
1657 bool can_use_guardband
;
1658 uint32_t needed_dynamic_state
;
1659 bool disable_out_of_order_rast_for_occlusion
;
1662 /* Used for rbplus */
1663 uint32_t col_format
;
1664 uint32_t cb_target_mask
;
1669 unsigned scratch_bytes_per_wave
;
1671 /* Not NULL if graphics pipeline uses streamout. */
1672 struct radv_shader_variant
*streamout_shader
;
1675 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1677 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1680 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1682 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1685 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1687 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1689 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1691 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1692 gl_shader_stage stage
,
1695 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1696 gl_shader_stage stage
);
1698 struct radv_graphics_pipeline_create_info
{
1700 bool db_depth_clear
;
1701 bool db_stencil_clear
;
1702 bool db_depth_disable_expclear
;
1703 bool db_stencil_disable_expclear
;
1704 bool depth_compress_disable
;
1705 bool stencil_compress_disable
;
1706 bool resummarize_enable
;
1707 uint32_t custom_blend_mode
;
1711 radv_graphics_pipeline_create(VkDevice device
,
1712 VkPipelineCache cache
,
1713 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1714 const struct radv_graphics_pipeline_create_info
*extra
,
1715 const VkAllocationCallbacks
*alloc
,
1716 VkPipeline
*pPipeline
);
1718 struct radv_binning_settings
{
1719 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1720 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1721 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1724 struct radv_binning_settings
1725 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1727 struct vk_format_description
;
1728 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1729 int first_non_void
);
1730 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1731 int first_non_void
);
1732 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1733 uint32_t radv_translate_colorformat(VkFormat format
);
1734 uint32_t radv_translate_color_numformat(VkFormat format
,
1735 const struct vk_format_description
*desc
,
1736 int first_non_void
);
1737 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1738 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1739 uint32_t radv_translate_dbformat(VkFormat format
);
1740 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1741 const struct vk_format_description
*desc
,
1742 int first_non_void
);
1743 uint32_t radv_translate_tex_numformat(VkFormat format
,
1744 const struct vk_format_description
*desc
,
1745 int first_non_void
);
1746 bool radv_format_pack_clear_color(VkFormat format
,
1747 uint32_t clear_vals
[2],
1748 VkClearColorValue
*value
);
1749 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1750 bool radv_dcc_formats_compatible(VkFormat format1
,
1752 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1754 struct radv_image_plane
{
1756 struct radeon_surf surface
;
1762 /* The original VkFormat provided by the client. This may not match any
1763 * of the actual surface formats.
1766 VkImageAspectFlags aspects
;
1767 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1768 struct ac_surf_info info
;
1769 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1770 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1775 unsigned queue_family_mask
;
1779 /* Set when bound */
1780 struct radeon_winsys_bo
*bo
;
1781 VkDeviceSize offset
;
1782 uint64_t dcc_offset
;
1783 uint64_t htile_offset
;
1784 bool tc_compatible_htile
;
1785 bool tc_compatible_cmask
;
1787 uint64_t cmask_offset
;
1788 uint64_t fmask_offset
;
1789 uint64_t clear_value_offset
;
1790 uint64_t fce_pred_offset
;
1791 uint64_t dcc_pred_offset
;
1794 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1795 * stored at this offset is UINT_MAX, the driver will emit
1796 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1797 * SET_CONTEXT_REG packet.
1799 uint64_t tc_compat_zrange_offset
;
1801 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1802 VkDeviceMemory owned_memory
;
1804 unsigned plane_count
;
1805 struct radv_image_plane planes
[0];
1808 /* Whether the image has a htile that is known consistent with the contents of
1809 * the image and is allowed to be in compressed form.
1811 * If this is false reads that don't use the htile should be able to return
1814 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1815 VkImageLayout layout
,
1816 bool in_render_loop
,
1817 unsigned queue_mask
);
1819 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1820 VkImageLayout layout
,
1821 bool in_render_loop
,
1822 unsigned queue_mask
);
1824 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1825 const struct radv_image
*image
,
1826 VkImageLayout layout
,
1827 bool in_render_loop
,
1828 unsigned queue_mask
);
1831 * Return whether the image has CMASK metadata for color surfaces.
1834 radv_image_has_cmask(const struct radv_image
*image
)
1836 return image
->cmask_offset
;
1840 * Return whether the image has FMASK metadata for color surfaces.
1843 radv_image_has_fmask(const struct radv_image
*image
)
1845 return image
->fmask_offset
;
1849 * Return whether the image has DCC metadata for color surfaces.
1852 radv_image_has_dcc(const struct radv_image
*image
)
1854 return image
->planes
[0].surface
.dcc_size
;
1858 * Return whether the image is TC-compatible CMASK.
1861 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1863 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1867 * Return whether DCC metadata is enabled for a level.
1870 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1872 return radv_image_has_dcc(image
) &&
1873 level
< image
->planes
[0].surface
.num_dcc_levels
;
1877 * Return whether the image has CB metadata.
1880 radv_image_has_CB_metadata(const struct radv_image
*image
)
1882 return radv_image_has_cmask(image
) ||
1883 radv_image_has_fmask(image
) ||
1884 radv_image_has_dcc(image
);
1888 * Return whether the image has HTILE metadata for depth surfaces.
1891 radv_image_has_htile(const struct radv_image
*image
)
1893 return image
->planes
[0].surface
.htile_size
;
1897 * Return whether HTILE metadata is enabled for a level.
1900 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1902 return radv_image_has_htile(image
) && level
== 0;
1906 * Return whether the image is TC-compatible HTILE.
1909 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1911 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1914 static inline uint64_t
1915 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1916 uint32_t base_level
)
1918 uint64_t va
= radv_buffer_get_va(image
->bo
);
1919 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1923 static inline uint64_t
1924 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1925 uint32_t base_level
)
1927 uint64_t va
= radv_buffer_get_va(image
->bo
);
1928 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1932 static inline uint64_t
1933 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1934 uint32_t base_level
)
1936 uint64_t va
= radv_buffer_get_va(image
->bo
);
1937 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1941 static inline uint64_t
1942 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1943 uint32_t base_level
)
1945 uint64_t va
= radv_buffer_get_va(image
->bo
);
1946 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1950 static inline uint64_t
1951 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1952 uint32_t base_level
)
1954 uint64_t va
= radv_buffer_get_va(image
->bo
);
1955 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1959 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1961 static inline uint32_t
1962 radv_get_layerCount(const struct radv_image
*image
,
1963 const VkImageSubresourceRange
*range
)
1965 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1966 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1969 static inline uint32_t
1970 radv_get_levelCount(const struct radv_image
*image
,
1971 const VkImageSubresourceRange
*range
)
1973 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1974 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1977 struct radeon_bo_metadata
;
1979 radv_init_metadata(struct radv_device
*device
,
1980 struct radv_image
*image
,
1981 struct radeon_bo_metadata
*metadata
);
1984 radv_image_override_offset_stride(struct radv_device
*device
,
1985 struct radv_image
*image
,
1986 uint64_t offset
, uint32_t stride
);
1988 union radv_descriptor
{
1990 uint32_t plane0_descriptor
[8];
1991 uint32_t fmask_descriptor
[8];
1994 uint32_t plane_descriptors
[3][8];
1998 struct radv_image_view
{
1999 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
2000 struct radeon_winsys_bo
*bo
;
2002 VkImageViewType type
;
2003 VkImageAspectFlags aspect_mask
;
2006 bool multiple_planes
;
2007 uint32_t base_layer
;
2008 uint32_t layer_count
;
2010 uint32_t level_count
;
2011 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2013 union radv_descriptor descriptor
;
2015 /* Descriptor for use as a storage image as opposed to a sampled image.
2016 * This has a few differences for cube maps (e.g. type).
2018 union radv_descriptor storage_descriptor
;
2021 struct radv_image_create_info
{
2022 const VkImageCreateInfo
*vk_info
;
2024 bool no_metadata_planes
;
2025 const struct radeon_bo_metadata
*bo_metadata
;
2029 radv_image_create_layout(struct radv_device
*device
,
2030 struct radv_image_create_info create_info
,
2031 struct radv_image
*image
);
2033 VkResult
radv_image_create(VkDevice _device
,
2034 const struct radv_image_create_info
*info
,
2035 const VkAllocationCallbacks
* alloc
,
2038 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2041 radv_image_from_gralloc(VkDevice device_h
,
2042 const VkImageCreateInfo
*base_info
,
2043 const VkNativeBufferANDROID
*gralloc_info
,
2044 const VkAllocationCallbacks
*alloc
,
2045 VkImage
*out_image_h
);
2047 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2048 const VkImageUsageFlags vk_usage
);
2050 radv_import_ahb_memory(struct radv_device
*device
,
2051 struct radv_device_memory
*mem
,
2053 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2055 radv_create_ahb_memory(struct radv_device
*device
,
2056 struct radv_device_memory
*mem
,
2058 const VkMemoryAllocateInfo
*pAllocateInfo
);
2061 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2063 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2065 struct radv_image_view_extra_create_info
{
2066 bool disable_compression
;
2069 void radv_image_view_init(struct radv_image_view
*view
,
2070 struct radv_device
*device
,
2071 const VkImageViewCreateInfo
*pCreateInfo
,
2072 const struct radv_image_view_extra_create_info
* extra_create_info
);
2074 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2076 struct radv_sampler_ycbcr_conversion
{
2078 VkSamplerYcbcrModelConversion ycbcr_model
;
2079 VkSamplerYcbcrRange ycbcr_range
;
2080 VkComponentMapping components
;
2081 VkChromaLocation chroma_offsets
[2];
2082 VkFilter chroma_filter
;
2085 struct radv_buffer_view
{
2086 struct radeon_winsys_bo
*bo
;
2088 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2091 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2092 struct radv_device
*device
,
2093 const VkBufferViewCreateInfo
* pCreateInfo
);
2095 static inline struct VkExtent3D
2096 radv_sanitize_image_extent(const VkImageType imageType
,
2097 const struct VkExtent3D imageExtent
)
2099 switch (imageType
) {
2100 case VK_IMAGE_TYPE_1D
:
2101 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2102 case VK_IMAGE_TYPE_2D
:
2103 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2104 case VK_IMAGE_TYPE_3D
:
2107 unreachable("invalid image type");
2111 static inline struct VkOffset3D
2112 radv_sanitize_image_offset(const VkImageType imageType
,
2113 const struct VkOffset3D imageOffset
)
2115 switch (imageType
) {
2116 case VK_IMAGE_TYPE_1D
:
2117 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2118 case VK_IMAGE_TYPE_2D
:
2119 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2120 case VK_IMAGE_TYPE_3D
:
2123 unreachable("invalid image type");
2128 radv_image_extent_compare(const struct radv_image
*image
,
2129 const VkExtent3D
*extent
)
2131 if (extent
->width
!= image
->info
.width
||
2132 extent
->height
!= image
->info
.height
||
2133 extent
->depth
!= image
->info
.depth
)
2138 struct radv_sampler
{
2140 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2143 struct radv_framebuffer
{
2148 uint32_t attachment_count
;
2149 struct radv_image_view
*attachments
[0];
2152 struct radv_subpass_barrier
{
2153 VkPipelineStageFlags src_stage_mask
;
2154 VkAccessFlags src_access_mask
;
2155 VkAccessFlags dst_access_mask
;
2158 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2159 const struct radv_subpass_barrier
*barrier
);
2161 struct radv_subpass_attachment
{
2162 uint32_t attachment
;
2163 VkImageLayout layout
;
2164 VkImageLayout stencil_layout
;
2165 bool in_render_loop
;
2168 struct radv_subpass
{
2169 uint32_t attachment_count
;
2170 struct radv_subpass_attachment
* attachments
;
2172 uint32_t input_count
;
2173 uint32_t color_count
;
2174 struct radv_subpass_attachment
* input_attachments
;
2175 struct radv_subpass_attachment
* color_attachments
;
2176 struct radv_subpass_attachment
* resolve_attachments
;
2177 struct radv_subpass_attachment
* depth_stencil_attachment
;
2178 struct radv_subpass_attachment
* ds_resolve_attachment
;
2179 VkResolveModeFlagBits depth_resolve_mode
;
2180 VkResolveModeFlagBits stencil_resolve_mode
;
2182 /** Subpass has at least one color resolve attachment */
2183 bool has_color_resolve
;
2185 /** Subpass has at least one color attachment */
2188 struct radv_subpass_barrier start_barrier
;
2192 VkSampleCountFlagBits color_sample_count
;
2193 VkSampleCountFlagBits depth_sample_count
;
2194 VkSampleCountFlagBits max_sample_count
;
2198 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2200 struct radv_render_pass_attachment
{
2203 VkAttachmentLoadOp load_op
;
2204 VkAttachmentLoadOp stencil_load_op
;
2205 VkImageLayout initial_layout
;
2206 VkImageLayout final_layout
;
2207 VkImageLayout stencil_initial_layout
;
2208 VkImageLayout stencil_final_layout
;
2210 /* The subpass id in which the attachment will be used first/last. */
2211 uint32_t first_subpass_idx
;
2212 uint32_t last_subpass_idx
;
2215 struct radv_render_pass
{
2216 uint32_t attachment_count
;
2217 uint32_t subpass_count
;
2218 struct radv_subpass_attachment
* subpass_attachments
;
2219 struct radv_render_pass_attachment
* attachments
;
2220 struct radv_subpass_barrier end_barrier
;
2221 struct radv_subpass subpasses
[0];
2224 VkResult
radv_device_init_meta(struct radv_device
*device
);
2225 void radv_device_finish_meta(struct radv_device
*device
);
2227 struct radv_query_pool
{
2228 struct radeon_winsys_bo
*bo
;
2230 uint32_t availability_offset
;
2234 uint32_t pipeline_stats_mask
;
2238 RADV_SEMAPHORE_NONE
,
2239 RADV_SEMAPHORE_WINSYS
,
2240 RADV_SEMAPHORE_SYNCOBJ
,
2241 RADV_SEMAPHORE_TIMELINE
,
2242 } radv_semaphore_kind
;
2244 struct radv_deferred_queue_submission
;
2246 struct radv_timeline_waiter
{
2247 struct list_head list
;
2248 struct radv_deferred_queue_submission
*submission
;
2252 struct radv_timeline_point
{
2253 struct list_head list
;
2258 /* Separate from the list to accomodate CPU wait being async, as well
2259 * as prevent point deletion during submission. */
2260 unsigned wait_count
;
2263 struct radv_timeline
{
2264 /* Using a pthread mutex to be compatible with condition variables. */
2265 pthread_mutex_t mutex
;
2267 uint64_t highest_signaled
;
2268 uint64_t highest_submitted
;
2270 struct list_head points
;
2272 /* Keep free points on hand so we do not have to recreate syncobjs all
2274 struct list_head free_points
;
2276 /* Submissions that are deferred waiting for a specific value to be
2278 struct list_head waiters
;
2281 struct radv_semaphore_part
{
2282 radv_semaphore_kind kind
;
2285 struct radeon_winsys_sem
*ws_sem
;
2286 struct radv_timeline timeline
;
2290 struct radv_semaphore
{
2291 struct radv_semaphore_part permanent
;
2292 struct radv_semaphore_part temporary
;
2295 bool radv_queue_internal_submit(struct radv_queue
*queue
,
2296 struct radeon_cmdbuf
*cs
);
2298 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2299 VkPipelineBindPoint bind_point
,
2300 struct radv_descriptor_set
*set
,
2304 radv_update_descriptor_sets(struct radv_device
*device
,
2305 struct radv_cmd_buffer
*cmd_buffer
,
2306 VkDescriptorSet overrideSet
,
2307 uint32_t descriptorWriteCount
,
2308 const VkWriteDescriptorSet
*pDescriptorWrites
,
2309 uint32_t descriptorCopyCount
,
2310 const VkCopyDescriptorSet
*pDescriptorCopies
);
2313 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2314 struct radv_cmd_buffer
*cmd_buffer
,
2315 struct radv_descriptor_set
*set
,
2316 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2319 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2320 VkPipelineBindPoint pipelineBindPoint
,
2321 VkPipelineLayout _layout
,
2323 uint32_t descriptorWriteCount
,
2324 const VkWriteDescriptorSet
*pDescriptorWrites
);
2326 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2327 struct radv_image
*image
,
2328 const VkImageSubresourceRange
*range
, uint32_t value
);
2330 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2331 struct radv_image
*image
,
2332 const VkImageSubresourceRange
*range
);
2335 struct radeon_winsys_fence
*fence
;
2336 struct wsi_fence
*fence_wsi
;
2339 uint32_t temp_syncobj
;
2342 /* radv_nir_to_llvm.c */
2343 struct radv_shader_args
;
2345 void llvm_compile_shader(struct radv_device
*device
,
2346 unsigned shader_count
,
2347 struct nir_shader
*const *shaders
,
2348 struct radv_shader_binary
**binary
,
2349 struct radv_shader_args
*args
);
2351 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2352 gl_shader_stage stage
,
2353 const struct nir_shader
*nir
);
2355 /* radv_shader_info.h */
2356 struct radv_shader_info
;
2357 struct radv_shader_variant_key
;
2359 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2360 const struct radv_pipeline_layout
*layout
,
2361 const struct radv_shader_variant_key
*key
,
2362 struct radv_shader_info
*info
);
2364 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2367 struct radv_thread_trace_info
{
2368 uint32_t cur_offset
;
2369 uint32_t trace_status
;
2371 uint32_t gfx9_write_counter
;
2372 uint32_t gfx10_dropped_cntr
;
2376 struct radv_thread_trace_se
{
2377 struct radv_thread_trace_info info
;
2379 uint32_t shader_engine
;
2380 uint32_t compute_unit
;
2383 struct radv_thread_trace
{
2384 uint32_t num_traces
;
2385 struct radv_thread_trace_se traces
[4];
2388 bool radv_thread_trace_init(struct radv_device
*device
);
2389 void radv_thread_trace_finish(struct radv_device
*device
);
2390 bool radv_begin_thread_trace(struct radv_queue
*queue
);
2391 bool radv_end_thread_trace(struct radv_queue
*queue
);
2392 bool radv_get_thread_trace(struct radv_queue
*queue
,
2393 struct radv_thread_trace
*thread_trace
);
2394 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf
*cs
,
2395 const void *data
, uint32_t num_dwords
);
2398 int radv_dump_thread_trace(struct radv_device
*device
,
2399 const struct radv_thread_trace
*trace
);
2401 /* radv_sqtt_layer_.c */
2402 struct radv_barrier_data
{
2405 uint16_t depth_stencil_expand
: 1;
2406 uint16_t htile_hiz_range_expand
: 1;
2407 uint16_t depth_stencil_resummarize
: 1;
2408 uint16_t dcc_decompress
: 1;
2409 uint16_t fmask_decompress
: 1;
2410 uint16_t fast_clear_eliminate
: 1;
2411 uint16_t fmask_color_expand
: 1;
2412 uint16_t init_mask_ram
: 1;
2413 uint16_t reserved
: 8;
2416 } layout_transitions
;
2420 * Value for the reason field of an RGP barrier start marker originating from
2421 * the Vulkan client (does not include PAL-defined values). (Table 15)
2423 enum rgp_barrier_reason
{
2424 RGP_BARRIER_UNKNOWN_REASON
= 0xFFFFFFFF,
2426 /* External app-generated barrier reasons, i.e. API synchronization
2427 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2429 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
= 0x00000001,
2430 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
= 0x00000002,
2431 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
= 0x00000003,
2433 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2434 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2436 RGP_BARRIER_INTERNAL_BASE
= 0xC0000000,
2437 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 0,
2438 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 1,
2439 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL
= RGP_BARRIER_INTERNAL_BASE
+ 2,
2440 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 3
2443 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2444 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2445 void radv_describe_draw(struct radv_cmd_buffer
*cmd_buffer
);
2446 void radv_describe_dispatch(struct radv_cmd_buffer
*cmd_buffer
, int x
, int y
, int z
);
2447 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
,
2448 VkImageAspectFlagBits aspects
);
2449 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
);
2450 void radv_describe_barrier_start(struct radv_cmd_buffer
*cmd_buffer
,
2451 enum rgp_barrier_reason reason
);
2452 void radv_describe_barrier_end(struct radv_cmd_buffer
*cmd_buffer
);
2453 void radv_describe_layout_transition(struct radv_cmd_buffer
*cmd_buffer
,
2454 const struct radv_barrier_data
*barrier
);
2456 struct radeon_winsys_sem
;
2458 uint64_t radv_get_current_time(void);
2460 static inline uint32_t
2461 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2464 case 0: /* GL_POINTS */
2466 case 1: /* GL_LINES */
2467 case 3: /* GL_LINE_STRIP */
2469 case 4: /* GL_TRIANGLES */
2470 case 5: /* GL_TRIANGLE_STRIP */
2472 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2474 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2476 case 7: /* GL_QUADS */
2477 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2484 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
2485 const VkRenderPassBeginInfo
*pRenderPassBegin
);
2486 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
);
2488 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2490 static inline struct __radv_type * \
2491 __radv_type ## _from_handle(__VkType _handle) \
2493 return (struct __radv_type *) _handle; \
2496 static inline __VkType \
2497 __radv_type ## _to_handle(struct __radv_type *_obj) \
2499 return (__VkType) _obj; \
2502 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2504 static inline struct __radv_type * \
2505 __radv_type ## _from_handle(__VkType _handle) \
2507 return (struct __radv_type *)(uintptr_t) _handle; \
2510 static inline __VkType \
2511 __radv_type ## _to_handle(struct __radv_type *_obj) \
2513 return (__VkType)(uintptr_t) _obj; \
2516 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2517 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2519 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2520 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2521 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2522 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2523 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2525 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2526 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2527 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2528 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2529 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2530 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2531 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2532 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2533 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2534 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2535 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2536 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2537 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2538 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2539 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2540 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2541 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2542 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2543 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2544 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2545 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2546 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2548 #endif /* RADV_PRIVATE_H */