2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 /* Pre-declarations needed for WSI entrypoints */
71 typedef struct xcb_connection_t xcb_connection_t
;
72 typedef uint32_t xcb_visualid_t
;
73 typedef uint32_t xcb_window_t
;
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "radv_entrypoints.h"
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
89 * To actually enable the ext we also need
90 * the necessary kernel support.
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
100 unsigned img_format
:9;
102 /* Various formats are only supported with workarounds for vertex fetch,
103 * and some 32_32_32 formats are supported natively, but only for buffers
104 * (possibly with some image support, actually, but no filtering). */
108 #include "gfx10_format_table.h"
110 enum radv_secure_compile_type
{
111 RADV_SC_TYPE_INIT_SUCCESS
,
112 RADV_SC_TYPE_INIT_FAILURE
,
113 RADV_SC_TYPE_COMPILE_PIPELINE
,
114 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
115 RADV_SC_TYPE_READ_DISK_CACHE
,
116 RADV_SC_TYPE_WRITE_DISK_CACHE
,
117 RADV_SC_TYPE_FORK_DEVICE
,
118 RADV_SC_TYPE_DESTROY_DEVICE
,
122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
124 static inline uint32_t
125 align_u32(uint32_t v
, uint32_t a
)
127 assert(a
!= 0 && a
== (a
& -a
));
128 return (v
+ a
- 1) & ~(a
- 1);
131 static inline uint32_t
132 align_u32_npot(uint32_t v
, uint32_t a
)
134 return (v
+ a
- 1) / a
* a
;
137 static inline uint64_t
138 align_u64(uint64_t v
, uint64_t a
)
140 assert(a
!= 0 && a
== (a
& -a
));
141 return (v
+ a
- 1) & ~(a
- 1);
144 static inline int32_t
145 align_i32(int32_t v
, int32_t a
)
147 assert(a
!= 0 && a
== (a
& -a
));
148 return (v
+ a
- 1) & ~(a
- 1);
151 /** Alignment must be a power of 2. */
153 radv_is_aligned(uintmax_t n
, uintmax_t a
)
155 assert(a
== (a
& -a
));
156 return (n
& (a
- 1)) == 0;
159 static inline uint32_t
160 round_up_u32(uint32_t v
, uint32_t a
)
162 return (v
+ a
- 1) / a
;
165 static inline uint64_t
166 round_up_u64(uint64_t v
, uint64_t a
)
168 return (v
+ a
- 1) / a
;
171 static inline uint32_t
172 radv_minify(uint32_t n
, uint32_t levels
)
174 if (unlikely(n
== 0))
177 return MAX2(n
>> levels
, 1);
180 radv_clamp_f(float f
, float min
, float max
)
193 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
195 if (*inout_mask
& clear_mask
) {
196 *inout_mask
&= ~clear_mask
;
203 #define for_each_bit(b, dword) \
204 for (uint32_t __dword = (dword); \
205 (b) = __builtin_ffs(__dword) - 1, __dword; \
206 __dword &= ~(1 << (b)))
208 #define typed_memcpy(dest, src, count) ({ \
209 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
210 memcpy((dest), (src), (count) * sizeof(*(src))); \
213 /* Whenever we generate an error, pass it through this function. Useful for
214 * debugging, where we can break on it. Only call at error site, not when
215 * propagating errors. Might be useful to plug in a stack trace here.
218 struct radv_image_view
;
219 struct radv_instance
;
221 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
223 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
224 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
226 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
227 radv_printflike(3, 4);
228 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
229 void radv_loge_v(const char *format
, va_list va
);
230 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
231 void radv_logi_v(const char *format
, va_list va
);
234 * Print a FINISHME message, including its source location.
236 #define radv_finishme(format, ...) \
238 static bool reported = false; \
240 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
245 /* A non-fatal assert. Useful for debugging. */
247 #define radv_assert(x) ({ \
248 if (unlikely(!(x))) \
249 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
252 #define radv_assert(x) do {} while(0)
255 #define stub_return(v) \
257 radv_finishme("stub %s", __func__); \
263 radv_finishme("stub %s", __func__); \
267 int radv_get_instance_entrypoint_index(const char *name
);
268 int radv_get_device_entrypoint_index(const char *name
);
269 int radv_get_physical_device_entrypoint_index(const char *name
);
271 const char *radv_get_instance_entry_name(int index
);
272 const char *radv_get_physical_device_entry_name(int index
);
273 const char *radv_get_device_entry_name(int index
);
275 bool radv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
276 const struct radv_instance_extension_table
*instance
);
277 bool radv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
278 const struct radv_instance_extension_table
*instance
);
279 bool radv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
280 const struct radv_instance_extension_table
*instance
,
281 const struct radv_device_extension_table
*device
);
283 void *radv_lookup_entrypoint(const char *name
);
285 struct radv_physical_device
{
286 VK_LOADER_DATA _loader_data
;
288 /* Link in radv_instance::physical_devices */
289 struct list_head link
;
291 struct radv_instance
* instance
;
293 struct radeon_winsys
*ws
;
294 struct radeon_info rad_info
;
295 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
296 uint8_t driver_uuid
[VK_UUID_SIZE
];
297 uint8_t device_uuid
[VK_UUID_SIZE
];
298 uint8_t cache_uuid
[VK_UUID_SIZE
];
302 struct wsi_device wsi_device
;
304 bool out_of_order_rast_allowed
;
306 /* Whether DCC should be enabled for MSAA textures. */
307 bool dcc_msaa_allowed
;
309 /* Whether to enable the AMD_shader_ballot extension */
310 bool use_shader_ballot
;
312 /* Whether to enable NGG. */
315 /* Whether to enable NGG GS. */
318 /* Whether to enable NGG streamout. */
319 bool use_ngg_streamout
;
321 /* Number of threads per wave. */
322 uint8_t ps_wave_size
;
323 uint8_t cs_wave_size
;
324 uint8_t ge_wave_size
;
326 /* Whether to use the experimental compiler backend */
329 /* This is the drivers on-disk cache used as a fallback as opposed to
330 * the pipeline cache defined by apps.
332 struct disk_cache
* disk_cache
;
334 VkPhysicalDeviceMemoryProperties memory_properties
;
335 enum radeon_bo_domain memory_domains
[VK_MAX_MEMORY_TYPES
];
336 enum radeon_bo_flag memory_flags
[VK_MAX_MEMORY_TYPES
];
338 drmPciBusInfo bus_info
;
340 struct radv_device_extension_table supported_extensions
;
343 struct radv_instance
{
344 VK_LOADER_DATA _loader_data
;
346 VkAllocationCallbacks alloc
;
351 uint32_t engineVersion
;
353 uint64_t debug_flags
;
354 uint64_t perftest_flags
;
355 uint8_t num_sc_threads
;
357 struct vk_debug_report_instance debug_report_callbacks
;
359 struct radv_instance_extension_table enabled_extensions
;
360 struct radv_instance_dispatch_table dispatch
;
361 struct radv_physical_device_dispatch_table physical_device_dispatch
;
362 struct radv_device_dispatch_table device_dispatch
;
364 bool physical_devices_enumerated
;
365 struct list_head physical_devices
;
367 struct driOptionCache dri_options
;
368 struct driOptionCache available_dri_options
;
372 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
374 return instance
->num_sc_threads
;
377 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
378 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
380 bool radv_instance_extension_supported(const char *name
);
381 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
382 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
387 struct radv_pipeline_cache
{
388 struct radv_device
* device
;
389 pthread_mutex_t mutex
;
393 uint32_t kernel_count
;
394 struct cache_entry
** hash_table
;
397 VkAllocationCallbacks alloc
;
400 struct radv_pipeline_key
{
401 uint32_t instance_rate_inputs
;
402 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
403 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
404 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
405 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
406 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
407 uint64_t vertex_alpha_adjust
;
408 uint32_t vertex_post_shuffle
;
409 unsigned tess_input_vertices
;
413 uint8_t log2_ps_iter_samples
;
415 uint32_t has_multiview_view_index
: 1;
416 uint32_t optimisations_disabled
: 1;
419 /* Non-zero if a required subgroup size is specified via
420 * VK_EXT_subgroup_size_control.
422 uint8_t compute_subgroup_size
;
425 struct radv_shader_binary
;
426 struct radv_shader_variant
;
429 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
430 struct radv_device
*device
);
432 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
434 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
435 const void *data
, size_t size
);
438 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
439 struct radv_pipeline_cache
*cache
,
440 const unsigned char *sha1
,
441 struct radv_shader_variant
**variants
,
442 bool *found_in_application_cache
);
445 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
446 struct radv_pipeline_cache
*cache
,
447 const unsigned char *sha1
,
448 struct radv_shader_variant
**variants
,
449 struct radv_shader_binary
*const *binaries
);
451 enum radv_blit_ds_layout
{
452 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
453 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
454 RADV_BLIT_DS_LAYOUT_COUNT
,
457 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
459 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
462 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
464 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
467 enum radv_meta_dst_layout
{
468 RADV_META_DST_LAYOUT_GENERAL
,
469 RADV_META_DST_LAYOUT_OPTIMAL
,
470 RADV_META_DST_LAYOUT_COUNT
,
473 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
475 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
478 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
480 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
483 struct radv_meta_state
{
484 VkAllocationCallbacks alloc
;
486 struct radv_pipeline_cache cache
;
489 * For on-demand pipeline creation, makes sure that
490 * only one thread tries to build a pipeline at the same time.
495 * Use array element `i` for images with `2^i` samples.
498 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
499 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
501 VkRenderPass depthstencil_rp
;
502 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
503 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
504 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
506 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
507 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
508 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
509 } clear
[MAX_SAMPLES_LOG2
];
511 VkPipelineLayout clear_color_p_layout
;
512 VkPipelineLayout clear_depth_p_layout
;
513 VkPipelineLayout clear_depth_unrestricted_p_layout
;
515 /* Optimized compute fast HTILE clear for stencil or depth only. */
516 VkPipeline clear_htile_mask_pipeline
;
517 VkPipelineLayout clear_htile_mask_p_layout
;
518 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
521 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
523 /** Pipeline that blits from a 1D image. */
524 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
526 /** Pipeline that blits from a 2D image. */
527 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
529 /** Pipeline that blits from a 3D image. */
530 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
532 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
533 VkPipeline depth_only_1d_pipeline
;
534 VkPipeline depth_only_2d_pipeline
;
535 VkPipeline depth_only_3d_pipeline
;
537 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
538 VkPipeline stencil_only_1d_pipeline
;
539 VkPipeline stencil_only_2d_pipeline
;
540 VkPipeline stencil_only_3d_pipeline
;
541 VkPipelineLayout pipeline_layout
;
542 VkDescriptorSetLayout ds_layout
;
546 VkPipelineLayout p_layouts
[5];
547 VkDescriptorSetLayout ds_layouts
[5];
548 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
550 VkPipeline depth_only_pipeline
[5];
552 VkPipeline stencil_only_pipeline
[5];
553 } blit2d
[MAX_SAMPLES_LOG2
];
555 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
556 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
557 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
560 VkPipelineLayout img_p_layout
;
561 VkDescriptorSetLayout img_ds_layout
;
563 VkPipeline pipeline_3d
;
566 VkPipelineLayout img_p_layout
;
567 VkDescriptorSetLayout img_ds_layout
;
569 VkPipeline pipeline_3d
;
572 VkPipelineLayout img_p_layout
;
573 VkDescriptorSetLayout img_ds_layout
;
577 VkPipelineLayout img_p_layout
;
578 VkDescriptorSetLayout img_ds_layout
;
580 VkPipeline pipeline_3d
;
583 VkPipelineLayout img_p_layout
;
584 VkDescriptorSetLayout img_ds_layout
;
588 VkPipelineLayout img_p_layout
;
589 VkDescriptorSetLayout img_ds_layout
;
591 VkPipeline pipeline_3d
;
594 VkPipelineLayout img_p_layout
;
595 VkDescriptorSetLayout img_ds_layout
;
600 VkPipelineLayout p_layout
;
601 VkPipeline pipeline
[NUM_META_FS_KEYS
];
602 VkRenderPass pass
[NUM_META_FS_KEYS
];
606 VkDescriptorSetLayout ds_layout
;
607 VkPipelineLayout p_layout
;
610 VkPipeline i_pipeline
;
611 VkPipeline srgb_pipeline
;
612 } rc
[MAX_SAMPLES_LOG2
];
614 VkPipeline depth_zero_pipeline
;
616 VkPipeline average_pipeline
;
617 VkPipeline max_pipeline
;
618 VkPipeline min_pipeline
;
619 } depth
[MAX_SAMPLES_LOG2
];
621 VkPipeline stencil_zero_pipeline
;
623 VkPipeline max_pipeline
;
624 VkPipeline min_pipeline
;
625 } stencil
[MAX_SAMPLES_LOG2
];
629 VkDescriptorSetLayout ds_layout
;
630 VkPipelineLayout p_layout
;
633 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
634 VkPipeline pipeline
[NUM_META_FS_KEYS
];
635 } rc
[MAX_SAMPLES_LOG2
];
637 VkRenderPass depth_render_pass
;
638 VkPipeline depth_zero_pipeline
;
640 VkPipeline average_pipeline
;
641 VkPipeline max_pipeline
;
642 VkPipeline min_pipeline
;
643 } depth
[MAX_SAMPLES_LOG2
];
645 VkRenderPass stencil_render_pass
;
646 VkPipeline stencil_zero_pipeline
;
648 VkPipeline max_pipeline
;
649 VkPipeline min_pipeline
;
650 } stencil
[MAX_SAMPLES_LOG2
];
654 VkPipelineLayout p_layout
;
655 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
656 VkPipeline resummarize_pipeline
;
658 } depth_decomp
[MAX_SAMPLES_LOG2
];
661 VkPipelineLayout p_layout
;
662 VkPipeline cmask_eliminate_pipeline
;
663 VkPipeline fmask_decompress_pipeline
;
664 VkPipeline dcc_decompress_pipeline
;
667 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
668 VkPipelineLayout dcc_decompress_compute_p_layout
;
669 VkPipeline dcc_decompress_compute_pipeline
;
673 VkPipelineLayout fill_p_layout
;
674 VkPipelineLayout copy_p_layout
;
675 VkDescriptorSetLayout fill_ds_layout
;
676 VkDescriptorSetLayout copy_ds_layout
;
677 VkPipeline fill_pipeline
;
678 VkPipeline copy_pipeline
;
682 VkDescriptorSetLayout ds_layout
;
683 VkPipelineLayout p_layout
;
684 VkPipeline occlusion_query_pipeline
;
685 VkPipeline pipeline_statistics_query_pipeline
;
686 VkPipeline tfb_query_pipeline
;
687 VkPipeline timestamp_query_pipeline
;
691 VkDescriptorSetLayout ds_layout
;
692 VkPipelineLayout p_layout
;
693 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
698 #define RADV_QUEUE_GENERAL 0
699 #define RADV_QUEUE_COMPUTE 1
700 #define RADV_QUEUE_TRANSFER 2
702 #define RADV_MAX_QUEUE_FAMILIES 3
704 enum ring_type
radv_queue_family_to_ring(int f
);
707 VK_LOADER_DATA _loader_data
;
708 struct radv_device
* device
;
709 struct radeon_winsys_ctx
*hw_ctx
;
710 enum radeon_ctx_priority priority
;
711 uint32_t queue_family_index
;
713 VkDeviceQueueCreateFlags flags
;
715 uint32_t scratch_size_per_wave
;
716 uint32_t scratch_waves
;
717 uint32_t compute_scratch_size_per_wave
;
718 uint32_t compute_scratch_waves
;
719 uint32_t esgs_ring_size
;
720 uint32_t gsvs_ring_size
;
724 bool has_sample_positions
;
726 struct radeon_winsys_bo
*scratch_bo
;
727 struct radeon_winsys_bo
*descriptor_bo
;
728 struct radeon_winsys_bo
*compute_scratch_bo
;
729 struct radeon_winsys_bo
*esgs_ring_bo
;
730 struct radeon_winsys_bo
*gsvs_ring_bo
;
731 struct radeon_winsys_bo
*tess_rings_bo
;
732 struct radeon_winsys_bo
*gds_bo
;
733 struct radeon_winsys_bo
*gds_oa_bo
;
734 struct radeon_cmdbuf
*initial_preamble_cs
;
735 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
736 struct radeon_cmdbuf
*continue_preamble_cs
;
738 struct list_head pending_submissions
;
739 pthread_mutex_t pending_mutex
;
742 struct radv_bo_list
{
743 struct radv_winsys_bo_list list
;
745 pthread_mutex_t mutex
;
748 VkResult
radv_bo_list_add(struct radv_device
*device
,
749 struct radeon_winsys_bo
*bo
);
750 void radv_bo_list_remove(struct radv_device
*device
,
751 struct radeon_winsys_bo
*bo
);
753 struct radv_secure_compile_process
{
754 /* Secure process file descriptors. Used to communicate between the
755 * user facing device and the idle forked device used to fork a clean
756 * process for each new pipeline compile.
759 int fd_secure_output
;
761 /* FIFO file descriptors used to communicate between the user facing
762 * device and the secure process that does the actual secure compile.
767 /* Secure compile process id */
770 /* Is the secure compile process currently in use by a thread */
774 struct radv_secure_compile_state
{
775 struct radv_secure_compile_process
*secure_compile_processes
;
776 uint32_t secure_compile_thread_counter
;
777 mtx_t secure_compile_mutex
;
779 /* Unique process ID used to build name for FIFO file descriptor */
786 struct radv_instance
* instance
;
787 struct radeon_winsys
*ws
;
789 struct radv_meta_state meta_state
;
791 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
792 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
793 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
795 bool always_use_syncobj
;
798 uint32_t tess_offchip_block_dw_size
;
799 uint32_t scratch_waves
;
800 uint32_t dispatch_initiator
;
802 uint32_t gs_table_depth
;
804 /* MSAA sample locations.
805 * The first index is the sample index.
806 * The second index is the coordinate: X, Y. */
807 float sample_locations_1x
[1][2];
808 float sample_locations_2x
[2][2];
809 float sample_locations_4x
[4][2];
810 float sample_locations_8x
[8][2];
813 uint32_t gfx_init_size_dw
;
814 struct radeon_winsys_bo
*gfx_init
;
816 struct radeon_winsys_bo
*trace_bo
;
817 uint32_t *trace_id_ptr
;
819 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
820 bool keep_shader_info
;
822 struct radv_physical_device
*physical_device
;
824 /* Backup in-memory cache to be used if the app doesn't provide one */
825 struct radv_pipeline_cache
* mem_cache
;
828 * use different counters so MSAA MRTs get consecutive surface indices,
829 * even if MASK is allocated in between.
831 uint32_t image_mrt_offset_counter
;
832 uint32_t fmask_mrt_offset_counter
;
833 struct list_head shader_slabs
;
834 mtx_t shader_slab_mutex
;
836 /* For detecting VM faults reported by dmesg. */
837 uint64_t dmesg_timestamp
;
839 struct radv_device_extension_table enabled_extensions
;
840 struct radv_device_dispatch_table dispatch
;
842 /* Whether the app has enabled the robustBufferAccess feature. */
843 bool robust_buffer_access
;
845 /* Whether the driver uses a global BO list. */
846 bool use_global_bo_list
;
848 struct radv_bo_list bo_list
;
850 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
853 struct radv_secure_compile_state
*sc_state
;
855 /* Condition variable for legacy timelines, to notify waiters when a
856 * new point gets submitted. */
857 pthread_cond_t timeline_cond
;
860 struct radeon_cmdbuf
*thread_trace_start_cs
[2];
861 struct radeon_cmdbuf
*thread_trace_stop_cs
[2];
862 struct radeon_winsys_bo
*thread_trace_bo
;
863 void *thread_trace_ptr
;
864 uint32_t thread_trace_buffer_size
;
865 int thread_trace_start_frame
;
867 /* Overallocation. */
868 bool overallocation_disallowed
;
869 uint64_t allocated_memory_size
[VK_MAX_MEMORY_HEAPS
];
870 mtx_t overallocation_mutex
;
873 struct radv_device_memory
{
874 struct radeon_winsys_bo
*bo
;
875 /* for dedicated allocations */
876 struct radv_image
*image
;
877 struct radv_buffer
*buffer
;
883 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
884 struct AHardwareBuffer
* android_hardware_buffer
;
889 struct radv_descriptor_range
{
894 struct radv_descriptor_set
{
895 const struct radv_descriptor_set_layout
*layout
;
897 uint32_t buffer_count
;
899 struct radeon_winsys_bo
*bo
;
901 uint32_t *mapped_ptr
;
902 struct radv_descriptor_range
*dynamic_descriptors
;
904 struct radeon_winsys_bo
*descriptors
[0];
907 struct radv_push_descriptor_set
909 struct radv_descriptor_set set
;
913 struct radv_descriptor_pool_entry
{
916 struct radv_descriptor_set
*set
;
919 struct radv_descriptor_pool
{
920 struct radeon_winsys_bo
*bo
;
922 uint64_t current_offset
;
925 uint8_t *host_memory_base
;
926 uint8_t *host_memory_ptr
;
927 uint8_t *host_memory_end
;
929 uint32_t entry_count
;
930 uint32_t max_entry_count
;
931 struct radv_descriptor_pool_entry entries
[0];
934 struct radv_descriptor_update_template_entry
{
935 VkDescriptorType descriptor_type
;
937 /* The number of descriptors to update */
938 uint32_t descriptor_count
;
940 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
943 /* In dwords. Not valid/used for dynamic descriptors */
946 uint32_t buffer_offset
;
948 /* Only valid for combined image samplers and samplers */
950 uint8_t sampler_offset
;
956 /* For push descriptors */
957 const uint32_t *immutable_samplers
;
960 struct radv_descriptor_update_template
{
961 uint32_t entry_count
;
962 VkPipelineBindPoint bind_point
;
963 struct radv_descriptor_update_template_entry entry
[0];
969 VkBufferUsageFlags usage
;
970 VkBufferCreateFlags flags
;
973 struct radeon_winsys_bo
* bo
;
979 enum radv_dynamic_state_bits
{
980 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
981 RADV_DYNAMIC_SCISSOR
= 1 << 1,
982 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
983 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
984 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
985 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
986 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
987 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
988 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
989 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
990 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
991 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
992 RADV_DYNAMIC_ALL
= (1 << 12) - 1,
995 enum radv_cmd_dirty_bits
{
996 /* Keep the dynamic state dirty bits in sync with
997 * enum radv_dynamic_state_bits */
998 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
999 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
1000 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
1001 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
1002 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
1003 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
1004 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
1005 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
1006 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
1007 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
1008 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
1009 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
1010 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 12) - 1,
1011 RADV_CMD_DIRTY_PIPELINE
= 1 << 12,
1012 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 13,
1013 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 14,
1014 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 15,
1015 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 16,
1018 enum radv_cmd_flush_bits
{
1019 /* Instruction cache. */
1020 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1021 /* Scalar L1 cache. */
1022 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1023 /* Vector L1 cache. */
1024 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1025 /* L2 cache + L2 metadata cache writeback & invalidate.
1026 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1027 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1028 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1029 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1030 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1031 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1032 /* Framebuffer caches */
1033 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1034 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1035 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1036 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1037 /* Engine synchronization. */
1038 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1039 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1040 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1041 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1042 /* Pipeline query controls. */
1043 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1044 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1045 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1047 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1048 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1049 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1050 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1053 struct radv_vertex_binding
{
1054 struct radv_buffer
* buffer
;
1055 VkDeviceSize offset
;
1058 struct radv_streamout_binding
{
1059 struct radv_buffer
*buffer
;
1060 VkDeviceSize offset
;
1064 struct radv_streamout_state
{
1065 /* Mask of bound streamout buffers. */
1066 uint8_t enabled_mask
;
1068 /* External state that comes from the last vertex stage, it must be
1069 * set explicitely when binding a new graphics pipeline.
1071 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1072 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1074 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1075 uint32_t hw_enabled_mask
;
1077 /* State of VGT_STRMOUT_(CONFIG|EN) */
1078 bool streamout_enabled
;
1081 struct radv_viewport_state
{
1083 VkViewport viewports
[MAX_VIEWPORTS
];
1086 struct radv_scissor_state
{
1088 VkRect2D scissors
[MAX_SCISSORS
];
1091 struct radv_discard_rectangle_state
{
1093 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1096 struct radv_sample_locations_state
{
1097 VkSampleCountFlagBits per_pixel
;
1098 VkExtent2D grid_size
;
1100 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1103 struct radv_dynamic_state
{
1105 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1106 * Defines the set of saved dynamic state.
1110 struct radv_viewport_state viewport
;
1112 struct radv_scissor_state scissor
;
1122 float blend_constants
[4];
1132 } stencil_compare_mask
;
1137 } stencil_write_mask
;
1142 } stencil_reference
;
1144 struct radv_discard_rectangle_state discard_rectangle
;
1146 struct radv_sample_locations_state sample_location
;
1154 extern const struct radv_dynamic_state default_dynamic_state
;
1157 radv_get_debug_option_name(int id
);
1160 radv_get_perftest_option_name(int id
);
1162 struct radv_color_buffer_info
{
1163 uint64_t cb_color_base
;
1164 uint64_t cb_color_cmask
;
1165 uint64_t cb_color_fmask
;
1166 uint64_t cb_dcc_base
;
1167 uint32_t cb_color_slice
;
1168 uint32_t cb_color_view
;
1169 uint32_t cb_color_info
;
1170 uint32_t cb_color_attrib
;
1171 uint32_t cb_color_attrib2
; /* GFX9 and later */
1172 uint32_t cb_color_attrib3
; /* GFX10 and later */
1173 uint32_t cb_dcc_control
;
1174 uint32_t cb_color_cmask_slice
;
1175 uint32_t cb_color_fmask_slice
;
1177 uint32_t cb_color_pitch
; // GFX6-GFX8
1178 uint32_t cb_mrt_epitch
; // GFX9+
1182 struct radv_ds_buffer_info
{
1183 uint64_t db_z_read_base
;
1184 uint64_t db_stencil_read_base
;
1185 uint64_t db_z_write_base
;
1186 uint64_t db_stencil_write_base
;
1187 uint64_t db_htile_data_base
;
1188 uint32_t db_depth_info
;
1190 uint32_t db_stencil_info
;
1191 uint32_t db_depth_view
;
1192 uint32_t db_depth_size
;
1193 uint32_t db_depth_slice
;
1194 uint32_t db_htile_surface
;
1195 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1196 uint32_t db_z_info2
; /* GFX9 only */
1197 uint32_t db_stencil_info2
; /* GFX9 only */
1202 radv_initialise_color_surface(struct radv_device
*device
,
1203 struct radv_color_buffer_info
*cb
,
1204 struct radv_image_view
*iview
);
1206 radv_initialise_ds_surface(struct radv_device
*device
,
1207 struct radv_ds_buffer_info
*ds
,
1208 struct radv_image_view
*iview
);
1211 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1214 * Attachment state when recording a renderpass instance.
1216 * The clear value is valid only if there exists a pending clear.
1218 struct radv_attachment_state
{
1219 VkImageAspectFlags pending_clear_aspects
;
1220 uint32_t cleared_views
;
1221 VkClearValue clear_value
;
1222 VkImageLayout current_layout
;
1223 VkImageLayout current_stencil_layout
;
1224 bool current_in_render_loop
;
1225 struct radv_sample_locations_state sample_location
;
1228 struct radv_color_buffer_info cb
;
1229 struct radv_ds_buffer_info ds
;
1231 struct radv_image_view
*iview
;
1234 struct radv_descriptor_state
{
1235 struct radv_descriptor_set
*sets
[MAX_SETS
];
1238 struct radv_push_descriptor_set push_set
;
1240 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1243 struct radv_subpass_sample_locs_state
{
1244 uint32_t subpass_idx
;
1245 struct radv_sample_locations_state sample_location
;
1248 struct radv_cmd_state
{
1249 /* Vertex descriptors */
1256 uint32_t prefetch_L2_mask
;
1258 struct radv_pipeline
* pipeline
;
1259 struct radv_pipeline
* emitted_pipeline
;
1260 struct radv_pipeline
* compute_pipeline
;
1261 struct radv_pipeline
* emitted_compute_pipeline
;
1262 struct radv_framebuffer
* framebuffer
;
1263 struct radv_render_pass
* pass
;
1264 const struct radv_subpass
* subpass
;
1265 struct radv_dynamic_state dynamic
;
1266 struct radv_attachment_state
* attachments
;
1267 struct radv_streamout_state streamout
;
1268 VkRect2D render_area
;
1270 uint32_t num_subpass_sample_locs
;
1271 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1274 struct radv_buffer
*index_buffer
;
1275 uint64_t index_offset
;
1276 uint32_t index_type
;
1277 uint32_t max_index_count
;
1279 int32_t last_index_type
;
1281 int32_t last_primitive_reset_en
;
1282 uint32_t last_primitive_reset_index
;
1283 enum radv_cmd_flush_bits flush_bits
;
1284 unsigned active_occlusion_queries
;
1285 bool perfect_occlusion_queries_enabled
;
1286 unsigned active_pipeline_queries
;
1287 unsigned active_pipeline_gds_queries
;
1290 uint32_t last_ia_multi_vgt_param
;
1292 uint32_t last_num_instances
;
1293 uint32_t last_first_instance
;
1294 uint32_t last_vertex_offset
;
1296 uint32_t last_sx_ps_downconvert
;
1297 uint32_t last_sx_blend_opt_epsilon
;
1298 uint32_t last_sx_blend_opt_control
;
1300 /* Whether CP DMA is busy/idle. */
1303 /* Conditional rendering info. */
1304 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1305 uint64_t predication_va
;
1307 /* Inheritance info. */
1308 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1310 bool context_roll_without_scissor_emitted
;
1312 /* SQTT related state. */
1313 uint32_t current_event_type
;
1314 uint32_t num_events
;
1315 uint32_t num_layout_transitions
;
1318 struct radv_cmd_pool
{
1319 VkAllocationCallbacks alloc
;
1320 struct list_head cmd_buffers
;
1321 struct list_head free_cmd_buffers
;
1322 uint32_t queue_family_index
;
1325 struct radv_cmd_buffer_upload
{
1329 struct radeon_winsys_bo
*upload_bo
;
1330 struct list_head list
;
1333 enum radv_cmd_buffer_status
{
1334 RADV_CMD_BUFFER_STATUS_INVALID
,
1335 RADV_CMD_BUFFER_STATUS_INITIAL
,
1336 RADV_CMD_BUFFER_STATUS_RECORDING
,
1337 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1338 RADV_CMD_BUFFER_STATUS_PENDING
,
1341 struct radv_cmd_buffer
{
1342 VK_LOADER_DATA _loader_data
;
1344 struct radv_device
* device
;
1346 struct radv_cmd_pool
* pool
;
1347 struct list_head pool_link
;
1349 VkCommandBufferUsageFlags usage_flags
;
1350 VkCommandBufferLevel level
;
1351 enum radv_cmd_buffer_status status
;
1352 struct radeon_cmdbuf
*cs
;
1353 struct radv_cmd_state state
;
1354 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1355 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1356 uint32_t queue_family_index
;
1358 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1359 VkShaderStageFlags push_constant_stages
;
1360 struct radv_descriptor_set meta_push_descriptors
;
1362 struct radv_descriptor_state descriptors
[MAX_BIND_POINTS
];
1364 struct radv_cmd_buffer_upload upload
;
1366 uint32_t scratch_size_per_wave_needed
;
1367 uint32_t scratch_waves_wanted
;
1368 uint32_t compute_scratch_size_per_wave_needed
;
1369 uint32_t compute_scratch_waves_wanted
;
1370 uint32_t esgs_ring_size_needed
;
1371 uint32_t gsvs_ring_size_needed
;
1372 bool tess_rings_needed
;
1373 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1374 bool gds_oa_needed
; /* for GFX10 streamout */
1375 bool sample_positions_needed
;
1377 VkResult record_result
;
1379 uint64_t gfx9_fence_va
;
1380 uint32_t gfx9_fence_idx
;
1381 uint64_t gfx9_eop_bug_va
;
1384 * Whether a query pool has been resetted and we have to flush caches.
1386 bool pending_reset_query
;
1389 * Bitmask of pending active query flushes.
1391 enum radv_cmd_flush_bits active_query_flush_bits
;
1395 struct radv_image_view
;
1397 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1399 void si_emit_graphics(struct radv_device
*device
,
1400 struct radeon_cmdbuf
*cs
);
1401 void si_emit_compute(struct radv_physical_device
*physical_device
,
1402 struct radeon_cmdbuf
*cs
);
1404 void cik_create_gfx_config(struct radv_device
*device
);
1406 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1407 int count
, const VkViewport
*viewports
);
1408 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1409 int count
, const VkRect2D
*scissors
,
1410 const VkViewport
*viewports
, bool can_use_guardband
);
1411 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1412 bool instanced_draw
, bool indirect_draw
,
1413 bool count_from_stream_output
,
1414 uint32_t draw_vertex_count
);
1415 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1416 enum chip_class chip_class
,
1418 unsigned event
, unsigned event_flags
,
1419 unsigned dst_sel
, unsigned data_sel
,
1422 uint64_t gfx9_eop_bug_va
);
1424 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1425 uint32_t ref
, uint32_t mask
);
1426 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1427 enum chip_class chip_class
,
1428 uint32_t *fence_ptr
, uint64_t va
,
1430 enum radv_cmd_flush_bits flush_bits
,
1431 uint64_t gfx9_eop_bug_va
);
1432 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1433 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1434 bool inverted
, uint64_t va
);
1435 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1436 uint64_t src_va
, uint64_t dest_va
,
1438 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1440 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1441 uint64_t size
, unsigned value
);
1442 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1444 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1446 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1449 unsigned *out_offset
,
1452 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1453 const struct radv_subpass
*subpass
);
1455 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1456 unsigned size
, unsigned alignmnet
,
1457 const void *data
, unsigned *out_offset
);
1459 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1460 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1461 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1462 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1463 VkImageAspectFlags aspects
,
1464 VkResolveModeFlagBits resolve_mode
);
1465 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1466 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1467 VkImageAspectFlags aspects
,
1468 VkResolveModeFlagBits resolve_mode
);
1469 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1470 unsigned radv_get_default_max_sample_dist(int log_samples
);
1471 void radv_device_init_msaa(struct radv_device
*device
);
1473 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1474 const struct radv_image_view
*iview
,
1475 VkClearDepthStencilValue ds_clear_value
,
1476 VkImageAspectFlags aspects
);
1478 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1479 const struct radv_image_view
*iview
,
1481 uint32_t color_values
[2]);
1483 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1484 struct radv_image
*image
,
1485 const VkImageSubresourceRange
*range
, bool value
);
1487 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1488 struct radv_image
*image
,
1489 const VkImageSubresourceRange
*range
, bool value
);
1491 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1492 struct radeon_winsys_bo
*bo
,
1493 uint64_t offset
, uint64_t size
, uint32_t value
);
1494 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1495 bool radv_get_memory_fd(struct radv_device
*device
,
1496 struct radv_device_memory
*memory
,
1500 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1501 unsigned sh_offset
, unsigned pointer_count
,
1502 bool use_32bit_pointers
)
1504 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1505 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1509 radv_emit_shader_pointer_body(struct radv_device
*device
,
1510 struct radeon_cmdbuf
*cs
,
1511 uint64_t va
, bool use_32bit_pointers
)
1513 radeon_emit(cs
, va
);
1515 if (use_32bit_pointers
) {
1517 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1519 radeon_emit(cs
, va
>> 32);
1524 radv_emit_shader_pointer(struct radv_device
*device
,
1525 struct radeon_cmdbuf
*cs
,
1526 uint32_t sh_offset
, uint64_t va
, bool global
)
1528 bool use_32bit_pointers
= !global
;
1530 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1531 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1534 static inline struct radv_descriptor_state
*
1535 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1536 VkPipelineBindPoint bind_point
)
1538 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1539 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1540 return &cmd_buffer
->descriptors
[bind_point
];
1544 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1546 * Limitations: Can't call normal dispatch functions without binding or rebinding
1547 * the compute pipeline.
1549 void radv_unaligned_dispatch(
1550 struct radv_cmd_buffer
*cmd_buffer
,
1556 struct radeon_winsys_bo
*bo
;
1560 struct radv_shader_module
;
1562 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1563 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1564 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1565 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1566 #define RADV_HASH_SHADER_ACO (1 << 4)
1569 radv_hash_shaders(unsigned char *hash
,
1570 const VkPipelineShaderStageCreateInfo
**stages
,
1571 const struct radv_pipeline_layout
*layout
,
1572 const struct radv_pipeline_key
*key
,
1575 static inline gl_shader_stage
1576 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1578 assert(__builtin_popcount(vk_stage
) == 1);
1579 return ffs(vk_stage
) - 1;
1582 static inline VkShaderStageFlagBits
1583 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1585 return (1 << mesa_stage
);
1588 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1590 #define radv_foreach_stage(stage, stage_bits) \
1591 for (gl_shader_stage stage, \
1592 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1593 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1594 __tmp &= ~(1 << (stage)))
1596 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1597 unsigned radv_format_meta_fs_key(VkFormat format
);
1599 struct radv_multisample_state
{
1601 uint32_t pa_sc_line_cntl
;
1602 uint32_t pa_sc_mode_cntl_0
;
1603 uint32_t pa_sc_mode_cntl_1
;
1604 uint32_t pa_sc_aa_config
;
1605 uint32_t pa_sc_aa_mask
[2];
1606 unsigned num_samples
;
1609 struct radv_prim_vertex_count
{
1614 struct radv_vertex_elements_info
{
1615 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1618 struct radv_ia_multi_vgt_param_helpers
{
1620 bool partial_es_wave
;
1621 uint8_t primgroup_size
;
1622 bool wd_switch_on_eop
;
1623 bool ia_switch_on_eoi
;
1624 bool partial_vs_wave
;
1627 struct radv_binning_state
{
1628 uint32_t pa_sc_binner_cntl_0
;
1629 uint32_t db_dfsm_control
;
1632 #define SI_GS_PER_ES 128
1634 struct radv_pipeline
{
1635 struct radv_device
* device
;
1636 struct radv_dynamic_state dynamic_state
;
1638 struct radv_pipeline_layout
* layout
;
1640 bool need_indirect_descriptor_sets
;
1641 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1642 struct radv_shader_variant
*gs_copy_shader
;
1643 VkShaderStageFlags active_stages
;
1645 struct radeon_cmdbuf cs
;
1646 uint32_t ctx_cs_hash
;
1647 struct radeon_cmdbuf ctx_cs
;
1649 struct radv_vertex_elements_info vertex_elements
;
1651 uint32_t binding_stride
[MAX_VBS
];
1652 uint8_t num_vertex_bindings
;
1654 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1657 struct radv_multisample_state ms
;
1658 struct radv_binning_state binning
;
1659 uint32_t spi_baryc_cntl
;
1660 bool prim_restart_enable
;
1661 unsigned esgs_ring_size
;
1662 unsigned gsvs_ring_size
;
1663 uint32_t vtx_base_sgpr
;
1664 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1665 uint8_t vtx_emit_num
;
1666 struct radv_prim_vertex_count prim_vertex_count
;
1667 bool can_use_guardband
;
1668 uint32_t needed_dynamic_state
;
1669 bool disable_out_of_order_rast_for_occlusion
;
1672 /* Used for rbplus */
1673 uint32_t col_format
;
1674 uint32_t cb_target_mask
;
1679 unsigned scratch_bytes_per_wave
;
1681 /* Not NULL if graphics pipeline uses streamout. */
1682 struct radv_shader_variant
*streamout_shader
;
1685 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1687 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1690 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1692 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1695 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1697 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1699 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1701 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1702 gl_shader_stage stage
,
1705 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1706 gl_shader_stage stage
);
1708 struct radv_graphics_pipeline_create_info
{
1710 bool db_depth_clear
;
1711 bool db_stencil_clear
;
1712 bool db_depth_disable_expclear
;
1713 bool db_stencil_disable_expclear
;
1714 bool depth_compress_disable
;
1715 bool stencil_compress_disable
;
1716 bool resummarize_enable
;
1717 uint32_t custom_blend_mode
;
1721 radv_graphics_pipeline_create(VkDevice device
,
1722 VkPipelineCache cache
,
1723 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1724 const struct radv_graphics_pipeline_create_info
*extra
,
1725 const VkAllocationCallbacks
*alloc
,
1726 VkPipeline
*pPipeline
);
1728 struct radv_binning_settings
{
1729 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1730 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1731 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1734 struct radv_binning_settings
1735 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1737 struct vk_format_description
;
1738 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1739 int first_non_void
);
1740 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1741 int first_non_void
);
1742 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1743 uint32_t radv_translate_colorformat(VkFormat format
);
1744 uint32_t radv_translate_color_numformat(VkFormat format
,
1745 const struct vk_format_description
*desc
,
1746 int first_non_void
);
1747 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1748 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1749 uint32_t radv_translate_dbformat(VkFormat format
);
1750 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1751 const struct vk_format_description
*desc
,
1752 int first_non_void
);
1753 uint32_t radv_translate_tex_numformat(VkFormat format
,
1754 const struct vk_format_description
*desc
,
1755 int first_non_void
);
1756 bool radv_format_pack_clear_color(VkFormat format
,
1757 uint32_t clear_vals
[2],
1758 VkClearColorValue
*value
);
1759 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1760 bool radv_dcc_formats_compatible(VkFormat format1
,
1762 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1764 struct radv_image_plane
{
1766 struct radeon_surf surface
;
1772 /* The original VkFormat provided by the client. This may not match any
1773 * of the actual surface formats.
1776 VkImageAspectFlags aspects
;
1777 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1778 struct ac_surf_info info
;
1779 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1780 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1785 unsigned queue_family_mask
;
1789 /* Set when bound */
1790 struct radeon_winsys_bo
*bo
;
1791 VkDeviceSize offset
;
1792 uint64_t dcc_offset
;
1793 uint64_t htile_offset
;
1794 bool tc_compatible_htile
;
1795 bool tc_compatible_cmask
;
1797 uint64_t cmask_offset
;
1798 uint64_t fmask_offset
;
1799 uint64_t clear_value_offset
;
1800 uint64_t fce_pred_offset
;
1801 uint64_t dcc_pred_offset
;
1804 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1805 * stored at this offset is UINT_MAX, the driver will emit
1806 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1807 * SET_CONTEXT_REG packet.
1809 uint64_t tc_compat_zrange_offset
;
1811 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1812 VkDeviceMemory owned_memory
;
1814 unsigned plane_count
;
1815 struct radv_image_plane planes
[0];
1818 /* Whether the image has a htile that is known consistent with the contents of
1819 * the image and is allowed to be in compressed form.
1821 * If this is false reads that don't use the htile should be able to return
1824 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1825 VkImageLayout layout
,
1826 bool in_render_loop
,
1827 unsigned queue_mask
);
1829 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1830 VkImageLayout layout
,
1831 bool in_render_loop
,
1832 unsigned queue_mask
);
1834 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1835 const struct radv_image
*image
,
1836 VkImageLayout layout
,
1837 bool in_render_loop
,
1838 unsigned queue_mask
);
1841 * Return whether the image has CMASK metadata for color surfaces.
1844 radv_image_has_cmask(const struct radv_image
*image
)
1846 return image
->cmask_offset
;
1850 * Return whether the image has FMASK metadata for color surfaces.
1853 radv_image_has_fmask(const struct radv_image
*image
)
1855 return image
->fmask_offset
;
1859 * Return whether the image has DCC metadata for color surfaces.
1862 radv_image_has_dcc(const struct radv_image
*image
)
1864 return image
->planes
[0].surface
.dcc_size
;
1868 * Return whether the image is TC-compatible CMASK.
1871 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1873 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1877 * Return whether DCC metadata is enabled for a level.
1880 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1882 return radv_image_has_dcc(image
) &&
1883 level
< image
->planes
[0].surface
.num_dcc_levels
;
1887 * Return whether the image has CB metadata.
1890 radv_image_has_CB_metadata(const struct radv_image
*image
)
1892 return radv_image_has_cmask(image
) ||
1893 radv_image_has_fmask(image
) ||
1894 radv_image_has_dcc(image
);
1898 * Return whether the image has HTILE metadata for depth surfaces.
1901 radv_image_has_htile(const struct radv_image
*image
)
1903 return image
->planes
[0].surface
.htile_size
;
1907 * Return whether HTILE metadata is enabled for a level.
1910 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1912 return radv_image_has_htile(image
) && level
== 0;
1916 * Return whether the image is TC-compatible HTILE.
1919 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1921 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1924 static inline uint64_t
1925 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1926 uint32_t base_level
)
1928 uint64_t va
= radv_buffer_get_va(image
->bo
);
1929 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1933 static inline uint64_t
1934 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1935 uint32_t base_level
)
1937 uint64_t va
= radv_buffer_get_va(image
->bo
);
1938 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1942 static inline uint64_t
1943 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1944 uint32_t base_level
)
1946 uint64_t va
= radv_buffer_get_va(image
->bo
);
1947 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1951 static inline uint64_t
1952 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1953 uint32_t base_level
)
1955 uint64_t va
= radv_buffer_get_va(image
->bo
);
1956 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1960 static inline uint64_t
1961 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1962 uint32_t base_level
)
1964 uint64_t va
= radv_buffer_get_va(image
->bo
);
1965 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1969 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1971 static inline uint32_t
1972 radv_get_layerCount(const struct radv_image
*image
,
1973 const VkImageSubresourceRange
*range
)
1975 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1976 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1979 static inline uint32_t
1980 radv_get_levelCount(const struct radv_image
*image
,
1981 const VkImageSubresourceRange
*range
)
1983 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1984 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1987 struct radeon_bo_metadata
;
1989 radv_init_metadata(struct radv_device
*device
,
1990 struct radv_image
*image
,
1991 struct radeon_bo_metadata
*metadata
);
1994 radv_image_override_offset_stride(struct radv_device
*device
,
1995 struct radv_image
*image
,
1996 uint64_t offset
, uint32_t stride
);
1998 union radv_descriptor
{
2000 uint32_t plane0_descriptor
[8];
2001 uint32_t fmask_descriptor
[8];
2004 uint32_t plane_descriptors
[3][8];
2008 struct radv_image_view
{
2009 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
2010 struct radeon_winsys_bo
*bo
;
2012 VkImageViewType type
;
2013 VkImageAspectFlags aspect_mask
;
2016 bool multiple_planes
;
2017 uint32_t base_layer
;
2018 uint32_t layer_count
;
2020 uint32_t level_count
;
2021 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2023 union radv_descriptor descriptor
;
2025 /* Descriptor for use as a storage image as opposed to a sampled image.
2026 * This has a few differences for cube maps (e.g. type).
2028 union radv_descriptor storage_descriptor
;
2031 struct radv_image_create_info
{
2032 const VkImageCreateInfo
*vk_info
;
2034 bool no_metadata_planes
;
2035 const struct radeon_bo_metadata
*bo_metadata
;
2039 radv_image_create_layout(struct radv_device
*device
,
2040 struct radv_image_create_info create_info
,
2041 struct radv_image
*image
);
2043 VkResult
radv_image_create(VkDevice _device
,
2044 const struct radv_image_create_info
*info
,
2045 const VkAllocationCallbacks
* alloc
,
2048 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2051 radv_image_from_gralloc(VkDevice device_h
,
2052 const VkImageCreateInfo
*base_info
,
2053 const VkNativeBufferANDROID
*gralloc_info
,
2054 const VkAllocationCallbacks
*alloc
,
2055 VkImage
*out_image_h
);
2057 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2058 const VkImageUsageFlags vk_usage
);
2060 radv_import_ahb_memory(struct radv_device
*device
,
2061 struct radv_device_memory
*mem
,
2063 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2065 radv_create_ahb_memory(struct radv_device
*device
,
2066 struct radv_device_memory
*mem
,
2068 const VkMemoryAllocateInfo
*pAllocateInfo
);
2071 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2073 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2075 struct radv_image_view_extra_create_info
{
2076 bool disable_compression
;
2079 void radv_image_view_init(struct radv_image_view
*view
,
2080 struct radv_device
*device
,
2081 const VkImageViewCreateInfo
*pCreateInfo
,
2082 const struct radv_image_view_extra_create_info
* extra_create_info
);
2084 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2086 struct radv_sampler_ycbcr_conversion
{
2088 VkSamplerYcbcrModelConversion ycbcr_model
;
2089 VkSamplerYcbcrRange ycbcr_range
;
2090 VkComponentMapping components
;
2091 VkChromaLocation chroma_offsets
[2];
2092 VkFilter chroma_filter
;
2095 struct radv_buffer_view
{
2096 struct radeon_winsys_bo
*bo
;
2098 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2101 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2102 struct radv_device
*device
,
2103 const VkBufferViewCreateInfo
* pCreateInfo
);
2105 static inline struct VkExtent3D
2106 radv_sanitize_image_extent(const VkImageType imageType
,
2107 const struct VkExtent3D imageExtent
)
2109 switch (imageType
) {
2110 case VK_IMAGE_TYPE_1D
:
2111 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2112 case VK_IMAGE_TYPE_2D
:
2113 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2114 case VK_IMAGE_TYPE_3D
:
2117 unreachable("invalid image type");
2121 static inline struct VkOffset3D
2122 radv_sanitize_image_offset(const VkImageType imageType
,
2123 const struct VkOffset3D imageOffset
)
2125 switch (imageType
) {
2126 case VK_IMAGE_TYPE_1D
:
2127 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2128 case VK_IMAGE_TYPE_2D
:
2129 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2130 case VK_IMAGE_TYPE_3D
:
2133 unreachable("invalid image type");
2138 radv_image_extent_compare(const struct radv_image
*image
,
2139 const VkExtent3D
*extent
)
2141 if (extent
->width
!= image
->info
.width
||
2142 extent
->height
!= image
->info
.height
||
2143 extent
->depth
!= image
->info
.depth
)
2148 struct radv_sampler
{
2150 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2153 struct radv_framebuffer
{
2158 uint32_t attachment_count
;
2159 struct radv_image_view
*attachments
[0];
2162 struct radv_subpass_barrier
{
2163 VkPipelineStageFlags src_stage_mask
;
2164 VkAccessFlags src_access_mask
;
2165 VkAccessFlags dst_access_mask
;
2168 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2169 const struct radv_subpass_barrier
*barrier
);
2171 struct radv_subpass_attachment
{
2172 uint32_t attachment
;
2173 VkImageLayout layout
;
2174 VkImageLayout stencil_layout
;
2175 bool in_render_loop
;
2178 struct radv_subpass
{
2179 uint32_t attachment_count
;
2180 struct radv_subpass_attachment
* attachments
;
2182 uint32_t input_count
;
2183 uint32_t color_count
;
2184 struct radv_subpass_attachment
* input_attachments
;
2185 struct radv_subpass_attachment
* color_attachments
;
2186 struct radv_subpass_attachment
* resolve_attachments
;
2187 struct radv_subpass_attachment
* depth_stencil_attachment
;
2188 struct radv_subpass_attachment
* ds_resolve_attachment
;
2189 VkResolveModeFlagBits depth_resolve_mode
;
2190 VkResolveModeFlagBits stencil_resolve_mode
;
2192 /** Subpass has at least one color resolve attachment */
2193 bool has_color_resolve
;
2195 /** Subpass has at least one color attachment */
2198 struct radv_subpass_barrier start_barrier
;
2202 VkSampleCountFlagBits color_sample_count
;
2203 VkSampleCountFlagBits depth_sample_count
;
2204 VkSampleCountFlagBits max_sample_count
;
2208 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2210 struct radv_render_pass_attachment
{
2213 VkAttachmentLoadOp load_op
;
2214 VkAttachmentLoadOp stencil_load_op
;
2215 VkImageLayout initial_layout
;
2216 VkImageLayout final_layout
;
2217 VkImageLayout stencil_initial_layout
;
2218 VkImageLayout stencil_final_layout
;
2220 /* The subpass id in which the attachment will be used first/last. */
2221 uint32_t first_subpass_idx
;
2222 uint32_t last_subpass_idx
;
2225 struct radv_render_pass
{
2226 uint32_t attachment_count
;
2227 uint32_t subpass_count
;
2228 struct radv_subpass_attachment
* subpass_attachments
;
2229 struct radv_render_pass_attachment
* attachments
;
2230 struct radv_subpass_barrier end_barrier
;
2231 struct radv_subpass subpasses
[0];
2234 VkResult
radv_device_init_meta(struct radv_device
*device
);
2235 void radv_device_finish_meta(struct radv_device
*device
);
2237 struct radv_query_pool
{
2238 struct radeon_winsys_bo
*bo
;
2240 uint32_t availability_offset
;
2244 uint32_t pipeline_stats_mask
;
2248 RADV_SEMAPHORE_NONE
,
2249 RADV_SEMAPHORE_WINSYS
,
2250 RADV_SEMAPHORE_SYNCOBJ
,
2251 RADV_SEMAPHORE_TIMELINE
,
2252 } radv_semaphore_kind
;
2254 struct radv_deferred_queue_submission
;
2256 struct radv_timeline_waiter
{
2257 struct list_head list
;
2258 struct radv_deferred_queue_submission
*submission
;
2262 struct radv_timeline_point
{
2263 struct list_head list
;
2268 /* Separate from the list to accomodate CPU wait being async, as well
2269 * as prevent point deletion during submission. */
2270 unsigned wait_count
;
2273 struct radv_timeline
{
2274 /* Using a pthread mutex to be compatible with condition variables. */
2275 pthread_mutex_t mutex
;
2277 uint64_t highest_signaled
;
2278 uint64_t highest_submitted
;
2280 struct list_head points
;
2282 /* Keep free points on hand so we do not have to recreate syncobjs all
2284 struct list_head free_points
;
2286 /* Submissions that are deferred waiting for a specific value to be
2288 struct list_head waiters
;
2291 struct radv_semaphore_part
{
2292 radv_semaphore_kind kind
;
2295 struct radeon_winsys_sem
*ws_sem
;
2296 struct radv_timeline timeline
;
2300 struct radv_semaphore
{
2301 struct radv_semaphore_part permanent
;
2302 struct radv_semaphore_part temporary
;
2305 bool radv_queue_internal_submit(struct radv_queue
*queue
,
2306 struct radeon_cmdbuf
*cs
);
2308 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2309 VkPipelineBindPoint bind_point
,
2310 struct radv_descriptor_set
*set
,
2314 radv_update_descriptor_sets(struct radv_device
*device
,
2315 struct radv_cmd_buffer
*cmd_buffer
,
2316 VkDescriptorSet overrideSet
,
2317 uint32_t descriptorWriteCount
,
2318 const VkWriteDescriptorSet
*pDescriptorWrites
,
2319 uint32_t descriptorCopyCount
,
2320 const VkCopyDescriptorSet
*pDescriptorCopies
);
2323 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2324 struct radv_cmd_buffer
*cmd_buffer
,
2325 struct radv_descriptor_set
*set
,
2326 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2329 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2330 VkPipelineBindPoint pipelineBindPoint
,
2331 VkPipelineLayout _layout
,
2333 uint32_t descriptorWriteCount
,
2334 const VkWriteDescriptorSet
*pDescriptorWrites
);
2336 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2337 struct radv_image
*image
,
2338 const VkImageSubresourceRange
*range
, uint32_t value
);
2340 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2341 struct radv_image
*image
,
2342 const VkImageSubresourceRange
*range
);
2345 struct radeon_winsys_fence
*fence
;
2346 struct wsi_fence
*fence_wsi
;
2349 uint32_t temp_syncobj
;
2352 /* radv_nir_to_llvm.c */
2353 struct radv_shader_args
;
2355 void llvm_compile_shader(struct radv_device
*device
,
2356 unsigned shader_count
,
2357 struct nir_shader
*const *shaders
,
2358 struct radv_shader_binary
**binary
,
2359 struct radv_shader_args
*args
);
2361 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2362 gl_shader_stage stage
,
2363 const struct nir_shader
*nir
);
2365 /* radv_shader_info.h */
2366 struct radv_shader_info
;
2367 struct radv_shader_variant_key
;
2369 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2370 const struct radv_pipeline_layout
*layout
,
2371 const struct radv_shader_variant_key
*key
,
2372 struct radv_shader_info
*info
,
2375 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2378 struct radv_thread_trace_info
{
2379 uint32_t cur_offset
;
2380 uint32_t trace_status
;
2382 uint32_t gfx9_write_counter
;
2383 uint32_t gfx10_dropped_cntr
;
2387 struct radv_thread_trace_se
{
2388 struct radv_thread_trace_info info
;
2390 uint32_t shader_engine
;
2391 uint32_t compute_unit
;
2394 struct radv_thread_trace
{
2395 uint32_t num_traces
;
2396 struct radv_thread_trace_se traces
[4];
2399 bool radv_thread_trace_init(struct radv_device
*device
);
2400 void radv_thread_trace_finish(struct radv_device
*device
);
2401 bool radv_begin_thread_trace(struct radv_queue
*queue
);
2402 bool radv_end_thread_trace(struct radv_queue
*queue
);
2403 bool radv_get_thread_trace(struct radv_queue
*queue
,
2404 struct radv_thread_trace
*thread_trace
);
2405 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf
*cs
,
2406 const void *data
, uint32_t num_dwords
);
2409 int radv_dump_thread_trace(struct radv_device
*device
,
2410 const struct radv_thread_trace
*trace
);
2412 /* radv_sqtt_layer_.c */
2413 struct radv_barrier_data
{
2416 uint16_t depth_stencil_expand
: 1;
2417 uint16_t htile_hiz_range_expand
: 1;
2418 uint16_t depth_stencil_resummarize
: 1;
2419 uint16_t dcc_decompress
: 1;
2420 uint16_t fmask_decompress
: 1;
2421 uint16_t fast_clear_eliminate
: 1;
2422 uint16_t fmask_color_expand
: 1;
2423 uint16_t init_mask_ram
: 1;
2424 uint16_t reserved
: 8;
2427 } layout_transitions
;
2431 * Value for the reason field of an RGP barrier start marker originating from
2432 * the Vulkan client (does not include PAL-defined values). (Table 15)
2434 enum rgp_barrier_reason
{
2435 RGP_BARRIER_UNKNOWN_REASON
= 0xFFFFFFFF,
2437 /* External app-generated barrier reasons, i.e. API synchronization
2438 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2440 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
= 0x00000001,
2441 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
= 0x00000002,
2442 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
= 0x00000003,
2444 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2445 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2447 RGP_BARRIER_INTERNAL_BASE
= 0xC0000000,
2448 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 0,
2449 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 1,
2450 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL
= RGP_BARRIER_INTERNAL_BASE
+ 2,
2451 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 3
2454 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2455 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2456 void radv_describe_draw(struct radv_cmd_buffer
*cmd_buffer
);
2457 void radv_describe_dispatch(struct radv_cmd_buffer
*cmd_buffer
, int x
, int y
, int z
);
2458 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
,
2459 VkImageAspectFlagBits aspects
);
2460 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
);
2461 void radv_describe_barrier_start(struct radv_cmd_buffer
*cmd_buffer
,
2462 enum rgp_barrier_reason reason
);
2463 void radv_describe_barrier_end(struct radv_cmd_buffer
*cmd_buffer
);
2464 void radv_describe_layout_transition(struct radv_cmd_buffer
*cmd_buffer
,
2465 const struct radv_barrier_data
*barrier
);
2467 struct radeon_winsys_sem
;
2469 uint64_t radv_get_current_time(void);
2471 static inline uint32_t
2472 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2475 case 0: /* GL_POINTS */
2477 case 1: /* GL_LINES */
2478 case 3: /* GL_LINE_STRIP */
2480 case 4: /* GL_TRIANGLES */
2481 case 5: /* GL_TRIANGLE_STRIP */
2483 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2485 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2487 case 7: /* GL_QUADS */
2488 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2495 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
2496 const VkRenderPassBeginInfo
*pRenderPassBegin
);
2497 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
);
2499 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2501 static inline struct __radv_type * \
2502 __radv_type ## _from_handle(__VkType _handle) \
2504 return (struct __radv_type *) _handle; \
2507 static inline __VkType \
2508 __radv_type ## _to_handle(struct __radv_type *_obj) \
2510 return (__VkType) _obj; \
2513 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2515 static inline struct __radv_type * \
2516 __radv_type ## _from_handle(__VkType _handle) \
2518 return (struct __radv_type *)(uintptr_t) _handle; \
2521 static inline __VkType \
2522 __radv_type ## _to_handle(struct __radv_type *_obj) \
2524 return (__VkType)(uintptr_t) _obj; \
2527 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2528 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2530 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2531 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2532 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2533 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2534 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2536 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2537 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2538 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2539 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2540 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2541 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2542 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2543 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2544 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2545 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2546 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2547 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2548 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2549 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2550 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2551 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2552 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2553 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2554 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2555 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2556 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2557 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2559 #endif /* RADV_PRIVATE_H */