2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 /* Pre-declarations needed for WSI entrypoints */
71 typedef struct xcb_connection_t xcb_connection_t
;
72 typedef uint32_t xcb_visualid_t
;
73 typedef uint32_t xcb_window_t
;
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "radv_entrypoints.h"
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
89 * To actually enable the ext we also need
90 * the necessary kernel support.
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
98 enum radv_secure_compile_type
{
99 RADV_SC_TYPE_INIT_SUCCESS
,
100 RADV_SC_TYPE_INIT_FAILURE
,
101 RADV_SC_TYPE_COMPILE_PIPELINE
,
102 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
103 RADV_SC_TYPE_READ_DISK_CACHE
,
104 RADV_SC_TYPE_WRITE_DISK_CACHE
,
105 RADV_SC_TYPE_FORK_DEVICE
,
106 RADV_SC_TYPE_DESTROY_DEVICE
,
110 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
112 static inline uint32_t
113 align_u32(uint32_t v
, uint32_t a
)
115 assert(a
!= 0 && a
== (a
& -a
));
116 return (v
+ a
- 1) & ~(a
- 1);
119 static inline uint32_t
120 align_u32_npot(uint32_t v
, uint32_t a
)
122 return (v
+ a
- 1) / a
* a
;
125 static inline uint64_t
126 align_u64(uint64_t v
, uint64_t a
)
128 assert(a
!= 0 && a
== (a
& -a
));
129 return (v
+ a
- 1) & ~(a
- 1);
132 static inline int32_t
133 align_i32(int32_t v
, int32_t a
)
135 assert(a
!= 0 && a
== (a
& -a
));
136 return (v
+ a
- 1) & ~(a
- 1);
139 /** Alignment must be a power of 2. */
141 radv_is_aligned(uintmax_t n
, uintmax_t a
)
143 assert(a
== (a
& -a
));
144 return (n
& (a
- 1)) == 0;
147 static inline uint32_t
148 round_up_u32(uint32_t v
, uint32_t a
)
150 return (v
+ a
- 1) / a
;
153 static inline uint64_t
154 round_up_u64(uint64_t v
, uint64_t a
)
156 return (v
+ a
- 1) / a
;
159 static inline uint32_t
160 radv_minify(uint32_t n
, uint32_t levels
)
162 if (unlikely(n
== 0))
165 return MAX2(n
>> levels
, 1);
168 radv_clamp_f(float f
, float min
, float max
)
181 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
183 if (*inout_mask
& clear_mask
) {
184 *inout_mask
&= ~clear_mask
;
191 #define for_each_bit(b, dword) \
192 for (uint32_t __dword = (dword); \
193 (b) = __builtin_ffs(__dword) - 1, __dword; \
194 __dword &= ~(1 << (b)))
196 #define typed_memcpy(dest, src, count) ({ \
197 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
198 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 /* Whenever we generate an error, pass it through this function. Useful for
202 * debugging, where we can break on it. Only call at error site, not when
203 * propagating errors. Might be useful to plug in a stack trace here.
206 struct radv_image_view
;
207 struct radv_instance
;
209 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
211 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
212 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
214 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
215 radv_printflike(3, 4);
216 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
217 void radv_loge_v(const char *format
, va_list va
);
218 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
219 void radv_logi_v(const char *format
, va_list va
);
222 * Print a FINISHME message, including its source location.
224 #define radv_finishme(format, ...) \
226 static bool reported = false; \
228 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
233 /* A non-fatal assert. Useful for debugging. */
235 #define radv_assert(x) ({ \
236 if (unlikely(!(x))) \
237 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 #define radv_assert(x) do {} while(0)
243 #define stub_return(v) \
245 radv_finishme("stub %s", __func__); \
251 radv_finishme("stub %s", __func__); \
255 int radv_get_instance_entrypoint_index(const char *name
);
256 int radv_get_device_entrypoint_index(const char *name
);
257 int radv_get_physical_device_entrypoint_index(const char *name
);
259 const char *radv_get_instance_entry_name(int index
);
260 const char *radv_get_physical_device_entry_name(int index
);
261 const char *radv_get_device_entry_name(int index
);
263 bool radv_instance_entrypoint_is_enabled(int index
, uint32_t core_version
,
264 const struct radv_instance_extension_table
*instance
);
265 bool radv_physical_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
266 const struct radv_instance_extension_table
*instance
);
267 bool radv_device_entrypoint_is_enabled(int index
, uint32_t core_version
,
268 const struct radv_instance_extension_table
*instance
,
269 const struct radv_device_extension_table
*device
);
271 void *radv_lookup_entrypoint(const char *name
);
273 struct radv_physical_device
{
274 VK_LOADER_DATA _loader_data
;
276 /* Link in radv_instance::physical_devices */
277 struct list_head link
;
279 struct radv_instance
* instance
;
281 struct radeon_winsys
*ws
;
282 struct radeon_info rad_info
;
283 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
284 uint8_t driver_uuid
[VK_UUID_SIZE
];
285 uint8_t device_uuid
[VK_UUID_SIZE
];
286 uint8_t cache_uuid
[VK_UUID_SIZE
];
290 struct wsi_device wsi_device
;
292 bool out_of_order_rast_allowed
;
294 /* Whether DCC should be enabled for MSAA textures. */
295 bool dcc_msaa_allowed
;
297 /* Whether to enable NGG. */
300 /* Whether to enable NGG GS. */
303 /* Whether to enable NGG streamout. */
304 bool use_ngg_streamout
;
306 /* Number of threads per wave. */
307 uint8_t ps_wave_size
;
308 uint8_t cs_wave_size
;
309 uint8_t ge_wave_size
;
311 /* Whether to use the LLVM compiler backend */
314 /* This is the drivers on-disk cache used as a fallback as opposed to
315 * the pipeline cache defined by apps.
317 struct disk_cache
* disk_cache
;
319 VkPhysicalDeviceMemoryProperties memory_properties
;
320 enum radeon_bo_domain memory_domains
[VK_MAX_MEMORY_TYPES
];
321 enum radeon_bo_flag memory_flags
[VK_MAX_MEMORY_TYPES
];
323 drmPciBusInfo bus_info
;
325 struct radv_device_extension_table supported_extensions
;
328 struct radv_instance
{
329 struct vk_object_base base
;
331 VkAllocationCallbacks alloc
;
336 uint32_t engineVersion
;
338 uint64_t debug_flags
;
339 uint64_t perftest_flags
;
340 uint8_t num_sc_threads
;
342 struct vk_debug_report_instance debug_report_callbacks
;
344 struct radv_instance_extension_table enabled_extensions
;
345 struct radv_instance_dispatch_table dispatch
;
346 struct radv_physical_device_dispatch_table physical_device_dispatch
;
347 struct radv_device_dispatch_table device_dispatch
;
349 bool physical_devices_enumerated
;
350 struct list_head physical_devices
;
352 struct driOptionCache dri_options
;
353 struct driOptionCache available_dri_options
;
356 * Workarounds for game bugs.
358 bool enable_mrt_output_nan_fixup
;
362 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
364 return instance
->num_sc_threads
;
367 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
368 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
370 bool radv_instance_extension_supported(const char *name
);
371 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
372 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
377 struct radv_pipeline_cache
{
378 struct vk_object_base base
;
379 struct radv_device
* device
;
380 pthread_mutex_t mutex
;
381 VkPipelineCacheCreateFlags flags
;
385 uint32_t kernel_count
;
386 struct cache_entry
** hash_table
;
389 VkAllocationCallbacks alloc
;
392 struct radv_pipeline_key
{
393 uint32_t instance_rate_inputs
;
394 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
395 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
396 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
397 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
398 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
399 uint64_t vertex_alpha_adjust
;
400 uint32_t vertex_post_shuffle
;
401 unsigned tess_input_vertices
;
405 uint8_t log2_ps_iter_samples
;
408 uint32_t has_multiview_view_index
: 1;
409 uint32_t optimisations_disabled
: 1;
412 /* Non-zero if a required subgroup size is specified via
413 * VK_EXT_subgroup_size_control.
415 uint8_t compute_subgroup_size
;
418 struct radv_shader_binary
;
419 struct radv_shader_variant
;
422 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
423 struct radv_device
*device
);
425 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
427 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
428 const void *data
, size_t size
);
431 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
432 struct radv_pipeline_cache
*cache
,
433 const unsigned char *sha1
,
434 struct radv_shader_variant
**variants
,
435 bool *found_in_application_cache
);
438 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
439 struct radv_pipeline_cache
*cache
,
440 const unsigned char *sha1
,
441 struct radv_shader_variant
**variants
,
442 struct radv_shader_binary
*const *binaries
);
444 enum radv_blit_ds_layout
{
445 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
446 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
447 RADV_BLIT_DS_LAYOUT_COUNT
,
450 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
452 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
455 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
457 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
460 enum radv_meta_dst_layout
{
461 RADV_META_DST_LAYOUT_GENERAL
,
462 RADV_META_DST_LAYOUT_OPTIMAL
,
463 RADV_META_DST_LAYOUT_COUNT
,
466 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
468 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
471 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
473 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
476 struct radv_meta_state
{
477 VkAllocationCallbacks alloc
;
479 struct radv_pipeline_cache cache
;
482 * For on-demand pipeline creation, makes sure that
483 * only one thread tries to build a pipeline at the same time.
488 * Use array element `i` for images with `2^i` samples.
491 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
492 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
494 VkRenderPass depthstencil_rp
;
495 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
496 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
497 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
499 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
500 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
501 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
502 } clear
[MAX_SAMPLES_LOG2
];
504 VkPipelineLayout clear_color_p_layout
;
505 VkPipelineLayout clear_depth_p_layout
;
506 VkPipelineLayout clear_depth_unrestricted_p_layout
;
508 /* Optimized compute fast HTILE clear for stencil or depth only. */
509 VkPipeline clear_htile_mask_pipeline
;
510 VkPipelineLayout clear_htile_mask_p_layout
;
511 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
514 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
516 /** Pipeline that blits from a 1D image. */
517 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
519 /** Pipeline that blits from a 2D image. */
520 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
522 /** Pipeline that blits from a 3D image. */
523 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
525 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
526 VkPipeline depth_only_1d_pipeline
;
527 VkPipeline depth_only_2d_pipeline
;
528 VkPipeline depth_only_3d_pipeline
;
530 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
531 VkPipeline stencil_only_1d_pipeline
;
532 VkPipeline stencil_only_2d_pipeline
;
533 VkPipeline stencil_only_3d_pipeline
;
534 VkPipelineLayout pipeline_layout
;
535 VkDescriptorSetLayout ds_layout
;
539 VkPipelineLayout p_layouts
[5];
540 VkDescriptorSetLayout ds_layouts
[5];
541 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
543 VkPipeline depth_only_pipeline
[5];
545 VkPipeline stencil_only_pipeline
[5];
546 } blit2d
[MAX_SAMPLES_LOG2
];
548 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
549 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
550 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
553 VkPipelineLayout img_p_layout
;
554 VkDescriptorSetLayout img_ds_layout
;
556 VkPipeline pipeline_3d
;
559 VkPipelineLayout img_p_layout
;
560 VkDescriptorSetLayout img_ds_layout
;
562 VkPipeline pipeline_3d
;
565 VkPipelineLayout img_p_layout
;
566 VkDescriptorSetLayout img_ds_layout
;
570 VkPipelineLayout img_p_layout
;
571 VkDescriptorSetLayout img_ds_layout
;
573 VkPipeline pipeline_3d
;
576 VkPipelineLayout img_p_layout
;
577 VkDescriptorSetLayout img_ds_layout
;
581 VkPipelineLayout img_p_layout
;
582 VkDescriptorSetLayout img_ds_layout
;
584 VkPipeline pipeline_3d
;
587 VkPipelineLayout img_p_layout
;
588 VkDescriptorSetLayout img_ds_layout
;
593 VkPipelineLayout p_layout
;
594 VkPipeline pipeline
[NUM_META_FS_KEYS
];
595 VkRenderPass pass
[NUM_META_FS_KEYS
];
599 VkDescriptorSetLayout ds_layout
;
600 VkPipelineLayout p_layout
;
603 VkPipeline i_pipeline
;
604 VkPipeline srgb_pipeline
;
605 } rc
[MAX_SAMPLES_LOG2
];
607 VkPipeline depth_zero_pipeline
;
609 VkPipeline average_pipeline
;
610 VkPipeline max_pipeline
;
611 VkPipeline min_pipeline
;
612 } depth
[MAX_SAMPLES_LOG2
];
614 VkPipeline stencil_zero_pipeline
;
616 VkPipeline max_pipeline
;
617 VkPipeline min_pipeline
;
618 } stencil
[MAX_SAMPLES_LOG2
];
622 VkDescriptorSetLayout ds_layout
;
623 VkPipelineLayout p_layout
;
626 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
627 VkPipeline pipeline
[NUM_META_FS_KEYS
];
628 } rc
[MAX_SAMPLES_LOG2
];
630 VkRenderPass depth_render_pass
;
631 VkPipeline depth_zero_pipeline
;
633 VkPipeline average_pipeline
;
634 VkPipeline max_pipeline
;
635 VkPipeline min_pipeline
;
636 } depth
[MAX_SAMPLES_LOG2
];
638 VkRenderPass stencil_render_pass
;
639 VkPipeline stencil_zero_pipeline
;
641 VkPipeline max_pipeline
;
642 VkPipeline min_pipeline
;
643 } stencil
[MAX_SAMPLES_LOG2
];
647 VkPipelineLayout p_layout
;
648 VkPipeline decompress_pipeline
[NUM_DEPTH_DECOMPRESS_PIPELINES
];
649 VkPipeline resummarize_pipeline
;
651 } depth_decomp
[MAX_SAMPLES_LOG2
];
654 VkPipelineLayout p_layout
;
655 VkPipeline cmask_eliminate_pipeline
;
656 VkPipeline fmask_decompress_pipeline
;
657 VkPipeline dcc_decompress_pipeline
;
660 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
661 VkPipelineLayout dcc_decompress_compute_p_layout
;
662 VkPipeline dcc_decompress_compute_pipeline
;
666 VkPipelineLayout fill_p_layout
;
667 VkPipelineLayout copy_p_layout
;
668 VkDescriptorSetLayout fill_ds_layout
;
669 VkDescriptorSetLayout copy_ds_layout
;
670 VkPipeline fill_pipeline
;
671 VkPipeline copy_pipeline
;
675 VkDescriptorSetLayout ds_layout
;
676 VkPipelineLayout p_layout
;
677 VkPipeline occlusion_query_pipeline
;
678 VkPipeline pipeline_statistics_query_pipeline
;
679 VkPipeline tfb_query_pipeline
;
680 VkPipeline timestamp_query_pipeline
;
684 VkDescriptorSetLayout ds_layout
;
685 VkPipelineLayout p_layout
;
686 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
691 #define RADV_QUEUE_GENERAL 0
692 #define RADV_QUEUE_COMPUTE 1
693 #define RADV_QUEUE_TRANSFER 2
695 #define RADV_MAX_QUEUE_FAMILIES 3
697 enum ring_type
radv_queue_family_to_ring(int f
);
700 VK_LOADER_DATA _loader_data
;
701 struct radv_device
* device
;
702 struct radeon_winsys_ctx
*hw_ctx
;
703 enum radeon_ctx_priority priority
;
704 uint32_t queue_family_index
;
706 VkDeviceQueueCreateFlags flags
;
708 uint32_t scratch_size_per_wave
;
709 uint32_t scratch_waves
;
710 uint32_t compute_scratch_size_per_wave
;
711 uint32_t compute_scratch_waves
;
712 uint32_t esgs_ring_size
;
713 uint32_t gsvs_ring_size
;
717 bool has_sample_positions
;
719 struct radeon_winsys_bo
*scratch_bo
;
720 struct radeon_winsys_bo
*descriptor_bo
;
721 struct radeon_winsys_bo
*compute_scratch_bo
;
722 struct radeon_winsys_bo
*esgs_ring_bo
;
723 struct radeon_winsys_bo
*gsvs_ring_bo
;
724 struct radeon_winsys_bo
*tess_rings_bo
;
725 struct radeon_winsys_bo
*gds_bo
;
726 struct radeon_winsys_bo
*gds_oa_bo
;
727 struct radeon_cmdbuf
*initial_preamble_cs
;
728 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
729 struct radeon_cmdbuf
*continue_preamble_cs
;
731 struct list_head pending_submissions
;
732 pthread_mutex_t pending_mutex
;
735 struct radv_bo_list
{
736 struct radv_winsys_bo_list list
;
738 pthread_mutex_t mutex
;
741 VkResult
radv_bo_list_add(struct radv_device
*device
,
742 struct radeon_winsys_bo
*bo
);
743 void radv_bo_list_remove(struct radv_device
*device
,
744 struct radeon_winsys_bo
*bo
);
746 struct radv_secure_compile_process
{
747 /* Secure process file descriptors. Used to communicate between the
748 * user facing device and the idle forked device used to fork a clean
749 * process for each new pipeline compile.
752 int fd_secure_output
;
754 /* FIFO file descriptors used to communicate between the user facing
755 * device and the secure process that does the actual secure compile.
760 /* Secure compile process id */
763 /* Is the secure compile process currently in use by a thread */
767 struct radv_secure_compile_state
{
768 struct radv_secure_compile_process
*secure_compile_processes
;
769 uint32_t secure_compile_thread_counter
;
770 mtx_t secure_compile_mutex
;
772 /* Unique process ID used to build name for FIFO file descriptor */
776 #define RADV_BORDER_COLOR_COUNT 4096
777 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
779 struct radv_device_border_color_data
{
780 bool used
[RADV_BORDER_COLOR_COUNT
];
782 struct radeon_winsys_bo
*bo
;
783 VkClearColorValue
*colors_gpu_ptr
;
785 /* Mutex is required to guarantee vkCreateSampler thread safety
786 * given that we are writing to a buffer and checking color occupation */
787 pthread_mutex_t mutex
;
793 struct radv_instance
* instance
;
794 struct radeon_winsys
*ws
;
796 struct radv_meta_state meta_state
;
798 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
799 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
800 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
802 bool always_use_syncobj
;
805 uint32_t tess_offchip_block_dw_size
;
806 uint32_t scratch_waves
;
807 uint32_t dispatch_initiator
;
809 uint32_t gs_table_depth
;
811 /* MSAA sample locations.
812 * The first index is the sample index.
813 * The second index is the coordinate: X, Y. */
814 float sample_locations_1x
[1][2];
815 float sample_locations_2x
[2][2];
816 float sample_locations_4x
[4][2];
817 float sample_locations_8x
[8][2];
820 uint32_t gfx_init_size_dw
;
821 struct radeon_winsys_bo
*gfx_init
;
823 struct radeon_winsys_bo
*trace_bo
;
824 uint32_t *trace_id_ptr
;
826 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
827 bool keep_shader_info
;
829 struct radv_physical_device
*physical_device
;
831 /* Backup in-memory cache to be used if the app doesn't provide one */
832 struct radv_pipeline_cache
* mem_cache
;
835 * use different counters so MSAA MRTs get consecutive surface indices,
836 * even if MASK is allocated in between.
838 uint32_t image_mrt_offset_counter
;
839 uint32_t fmask_mrt_offset_counter
;
840 struct list_head shader_slabs
;
841 mtx_t shader_slab_mutex
;
843 /* For detecting VM faults reported by dmesg. */
844 uint64_t dmesg_timestamp
;
846 struct radv_device_extension_table enabled_extensions
;
847 struct radv_device_dispatch_table dispatch
;
849 /* Whether the app has enabled the robustBufferAccess feature. */
850 bool robust_buffer_access
;
852 /* Whether the driver uses a global BO list. */
853 bool use_global_bo_list
;
855 struct radv_bo_list bo_list
;
857 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
860 struct radv_device_border_color_data border_color_data
;
862 struct radv_secure_compile_state
*sc_state
;
864 /* Condition variable for legacy timelines, to notify waiters when a
865 * new point gets submitted. */
866 pthread_cond_t timeline_cond
;
869 struct radeon_cmdbuf
*thread_trace_start_cs
[2];
870 struct radeon_cmdbuf
*thread_trace_stop_cs
[2];
871 struct radeon_winsys_bo
*thread_trace_bo
;
872 void *thread_trace_ptr
;
873 uint32_t thread_trace_buffer_size
;
874 int thread_trace_start_frame
;
876 /* Overallocation. */
877 bool overallocation_disallowed
;
878 uint64_t allocated_memory_size
[VK_MAX_MEMORY_HEAPS
];
879 mtx_t overallocation_mutex
;
882 struct radv_device_memory
{
883 struct vk_object_base base
;
884 struct radeon_winsys_bo
*bo
;
885 /* for dedicated allocations */
886 struct radv_image
*image
;
887 struct radv_buffer
*buffer
;
893 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
894 struct AHardwareBuffer
* android_hardware_buffer
;
899 struct radv_descriptor_range
{
904 struct radv_descriptor_set
{
905 struct vk_object_base base
;
906 const struct radv_descriptor_set_layout
*layout
;
908 uint32_t buffer_count
;
910 struct radeon_winsys_bo
*bo
;
912 uint32_t *mapped_ptr
;
913 struct radv_descriptor_range
*dynamic_descriptors
;
915 struct radeon_winsys_bo
*descriptors
[0];
918 struct radv_push_descriptor_set
920 struct radv_descriptor_set set
;
924 struct radv_descriptor_pool_entry
{
927 struct radv_descriptor_set
*set
;
930 struct radv_descriptor_pool
{
931 struct vk_object_base base
;
932 struct radeon_winsys_bo
*bo
;
934 uint64_t current_offset
;
937 uint8_t *host_memory_base
;
938 uint8_t *host_memory_ptr
;
939 uint8_t *host_memory_end
;
941 uint32_t entry_count
;
942 uint32_t max_entry_count
;
943 struct radv_descriptor_pool_entry entries
[0];
946 struct radv_descriptor_update_template_entry
{
947 VkDescriptorType descriptor_type
;
949 /* The number of descriptors to update */
950 uint32_t descriptor_count
;
952 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
955 /* In dwords. Not valid/used for dynamic descriptors */
958 uint32_t buffer_offset
;
960 /* Only valid for combined image samplers and samplers */
962 uint8_t sampler_offset
;
968 /* For push descriptors */
969 const uint32_t *immutable_samplers
;
972 struct radv_descriptor_update_template
{
973 struct vk_object_base base
;
974 uint32_t entry_count
;
975 VkPipelineBindPoint bind_point
;
976 struct radv_descriptor_update_template_entry entry
[0];
980 struct vk_object_base base
;
983 VkBufferUsageFlags usage
;
984 VkBufferCreateFlags flags
;
987 struct radeon_winsys_bo
* bo
;
993 enum radv_dynamic_state_bits
{
994 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
995 RADV_DYNAMIC_SCISSOR
= 1 << 1,
996 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
997 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
998 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
999 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
1000 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
1001 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
1002 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
1003 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
1004 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
1005 RADV_DYNAMIC_LINE_STIPPLE
= 1 << 11,
1006 RADV_DYNAMIC_ALL
= (1 << 12) - 1,
1009 enum radv_cmd_dirty_bits
{
1010 /* Keep the dynamic state dirty bits in sync with
1011 * enum radv_dynamic_state_bits */
1012 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
1013 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
1014 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
1015 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
1016 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
1017 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
1018 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
1019 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
1020 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
1021 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
1022 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
1023 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE
= 1 << 11,
1024 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 12) - 1,
1025 RADV_CMD_DIRTY_PIPELINE
= 1 << 12,
1026 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 13,
1027 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 14,
1028 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 15,
1029 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 16,
1032 enum radv_cmd_flush_bits
{
1033 /* Instruction cache. */
1034 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
1035 /* Scalar L1 cache. */
1036 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
1037 /* Vector L1 cache. */
1038 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
1039 /* L2 cache + L2 metadata cache writeback & invalidate.
1040 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1041 RADV_CMD_FLAG_INV_L2
= 1 << 3,
1042 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1043 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1044 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1045 RADV_CMD_FLAG_WB_L2
= 1 << 4,
1046 /* Framebuffer caches */
1047 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
1048 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
1049 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
1050 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
1051 /* Engine synchronization. */
1052 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1053 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1054 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1055 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1056 /* Pipeline query controls. */
1057 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1058 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1059 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1061 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1062 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1063 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1064 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1067 struct radv_vertex_binding
{
1068 struct radv_buffer
* buffer
;
1069 VkDeviceSize offset
;
1072 struct radv_streamout_binding
{
1073 struct radv_buffer
*buffer
;
1074 VkDeviceSize offset
;
1078 struct radv_streamout_state
{
1079 /* Mask of bound streamout buffers. */
1080 uint8_t enabled_mask
;
1082 /* External state that comes from the last vertex stage, it must be
1083 * set explicitely when binding a new graphics pipeline.
1085 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1086 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1088 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1089 uint32_t hw_enabled_mask
;
1091 /* State of VGT_STRMOUT_(CONFIG|EN) */
1092 bool streamout_enabled
;
1095 struct radv_viewport_state
{
1097 VkViewport viewports
[MAX_VIEWPORTS
];
1100 struct radv_scissor_state
{
1102 VkRect2D scissors
[MAX_SCISSORS
];
1105 struct radv_discard_rectangle_state
{
1107 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1110 struct radv_sample_locations_state
{
1111 VkSampleCountFlagBits per_pixel
;
1112 VkExtent2D grid_size
;
1114 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1117 struct radv_dynamic_state
{
1119 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1120 * Defines the set of saved dynamic state.
1124 struct radv_viewport_state viewport
;
1126 struct radv_scissor_state scissor
;
1136 float blend_constants
[4];
1146 } stencil_compare_mask
;
1151 } stencil_write_mask
;
1156 } stencil_reference
;
1158 struct radv_discard_rectangle_state discard_rectangle
;
1160 struct radv_sample_locations_state sample_location
;
1168 extern const struct radv_dynamic_state default_dynamic_state
;
1171 radv_get_debug_option_name(int id
);
1174 radv_get_perftest_option_name(int id
);
1176 struct radv_color_buffer_info
{
1177 uint64_t cb_color_base
;
1178 uint64_t cb_color_cmask
;
1179 uint64_t cb_color_fmask
;
1180 uint64_t cb_dcc_base
;
1181 uint32_t cb_color_slice
;
1182 uint32_t cb_color_view
;
1183 uint32_t cb_color_info
;
1184 uint32_t cb_color_attrib
;
1185 uint32_t cb_color_attrib2
; /* GFX9 and later */
1186 uint32_t cb_color_attrib3
; /* GFX10 and later */
1187 uint32_t cb_dcc_control
;
1188 uint32_t cb_color_cmask_slice
;
1189 uint32_t cb_color_fmask_slice
;
1191 uint32_t cb_color_pitch
; // GFX6-GFX8
1192 uint32_t cb_mrt_epitch
; // GFX9+
1196 struct radv_ds_buffer_info
{
1197 uint64_t db_z_read_base
;
1198 uint64_t db_stencil_read_base
;
1199 uint64_t db_z_write_base
;
1200 uint64_t db_stencil_write_base
;
1201 uint64_t db_htile_data_base
;
1202 uint32_t db_depth_info
;
1204 uint32_t db_stencil_info
;
1205 uint32_t db_depth_view
;
1206 uint32_t db_depth_size
;
1207 uint32_t db_depth_slice
;
1208 uint32_t db_htile_surface
;
1209 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1210 uint32_t db_z_info2
; /* GFX9 only */
1211 uint32_t db_stencil_info2
; /* GFX9 only */
1216 radv_initialise_color_surface(struct radv_device
*device
,
1217 struct radv_color_buffer_info
*cb
,
1218 struct radv_image_view
*iview
);
1220 radv_initialise_ds_surface(struct radv_device
*device
,
1221 struct radv_ds_buffer_info
*ds
,
1222 struct radv_image_view
*iview
);
1225 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1228 * Attachment state when recording a renderpass instance.
1230 * The clear value is valid only if there exists a pending clear.
1232 struct radv_attachment_state
{
1233 VkImageAspectFlags pending_clear_aspects
;
1234 uint32_t cleared_views
;
1235 VkClearValue clear_value
;
1236 VkImageLayout current_layout
;
1237 VkImageLayout current_stencil_layout
;
1238 bool current_in_render_loop
;
1239 struct radv_sample_locations_state sample_location
;
1242 struct radv_color_buffer_info cb
;
1243 struct radv_ds_buffer_info ds
;
1245 struct radv_image_view
*iview
;
1248 struct radv_descriptor_state
{
1249 struct radv_descriptor_set
*sets
[MAX_SETS
];
1252 struct radv_push_descriptor_set push_set
;
1254 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1257 struct radv_subpass_sample_locs_state
{
1258 uint32_t subpass_idx
;
1259 struct radv_sample_locations_state sample_location
;
1262 struct radv_cmd_state
{
1263 /* Vertex descriptors */
1270 uint32_t prefetch_L2_mask
;
1272 struct radv_pipeline
* pipeline
;
1273 struct radv_pipeline
* emitted_pipeline
;
1274 struct radv_pipeline
* compute_pipeline
;
1275 struct radv_pipeline
* emitted_compute_pipeline
;
1276 struct radv_framebuffer
* framebuffer
;
1277 struct radv_render_pass
* pass
;
1278 const struct radv_subpass
* subpass
;
1279 struct radv_dynamic_state dynamic
;
1280 struct radv_attachment_state
* attachments
;
1281 struct radv_streamout_state streamout
;
1282 VkRect2D render_area
;
1284 uint32_t num_subpass_sample_locs
;
1285 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1288 struct radv_buffer
*index_buffer
;
1289 uint64_t index_offset
;
1290 uint32_t index_type
;
1291 uint32_t max_index_count
;
1293 int32_t last_index_type
;
1295 int32_t last_primitive_reset_en
;
1296 uint32_t last_primitive_reset_index
;
1297 enum radv_cmd_flush_bits flush_bits
;
1298 unsigned active_occlusion_queries
;
1299 bool perfect_occlusion_queries_enabled
;
1300 unsigned active_pipeline_queries
;
1301 unsigned active_pipeline_gds_queries
;
1304 uint32_t last_ia_multi_vgt_param
;
1306 uint32_t last_num_instances
;
1307 uint32_t last_first_instance
;
1308 uint32_t last_vertex_offset
;
1310 uint32_t last_sx_ps_downconvert
;
1311 uint32_t last_sx_blend_opt_epsilon
;
1312 uint32_t last_sx_blend_opt_control
;
1314 /* Whether CP DMA is busy/idle. */
1317 /* Conditional rendering info. */
1318 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1319 uint64_t predication_va
;
1321 /* Inheritance info. */
1322 VkQueryPipelineStatisticFlags inherited_pipeline_statistics
;
1324 bool context_roll_without_scissor_emitted
;
1326 /* SQTT related state. */
1327 uint32_t current_event_type
;
1328 uint32_t num_events
;
1329 uint32_t num_layout_transitions
;
1332 struct radv_cmd_pool
{
1333 struct vk_object_base base
;
1334 VkAllocationCallbacks alloc
;
1335 struct list_head cmd_buffers
;
1336 struct list_head free_cmd_buffers
;
1337 uint32_t queue_family_index
;
1340 struct radv_cmd_buffer_upload
{
1344 struct radeon_winsys_bo
*upload_bo
;
1345 struct list_head list
;
1348 enum radv_cmd_buffer_status
{
1349 RADV_CMD_BUFFER_STATUS_INVALID
,
1350 RADV_CMD_BUFFER_STATUS_INITIAL
,
1351 RADV_CMD_BUFFER_STATUS_RECORDING
,
1352 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1353 RADV_CMD_BUFFER_STATUS_PENDING
,
1356 struct radv_cmd_buffer
{
1357 struct vk_object_base base
;
1359 struct radv_device
* device
;
1361 struct radv_cmd_pool
* pool
;
1362 struct list_head pool_link
;
1364 VkCommandBufferUsageFlags usage_flags
;
1365 VkCommandBufferLevel level
;
1366 enum radv_cmd_buffer_status status
;
1367 struct radeon_cmdbuf
*cs
;
1368 struct radv_cmd_state state
;
1369 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1370 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1371 uint32_t queue_family_index
;
1373 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1374 VkShaderStageFlags push_constant_stages
;
1375 struct radv_descriptor_set meta_push_descriptors
;
1377 struct radv_descriptor_state descriptors
[MAX_BIND_POINTS
];
1379 struct radv_cmd_buffer_upload upload
;
1381 uint32_t scratch_size_per_wave_needed
;
1382 uint32_t scratch_waves_wanted
;
1383 uint32_t compute_scratch_size_per_wave_needed
;
1384 uint32_t compute_scratch_waves_wanted
;
1385 uint32_t esgs_ring_size_needed
;
1386 uint32_t gsvs_ring_size_needed
;
1387 bool tess_rings_needed
;
1388 bool gds_needed
; /* for GFX10 streamout and NGG GS queries */
1389 bool gds_oa_needed
; /* for GFX10 streamout */
1390 bool sample_positions_needed
;
1392 VkResult record_result
;
1394 uint64_t gfx9_fence_va
;
1395 uint32_t gfx9_fence_idx
;
1396 uint64_t gfx9_eop_bug_va
;
1399 * Whether a query pool has been resetted and we have to flush caches.
1401 bool pending_reset_query
;
1404 * Bitmask of pending active query flushes.
1406 enum radv_cmd_flush_bits active_query_flush_bits
;
1410 struct radv_image_view
;
1412 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1414 void si_emit_graphics(struct radv_device
*device
,
1415 struct radeon_cmdbuf
*cs
);
1416 void si_emit_compute(struct radv_physical_device
*physical_device
,
1417 struct radeon_cmdbuf
*cs
);
1419 void cik_create_gfx_config(struct radv_device
*device
);
1421 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1422 int count
, const VkViewport
*viewports
);
1423 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1424 int count
, const VkRect2D
*scissors
,
1425 const VkViewport
*viewports
, bool can_use_guardband
);
1426 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1427 bool instanced_draw
, bool indirect_draw
,
1428 bool count_from_stream_output
,
1429 uint32_t draw_vertex_count
);
1430 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1431 enum chip_class chip_class
,
1433 unsigned event
, unsigned event_flags
,
1434 unsigned dst_sel
, unsigned data_sel
,
1437 uint64_t gfx9_eop_bug_va
);
1439 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1440 uint32_t ref
, uint32_t mask
);
1441 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1442 enum chip_class chip_class
,
1443 uint32_t *fence_ptr
, uint64_t va
,
1445 enum radv_cmd_flush_bits flush_bits
,
1446 uint64_t gfx9_eop_bug_va
);
1447 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1448 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1449 bool inverted
, uint64_t va
);
1450 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1451 uint64_t src_va
, uint64_t dest_va
,
1453 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1455 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1456 uint64_t size
, unsigned value
);
1457 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1459 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1461 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1464 unsigned *out_offset
,
1467 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1468 const struct radv_subpass
*subpass
);
1470 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1471 unsigned size
, unsigned alignmnet
,
1472 const void *data
, unsigned *out_offset
);
1474 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1475 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1476 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1477 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1478 VkImageAspectFlags aspects
,
1479 VkResolveModeFlagBits resolve_mode
);
1480 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1481 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1482 VkImageAspectFlags aspects
,
1483 VkResolveModeFlagBits resolve_mode
);
1484 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1485 unsigned radv_get_default_max_sample_dist(int log_samples
);
1486 void radv_device_init_msaa(struct radv_device
*device
);
1488 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1489 const struct radv_image_view
*iview
,
1490 VkClearDepthStencilValue ds_clear_value
,
1491 VkImageAspectFlags aspects
);
1493 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1494 const struct radv_image_view
*iview
,
1496 uint32_t color_values
[2]);
1498 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1499 struct radv_image
*image
,
1500 const VkImageSubresourceRange
*range
, bool value
);
1502 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1503 struct radv_image
*image
,
1504 const VkImageSubresourceRange
*range
, bool value
);
1506 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1507 struct radeon_winsys_bo
*bo
,
1508 uint64_t offset
, uint64_t size
, uint32_t value
);
1509 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1510 bool radv_get_memory_fd(struct radv_device
*device
,
1511 struct radv_device_memory
*memory
,
1515 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1516 unsigned sh_offset
, unsigned pointer_count
,
1517 bool use_32bit_pointers
)
1519 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1520 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1524 radv_emit_shader_pointer_body(struct radv_device
*device
,
1525 struct radeon_cmdbuf
*cs
,
1526 uint64_t va
, bool use_32bit_pointers
)
1528 radeon_emit(cs
, va
);
1530 if (use_32bit_pointers
) {
1532 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1534 radeon_emit(cs
, va
>> 32);
1539 radv_emit_shader_pointer(struct radv_device
*device
,
1540 struct radeon_cmdbuf
*cs
,
1541 uint32_t sh_offset
, uint64_t va
, bool global
)
1543 bool use_32bit_pointers
= !global
;
1545 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1546 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1549 static inline struct radv_descriptor_state
*
1550 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1551 VkPipelineBindPoint bind_point
)
1553 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1554 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1555 return &cmd_buffer
->descriptors
[bind_point
];
1559 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1561 * Limitations: Can't call normal dispatch functions without binding or rebinding
1562 * the compute pipeline.
1564 void radv_unaligned_dispatch(
1565 struct radv_cmd_buffer
*cmd_buffer
,
1571 struct vk_object_base base
;
1572 struct radeon_winsys_bo
*bo
;
1576 struct radv_shader_module
;
1578 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1579 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1580 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1581 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1582 #define RADV_HASH_SHADER_LLVM (1 << 4)
1585 radv_hash_shaders(unsigned char *hash
,
1586 const VkPipelineShaderStageCreateInfo
**stages
,
1587 const struct radv_pipeline_layout
*layout
,
1588 const struct radv_pipeline_key
*key
,
1591 static inline gl_shader_stage
1592 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1594 assert(__builtin_popcount(vk_stage
) == 1);
1595 return ffs(vk_stage
) - 1;
1598 static inline VkShaderStageFlagBits
1599 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1601 return (1 << mesa_stage
);
1604 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1606 #define radv_foreach_stage(stage, stage_bits) \
1607 for (gl_shader_stage stage, \
1608 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1609 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1610 __tmp &= ~(1 << (stage)))
1612 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1613 unsigned radv_format_meta_fs_key(VkFormat format
);
1615 struct radv_multisample_state
{
1617 uint32_t pa_sc_line_cntl
;
1618 uint32_t pa_sc_mode_cntl_0
;
1619 uint32_t pa_sc_mode_cntl_1
;
1620 uint32_t pa_sc_aa_config
;
1621 uint32_t pa_sc_aa_mask
[2];
1622 unsigned num_samples
;
1625 struct radv_prim_vertex_count
{
1630 struct radv_vertex_elements_info
{
1631 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1634 struct radv_ia_multi_vgt_param_helpers
{
1636 bool partial_es_wave
;
1637 uint8_t primgroup_size
;
1638 bool wd_switch_on_eop
;
1639 bool ia_switch_on_eoi
;
1640 bool partial_vs_wave
;
1643 struct radv_binning_state
{
1644 uint32_t pa_sc_binner_cntl_0
;
1645 uint32_t db_dfsm_control
;
1648 #define SI_GS_PER_ES 128
1650 struct radv_pipeline
{
1651 struct vk_object_base base
;
1652 struct radv_device
* device
;
1653 struct radv_dynamic_state dynamic_state
;
1655 struct radv_pipeline_layout
* layout
;
1657 bool need_indirect_descriptor_sets
;
1658 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1659 struct radv_shader_variant
*gs_copy_shader
;
1660 VkShaderStageFlags active_stages
;
1662 struct radeon_cmdbuf cs
;
1663 uint32_t ctx_cs_hash
;
1664 struct radeon_cmdbuf ctx_cs
;
1666 struct radv_vertex_elements_info vertex_elements
;
1668 uint32_t binding_stride
[MAX_VBS
];
1669 uint8_t num_vertex_bindings
;
1671 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1674 struct radv_multisample_state ms
;
1675 struct radv_binning_state binning
;
1676 uint32_t spi_baryc_cntl
;
1677 bool prim_restart_enable
;
1678 unsigned esgs_ring_size
;
1679 unsigned gsvs_ring_size
;
1680 uint32_t vtx_base_sgpr
;
1681 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1682 uint8_t vtx_emit_num
;
1683 struct radv_prim_vertex_count prim_vertex_count
;
1684 bool can_use_guardband
;
1685 uint32_t needed_dynamic_state
;
1686 bool disable_out_of_order_rast_for_occlusion
;
1689 /* Used for rbplus */
1690 uint32_t col_format
;
1691 uint32_t cb_target_mask
;
1697 unsigned scratch_bytes_per_wave
;
1699 /* Not NULL if graphics pipeline uses streamout. */
1700 struct radv_shader_variant
*streamout_shader
;
1703 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1705 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1708 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1710 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1713 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1715 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
);
1717 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1719 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1720 gl_shader_stage stage
,
1723 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1724 gl_shader_stage stage
);
1726 struct radv_graphics_pipeline_create_info
{
1728 bool db_depth_clear
;
1729 bool db_stencil_clear
;
1730 bool db_depth_disable_expclear
;
1731 bool db_stencil_disable_expclear
;
1732 bool depth_compress_disable
;
1733 bool stencil_compress_disable
;
1734 bool resummarize_enable
;
1735 uint32_t custom_blend_mode
;
1739 radv_graphics_pipeline_create(VkDevice device
,
1740 VkPipelineCache cache
,
1741 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1742 const struct radv_graphics_pipeline_create_info
*extra
,
1743 const VkAllocationCallbacks
*alloc
,
1744 VkPipeline
*pPipeline
);
1746 struct radv_binning_settings
{
1747 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
1748 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
1749 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
1752 struct radv_binning_settings
1753 radv_get_binning_settings(const struct radv_physical_device
*pdev
);
1755 struct vk_format_description
;
1756 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1757 int first_non_void
);
1758 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1759 int first_non_void
);
1760 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1761 uint32_t radv_translate_colorformat(VkFormat format
);
1762 uint32_t radv_translate_color_numformat(VkFormat format
,
1763 const struct vk_format_description
*desc
,
1764 int first_non_void
);
1765 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1766 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1767 uint32_t radv_translate_dbformat(VkFormat format
);
1768 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1769 const struct vk_format_description
*desc
,
1770 int first_non_void
);
1771 uint32_t radv_translate_tex_numformat(VkFormat format
,
1772 const struct vk_format_description
*desc
,
1773 int first_non_void
);
1774 bool radv_format_pack_clear_color(VkFormat format
,
1775 uint32_t clear_vals
[2],
1776 VkClearColorValue
*value
);
1777 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1778 bool radv_dcc_formats_compatible(VkFormat format1
,
1780 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1782 struct radv_image_plane
{
1784 struct radeon_surf surface
;
1789 struct vk_object_base base
;
1791 /* The original VkFormat provided by the client. This may not match any
1792 * of the actual surface formats.
1795 VkImageAspectFlags aspects
;
1796 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1797 struct ac_surf_info info
;
1798 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1799 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1804 unsigned queue_family_mask
;
1808 /* Set when bound */
1809 struct radeon_winsys_bo
*bo
;
1810 VkDeviceSize offset
;
1811 bool tc_compatible_htile
;
1812 bool tc_compatible_cmask
;
1814 uint64_t clear_value_offset
;
1815 uint64_t fce_pred_offset
;
1816 uint64_t dcc_pred_offset
;
1819 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1820 * stored at this offset is UINT_MAX, the driver will emit
1821 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1822 * SET_CONTEXT_REG packet.
1824 uint64_t tc_compat_zrange_offset
;
1826 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1827 VkDeviceMemory owned_memory
;
1829 unsigned plane_count
;
1830 struct radv_image_plane planes
[0];
1833 /* Whether the image has a htile that is known consistent with the contents of
1834 * the image and is allowed to be in compressed form.
1836 * If this is false reads that don't use the htile should be able to return
1839 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1840 VkImageLayout layout
,
1841 bool in_render_loop
,
1842 unsigned queue_mask
);
1844 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1845 VkImageLayout layout
,
1846 bool in_render_loop
,
1847 unsigned queue_mask
);
1849 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1850 const struct radv_image
*image
,
1851 VkImageLayout layout
,
1852 bool in_render_loop
,
1853 unsigned queue_mask
);
1856 * Return whether the image has CMASK metadata for color surfaces.
1859 radv_image_has_cmask(const struct radv_image
*image
)
1861 return image
->planes
[0].surface
.cmask_offset
;
1865 * Return whether the image has FMASK metadata for color surfaces.
1868 radv_image_has_fmask(const struct radv_image
*image
)
1870 return image
->planes
[0].surface
.fmask_offset
;
1874 * Return whether the image has DCC metadata for color surfaces.
1877 radv_image_has_dcc(const struct radv_image
*image
)
1879 return image
->planes
[0].surface
.dcc_size
;
1883 * Return whether the image is TC-compatible CMASK.
1886 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1888 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1892 * Return whether DCC metadata is enabled for a level.
1895 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1897 return radv_image_has_dcc(image
) &&
1898 level
< image
->planes
[0].surface
.num_dcc_levels
;
1902 * Return whether the image has CB metadata.
1905 radv_image_has_CB_metadata(const struct radv_image
*image
)
1907 return radv_image_has_cmask(image
) ||
1908 radv_image_has_fmask(image
) ||
1909 radv_image_has_dcc(image
);
1913 * Return whether the image has HTILE metadata for depth surfaces.
1916 radv_image_has_htile(const struct radv_image
*image
)
1918 return image
->planes
[0].surface
.htile_size
;
1922 * Return whether HTILE metadata is enabled for a level.
1925 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1927 return radv_image_has_htile(image
) && level
== 0;
1931 * Return whether the image is TC-compatible HTILE.
1934 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1936 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1939 static inline uint64_t
1940 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1941 uint32_t base_level
)
1943 uint64_t va
= radv_buffer_get_va(image
->bo
);
1944 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1948 static inline uint64_t
1949 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1950 uint32_t base_level
)
1952 uint64_t va
= radv_buffer_get_va(image
->bo
);
1953 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1957 static inline uint64_t
1958 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1959 uint32_t base_level
)
1961 uint64_t va
= radv_buffer_get_va(image
->bo
);
1962 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1966 static inline uint64_t
1967 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1968 uint32_t base_level
)
1970 uint64_t va
= radv_buffer_get_va(image
->bo
);
1971 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1975 static inline uint64_t
1976 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1977 uint32_t base_level
)
1979 uint64_t va
= radv_buffer_get_va(image
->bo
);
1980 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1984 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1986 static inline uint32_t
1987 radv_get_layerCount(const struct radv_image
*image
,
1988 const VkImageSubresourceRange
*range
)
1990 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1991 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1994 static inline uint32_t
1995 radv_get_levelCount(const struct radv_image
*image
,
1996 const VkImageSubresourceRange
*range
)
1998 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1999 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
2002 struct radeon_bo_metadata
;
2004 radv_init_metadata(struct radv_device
*device
,
2005 struct radv_image
*image
,
2006 struct radeon_bo_metadata
*metadata
);
2009 radv_image_override_offset_stride(struct radv_device
*device
,
2010 struct radv_image
*image
,
2011 uint64_t offset
, uint32_t stride
);
2013 union radv_descriptor
{
2015 uint32_t plane0_descriptor
[8];
2016 uint32_t fmask_descriptor
[8];
2019 uint32_t plane_descriptors
[3][8];
2023 struct radv_image_view
{
2024 struct vk_object_base base
;
2025 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
2026 struct radeon_winsys_bo
*bo
;
2028 VkImageViewType type
;
2029 VkImageAspectFlags aspect_mask
;
2032 bool multiple_planes
;
2033 uint32_t base_layer
;
2034 uint32_t layer_count
;
2036 uint32_t level_count
;
2037 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2039 union radv_descriptor descriptor
;
2041 /* Descriptor for use as a storage image as opposed to a sampled image.
2042 * This has a few differences for cube maps (e.g. type).
2044 union radv_descriptor storage_descriptor
;
2047 struct radv_image_create_info
{
2048 const VkImageCreateInfo
*vk_info
;
2050 bool no_metadata_planes
;
2051 const struct radeon_bo_metadata
*bo_metadata
;
2055 radv_image_create_layout(struct radv_device
*device
,
2056 struct radv_image_create_info create_info
,
2057 struct radv_image
*image
);
2059 VkResult
radv_image_create(VkDevice _device
,
2060 const struct radv_image_create_info
*info
,
2061 const VkAllocationCallbacks
* alloc
,
2064 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
2067 radv_image_from_gralloc(VkDevice device_h
,
2068 const VkImageCreateInfo
*base_info
,
2069 const VkNativeBufferANDROID
*gralloc_info
,
2070 const VkAllocationCallbacks
*alloc
,
2071 VkImage
*out_image_h
);
2073 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
2074 const VkImageUsageFlags vk_usage
);
2076 radv_import_ahb_memory(struct radv_device
*device
,
2077 struct radv_device_memory
*mem
,
2079 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2081 radv_create_ahb_memory(struct radv_device
*device
,
2082 struct radv_device_memory
*mem
,
2084 const VkMemoryAllocateInfo
*pAllocateInfo
);
2087 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2089 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2091 struct radv_image_view_extra_create_info
{
2092 bool disable_compression
;
2095 void radv_image_view_init(struct radv_image_view
*view
,
2096 struct radv_device
*device
,
2097 const VkImageViewCreateInfo
*pCreateInfo
,
2098 const struct radv_image_view_extra_create_info
* extra_create_info
);
2100 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2102 struct radv_sampler_ycbcr_conversion
{
2103 struct vk_object_base base
;
2105 VkSamplerYcbcrModelConversion ycbcr_model
;
2106 VkSamplerYcbcrRange ycbcr_range
;
2107 VkComponentMapping components
;
2108 VkChromaLocation chroma_offsets
[2];
2109 VkFilter chroma_filter
;
2112 struct radv_buffer_view
{
2113 struct vk_object_base base
;
2114 struct radeon_winsys_bo
*bo
;
2116 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2119 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2120 struct radv_device
*device
,
2121 const VkBufferViewCreateInfo
* pCreateInfo
);
2123 static inline struct VkExtent3D
2124 radv_sanitize_image_extent(const VkImageType imageType
,
2125 const struct VkExtent3D imageExtent
)
2127 switch (imageType
) {
2128 case VK_IMAGE_TYPE_1D
:
2129 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2130 case VK_IMAGE_TYPE_2D
:
2131 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2132 case VK_IMAGE_TYPE_3D
:
2135 unreachable("invalid image type");
2139 static inline struct VkOffset3D
2140 radv_sanitize_image_offset(const VkImageType imageType
,
2141 const struct VkOffset3D imageOffset
)
2143 switch (imageType
) {
2144 case VK_IMAGE_TYPE_1D
:
2145 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2146 case VK_IMAGE_TYPE_2D
:
2147 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2148 case VK_IMAGE_TYPE_3D
:
2151 unreachable("invalid image type");
2156 radv_image_extent_compare(const struct radv_image
*image
,
2157 const VkExtent3D
*extent
)
2159 if (extent
->width
!= image
->info
.width
||
2160 extent
->height
!= image
->info
.height
||
2161 extent
->depth
!= image
->info
.depth
)
2166 struct radv_sampler
{
2167 struct vk_object_base base
;
2169 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2170 uint32_t border_color_slot
;
2173 struct radv_framebuffer
{
2174 struct vk_object_base base
;
2179 uint32_t attachment_count
;
2180 struct radv_image_view
*attachments
[0];
2183 struct radv_subpass_barrier
{
2184 VkPipelineStageFlags src_stage_mask
;
2185 VkAccessFlags src_access_mask
;
2186 VkAccessFlags dst_access_mask
;
2189 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2190 const struct radv_subpass_barrier
*barrier
);
2192 struct radv_subpass_attachment
{
2193 uint32_t attachment
;
2194 VkImageLayout layout
;
2195 VkImageLayout stencil_layout
;
2196 bool in_render_loop
;
2199 struct radv_subpass
{
2200 uint32_t attachment_count
;
2201 struct radv_subpass_attachment
* attachments
;
2203 uint32_t input_count
;
2204 uint32_t color_count
;
2205 struct radv_subpass_attachment
* input_attachments
;
2206 struct radv_subpass_attachment
* color_attachments
;
2207 struct radv_subpass_attachment
* resolve_attachments
;
2208 struct radv_subpass_attachment
* depth_stencil_attachment
;
2209 struct radv_subpass_attachment
* ds_resolve_attachment
;
2210 VkResolveModeFlagBits depth_resolve_mode
;
2211 VkResolveModeFlagBits stencil_resolve_mode
;
2213 /** Subpass has at least one color resolve attachment */
2214 bool has_color_resolve
;
2216 /** Subpass has at least one color attachment */
2219 struct radv_subpass_barrier start_barrier
;
2223 VkSampleCountFlagBits color_sample_count
;
2224 VkSampleCountFlagBits depth_sample_count
;
2225 VkSampleCountFlagBits max_sample_count
;
2229 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2231 struct radv_render_pass_attachment
{
2234 VkAttachmentLoadOp load_op
;
2235 VkAttachmentLoadOp stencil_load_op
;
2236 VkImageLayout initial_layout
;
2237 VkImageLayout final_layout
;
2238 VkImageLayout stencil_initial_layout
;
2239 VkImageLayout stencil_final_layout
;
2241 /* The subpass id in which the attachment will be used first/last. */
2242 uint32_t first_subpass_idx
;
2243 uint32_t last_subpass_idx
;
2246 struct radv_render_pass
{
2247 struct vk_object_base base
;
2248 uint32_t attachment_count
;
2249 uint32_t subpass_count
;
2250 struct radv_subpass_attachment
* subpass_attachments
;
2251 struct radv_render_pass_attachment
* attachments
;
2252 struct radv_subpass_barrier end_barrier
;
2253 struct radv_subpass subpasses
[0];
2256 VkResult
radv_device_init_meta(struct radv_device
*device
);
2257 void radv_device_finish_meta(struct radv_device
*device
);
2259 struct radv_query_pool
{
2260 struct vk_object_base base
;
2261 struct radeon_winsys_bo
*bo
;
2263 uint32_t availability_offset
;
2267 uint32_t pipeline_stats_mask
;
2271 RADV_SEMAPHORE_NONE
,
2272 RADV_SEMAPHORE_WINSYS
,
2273 RADV_SEMAPHORE_SYNCOBJ
,
2274 RADV_SEMAPHORE_TIMELINE
,
2275 } radv_semaphore_kind
;
2277 struct radv_deferred_queue_submission
;
2279 struct radv_timeline_waiter
{
2280 struct list_head list
;
2281 struct radv_deferred_queue_submission
*submission
;
2285 struct radv_timeline_point
{
2286 struct list_head list
;
2291 /* Separate from the list to accomodate CPU wait being async, as well
2292 * as prevent point deletion during submission. */
2293 unsigned wait_count
;
2296 struct radv_timeline
{
2297 /* Using a pthread mutex to be compatible with condition variables. */
2298 pthread_mutex_t mutex
;
2300 uint64_t highest_signaled
;
2301 uint64_t highest_submitted
;
2303 struct list_head points
;
2305 /* Keep free points on hand so we do not have to recreate syncobjs all
2307 struct list_head free_points
;
2309 /* Submissions that are deferred waiting for a specific value to be
2311 struct list_head waiters
;
2314 struct radv_semaphore_part
{
2315 radv_semaphore_kind kind
;
2318 struct radeon_winsys_sem
*ws_sem
;
2319 struct radv_timeline timeline
;
2323 struct radv_semaphore
{
2324 struct vk_object_base base
;
2325 struct radv_semaphore_part permanent
;
2326 struct radv_semaphore_part temporary
;
2329 bool radv_queue_internal_submit(struct radv_queue
*queue
,
2330 struct radeon_cmdbuf
*cs
);
2332 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2333 VkPipelineBindPoint bind_point
,
2334 struct radv_descriptor_set
*set
,
2338 radv_update_descriptor_sets(struct radv_device
*device
,
2339 struct radv_cmd_buffer
*cmd_buffer
,
2340 VkDescriptorSet overrideSet
,
2341 uint32_t descriptorWriteCount
,
2342 const VkWriteDescriptorSet
*pDescriptorWrites
,
2343 uint32_t descriptorCopyCount
,
2344 const VkCopyDescriptorSet
*pDescriptorCopies
);
2347 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2348 struct radv_cmd_buffer
*cmd_buffer
,
2349 struct radv_descriptor_set
*set
,
2350 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2353 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2354 VkPipelineBindPoint pipelineBindPoint
,
2355 VkPipelineLayout _layout
,
2357 uint32_t descriptorWriteCount
,
2358 const VkWriteDescriptorSet
*pDescriptorWrites
);
2360 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2361 struct radv_image
*image
,
2362 const VkImageSubresourceRange
*range
, uint32_t value
);
2364 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2365 struct radv_image
*image
,
2366 const VkImageSubresourceRange
*range
);
2369 struct vk_object_base base
;
2370 struct radeon_winsys_fence
*fence
;
2371 struct wsi_fence
*fence_wsi
;
2374 uint32_t temp_syncobj
;
2377 /* radv_nir_to_llvm.c */
2378 struct radv_shader_args
;
2380 void llvm_compile_shader(struct radv_device
*device
,
2381 unsigned shader_count
,
2382 struct nir_shader
*const *shaders
,
2383 struct radv_shader_binary
**binary
,
2384 struct radv_shader_args
*args
);
2386 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2387 gl_shader_stage stage
,
2388 const struct nir_shader
*nir
);
2390 /* radv_shader_info.h */
2391 struct radv_shader_info
;
2392 struct radv_shader_variant_key
;
2394 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2395 const struct radv_pipeline_layout
*layout
,
2396 const struct radv_shader_variant_key
*key
,
2397 struct radv_shader_info
*info
,
2400 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2403 struct radv_thread_trace_info
{
2404 uint32_t cur_offset
;
2405 uint32_t trace_status
;
2407 uint32_t gfx9_write_counter
;
2408 uint32_t gfx10_dropped_cntr
;
2412 struct radv_thread_trace_se
{
2413 struct radv_thread_trace_info info
;
2415 uint32_t shader_engine
;
2416 uint32_t compute_unit
;
2419 struct radv_thread_trace
{
2420 uint32_t num_traces
;
2421 struct radv_thread_trace_se traces
[4];
2424 bool radv_thread_trace_init(struct radv_device
*device
);
2425 void radv_thread_trace_finish(struct radv_device
*device
);
2426 bool radv_begin_thread_trace(struct radv_queue
*queue
);
2427 bool radv_end_thread_trace(struct radv_queue
*queue
);
2428 bool radv_get_thread_trace(struct radv_queue
*queue
,
2429 struct radv_thread_trace
*thread_trace
);
2430 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf
*cs
,
2431 const void *data
, uint32_t num_dwords
);
2434 int radv_dump_thread_trace(struct radv_device
*device
,
2435 const struct radv_thread_trace
*trace
);
2437 /* radv_sqtt_layer_.c */
2438 struct radv_barrier_data
{
2441 uint16_t depth_stencil_expand
: 1;
2442 uint16_t htile_hiz_range_expand
: 1;
2443 uint16_t depth_stencil_resummarize
: 1;
2444 uint16_t dcc_decompress
: 1;
2445 uint16_t fmask_decompress
: 1;
2446 uint16_t fast_clear_eliminate
: 1;
2447 uint16_t fmask_color_expand
: 1;
2448 uint16_t init_mask_ram
: 1;
2449 uint16_t reserved
: 8;
2452 } layout_transitions
;
2456 * Value for the reason field of an RGP barrier start marker originating from
2457 * the Vulkan client (does not include PAL-defined values). (Table 15)
2459 enum rgp_barrier_reason
{
2460 RGP_BARRIER_UNKNOWN_REASON
= 0xFFFFFFFF,
2462 /* External app-generated barrier reasons, i.e. API synchronization
2463 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2465 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER
= 0x00000001,
2466 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC
= 0x00000002,
2467 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS
= 0x00000003,
2469 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2470 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2472 RGP_BARRIER_INTERNAL_BASE
= 0xC0000000,
2473 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 0,
2474 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 1,
2475 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL
= RGP_BARRIER_INTERNAL_BASE
+ 2,
2476 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC
= RGP_BARRIER_INTERNAL_BASE
+ 3
2479 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2480 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer
);
2481 void radv_describe_draw(struct radv_cmd_buffer
*cmd_buffer
);
2482 void radv_describe_dispatch(struct radv_cmd_buffer
*cmd_buffer
, int x
, int y
, int z
);
2483 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
,
2484 VkImageAspectFlagBits aspects
);
2485 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer
*cmd_buffer
);
2486 void radv_describe_barrier_start(struct radv_cmd_buffer
*cmd_buffer
,
2487 enum rgp_barrier_reason reason
);
2488 void radv_describe_barrier_end(struct radv_cmd_buffer
*cmd_buffer
);
2489 void radv_describe_layout_transition(struct radv_cmd_buffer
*cmd_buffer
,
2490 const struct radv_barrier_data
*barrier
);
2492 struct radeon_winsys_sem
;
2494 uint64_t radv_get_current_time(void);
2496 static inline uint32_t
2497 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2500 case 0: /* GL_POINTS */
2502 case 1: /* GL_LINES */
2503 case 3: /* GL_LINE_STRIP */
2505 case 4: /* GL_TRIANGLES */
2506 case 5: /* GL_TRIANGLE_STRIP */
2508 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2510 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2512 case 7: /* GL_QUADS */
2513 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2520 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer
*cmd_buffer
,
2521 const VkRenderPassBeginInfo
*pRenderPassBegin
);
2522 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer
*cmd_buffer
);
2524 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2526 static inline struct __radv_type * \
2527 __radv_type ## _from_handle(__VkType _handle) \
2529 return (struct __radv_type *) _handle; \
2532 static inline __VkType \
2533 __radv_type ## _to_handle(struct __radv_type *_obj) \
2535 return (__VkType) _obj; \
2538 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2540 static inline struct __radv_type * \
2541 __radv_type ## _from_handle(__VkType _handle) \
2543 return (struct __radv_type *)(uintptr_t) _handle; \
2546 static inline __VkType \
2547 __radv_type ## _to_handle(struct __radv_type *_obj) \
2549 return (__VkType)(uintptr_t) _obj; \
2552 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2553 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2555 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2556 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2557 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2558 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2559 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2561 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2562 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2563 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2564 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2565 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2566 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2567 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2568 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2569 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2570 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2571 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2572 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2573 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2574 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2575 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2576 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2577 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2578 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2579 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2580 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2581 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2582 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2584 #endif /* RADV_PRIVATE_H */