2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
82 #include "radv_entrypoints.h"
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
88 unsigned img_format
:9;
90 /* Various formats are only supported with workarounds for vertex fetch,
91 * and some 32_32_32 formats are supported natively, but only for buffers
92 * (possibly with some image support, actually, but no filtering). */
96 #include "gfx10_format_table.h"
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
109 RADV_MEM_TYPE_GTT_CACHED
,
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115 static inline uint32_t
116 align_u32(uint32_t v
, uint32_t a
)
118 assert(a
!= 0 && a
== (a
& -a
));
119 return (v
+ a
- 1) & ~(a
- 1);
122 static inline uint32_t
123 align_u32_npot(uint32_t v
, uint32_t a
)
125 return (v
+ a
- 1) / a
* a
;
128 static inline uint64_t
129 align_u64(uint64_t v
, uint64_t a
)
131 assert(a
!= 0 && a
== (a
& -a
));
132 return (v
+ a
- 1) & ~(a
- 1);
135 static inline int32_t
136 align_i32(int32_t v
, int32_t a
)
138 assert(a
!= 0 && a
== (a
& -a
));
139 return (v
+ a
- 1) & ~(a
- 1);
142 /** Alignment must be a power of 2. */
144 radv_is_aligned(uintmax_t n
, uintmax_t a
)
146 assert(a
== (a
& -a
));
147 return (n
& (a
- 1)) == 0;
150 static inline uint32_t
151 round_up_u32(uint32_t v
, uint32_t a
)
153 return (v
+ a
- 1) / a
;
156 static inline uint64_t
157 round_up_u64(uint64_t v
, uint64_t a
)
159 return (v
+ a
- 1) / a
;
162 static inline uint32_t
163 radv_minify(uint32_t n
, uint32_t levels
)
165 if (unlikely(n
== 0))
168 return MAX2(n
>> levels
, 1);
171 radv_clamp_f(float f
, float min
, float max
)
184 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
186 if (*inout_mask
& clear_mask
) {
187 *inout_mask
&= ~clear_mask
;
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
209 struct radv_image_view
;
210 struct radv_instance
;
212 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
214 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
215 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
217 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
218 radv_printflike(3, 4);
219 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
220 void radv_loge_v(const char *format
, va_list va
);
221 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
222 void radv_logi_v(const char *format
, va_list va
);
225 * Print a FINISHME message, including its source location.
227 #define radv_finishme(format, ...) \
229 static bool reported = false; \
231 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 /* A non-fatal assert. Useful for debugging. */
238 #define radv_assert(x) ({ \
239 if (unlikely(!(x))) \
240 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
243 #define radv_assert(x)
246 #define stub_return(v) \
248 radv_finishme("stub %s", __func__); \
254 radv_finishme("stub %s", __func__); \
258 void *radv_lookup_entrypoint_unchecked(const char *name
);
259 void *radv_lookup_entrypoint_checked(const char *name
,
260 uint32_t core_version
,
261 const struct radv_instance_extension_table
*instance
,
262 const struct radv_device_extension_table
*device
);
263 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
264 uint32_t core_version
,
265 const struct radv_instance_extension_table
*instance
);
267 struct radv_physical_device
{
268 VK_LOADER_DATA _loader_data
;
270 struct radv_instance
* instance
;
272 struct radeon_winsys
*ws
;
273 struct radeon_info rad_info
;
274 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
275 uint8_t driver_uuid
[VK_UUID_SIZE
];
276 uint8_t device_uuid
[VK_UUID_SIZE
];
277 uint8_t cache_uuid
[VK_UUID_SIZE
];
281 struct wsi_device wsi_device
;
283 bool out_of_order_rast_allowed
;
285 /* Whether DCC should be enabled for MSAA textures. */
286 bool dcc_msaa_allowed
;
288 /* Whether to enable the AMD_shader_ballot extension */
289 bool use_shader_ballot
;
291 /* Number of threads per wave. */
292 uint8_t ps_wave_size
;
293 uint8_t cs_wave_size
;
294 uint8_t ge_wave_size
;
296 /* This is the drivers on-disk cache used as a fallback as opposed to
297 * the pipeline cache defined by apps.
299 struct disk_cache
* disk_cache
;
301 VkPhysicalDeviceMemoryProperties memory_properties
;
302 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
304 drmPciBusInfo bus_info
;
306 struct radv_device_extension_table supported_extensions
;
309 struct radv_instance
{
310 VK_LOADER_DATA _loader_data
;
312 VkAllocationCallbacks alloc
;
315 int physicalDeviceCount
;
316 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
318 uint64_t debug_flags
;
319 uint64_t perftest_flags
;
321 struct vk_debug_report_instance debug_report_callbacks
;
323 struct radv_instance_extension_table enabled_extensions
;
325 struct driOptionCache dri_options
;
326 struct driOptionCache available_dri_options
;
329 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
330 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
332 bool radv_instance_extension_supported(const char *name
);
333 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
334 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
339 struct radv_pipeline_cache
{
340 struct radv_device
* device
;
341 pthread_mutex_t mutex
;
345 uint32_t kernel_count
;
346 struct cache_entry
** hash_table
;
349 VkAllocationCallbacks alloc
;
352 struct radv_pipeline_key
{
353 uint32_t instance_rate_inputs
;
354 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
355 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
356 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
357 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
358 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
359 uint64_t vertex_alpha_adjust
;
360 uint32_t vertex_post_shuffle
;
361 unsigned tess_input_vertices
;
365 uint8_t log2_ps_iter_samples
;
367 uint32_t has_multiview_view_index
: 1;
368 uint32_t optimisations_disabled
: 1;
371 struct radv_shader_binary
;
372 struct radv_shader_variant
;
375 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
376 struct radv_device
*device
);
378 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
380 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
381 const void *data
, size_t size
);
384 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
385 struct radv_pipeline_cache
*cache
,
386 const unsigned char *sha1
,
387 struct radv_shader_variant
**variants
,
388 bool *found_in_application_cache
);
391 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
392 struct radv_pipeline_cache
*cache
,
393 const unsigned char *sha1
,
394 struct radv_shader_variant
**variants
,
395 struct radv_shader_binary
*const *binaries
);
397 enum radv_blit_ds_layout
{
398 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
399 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
400 RADV_BLIT_DS_LAYOUT_COUNT
,
403 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
405 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
408 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
410 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
413 enum radv_meta_dst_layout
{
414 RADV_META_DST_LAYOUT_GENERAL
,
415 RADV_META_DST_LAYOUT_OPTIMAL
,
416 RADV_META_DST_LAYOUT_COUNT
,
419 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
421 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
424 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
426 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
429 struct radv_meta_state
{
430 VkAllocationCallbacks alloc
;
432 struct radv_pipeline_cache cache
;
435 * For on-demand pipeline creation, makes sure that
436 * only one thread tries to build a pipeline at the same time.
441 * Use array element `i` for images with `2^i` samples.
444 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
445 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
447 VkRenderPass depthstencil_rp
;
448 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
449 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
450 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
451 } clear
[1 + MAX_SAMPLES_LOG2
];
453 VkPipelineLayout clear_color_p_layout
;
454 VkPipelineLayout clear_depth_p_layout
;
456 /* Optimized compute fast HTILE clear for stencil or depth only. */
457 VkPipeline clear_htile_mask_pipeline
;
458 VkPipelineLayout clear_htile_mask_p_layout
;
459 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
462 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
464 /** Pipeline that blits from a 1D image. */
465 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
467 /** Pipeline that blits from a 2D image. */
468 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
470 /** Pipeline that blits from a 3D image. */
471 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
473 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
474 VkPipeline depth_only_1d_pipeline
;
475 VkPipeline depth_only_2d_pipeline
;
476 VkPipeline depth_only_3d_pipeline
;
478 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
479 VkPipeline stencil_only_1d_pipeline
;
480 VkPipeline stencil_only_2d_pipeline
;
481 VkPipeline stencil_only_3d_pipeline
;
482 VkPipelineLayout pipeline_layout
;
483 VkDescriptorSetLayout ds_layout
;
487 VkPipelineLayout p_layouts
[5];
488 VkDescriptorSetLayout ds_layouts
[5];
489 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
491 VkPipeline depth_only_pipeline
[5];
493 VkPipeline stencil_only_pipeline
[5];
494 } blit2d
[1 + MAX_SAMPLES_LOG2
];
496 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
497 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
498 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
501 VkPipelineLayout img_p_layout
;
502 VkDescriptorSetLayout img_ds_layout
;
504 VkPipeline pipeline_3d
;
507 VkPipelineLayout img_p_layout
;
508 VkDescriptorSetLayout img_ds_layout
;
510 VkPipeline pipeline_3d
;
513 VkPipelineLayout img_p_layout
;
514 VkDescriptorSetLayout img_ds_layout
;
518 VkPipelineLayout img_p_layout
;
519 VkDescriptorSetLayout img_ds_layout
;
521 VkPipeline pipeline_3d
;
524 VkPipelineLayout img_p_layout
;
525 VkDescriptorSetLayout img_ds_layout
;
529 VkPipelineLayout img_p_layout
;
530 VkDescriptorSetLayout img_ds_layout
;
532 VkPipeline pipeline_3d
;
535 VkPipelineLayout img_p_layout
;
536 VkDescriptorSetLayout img_ds_layout
;
541 VkPipelineLayout p_layout
;
542 VkPipeline pipeline
[NUM_META_FS_KEYS
];
543 VkRenderPass pass
[NUM_META_FS_KEYS
];
547 VkDescriptorSetLayout ds_layout
;
548 VkPipelineLayout p_layout
;
551 VkPipeline i_pipeline
;
552 VkPipeline srgb_pipeline
;
553 } rc
[MAX_SAMPLES_LOG2
];
555 VkPipeline depth_zero_pipeline
;
557 VkPipeline average_pipeline
;
558 VkPipeline max_pipeline
;
559 VkPipeline min_pipeline
;
560 } depth
[MAX_SAMPLES_LOG2
];
562 VkPipeline stencil_zero_pipeline
;
564 VkPipeline max_pipeline
;
565 VkPipeline min_pipeline
;
566 } stencil
[MAX_SAMPLES_LOG2
];
570 VkDescriptorSetLayout ds_layout
;
571 VkPipelineLayout p_layout
;
574 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
575 VkPipeline pipeline
[NUM_META_FS_KEYS
];
576 } rc
[MAX_SAMPLES_LOG2
];
578 VkRenderPass depth_render_pass
;
579 VkPipeline depth_zero_pipeline
;
581 VkPipeline average_pipeline
;
582 VkPipeline max_pipeline
;
583 VkPipeline min_pipeline
;
584 } depth
[MAX_SAMPLES_LOG2
];
586 VkRenderPass stencil_render_pass
;
587 VkPipeline stencil_zero_pipeline
;
589 VkPipeline max_pipeline
;
590 VkPipeline min_pipeline
;
591 } stencil
[MAX_SAMPLES_LOG2
];
595 VkPipelineLayout p_layout
;
596 VkPipeline decompress_pipeline
;
597 VkPipeline resummarize_pipeline
;
599 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
602 VkPipelineLayout p_layout
;
603 VkPipeline cmask_eliminate_pipeline
;
604 VkPipeline fmask_decompress_pipeline
;
605 VkPipeline dcc_decompress_pipeline
;
608 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
609 VkPipelineLayout dcc_decompress_compute_p_layout
;
610 VkPipeline dcc_decompress_compute_pipeline
;
614 VkPipelineLayout fill_p_layout
;
615 VkPipelineLayout copy_p_layout
;
616 VkDescriptorSetLayout fill_ds_layout
;
617 VkDescriptorSetLayout copy_ds_layout
;
618 VkPipeline fill_pipeline
;
619 VkPipeline copy_pipeline
;
623 VkDescriptorSetLayout ds_layout
;
624 VkPipelineLayout p_layout
;
625 VkPipeline occlusion_query_pipeline
;
626 VkPipeline pipeline_statistics_query_pipeline
;
627 VkPipeline tfb_query_pipeline
;
631 VkDescriptorSetLayout ds_layout
;
632 VkPipelineLayout p_layout
;
633 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
638 #define RADV_QUEUE_GENERAL 0
639 #define RADV_QUEUE_COMPUTE 1
640 #define RADV_QUEUE_TRANSFER 2
642 #define RADV_MAX_QUEUE_FAMILIES 3
644 enum ring_type
radv_queue_family_to_ring(int f
);
647 VK_LOADER_DATA _loader_data
;
648 struct radv_device
* device
;
649 struct radeon_winsys_ctx
*hw_ctx
;
650 enum radeon_ctx_priority priority
;
651 uint32_t queue_family_index
;
653 VkDeviceQueueCreateFlags flags
;
655 uint32_t scratch_size
;
656 uint32_t compute_scratch_size
;
657 uint32_t esgs_ring_size
;
658 uint32_t gsvs_ring_size
;
660 bool has_sample_positions
;
662 struct radeon_winsys_bo
*scratch_bo
;
663 struct radeon_winsys_bo
*descriptor_bo
;
664 struct radeon_winsys_bo
*compute_scratch_bo
;
665 struct radeon_winsys_bo
*esgs_ring_bo
;
666 struct radeon_winsys_bo
*gsvs_ring_bo
;
667 struct radeon_winsys_bo
*tess_rings_bo
;
668 struct radeon_cmdbuf
*initial_preamble_cs
;
669 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
670 struct radeon_cmdbuf
*continue_preamble_cs
;
673 struct radv_bo_list
{
674 struct radv_winsys_bo_list list
;
676 pthread_mutex_t mutex
;
680 VK_LOADER_DATA _loader_data
;
682 VkAllocationCallbacks alloc
;
684 struct radv_instance
* instance
;
685 struct radeon_winsys
*ws
;
687 struct radv_meta_state meta_state
;
689 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
690 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
691 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
693 bool always_use_syncobj
;
696 uint32_t tess_offchip_block_dw_size
;
697 uint32_t scratch_waves
;
698 uint32_t dispatch_initiator
;
700 uint32_t gs_table_depth
;
702 /* MSAA sample locations.
703 * The first index is the sample index.
704 * The second index is the coordinate: X, Y. */
705 float sample_locations_1x
[1][2];
706 float sample_locations_2x
[2][2];
707 float sample_locations_4x
[4][2];
708 float sample_locations_8x
[8][2];
711 uint32_t gfx_init_size_dw
;
712 struct radeon_winsys_bo
*gfx_init
;
714 struct radeon_winsys_bo
*trace_bo
;
715 uint32_t *trace_id_ptr
;
717 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
718 bool keep_shader_info
;
720 struct radv_physical_device
*physical_device
;
722 /* Backup in-memory cache to be used if the app doesn't provide one */
723 struct radv_pipeline_cache
* mem_cache
;
726 * use different counters so MSAA MRTs get consecutive surface indices,
727 * even if MASK is allocated in between.
729 uint32_t image_mrt_offset_counter
;
730 uint32_t fmask_mrt_offset_counter
;
731 struct list_head shader_slabs
;
732 mtx_t shader_slab_mutex
;
734 /* For detecting VM faults reported by dmesg. */
735 uint64_t dmesg_timestamp
;
737 struct radv_device_extension_table enabled_extensions
;
739 /* Whether the app has enabled the robustBufferAccess feature. */
740 bool robust_buffer_access
;
742 /* Whether the driver uses a global BO list. */
743 bool use_global_bo_list
;
745 struct radv_bo_list bo_list
;
747 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
751 struct radv_device_memory
{
752 struct radeon_winsys_bo
*bo
;
753 /* for dedicated allocations */
754 struct radv_image
*image
;
755 struct radv_buffer
*buffer
;
757 VkDeviceSize map_size
;
763 struct radv_descriptor_range
{
768 struct radv_descriptor_set
{
769 const struct radv_descriptor_set_layout
*layout
;
772 struct radeon_winsys_bo
*bo
;
774 uint32_t *mapped_ptr
;
775 struct radv_descriptor_range
*dynamic_descriptors
;
777 struct radeon_winsys_bo
*descriptors
[0];
780 struct radv_push_descriptor_set
782 struct radv_descriptor_set set
;
786 struct radv_descriptor_pool_entry
{
789 struct radv_descriptor_set
*set
;
792 struct radv_descriptor_pool
{
793 struct radeon_winsys_bo
*bo
;
795 uint64_t current_offset
;
798 uint8_t *host_memory_base
;
799 uint8_t *host_memory_ptr
;
800 uint8_t *host_memory_end
;
802 uint32_t entry_count
;
803 uint32_t max_entry_count
;
804 struct radv_descriptor_pool_entry entries
[0];
807 struct radv_descriptor_update_template_entry
{
808 VkDescriptorType descriptor_type
;
810 /* The number of descriptors to update */
811 uint32_t descriptor_count
;
813 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
816 /* In dwords. Not valid/used for dynamic descriptors */
819 uint32_t buffer_offset
;
821 /* Only valid for combined image samplers and samplers */
823 uint8_t sampler_offset
;
829 /* For push descriptors */
830 const uint32_t *immutable_samplers
;
833 struct radv_descriptor_update_template
{
834 uint32_t entry_count
;
835 VkPipelineBindPoint bind_point
;
836 struct radv_descriptor_update_template_entry entry
[0];
842 VkBufferUsageFlags usage
;
843 VkBufferCreateFlags flags
;
846 struct radeon_winsys_bo
* bo
;
852 enum radv_dynamic_state_bits
{
853 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
854 RADV_DYNAMIC_SCISSOR
= 1 << 1,
855 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
856 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
857 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
858 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
859 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
860 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
861 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
862 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
863 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
864 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
867 enum radv_cmd_dirty_bits
{
868 /* Keep the dynamic state dirty bits in sync with
869 * enum radv_dynamic_state_bits */
870 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
871 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
872 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
873 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
874 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
875 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
876 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
877 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
878 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
879 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
880 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
881 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
882 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
883 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
884 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
885 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
886 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
889 enum radv_cmd_flush_bits
{
890 /* Instruction cache. */
891 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
892 /* Scalar L1 cache. */
893 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
894 /* Vector L1 cache. */
895 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
896 /* L2 cache + L2 metadata cache writeback & invalidate.
897 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
898 RADV_CMD_FLAG_INV_L2
= 1 << 3,
899 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
900 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
901 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
902 RADV_CMD_FLAG_WB_L2
= 1 << 4,
903 /* Framebuffer caches */
904 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
905 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
906 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
907 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
908 /* Engine synchronization. */
909 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
910 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
911 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
912 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
913 /* Pipeline query controls. */
914 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
915 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
916 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
918 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
919 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
920 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
921 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
924 struct radv_vertex_binding
{
925 struct radv_buffer
* buffer
;
929 struct radv_streamout_binding
{
930 struct radv_buffer
*buffer
;
935 struct radv_streamout_state
{
936 /* Mask of bound streamout buffers. */
937 uint8_t enabled_mask
;
939 /* External state that comes from the last vertex stage, it must be
940 * set explicitely when binding a new graphics pipeline.
942 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
943 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
945 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
946 uint32_t hw_enabled_mask
;
948 /* State of VGT_STRMOUT_(CONFIG|EN) */
949 bool streamout_enabled
;
952 struct radv_viewport_state
{
954 VkViewport viewports
[MAX_VIEWPORTS
];
957 struct radv_scissor_state
{
959 VkRect2D scissors
[MAX_SCISSORS
];
962 struct radv_discard_rectangle_state
{
964 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
967 struct radv_sample_locations_state
{
968 VkSampleCountFlagBits per_pixel
;
969 VkExtent2D grid_size
;
971 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
974 struct radv_dynamic_state
{
976 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
977 * Defines the set of saved dynamic state.
981 struct radv_viewport_state viewport
;
983 struct radv_scissor_state scissor
;
993 float blend_constants
[4];
1003 } stencil_compare_mask
;
1008 } stencil_write_mask
;
1013 } stencil_reference
;
1015 struct radv_discard_rectangle_state discard_rectangle
;
1017 struct radv_sample_locations_state sample_location
;
1020 extern const struct radv_dynamic_state default_dynamic_state
;
1023 radv_get_debug_option_name(int id
);
1026 radv_get_perftest_option_name(int id
);
1028 struct radv_color_buffer_info
{
1029 uint64_t cb_color_base
;
1030 uint64_t cb_color_cmask
;
1031 uint64_t cb_color_fmask
;
1032 uint64_t cb_dcc_base
;
1033 uint32_t cb_color_slice
;
1034 uint32_t cb_color_view
;
1035 uint32_t cb_color_info
;
1036 uint32_t cb_color_attrib
;
1037 uint32_t cb_color_attrib2
; /* GFX9 and later */
1038 uint32_t cb_color_attrib3
; /* GFX10 and later */
1039 uint32_t cb_dcc_control
;
1040 uint32_t cb_color_cmask_slice
;
1041 uint32_t cb_color_fmask_slice
;
1043 uint32_t cb_color_pitch
; // GFX6-GFX8
1044 uint32_t cb_mrt_epitch
; // GFX9+
1048 struct radv_ds_buffer_info
{
1049 uint64_t db_z_read_base
;
1050 uint64_t db_stencil_read_base
;
1051 uint64_t db_z_write_base
;
1052 uint64_t db_stencil_write_base
;
1053 uint64_t db_htile_data_base
;
1054 uint32_t db_depth_info
;
1056 uint32_t db_stencil_info
;
1057 uint32_t db_depth_view
;
1058 uint32_t db_depth_size
;
1059 uint32_t db_depth_slice
;
1060 uint32_t db_htile_surface
;
1061 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1062 uint32_t db_z_info2
; /* GFX9 only */
1063 uint32_t db_stencil_info2
; /* GFX9 only */
1068 radv_initialise_color_surface(struct radv_device
*device
,
1069 struct radv_color_buffer_info
*cb
,
1070 struct radv_image_view
*iview
);
1072 radv_initialise_ds_surface(struct radv_device
*device
,
1073 struct radv_ds_buffer_info
*ds
,
1074 struct radv_image_view
*iview
);
1077 * Attachment state when recording a renderpass instance.
1079 * The clear value is valid only if there exists a pending clear.
1081 struct radv_attachment_state
{
1082 VkImageAspectFlags pending_clear_aspects
;
1083 uint32_t cleared_views
;
1084 VkClearValue clear_value
;
1085 VkImageLayout current_layout
;
1086 bool current_in_render_loop
;
1087 struct radv_sample_locations_state sample_location
;
1090 struct radv_color_buffer_info cb
;
1091 struct radv_ds_buffer_info ds
;
1093 struct radv_image_view
*iview
;
1096 struct radv_descriptor_state
{
1097 struct radv_descriptor_set
*sets
[MAX_SETS
];
1100 struct radv_push_descriptor_set push_set
;
1102 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1105 struct radv_subpass_sample_locs_state
{
1106 uint32_t subpass_idx
;
1107 struct radv_sample_locations_state sample_location
;
1110 struct radv_cmd_state
{
1111 /* Vertex descriptors */
1118 uint32_t prefetch_L2_mask
;
1120 struct radv_pipeline
* pipeline
;
1121 struct radv_pipeline
* emitted_pipeline
;
1122 struct radv_pipeline
* compute_pipeline
;
1123 struct radv_pipeline
* emitted_compute_pipeline
;
1124 struct radv_framebuffer
* framebuffer
;
1125 struct radv_render_pass
* pass
;
1126 const struct radv_subpass
* subpass
;
1127 struct radv_dynamic_state dynamic
;
1128 struct radv_attachment_state
* attachments
;
1129 struct radv_streamout_state streamout
;
1130 VkRect2D render_area
;
1132 uint32_t num_subpass_sample_locs
;
1133 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1136 struct radv_buffer
*index_buffer
;
1137 uint64_t index_offset
;
1138 uint32_t index_type
;
1139 uint32_t max_index_count
;
1141 int32_t last_index_type
;
1143 int32_t last_primitive_reset_en
;
1144 uint32_t last_primitive_reset_index
;
1145 enum radv_cmd_flush_bits flush_bits
;
1146 unsigned active_occlusion_queries
;
1147 bool perfect_occlusion_queries_enabled
;
1148 unsigned active_pipeline_queries
;
1151 uint32_t last_ia_multi_vgt_param
;
1153 uint32_t last_num_instances
;
1154 uint32_t last_first_instance
;
1155 uint32_t last_vertex_offset
;
1157 /* Whether CP DMA is busy/idle. */
1160 /* Conditional rendering info. */
1161 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1162 uint64_t predication_va
;
1164 bool context_roll_without_scissor_emitted
;
1167 struct radv_cmd_pool
{
1168 VkAllocationCallbacks alloc
;
1169 struct list_head cmd_buffers
;
1170 struct list_head free_cmd_buffers
;
1171 uint32_t queue_family_index
;
1174 struct radv_cmd_buffer_upload
{
1178 struct radeon_winsys_bo
*upload_bo
;
1179 struct list_head list
;
1182 enum radv_cmd_buffer_status
{
1183 RADV_CMD_BUFFER_STATUS_INVALID
,
1184 RADV_CMD_BUFFER_STATUS_INITIAL
,
1185 RADV_CMD_BUFFER_STATUS_RECORDING
,
1186 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1187 RADV_CMD_BUFFER_STATUS_PENDING
,
1190 struct radv_cmd_buffer
{
1191 VK_LOADER_DATA _loader_data
;
1193 struct radv_device
* device
;
1195 struct radv_cmd_pool
* pool
;
1196 struct list_head pool_link
;
1198 VkCommandBufferUsageFlags usage_flags
;
1199 VkCommandBufferLevel level
;
1200 enum radv_cmd_buffer_status status
;
1201 struct radeon_cmdbuf
*cs
;
1202 struct radv_cmd_state state
;
1203 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1204 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1205 uint32_t queue_family_index
;
1207 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1208 VkShaderStageFlags push_constant_stages
;
1209 struct radv_descriptor_set meta_push_descriptors
;
1211 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1213 struct radv_cmd_buffer_upload upload
;
1215 uint32_t scratch_size_needed
;
1216 uint32_t compute_scratch_size_needed
;
1217 uint32_t esgs_ring_size_needed
;
1218 uint32_t gsvs_ring_size_needed
;
1219 bool tess_rings_needed
;
1220 bool sample_positions_needed
;
1222 VkResult record_result
;
1224 uint64_t gfx9_fence_va
;
1225 uint32_t gfx9_fence_idx
;
1226 uint64_t gfx9_eop_bug_va
;
1229 * Whether a query pool has been resetted and we have to flush caches.
1231 bool pending_reset_query
;
1234 * Bitmask of pending active query flushes.
1236 enum radv_cmd_flush_bits active_query_flush_bits
;
1240 struct radv_image_view
;
1242 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1244 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1245 struct radeon_cmdbuf
*cs
);
1246 void si_emit_compute(struct radv_physical_device
*physical_device
,
1247 struct radeon_cmdbuf
*cs
);
1249 void cik_create_gfx_config(struct radv_device
*device
);
1251 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1252 int count
, const VkViewport
*viewports
);
1253 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1254 int count
, const VkRect2D
*scissors
,
1255 const VkViewport
*viewports
, bool can_use_guardband
);
1256 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1257 bool instanced_draw
, bool indirect_draw
,
1258 bool count_from_stream_output
,
1259 uint32_t draw_vertex_count
);
1260 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1261 enum chip_class chip_class
,
1263 unsigned event
, unsigned event_flags
,
1264 unsigned dst_sel
, unsigned data_sel
,
1267 uint64_t gfx9_eop_bug_va
);
1269 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1270 uint32_t ref
, uint32_t mask
);
1271 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1272 enum chip_class chip_class
,
1273 uint32_t *fence_ptr
, uint64_t va
,
1275 enum radv_cmd_flush_bits flush_bits
,
1276 uint64_t gfx9_eop_bug_va
);
1277 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1278 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1279 bool inverted
, uint64_t va
);
1280 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1281 uint64_t src_va
, uint64_t dest_va
,
1283 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1285 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1286 uint64_t size
, unsigned value
);
1287 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1289 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1291 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1294 unsigned *out_offset
,
1297 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1298 const struct radv_subpass
*subpass
);
1300 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1301 unsigned size
, unsigned alignmnet
,
1302 const void *data
, unsigned *out_offset
);
1304 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1305 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1306 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1307 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1308 VkImageAspectFlags aspects
,
1309 VkResolveModeFlagBitsKHR resolve_mode
);
1310 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1311 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1312 VkImageAspectFlags aspects
,
1313 VkResolveModeFlagBitsKHR resolve_mode
);
1314 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1315 unsigned radv_get_default_max_sample_dist(int log_samples
);
1316 void radv_device_init_msaa(struct radv_device
*device
);
1318 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1319 const struct radv_image_view
*iview
,
1320 VkClearDepthStencilValue ds_clear_value
,
1321 VkImageAspectFlags aspects
);
1323 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1324 const struct radv_image_view
*iview
,
1326 uint32_t color_values
[2]);
1328 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1329 struct radv_image
*image
,
1330 const VkImageSubresourceRange
*range
, bool value
);
1332 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1333 struct radv_image
*image
,
1334 const VkImageSubresourceRange
*range
, bool value
);
1336 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1337 struct radeon_winsys_bo
*bo
,
1338 uint64_t offset
, uint64_t size
, uint32_t value
);
1339 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1340 bool radv_get_memory_fd(struct radv_device
*device
,
1341 struct radv_device_memory
*memory
,
1345 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1346 unsigned sh_offset
, unsigned pointer_count
,
1347 bool use_32bit_pointers
)
1349 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1350 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1354 radv_emit_shader_pointer_body(struct radv_device
*device
,
1355 struct radeon_cmdbuf
*cs
,
1356 uint64_t va
, bool use_32bit_pointers
)
1358 radeon_emit(cs
, va
);
1360 if (use_32bit_pointers
) {
1362 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1364 radeon_emit(cs
, va
>> 32);
1369 radv_emit_shader_pointer(struct radv_device
*device
,
1370 struct radeon_cmdbuf
*cs
,
1371 uint32_t sh_offset
, uint64_t va
, bool global
)
1373 bool use_32bit_pointers
= !global
;
1375 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1376 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1379 static inline struct radv_descriptor_state
*
1380 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1381 VkPipelineBindPoint bind_point
)
1383 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1384 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1385 return &cmd_buffer
->descriptors
[bind_point
];
1389 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1391 * Limitations: Can't call normal dispatch functions without binding or rebinding
1392 * the compute pipeline.
1394 void radv_unaligned_dispatch(
1395 struct radv_cmd_buffer
*cmd_buffer
,
1401 struct radeon_winsys_bo
*bo
;
1405 struct radv_shader_module
;
1407 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1408 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1409 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1410 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1411 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1412 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1413 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1416 radv_hash_shaders(unsigned char *hash
,
1417 const VkPipelineShaderStageCreateInfo
**stages
,
1418 const struct radv_pipeline_layout
*layout
,
1419 const struct radv_pipeline_key
*key
,
1422 static inline gl_shader_stage
1423 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1425 assert(__builtin_popcount(vk_stage
) == 1);
1426 return ffs(vk_stage
) - 1;
1429 static inline VkShaderStageFlagBits
1430 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1432 return (1 << mesa_stage
);
1435 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1437 #define radv_foreach_stage(stage, stage_bits) \
1438 for (gl_shader_stage stage, \
1439 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1440 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1441 __tmp &= ~(1 << (stage)))
1443 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1444 unsigned radv_format_meta_fs_key(VkFormat format
);
1446 struct radv_multisample_state
{
1448 uint32_t pa_sc_line_cntl
;
1449 uint32_t pa_sc_mode_cntl_0
;
1450 uint32_t pa_sc_mode_cntl_1
;
1451 uint32_t pa_sc_aa_config
;
1452 uint32_t pa_sc_aa_mask
[2];
1453 unsigned num_samples
;
1456 struct radv_prim_vertex_count
{
1461 struct radv_vertex_elements_info
{
1462 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1465 struct radv_ia_multi_vgt_param_helpers
{
1467 bool partial_es_wave
;
1468 uint8_t primgroup_size
;
1469 bool wd_switch_on_eop
;
1470 bool ia_switch_on_eoi
;
1471 bool partial_vs_wave
;
1474 struct radv_binning_state
{
1475 uint32_t pa_sc_binner_cntl_0
;
1476 uint32_t db_dfsm_control
;
1479 #define SI_GS_PER_ES 128
1481 struct radv_pipeline
{
1482 struct radv_device
* device
;
1483 struct radv_dynamic_state dynamic_state
;
1485 struct radv_pipeline_layout
* layout
;
1487 bool need_indirect_descriptor_sets
;
1488 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1489 struct radv_shader_variant
*gs_copy_shader
;
1490 VkShaderStageFlags active_stages
;
1492 struct radeon_cmdbuf cs
;
1493 uint32_t ctx_cs_hash
;
1494 struct radeon_cmdbuf ctx_cs
;
1496 struct radv_vertex_elements_info vertex_elements
;
1498 uint32_t binding_stride
[MAX_VBS
];
1499 uint8_t num_vertex_bindings
;
1501 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1504 struct radv_multisample_state ms
;
1505 struct radv_binning_state binning
;
1506 uint32_t spi_baryc_cntl
;
1507 bool prim_restart_enable
;
1508 unsigned esgs_ring_size
;
1509 unsigned gsvs_ring_size
;
1510 uint32_t vtx_base_sgpr
;
1511 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1512 uint8_t vtx_emit_num
;
1513 struct radv_prim_vertex_count prim_vertex_count
;
1514 bool can_use_guardband
;
1515 uint32_t needed_dynamic_state
;
1516 bool disable_out_of_order_rast_for_occlusion
;
1518 /* Used for rbplus */
1519 uint32_t col_format
;
1520 uint32_t cb_target_mask
;
1525 unsigned scratch_bytes_per_wave
;
1527 /* Not NULL if graphics pipeline uses streamout. */
1528 struct radv_shader_variant
*streamout_shader
;
1531 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1533 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1536 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1538 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1541 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1543 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1545 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1546 gl_shader_stage stage
,
1549 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1550 gl_shader_stage stage
);
1552 struct radv_graphics_pipeline_create_info
{
1554 bool db_depth_clear
;
1555 bool db_stencil_clear
;
1556 bool db_depth_disable_expclear
;
1557 bool db_stencil_disable_expclear
;
1558 bool db_flush_depth_inplace
;
1559 bool db_flush_stencil_inplace
;
1560 bool db_resummarize
;
1561 uint32_t custom_blend_mode
;
1565 radv_graphics_pipeline_create(VkDevice device
,
1566 VkPipelineCache cache
,
1567 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1568 const struct radv_graphics_pipeline_create_info
*extra
,
1569 const VkAllocationCallbacks
*alloc
,
1570 VkPipeline
*pPipeline
);
1572 struct vk_format_description
;
1573 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1574 int first_non_void
);
1575 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1576 int first_non_void
);
1577 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1578 uint32_t radv_translate_colorformat(VkFormat format
);
1579 uint32_t radv_translate_color_numformat(VkFormat format
,
1580 const struct vk_format_description
*desc
,
1581 int first_non_void
);
1582 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1583 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1584 uint32_t radv_translate_dbformat(VkFormat format
);
1585 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1586 const struct vk_format_description
*desc
,
1587 int first_non_void
);
1588 uint32_t radv_translate_tex_numformat(VkFormat format
,
1589 const struct vk_format_description
*desc
,
1590 int first_non_void
);
1591 bool radv_format_pack_clear_color(VkFormat format
,
1592 uint32_t clear_vals
[2],
1593 VkClearColorValue
*value
);
1594 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1595 bool radv_dcc_formats_compatible(VkFormat format1
,
1597 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1599 struct radv_image_plane
{
1601 struct radeon_surf surface
;
1607 /* The original VkFormat provided by the client. This may not match any
1608 * of the actual surface formats.
1611 VkImageAspectFlags aspects
;
1612 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1613 struct ac_surf_info info
;
1614 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1615 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1620 unsigned queue_family_mask
;
1624 /* Set when bound */
1625 struct radeon_winsys_bo
*bo
;
1626 VkDeviceSize offset
;
1627 uint64_t dcc_offset
;
1628 uint64_t htile_offset
;
1629 bool tc_compatible_htile
;
1630 bool tc_compatible_cmask
;
1632 uint64_t cmask_offset
;
1633 uint64_t fmask_offset
;
1634 uint64_t clear_value_offset
;
1635 uint64_t fce_pred_offset
;
1636 uint64_t dcc_pred_offset
;
1639 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1640 * stored at this offset is UINT_MAX, the driver will emit
1641 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1642 * SET_CONTEXT_REG packet.
1644 uint64_t tc_compat_zrange_offset
;
1646 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1647 VkDeviceMemory owned_memory
;
1649 unsigned plane_count
;
1650 struct radv_image_plane planes
[0];
1653 /* Whether the image has a htile that is known consistent with the contents of
1655 bool radv_layout_has_htile(const struct radv_image
*image
,
1656 VkImageLayout layout
,
1657 bool in_render_loop
,
1658 unsigned queue_mask
);
1660 /* Whether the image has a htile that is known consistent with the contents of
1661 * the image and is allowed to be in compressed form.
1663 * If this is false reads that don't use the htile should be able to return
1666 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1667 VkImageLayout layout
,
1668 bool in_render_loop
,
1669 unsigned queue_mask
);
1671 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1672 VkImageLayout layout
,
1673 bool in_render_loop
,
1674 unsigned queue_mask
);
1676 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1677 const struct radv_image
*image
,
1678 VkImageLayout layout
,
1679 bool in_render_loop
,
1680 unsigned queue_mask
);
1683 * Return whether the image has CMASK metadata for color surfaces.
1686 radv_image_has_cmask(const struct radv_image
*image
)
1688 return image
->cmask_offset
;
1692 * Return whether the image has FMASK metadata for color surfaces.
1695 radv_image_has_fmask(const struct radv_image
*image
)
1697 return image
->fmask_offset
;
1701 * Return whether the image has DCC metadata for color surfaces.
1704 radv_image_has_dcc(const struct radv_image
*image
)
1706 return image
->planes
[0].surface
.dcc_size
;
1710 * Return whether the image is TC-compatible CMASK.
1713 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1715 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1719 * Return whether DCC metadata is enabled for a level.
1722 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1724 return radv_image_has_dcc(image
) &&
1725 level
< image
->planes
[0].surface
.num_dcc_levels
;
1729 * Return whether the image has CB metadata.
1732 radv_image_has_CB_metadata(const struct radv_image
*image
)
1734 return radv_image_has_cmask(image
) ||
1735 radv_image_has_fmask(image
) ||
1736 radv_image_has_dcc(image
);
1740 * Return whether the image has HTILE metadata for depth surfaces.
1743 radv_image_has_htile(const struct radv_image
*image
)
1745 return image
->planes
[0].surface
.htile_size
;
1749 * Return whether HTILE metadata is enabled for a level.
1752 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1754 return radv_image_has_htile(image
) && level
== 0;
1758 * Return whether the image is TC-compatible HTILE.
1761 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1763 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1766 static inline uint64_t
1767 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1768 uint32_t base_level
)
1770 uint64_t va
= radv_buffer_get_va(image
->bo
);
1771 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1775 static inline uint64_t
1776 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1777 uint32_t base_level
)
1779 uint64_t va
= radv_buffer_get_va(image
->bo
);
1780 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1784 static inline uint64_t
1785 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1786 uint32_t base_level
)
1788 uint64_t va
= radv_buffer_get_va(image
->bo
);
1789 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1793 static inline uint64_t
1794 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1795 uint32_t base_level
)
1797 uint64_t va
= radv_buffer_get_va(image
->bo
);
1798 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1802 static inline uint64_t
1803 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1804 uint32_t base_level
)
1806 uint64_t va
= radv_buffer_get_va(image
->bo
);
1807 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1811 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1813 static inline uint32_t
1814 radv_get_layerCount(const struct radv_image
*image
,
1815 const VkImageSubresourceRange
*range
)
1817 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1818 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1821 static inline uint32_t
1822 radv_get_levelCount(const struct radv_image
*image
,
1823 const VkImageSubresourceRange
*range
)
1825 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1826 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1829 struct radeon_bo_metadata
;
1831 radv_init_metadata(struct radv_device
*device
,
1832 struct radv_image
*image
,
1833 struct radeon_bo_metadata
*metadata
);
1836 radv_image_override_offset_stride(struct radv_device
*device
,
1837 struct radv_image
*image
,
1838 uint64_t offset
, uint32_t stride
);
1840 union radv_descriptor
{
1842 uint32_t plane0_descriptor
[8];
1843 uint32_t fmask_descriptor
[8];
1846 uint32_t plane_descriptors
[3][8];
1850 struct radv_image_view
{
1851 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1852 struct radeon_winsys_bo
*bo
;
1854 VkImageViewType type
;
1855 VkImageAspectFlags aspect_mask
;
1858 bool multiple_planes
;
1859 uint32_t base_layer
;
1860 uint32_t layer_count
;
1862 uint32_t level_count
;
1863 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1865 union radv_descriptor descriptor
;
1867 /* Descriptor for use as a storage image as opposed to a sampled image.
1868 * This has a few differences for cube maps (e.g. type).
1870 union radv_descriptor storage_descriptor
;
1873 struct radv_image_create_info
{
1874 const VkImageCreateInfo
*vk_info
;
1876 bool no_metadata_planes
;
1877 const struct radeon_bo_metadata
*bo_metadata
;
1880 VkResult
radv_image_create(VkDevice _device
,
1881 const struct radv_image_create_info
*info
,
1882 const VkAllocationCallbacks
* alloc
,
1886 radv_image_from_gralloc(VkDevice device_h
,
1887 const VkImageCreateInfo
*base_info
,
1888 const VkNativeBufferANDROID
*gralloc_info
,
1889 const VkAllocationCallbacks
*alloc
,
1890 VkImage
*out_image_h
);
1892 struct radv_image_view_extra_create_info
{
1893 bool disable_compression
;
1896 void radv_image_view_init(struct radv_image_view
*view
,
1897 struct radv_device
*device
,
1898 const VkImageViewCreateInfo
*pCreateInfo
,
1899 const struct radv_image_view_extra_create_info
* extra_create_info
);
1901 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1903 struct radv_sampler_ycbcr_conversion
{
1905 VkSamplerYcbcrModelConversion ycbcr_model
;
1906 VkSamplerYcbcrRange ycbcr_range
;
1907 VkComponentMapping components
;
1908 VkChromaLocation chroma_offsets
[2];
1909 VkFilter chroma_filter
;
1912 struct radv_buffer_view
{
1913 struct radeon_winsys_bo
*bo
;
1915 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1918 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1919 struct radv_device
*device
,
1920 const VkBufferViewCreateInfo
* pCreateInfo
);
1922 static inline struct VkExtent3D
1923 radv_sanitize_image_extent(const VkImageType imageType
,
1924 const struct VkExtent3D imageExtent
)
1926 switch (imageType
) {
1927 case VK_IMAGE_TYPE_1D
:
1928 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1929 case VK_IMAGE_TYPE_2D
:
1930 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1931 case VK_IMAGE_TYPE_3D
:
1934 unreachable("invalid image type");
1938 static inline struct VkOffset3D
1939 radv_sanitize_image_offset(const VkImageType imageType
,
1940 const struct VkOffset3D imageOffset
)
1942 switch (imageType
) {
1943 case VK_IMAGE_TYPE_1D
:
1944 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1945 case VK_IMAGE_TYPE_2D
:
1946 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1947 case VK_IMAGE_TYPE_3D
:
1950 unreachable("invalid image type");
1955 radv_image_extent_compare(const struct radv_image
*image
,
1956 const VkExtent3D
*extent
)
1958 if (extent
->width
!= image
->info
.width
||
1959 extent
->height
!= image
->info
.height
||
1960 extent
->depth
!= image
->info
.depth
)
1965 struct radv_sampler
{
1967 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
1970 struct radv_framebuffer
{
1975 uint32_t attachment_count
;
1976 struct radv_image_view
*attachments
[0];
1979 struct radv_subpass_barrier
{
1980 VkPipelineStageFlags src_stage_mask
;
1981 VkAccessFlags src_access_mask
;
1982 VkAccessFlags dst_access_mask
;
1985 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
1986 const struct radv_subpass_barrier
*barrier
);
1988 struct radv_subpass_attachment
{
1989 uint32_t attachment
;
1990 VkImageLayout layout
;
1991 bool in_render_loop
;
1994 struct radv_subpass
{
1995 uint32_t attachment_count
;
1996 struct radv_subpass_attachment
* attachments
;
1998 uint32_t input_count
;
1999 uint32_t color_count
;
2000 struct radv_subpass_attachment
* input_attachments
;
2001 struct radv_subpass_attachment
* color_attachments
;
2002 struct radv_subpass_attachment
* resolve_attachments
;
2003 struct radv_subpass_attachment
* depth_stencil_attachment
;
2004 struct radv_subpass_attachment
* ds_resolve_attachment
;
2005 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2006 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2008 /** Subpass has at least one color resolve attachment */
2009 bool has_color_resolve
;
2011 /** Subpass has at least one color attachment */
2014 struct radv_subpass_barrier start_barrier
;
2017 VkSampleCountFlagBits max_sample_count
;
2021 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2023 struct radv_render_pass_attachment
{
2026 VkAttachmentLoadOp load_op
;
2027 VkAttachmentLoadOp stencil_load_op
;
2028 VkImageLayout initial_layout
;
2029 VkImageLayout final_layout
;
2031 /* The subpass id in which the attachment will be used first/last. */
2032 uint32_t first_subpass_idx
;
2033 uint32_t last_subpass_idx
;
2036 struct radv_render_pass
{
2037 uint32_t attachment_count
;
2038 uint32_t subpass_count
;
2039 struct radv_subpass_attachment
* subpass_attachments
;
2040 struct radv_render_pass_attachment
* attachments
;
2041 struct radv_subpass_barrier end_barrier
;
2042 struct radv_subpass subpasses
[0];
2045 VkResult
radv_device_init_meta(struct radv_device
*device
);
2046 void radv_device_finish_meta(struct radv_device
*device
);
2048 struct radv_query_pool
{
2049 struct radeon_winsys_bo
*bo
;
2051 uint32_t availability_offset
;
2055 uint32_t pipeline_stats_mask
;
2058 struct radv_semaphore
{
2059 /* use a winsys sem for non-exportable */
2060 struct radeon_winsys_sem
*sem
;
2062 uint32_t temp_syncobj
;
2065 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2066 VkPipelineBindPoint bind_point
,
2067 struct radv_descriptor_set
*set
,
2071 radv_update_descriptor_sets(struct radv_device
*device
,
2072 struct radv_cmd_buffer
*cmd_buffer
,
2073 VkDescriptorSet overrideSet
,
2074 uint32_t descriptorWriteCount
,
2075 const VkWriteDescriptorSet
*pDescriptorWrites
,
2076 uint32_t descriptorCopyCount
,
2077 const VkCopyDescriptorSet
*pDescriptorCopies
);
2080 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2081 struct radv_cmd_buffer
*cmd_buffer
,
2082 struct radv_descriptor_set
*set
,
2083 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2086 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2087 VkPipelineBindPoint pipelineBindPoint
,
2088 VkPipelineLayout _layout
,
2090 uint32_t descriptorWriteCount
,
2091 const VkWriteDescriptorSet
*pDescriptorWrites
);
2093 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2094 struct radv_image
*image
,
2095 const VkImageSubresourceRange
*range
, uint32_t value
);
2097 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2098 struct radv_image
*image
,
2099 const VkImageSubresourceRange
*range
);
2102 struct radeon_winsys_fence
*fence
;
2103 struct wsi_fence
*fence_wsi
;
2106 uint32_t temp_syncobj
;
2109 /* radv_nir_to_llvm.c */
2110 struct radv_shader_info
;
2111 struct radv_nir_compiler_options
;
2113 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2114 struct nir_shader
*geom_shader
,
2115 struct radv_shader_binary
**rbinary
,
2116 struct radv_shader_info
*info
,
2117 const struct radv_nir_compiler_options
*option
);
2119 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2120 struct radv_shader_binary
**rbinary
,
2121 struct radv_shader_info
*info
,
2122 struct nir_shader
*const *nir
,
2124 const struct radv_nir_compiler_options
*options
);
2126 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2127 gl_shader_stage stage
,
2128 const struct nir_shader
*nir
);
2130 /* radv_shader_info.h */
2131 struct radv_shader_info
;
2132 struct radv_shader_variant_key
;
2134 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2135 const struct radv_pipeline_layout
*layout
,
2136 const struct radv_shader_variant_key
*key
,
2137 struct radv_shader_info
*info
);
2139 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2141 struct radeon_winsys_sem
;
2143 uint64_t radv_get_current_time(void);
2145 static inline uint32_t
2146 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2149 case 0: /* GL_POINTS */
2151 case 1: /* GL_LINES */
2152 case 3: /* GL_LINE_STRIP */
2154 case 4: /* GL_TRIANGLES */
2155 case 5: /* GL_TRIANGLE_STRIP */
2157 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2159 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2161 case 7: /* GL_QUADS */
2162 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2169 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2171 static inline struct __radv_type * \
2172 __radv_type ## _from_handle(__VkType _handle) \
2174 return (struct __radv_type *) _handle; \
2177 static inline __VkType \
2178 __radv_type ## _to_handle(struct __radv_type *_obj) \
2180 return (__VkType) _obj; \
2183 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2185 static inline struct __radv_type * \
2186 __radv_type ## _from_handle(__VkType _handle) \
2188 return (struct __radv_type *)(uintptr_t) _handle; \
2191 static inline __VkType \
2192 __radv_type ## _to_handle(struct __radv_type *_obj) \
2194 return (__VkType)(uintptr_t) _obj; \
2197 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2198 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2200 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2201 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2202 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2203 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2204 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2206 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2208 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2209 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2210 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2211 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2212 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2213 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2214 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2215 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2216 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2217 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2218 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2219 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2220 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2221 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2222 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2223 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2224 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2225 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2226 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2227 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2229 #endif /* RADV_PRIVATE_H */