2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
82 #include "radv_entrypoints.h"
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
88 unsigned img_format
:9;
90 /* Various formats are only supported with workarounds for vertex fetch,
91 * and some 32_32_32 formats are supported natively, but only for buffers
92 * (possibly with some image support, actually, but no filtering). */
96 #include "gfx10_format_table.h"
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
109 RADV_MEM_TYPE_GTT_CACHED
,
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115 static inline uint32_t
116 align_u32(uint32_t v
, uint32_t a
)
118 assert(a
!= 0 && a
== (a
& -a
));
119 return (v
+ a
- 1) & ~(a
- 1);
122 static inline uint32_t
123 align_u32_npot(uint32_t v
, uint32_t a
)
125 return (v
+ a
- 1) / a
* a
;
128 static inline uint64_t
129 align_u64(uint64_t v
, uint64_t a
)
131 assert(a
!= 0 && a
== (a
& -a
));
132 return (v
+ a
- 1) & ~(a
- 1);
135 static inline int32_t
136 align_i32(int32_t v
, int32_t a
)
138 assert(a
!= 0 && a
== (a
& -a
));
139 return (v
+ a
- 1) & ~(a
- 1);
142 /** Alignment must be a power of 2. */
144 radv_is_aligned(uintmax_t n
, uintmax_t a
)
146 assert(a
== (a
& -a
));
147 return (n
& (a
- 1)) == 0;
150 static inline uint32_t
151 round_up_u32(uint32_t v
, uint32_t a
)
153 return (v
+ a
- 1) / a
;
156 static inline uint64_t
157 round_up_u64(uint64_t v
, uint64_t a
)
159 return (v
+ a
- 1) / a
;
162 static inline uint32_t
163 radv_minify(uint32_t n
, uint32_t levels
)
165 if (unlikely(n
== 0))
168 return MAX2(n
>> levels
, 1);
171 radv_clamp_f(float f
, float min
, float max
)
184 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
186 if (*inout_mask
& clear_mask
) {
187 *inout_mask
&= ~clear_mask
;
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
209 struct radv_image_view
;
210 struct radv_instance
;
212 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
214 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
215 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
217 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
218 radv_printflike(3, 4);
219 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
220 void radv_loge_v(const char *format
, va_list va
);
221 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
222 void radv_logi_v(const char *format
, va_list va
);
225 * Print a FINISHME message, including its source location.
227 #define radv_finishme(format, ...) \
229 static bool reported = false; \
231 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 /* A non-fatal assert. Useful for debugging. */
238 #define radv_assert(x) ({ \
239 if (unlikely(!(x))) \
240 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
243 #define radv_assert(x)
246 #define stub_return(v) \
248 radv_finishme("stub %s", __func__); \
254 radv_finishme("stub %s", __func__); \
258 void *radv_lookup_entrypoint_unchecked(const char *name
);
259 void *radv_lookup_entrypoint_checked(const char *name
,
260 uint32_t core_version
,
261 const struct radv_instance_extension_table
*instance
,
262 const struct radv_device_extension_table
*device
);
263 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
264 uint32_t core_version
,
265 const struct radv_instance_extension_table
*instance
);
267 struct radv_physical_device
{
268 VK_LOADER_DATA _loader_data
;
270 struct radv_instance
* instance
;
272 struct radeon_winsys
*ws
;
273 struct radeon_info rad_info
;
274 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
275 uint8_t driver_uuid
[VK_UUID_SIZE
];
276 uint8_t device_uuid
[VK_UUID_SIZE
];
277 uint8_t cache_uuid
[VK_UUID_SIZE
];
281 struct wsi_device wsi_device
;
283 bool rbplus_allowed
; /* if RB+ is allowed */
284 bool has_tc_compat_zrange_bug
;
286 bool out_of_order_rast_allowed
;
288 /* Whether DCC should be enabled for MSAA textures. */
289 bool dcc_msaa_allowed
;
291 /* Whether to enable the AMD_shader_ballot extension */
292 bool use_shader_ballot
;
294 /* Number of threads per wave. */
295 uint8_t ps_wave_size
;
296 uint8_t cs_wave_size
;
297 uint8_t ge_wave_size
;
299 /* This is the drivers on-disk cache used as a fallback as opposed to
300 * the pipeline cache defined by apps.
302 struct disk_cache
* disk_cache
;
304 VkPhysicalDeviceMemoryProperties memory_properties
;
305 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
307 drmPciBusInfo bus_info
;
309 struct radv_device_extension_table supported_extensions
;
312 struct radv_instance
{
313 VK_LOADER_DATA _loader_data
;
315 VkAllocationCallbacks alloc
;
318 int physicalDeviceCount
;
319 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
321 uint64_t debug_flags
;
322 uint64_t perftest_flags
;
324 struct vk_debug_report_instance debug_report_callbacks
;
326 struct radv_instance_extension_table enabled_extensions
;
328 struct driOptionCache dri_options
;
329 struct driOptionCache available_dri_options
;
332 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
333 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
335 bool radv_instance_extension_supported(const char *name
);
336 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
337 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
342 struct radv_pipeline_cache
{
343 struct radv_device
* device
;
344 pthread_mutex_t mutex
;
348 uint32_t kernel_count
;
349 struct cache_entry
** hash_table
;
352 VkAllocationCallbacks alloc
;
355 struct radv_pipeline_key
{
356 uint32_t instance_rate_inputs
;
357 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
358 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
359 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
360 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
361 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
362 uint64_t vertex_alpha_adjust
;
363 uint32_t vertex_post_shuffle
;
364 unsigned tess_input_vertices
;
368 uint8_t log2_ps_iter_samples
;
370 uint32_t has_multiview_view_index
: 1;
371 uint32_t optimisations_disabled
: 1;
374 struct radv_shader_binary
;
375 struct radv_shader_variant
;
378 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
379 struct radv_device
*device
);
381 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
383 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
384 const void *data
, size_t size
);
387 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
388 struct radv_pipeline_cache
*cache
,
389 const unsigned char *sha1
,
390 struct radv_shader_variant
**variants
,
391 bool *found_in_application_cache
);
394 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
395 struct radv_pipeline_cache
*cache
,
396 const unsigned char *sha1
,
397 struct radv_shader_variant
**variants
,
398 struct radv_shader_binary
*const *binaries
);
400 enum radv_blit_ds_layout
{
401 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
402 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
403 RADV_BLIT_DS_LAYOUT_COUNT
,
406 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
408 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
411 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
413 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
416 enum radv_meta_dst_layout
{
417 RADV_META_DST_LAYOUT_GENERAL
,
418 RADV_META_DST_LAYOUT_OPTIMAL
,
419 RADV_META_DST_LAYOUT_COUNT
,
422 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
424 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
427 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
429 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
432 struct radv_meta_state
{
433 VkAllocationCallbacks alloc
;
435 struct radv_pipeline_cache cache
;
438 * For on-demand pipeline creation, makes sure that
439 * only one thread tries to build a pipeline at the same time.
444 * Use array element `i` for images with `2^i` samples.
447 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
448 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
450 VkRenderPass depthstencil_rp
;
451 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
452 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
453 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
454 } clear
[1 + MAX_SAMPLES_LOG2
];
456 VkPipelineLayout clear_color_p_layout
;
457 VkPipelineLayout clear_depth_p_layout
;
459 /* Optimized compute fast HTILE clear for stencil or depth only. */
460 VkPipeline clear_htile_mask_pipeline
;
461 VkPipelineLayout clear_htile_mask_p_layout
;
462 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
465 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
467 /** Pipeline that blits from a 1D image. */
468 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
470 /** Pipeline that blits from a 2D image. */
471 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
473 /** Pipeline that blits from a 3D image. */
474 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
476 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
477 VkPipeline depth_only_1d_pipeline
;
478 VkPipeline depth_only_2d_pipeline
;
479 VkPipeline depth_only_3d_pipeline
;
481 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
482 VkPipeline stencil_only_1d_pipeline
;
483 VkPipeline stencil_only_2d_pipeline
;
484 VkPipeline stencil_only_3d_pipeline
;
485 VkPipelineLayout pipeline_layout
;
486 VkDescriptorSetLayout ds_layout
;
490 VkPipelineLayout p_layouts
[5];
491 VkDescriptorSetLayout ds_layouts
[5];
492 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
494 VkPipeline depth_only_pipeline
[5];
496 VkPipeline stencil_only_pipeline
[5];
497 } blit2d
[1 + MAX_SAMPLES_LOG2
];
499 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
500 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
501 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
504 VkPipelineLayout img_p_layout
;
505 VkDescriptorSetLayout img_ds_layout
;
507 VkPipeline pipeline_3d
;
510 VkPipelineLayout img_p_layout
;
511 VkDescriptorSetLayout img_ds_layout
;
513 VkPipeline pipeline_3d
;
516 VkPipelineLayout img_p_layout
;
517 VkDescriptorSetLayout img_ds_layout
;
521 VkPipelineLayout img_p_layout
;
522 VkDescriptorSetLayout img_ds_layout
;
524 VkPipeline pipeline_3d
;
527 VkPipelineLayout img_p_layout
;
528 VkDescriptorSetLayout img_ds_layout
;
532 VkPipelineLayout img_p_layout
;
533 VkDescriptorSetLayout img_ds_layout
;
535 VkPipeline pipeline_3d
;
538 VkPipelineLayout img_p_layout
;
539 VkDescriptorSetLayout img_ds_layout
;
544 VkPipelineLayout p_layout
;
545 VkPipeline pipeline
[NUM_META_FS_KEYS
];
546 VkRenderPass pass
[NUM_META_FS_KEYS
];
550 VkDescriptorSetLayout ds_layout
;
551 VkPipelineLayout p_layout
;
554 VkPipeline i_pipeline
;
555 VkPipeline srgb_pipeline
;
556 } rc
[MAX_SAMPLES_LOG2
];
558 VkPipeline depth_zero_pipeline
;
560 VkPipeline average_pipeline
;
561 VkPipeline max_pipeline
;
562 VkPipeline min_pipeline
;
563 } depth
[MAX_SAMPLES_LOG2
];
565 VkPipeline stencil_zero_pipeline
;
567 VkPipeline max_pipeline
;
568 VkPipeline min_pipeline
;
569 } stencil
[MAX_SAMPLES_LOG2
];
573 VkDescriptorSetLayout ds_layout
;
574 VkPipelineLayout p_layout
;
577 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
578 VkPipeline pipeline
[NUM_META_FS_KEYS
];
579 } rc
[MAX_SAMPLES_LOG2
];
581 VkRenderPass depth_render_pass
;
582 VkPipeline depth_zero_pipeline
;
584 VkPipeline average_pipeline
;
585 VkPipeline max_pipeline
;
586 VkPipeline min_pipeline
;
587 } depth
[MAX_SAMPLES_LOG2
];
589 VkRenderPass stencil_render_pass
;
590 VkPipeline stencil_zero_pipeline
;
592 VkPipeline max_pipeline
;
593 VkPipeline min_pipeline
;
594 } stencil
[MAX_SAMPLES_LOG2
];
598 VkPipelineLayout p_layout
;
599 VkPipeline decompress_pipeline
;
600 VkPipeline resummarize_pipeline
;
602 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
605 VkPipelineLayout p_layout
;
606 VkPipeline cmask_eliminate_pipeline
;
607 VkPipeline fmask_decompress_pipeline
;
608 VkPipeline dcc_decompress_pipeline
;
611 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
612 VkPipelineLayout dcc_decompress_compute_p_layout
;
613 VkPipeline dcc_decompress_compute_pipeline
;
617 VkPipelineLayout fill_p_layout
;
618 VkPipelineLayout copy_p_layout
;
619 VkDescriptorSetLayout fill_ds_layout
;
620 VkDescriptorSetLayout copy_ds_layout
;
621 VkPipeline fill_pipeline
;
622 VkPipeline copy_pipeline
;
626 VkDescriptorSetLayout ds_layout
;
627 VkPipelineLayout p_layout
;
628 VkPipeline occlusion_query_pipeline
;
629 VkPipeline pipeline_statistics_query_pipeline
;
630 VkPipeline tfb_query_pipeline
;
634 VkDescriptorSetLayout ds_layout
;
635 VkPipelineLayout p_layout
;
636 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
641 #define RADV_QUEUE_GENERAL 0
642 #define RADV_QUEUE_COMPUTE 1
643 #define RADV_QUEUE_TRANSFER 2
645 #define RADV_MAX_QUEUE_FAMILIES 3
647 enum ring_type
radv_queue_family_to_ring(int f
);
650 VK_LOADER_DATA _loader_data
;
651 struct radv_device
* device
;
652 struct radeon_winsys_ctx
*hw_ctx
;
653 enum radeon_ctx_priority priority
;
654 uint32_t queue_family_index
;
656 VkDeviceQueueCreateFlags flags
;
658 uint32_t scratch_size
;
659 uint32_t compute_scratch_size
;
660 uint32_t esgs_ring_size
;
661 uint32_t gsvs_ring_size
;
663 bool has_sample_positions
;
665 struct radeon_winsys_bo
*scratch_bo
;
666 struct radeon_winsys_bo
*descriptor_bo
;
667 struct radeon_winsys_bo
*compute_scratch_bo
;
668 struct radeon_winsys_bo
*esgs_ring_bo
;
669 struct radeon_winsys_bo
*gsvs_ring_bo
;
670 struct radeon_winsys_bo
*tess_rings_bo
;
671 struct radeon_cmdbuf
*initial_preamble_cs
;
672 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
673 struct radeon_cmdbuf
*continue_preamble_cs
;
676 struct radv_bo_list
{
677 struct radv_winsys_bo_list list
;
679 pthread_mutex_t mutex
;
683 VK_LOADER_DATA _loader_data
;
685 VkAllocationCallbacks alloc
;
687 struct radv_instance
* instance
;
688 struct radeon_winsys
*ws
;
690 struct radv_meta_state meta_state
;
692 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
693 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
694 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
696 bool always_use_syncobj
;
699 uint32_t tess_offchip_block_dw_size
;
700 uint32_t scratch_waves
;
701 uint32_t dispatch_initiator
;
703 uint32_t gs_table_depth
;
705 /* MSAA sample locations.
706 * The first index is the sample index.
707 * The second index is the coordinate: X, Y. */
708 float sample_locations_1x
[1][2];
709 float sample_locations_2x
[2][2];
710 float sample_locations_4x
[4][2];
711 float sample_locations_8x
[8][2];
714 uint32_t gfx_init_size_dw
;
715 struct radeon_winsys_bo
*gfx_init
;
717 struct radeon_winsys_bo
*trace_bo
;
718 uint32_t *trace_id_ptr
;
720 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
721 bool keep_shader_info
;
723 struct radv_physical_device
*physical_device
;
725 /* Backup in-memory cache to be used if the app doesn't provide one */
726 struct radv_pipeline_cache
* mem_cache
;
729 * use different counters so MSAA MRTs get consecutive surface indices,
730 * even if MASK is allocated in between.
732 uint32_t image_mrt_offset_counter
;
733 uint32_t fmask_mrt_offset_counter
;
734 struct list_head shader_slabs
;
735 mtx_t shader_slab_mutex
;
737 /* For detecting VM faults reported by dmesg. */
738 uint64_t dmesg_timestamp
;
740 struct radv_device_extension_table enabled_extensions
;
742 /* Whether the app has enabled the robustBufferAccess feature. */
743 bool robust_buffer_access
;
745 /* Whether the driver uses a global BO list. */
746 bool use_global_bo_list
;
748 struct radv_bo_list bo_list
;
750 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
754 struct radv_device_memory
{
755 struct radeon_winsys_bo
*bo
;
756 /* for dedicated allocations */
757 struct radv_image
*image
;
758 struct radv_buffer
*buffer
;
760 VkDeviceSize map_size
;
766 struct radv_descriptor_range
{
771 struct radv_descriptor_set
{
772 const struct radv_descriptor_set_layout
*layout
;
775 struct radeon_winsys_bo
*bo
;
777 uint32_t *mapped_ptr
;
778 struct radv_descriptor_range
*dynamic_descriptors
;
780 struct radeon_winsys_bo
*descriptors
[0];
783 struct radv_push_descriptor_set
785 struct radv_descriptor_set set
;
789 struct radv_descriptor_pool_entry
{
792 struct radv_descriptor_set
*set
;
795 struct radv_descriptor_pool
{
796 struct radeon_winsys_bo
*bo
;
798 uint64_t current_offset
;
801 uint8_t *host_memory_base
;
802 uint8_t *host_memory_ptr
;
803 uint8_t *host_memory_end
;
805 uint32_t entry_count
;
806 uint32_t max_entry_count
;
807 struct radv_descriptor_pool_entry entries
[0];
810 struct radv_descriptor_update_template_entry
{
811 VkDescriptorType descriptor_type
;
813 /* The number of descriptors to update */
814 uint32_t descriptor_count
;
816 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
819 /* In dwords. Not valid/used for dynamic descriptors */
822 uint32_t buffer_offset
;
824 /* Only valid for combined image samplers and samplers */
826 uint8_t sampler_offset
;
832 /* For push descriptors */
833 const uint32_t *immutable_samplers
;
836 struct radv_descriptor_update_template
{
837 uint32_t entry_count
;
838 VkPipelineBindPoint bind_point
;
839 struct radv_descriptor_update_template_entry entry
[0];
845 VkBufferUsageFlags usage
;
846 VkBufferCreateFlags flags
;
849 struct radeon_winsys_bo
* bo
;
855 enum radv_dynamic_state_bits
{
856 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
857 RADV_DYNAMIC_SCISSOR
= 1 << 1,
858 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
859 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
860 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
861 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
862 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
863 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
864 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
865 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
866 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
867 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
870 enum radv_cmd_dirty_bits
{
871 /* Keep the dynamic state dirty bits in sync with
872 * enum radv_dynamic_state_bits */
873 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
874 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
875 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
876 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
877 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
878 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
879 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
880 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
881 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
882 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
883 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
884 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
885 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
886 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
887 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
888 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
889 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
892 enum radv_cmd_flush_bits
{
893 /* Instruction cache. */
894 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
895 /* Scalar L1 cache. */
896 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
897 /* Vector L1 cache. */
898 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
899 /* L2 cache + L2 metadata cache writeback & invalidate.
900 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
901 RADV_CMD_FLAG_INV_L2
= 1 << 3,
902 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
903 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
904 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
905 RADV_CMD_FLAG_WB_L2
= 1 << 4,
906 /* Framebuffer caches */
907 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
908 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
909 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
910 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
911 /* Engine synchronization. */
912 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
913 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
914 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
915 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
916 /* Pipeline query controls. */
917 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
918 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
919 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
921 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
922 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
923 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
924 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
927 struct radv_vertex_binding
{
928 struct radv_buffer
* buffer
;
932 struct radv_streamout_binding
{
933 struct radv_buffer
*buffer
;
938 struct radv_streamout_state
{
939 /* Mask of bound streamout buffers. */
940 uint8_t enabled_mask
;
942 /* External state that comes from the last vertex stage, it must be
943 * set explicitely when binding a new graphics pipeline.
945 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
946 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
948 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
949 uint32_t hw_enabled_mask
;
951 /* State of VGT_STRMOUT_(CONFIG|EN) */
952 bool streamout_enabled
;
955 struct radv_viewport_state
{
957 VkViewport viewports
[MAX_VIEWPORTS
];
960 struct radv_scissor_state
{
962 VkRect2D scissors
[MAX_SCISSORS
];
965 struct radv_discard_rectangle_state
{
967 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
970 struct radv_sample_locations_state
{
971 VkSampleCountFlagBits per_pixel
;
972 VkExtent2D grid_size
;
974 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
977 struct radv_dynamic_state
{
979 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
980 * Defines the set of saved dynamic state.
984 struct radv_viewport_state viewport
;
986 struct radv_scissor_state scissor
;
996 float blend_constants
[4];
1006 } stencil_compare_mask
;
1011 } stencil_write_mask
;
1016 } stencil_reference
;
1018 struct radv_discard_rectangle_state discard_rectangle
;
1020 struct radv_sample_locations_state sample_location
;
1023 extern const struct radv_dynamic_state default_dynamic_state
;
1026 radv_get_debug_option_name(int id
);
1029 radv_get_perftest_option_name(int id
);
1031 struct radv_color_buffer_info
{
1032 uint64_t cb_color_base
;
1033 uint64_t cb_color_cmask
;
1034 uint64_t cb_color_fmask
;
1035 uint64_t cb_dcc_base
;
1036 uint32_t cb_color_slice
;
1037 uint32_t cb_color_view
;
1038 uint32_t cb_color_info
;
1039 uint32_t cb_color_attrib
;
1040 uint32_t cb_color_attrib2
; /* GFX9 and later */
1041 uint32_t cb_color_attrib3
; /* GFX10 and later */
1042 uint32_t cb_dcc_control
;
1043 uint32_t cb_color_cmask_slice
;
1044 uint32_t cb_color_fmask_slice
;
1046 uint32_t cb_color_pitch
; // GFX6-GFX8
1047 uint32_t cb_mrt_epitch
; // GFX9+
1051 struct radv_ds_buffer_info
{
1052 uint64_t db_z_read_base
;
1053 uint64_t db_stencil_read_base
;
1054 uint64_t db_z_write_base
;
1055 uint64_t db_stencil_write_base
;
1056 uint64_t db_htile_data_base
;
1057 uint32_t db_depth_info
;
1059 uint32_t db_stencil_info
;
1060 uint32_t db_depth_view
;
1061 uint32_t db_depth_size
;
1062 uint32_t db_depth_slice
;
1063 uint32_t db_htile_surface
;
1064 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1065 uint32_t db_z_info2
; /* GFX9 only */
1066 uint32_t db_stencil_info2
; /* GFX9 only */
1071 radv_initialise_color_surface(struct radv_device
*device
,
1072 struct radv_color_buffer_info
*cb
,
1073 struct radv_image_view
*iview
);
1075 radv_initialise_ds_surface(struct radv_device
*device
,
1076 struct radv_ds_buffer_info
*ds
,
1077 struct radv_image_view
*iview
);
1080 * Attachment state when recording a renderpass instance.
1082 * The clear value is valid only if there exists a pending clear.
1084 struct radv_attachment_state
{
1085 VkImageAspectFlags pending_clear_aspects
;
1086 uint32_t cleared_views
;
1087 VkClearValue clear_value
;
1088 VkImageLayout current_layout
;
1089 bool current_in_render_loop
;
1090 struct radv_sample_locations_state sample_location
;
1093 struct radv_color_buffer_info cb
;
1094 struct radv_ds_buffer_info ds
;
1096 struct radv_image_view
*iview
;
1099 struct radv_descriptor_state
{
1100 struct radv_descriptor_set
*sets
[MAX_SETS
];
1103 struct radv_push_descriptor_set push_set
;
1105 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1108 struct radv_subpass_sample_locs_state
{
1109 uint32_t subpass_idx
;
1110 struct radv_sample_locations_state sample_location
;
1113 struct radv_cmd_state
{
1114 /* Vertex descriptors */
1121 uint32_t prefetch_L2_mask
;
1123 struct radv_pipeline
* pipeline
;
1124 struct radv_pipeline
* emitted_pipeline
;
1125 struct radv_pipeline
* compute_pipeline
;
1126 struct radv_pipeline
* emitted_compute_pipeline
;
1127 struct radv_framebuffer
* framebuffer
;
1128 struct radv_render_pass
* pass
;
1129 const struct radv_subpass
* subpass
;
1130 struct radv_dynamic_state dynamic
;
1131 struct radv_attachment_state
* attachments
;
1132 struct radv_streamout_state streamout
;
1133 VkRect2D render_area
;
1135 uint32_t num_subpass_sample_locs
;
1136 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1139 struct radv_buffer
*index_buffer
;
1140 uint64_t index_offset
;
1141 uint32_t index_type
;
1142 uint32_t max_index_count
;
1144 int32_t last_index_type
;
1146 int32_t last_primitive_reset_en
;
1147 uint32_t last_primitive_reset_index
;
1148 enum radv_cmd_flush_bits flush_bits
;
1149 unsigned active_occlusion_queries
;
1150 bool perfect_occlusion_queries_enabled
;
1151 unsigned active_pipeline_queries
;
1154 uint32_t last_ia_multi_vgt_param
;
1156 uint32_t last_num_instances
;
1157 uint32_t last_first_instance
;
1158 uint32_t last_vertex_offset
;
1160 /* Whether CP DMA is busy/idle. */
1163 /* Conditional rendering info. */
1164 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1165 uint64_t predication_va
;
1167 bool context_roll_without_scissor_emitted
;
1170 struct radv_cmd_pool
{
1171 VkAllocationCallbacks alloc
;
1172 struct list_head cmd_buffers
;
1173 struct list_head free_cmd_buffers
;
1174 uint32_t queue_family_index
;
1177 struct radv_cmd_buffer_upload
{
1181 struct radeon_winsys_bo
*upload_bo
;
1182 struct list_head list
;
1185 enum radv_cmd_buffer_status
{
1186 RADV_CMD_BUFFER_STATUS_INVALID
,
1187 RADV_CMD_BUFFER_STATUS_INITIAL
,
1188 RADV_CMD_BUFFER_STATUS_RECORDING
,
1189 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1190 RADV_CMD_BUFFER_STATUS_PENDING
,
1193 struct radv_cmd_buffer
{
1194 VK_LOADER_DATA _loader_data
;
1196 struct radv_device
* device
;
1198 struct radv_cmd_pool
* pool
;
1199 struct list_head pool_link
;
1201 VkCommandBufferUsageFlags usage_flags
;
1202 VkCommandBufferLevel level
;
1203 enum radv_cmd_buffer_status status
;
1204 struct radeon_cmdbuf
*cs
;
1205 struct radv_cmd_state state
;
1206 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1207 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1208 uint32_t queue_family_index
;
1210 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1211 VkShaderStageFlags push_constant_stages
;
1212 struct radv_descriptor_set meta_push_descriptors
;
1214 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1216 struct radv_cmd_buffer_upload upload
;
1218 uint32_t scratch_size_needed
;
1219 uint32_t compute_scratch_size_needed
;
1220 uint32_t esgs_ring_size_needed
;
1221 uint32_t gsvs_ring_size_needed
;
1222 bool tess_rings_needed
;
1223 bool sample_positions_needed
;
1225 VkResult record_result
;
1227 uint64_t gfx9_fence_va
;
1228 uint32_t gfx9_fence_idx
;
1229 uint64_t gfx9_eop_bug_va
;
1232 * Whether a query pool has been resetted and we have to flush caches.
1234 bool pending_reset_query
;
1237 * Bitmask of pending active query flushes.
1239 enum radv_cmd_flush_bits active_query_flush_bits
;
1243 struct radv_image_view
;
1245 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1247 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1248 struct radeon_cmdbuf
*cs
);
1249 void si_emit_compute(struct radv_physical_device
*physical_device
,
1250 struct radeon_cmdbuf
*cs
);
1252 void cik_create_gfx_config(struct radv_device
*device
);
1254 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1255 int count
, const VkViewport
*viewports
);
1256 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1257 int count
, const VkRect2D
*scissors
,
1258 const VkViewport
*viewports
, bool can_use_guardband
);
1259 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1260 bool instanced_draw
, bool indirect_draw
,
1261 bool count_from_stream_output
,
1262 uint32_t draw_vertex_count
);
1263 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1264 enum chip_class chip_class
,
1266 unsigned event
, unsigned event_flags
,
1267 unsigned dst_sel
, unsigned data_sel
,
1270 uint64_t gfx9_eop_bug_va
);
1272 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1273 uint32_t ref
, uint32_t mask
);
1274 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1275 enum chip_class chip_class
,
1276 uint32_t *fence_ptr
, uint64_t va
,
1278 enum radv_cmd_flush_bits flush_bits
,
1279 uint64_t gfx9_eop_bug_va
);
1280 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1281 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1282 bool inverted
, uint64_t va
);
1283 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1284 uint64_t src_va
, uint64_t dest_va
,
1286 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1288 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1289 uint64_t size
, unsigned value
);
1290 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1292 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1294 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1297 unsigned *out_offset
,
1300 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1301 const struct radv_subpass
*subpass
);
1303 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1304 unsigned size
, unsigned alignmnet
,
1305 const void *data
, unsigned *out_offset
);
1307 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1308 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1309 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1310 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1311 VkImageAspectFlags aspects
,
1312 VkResolveModeFlagBitsKHR resolve_mode
);
1313 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1314 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1315 VkImageAspectFlags aspects
,
1316 VkResolveModeFlagBitsKHR resolve_mode
);
1317 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1318 unsigned radv_get_default_max_sample_dist(int log_samples
);
1319 void radv_device_init_msaa(struct radv_device
*device
);
1321 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1322 const struct radv_image_view
*iview
,
1323 VkClearDepthStencilValue ds_clear_value
,
1324 VkImageAspectFlags aspects
);
1326 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1327 const struct radv_image_view
*iview
,
1329 uint32_t color_values
[2]);
1331 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1332 struct radv_image
*image
,
1333 const VkImageSubresourceRange
*range
, bool value
);
1335 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1336 struct radv_image
*image
,
1337 const VkImageSubresourceRange
*range
, bool value
);
1339 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1340 struct radeon_winsys_bo
*bo
,
1341 uint64_t offset
, uint64_t size
, uint32_t value
);
1342 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1343 bool radv_get_memory_fd(struct radv_device
*device
,
1344 struct radv_device_memory
*memory
,
1348 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1349 unsigned sh_offset
, unsigned pointer_count
,
1350 bool use_32bit_pointers
)
1352 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1353 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1357 radv_emit_shader_pointer_body(struct radv_device
*device
,
1358 struct radeon_cmdbuf
*cs
,
1359 uint64_t va
, bool use_32bit_pointers
)
1361 radeon_emit(cs
, va
);
1363 if (use_32bit_pointers
) {
1365 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1367 radeon_emit(cs
, va
>> 32);
1372 radv_emit_shader_pointer(struct radv_device
*device
,
1373 struct radeon_cmdbuf
*cs
,
1374 uint32_t sh_offset
, uint64_t va
, bool global
)
1376 bool use_32bit_pointers
= !global
;
1378 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1379 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1382 static inline struct radv_descriptor_state
*
1383 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1384 VkPipelineBindPoint bind_point
)
1386 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1387 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1388 return &cmd_buffer
->descriptors
[bind_point
];
1392 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1394 * Limitations: Can't call normal dispatch functions without binding or rebinding
1395 * the compute pipeline.
1397 void radv_unaligned_dispatch(
1398 struct radv_cmd_buffer
*cmd_buffer
,
1404 struct radeon_winsys_bo
*bo
;
1408 struct radv_shader_module
;
1410 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1411 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1412 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1413 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1414 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1415 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1416 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1419 radv_hash_shaders(unsigned char *hash
,
1420 const VkPipelineShaderStageCreateInfo
**stages
,
1421 const struct radv_pipeline_layout
*layout
,
1422 const struct radv_pipeline_key
*key
,
1425 static inline gl_shader_stage
1426 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1428 assert(__builtin_popcount(vk_stage
) == 1);
1429 return ffs(vk_stage
) - 1;
1432 static inline VkShaderStageFlagBits
1433 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1435 return (1 << mesa_stage
);
1438 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1440 #define radv_foreach_stage(stage, stage_bits) \
1441 for (gl_shader_stage stage, \
1442 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1443 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1444 __tmp &= ~(1 << (stage)))
1446 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1447 unsigned radv_format_meta_fs_key(VkFormat format
);
1449 struct radv_multisample_state
{
1451 uint32_t pa_sc_line_cntl
;
1452 uint32_t pa_sc_mode_cntl_0
;
1453 uint32_t pa_sc_mode_cntl_1
;
1454 uint32_t pa_sc_aa_config
;
1455 uint32_t pa_sc_aa_mask
[2];
1456 unsigned num_samples
;
1459 struct radv_prim_vertex_count
{
1464 struct radv_vertex_elements_info
{
1465 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1468 struct radv_ia_multi_vgt_param_helpers
{
1470 bool partial_es_wave
;
1471 uint8_t primgroup_size
;
1472 bool wd_switch_on_eop
;
1473 bool ia_switch_on_eoi
;
1474 bool partial_vs_wave
;
1477 struct radv_binning_state
{
1478 uint32_t pa_sc_binner_cntl_0
;
1479 uint32_t db_dfsm_control
;
1482 #define SI_GS_PER_ES 128
1484 struct radv_pipeline
{
1485 struct radv_device
* device
;
1486 struct radv_dynamic_state dynamic_state
;
1488 struct radv_pipeline_layout
* layout
;
1490 bool need_indirect_descriptor_sets
;
1491 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1492 struct radv_shader_variant
*gs_copy_shader
;
1493 VkShaderStageFlags active_stages
;
1495 struct radeon_cmdbuf cs
;
1496 uint32_t ctx_cs_hash
;
1497 struct radeon_cmdbuf ctx_cs
;
1499 struct radv_vertex_elements_info vertex_elements
;
1501 uint32_t binding_stride
[MAX_VBS
];
1502 uint8_t num_vertex_bindings
;
1504 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1507 struct radv_multisample_state ms
;
1508 struct radv_binning_state binning
;
1509 uint32_t spi_baryc_cntl
;
1510 bool prim_restart_enable
;
1511 unsigned esgs_ring_size
;
1512 unsigned gsvs_ring_size
;
1513 uint32_t vtx_base_sgpr
;
1514 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1515 uint8_t vtx_emit_num
;
1516 struct radv_prim_vertex_count prim_vertex_count
;
1517 bool can_use_guardband
;
1518 uint32_t needed_dynamic_state
;
1519 bool disable_out_of_order_rast_for_occlusion
;
1521 /* Used for rbplus */
1522 uint32_t col_format
;
1523 uint32_t cb_target_mask
;
1528 unsigned scratch_bytes_per_wave
;
1530 /* Not NULL if graphics pipeline uses streamout. */
1531 struct radv_shader_variant
*streamout_shader
;
1534 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1536 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1539 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1541 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1544 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1546 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1548 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1549 gl_shader_stage stage
,
1552 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1553 gl_shader_stage stage
);
1555 struct radv_graphics_pipeline_create_info
{
1557 bool db_depth_clear
;
1558 bool db_stencil_clear
;
1559 bool db_depth_disable_expclear
;
1560 bool db_stencil_disable_expclear
;
1561 bool db_flush_depth_inplace
;
1562 bool db_flush_stencil_inplace
;
1563 bool db_resummarize
;
1564 uint32_t custom_blend_mode
;
1568 radv_graphics_pipeline_create(VkDevice device
,
1569 VkPipelineCache cache
,
1570 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1571 const struct radv_graphics_pipeline_create_info
*extra
,
1572 const VkAllocationCallbacks
*alloc
,
1573 VkPipeline
*pPipeline
);
1575 struct vk_format_description
;
1576 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1577 int first_non_void
);
1578 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1579 int first_non_void
);
1580 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1581 uint32_t radv_translate_colorformat(VkFormat format
);
1582 uint32_t radv_translate_color_numformat(VkFormat format
,
1583 const struct vk_format_description
*desc
,
1584 int first_non_void
);
1585 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1586 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1587 uint32_t radv_translate_dbformat(VkFormat format
);
1588 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1589 const struct vk_format_description
*desc
,
1590 int first_non_void
);
1591 uint32_t radv_translate_tex_numformat(VkFormat format
,
1592 const struct vk_format_description
*desc
,
1593 int first_non_void
);
1594 bool radv_format_pack_clear_color(VkFormat format
,
1595 uint32_t clear_vals
[2],
1596 VkClearColorValue
*value
);
1597 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1598 bool radv_dcc_formats_compatible(VkFormat format1
,
1600 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1602 struct radv_image_plane
{
1604 struct radeon_surf surface
;
1610 /* The original VkFormat provided by the client. This may not match any
1611 * of the actual surface formats.
1614 VkImageAspectFlags aspects
;
1615 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1616 struct ac_surf_info info
;
1617 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1618 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1623 unsigned queue_family_mask
;
1627 /* Set when bound */
1628 struct radeon_winsys_bo
*bo
;
1629 VkDeviceSize offset
;
1630 uint64_t dcc_offset
;
1631 uint64_t htile_offset
;
1632 bool tc_compatible_htile
;
1633 bool tc_compatible_cmask
;
1635 uint64_t cmask_offset
;
1636 uint64_t fmask_offset
;
1637 uint64_t clear_value_offset
;
1638 uint64_t fce_pred_offset
;
1639 uint64_t dcc_pred_offset
;
1642 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1643 * stored at this offset is UINT_MAX, the driver will emit
1644 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1645 * SET_CONTEXT_REG packet.
1647 uint64_t tc_compat_zrange_offset
;
1649 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1650 VkDeviceMemory owned_memory
;
1652 unsigned plane_count
;
1653 struct radv_image_plane planes
[0];
1656 /* Whether the image has a htile that is known consistent with the contents of
1658 bool radv_layout_has_htile(const struct radv_image
*image
,
1659 VkImageLayout layout
,
1660 bool in_render_loop
,
1661 unsigned queue_mask
);
1663 /* Whether the image has a htile that is known consistent with the contents of
1664 * the image and is allowed to be in compressed form.
1666 * If this is false reads that don't use the htile should be able to return
1669 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1670 VkImageLayout layout
,
1671 bool in_render_loop
,
1672 unsigned queue_mask
);
1674 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1675 VkImageLayout layout
,
1676 bool in_render_loop
,
1677 unsigned queue_mask
);
1679 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1680 const struct radv_image
*image
,
1681 VkImageLayout layout
,
1682 bool in_render_loop
,
1683 unsigned queue_mask
);
1686 * Return whether the image has CMASK metadata for color surfaces.
1689 radv_image_has_cmask(const struct radv_image
*image
)
1691 return image
->cmask_offset
;
1695 * Return whether the image has FMASK metadata for color surfaces.
1698 radv_image_has_fmask(const struct radv_image
*image
)
1700 return image
->fmask_offset
;
1704 * Return whether the image has DCC metadata for color surfaces.
1707 radv_image_has_dcc(const struct radv_image
*image
)
1709 return image
->planes
[0].surface
.dcc_size
;
1713 * Return whether the image is TC-compatible CMASK.
1716 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1718 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1722 * Return whether DCC metadata is enabled for a level.
1725 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1727 return radv_image_has_dcc(image
) &&
1728 level
< image
->planes
[0].surface
.num_dcc_levels
;
1732 * Return whether the image has CB metadata.
1735 radv_image_has_CB_metadata(const struct radv_image
*image
)
1737 return radv_image_has_cmask(image
) ||
1738 radv_image_has_fmask(image
) ||
1739 radv_image_has_dcc(image
);
1743 * Return whether the image has HTILE metadata for depth surfaces.
1746 radv_image_has_htile(const struct radv_image
*image
)
1748 return image
->planes
[0].surface
.htile_size
;
1752 * Return whether HTILE metadata is enabled for a level.
1755 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1757 return radv_image_has_htile(image
) && level
== 0;
1761 * Return whether the image is TC-compatible HTILE.
1764 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1766 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1769 static inline uint64_t
1770 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1771 uint32_t base_level
)
1773 uint64_t va
= radv_buffer_get_va(image
->bo
);
1774 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1778 static inline uint64_t
1779 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1780 uint32_t base_level
)
1782 uint64_t va
= radv_buffer_get_va(image
->bo
);
1783 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1787 static inline uint64_t
1788 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1789 uint32_t base_level
)
1791 uint64_t va
= radv_buffer_get_va(image
->bo
);
1792 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1796 static inline uint64_t
1797 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1798 uint32_t base_level
)
1800 uint64_t va
= radv_buffer_get_va(image
->bo
);
1801 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1805 static inline uint64_t
1806 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1807 uint32_t base_level
)
1809 uint64_t va
= radv_buffer_get_va(image
->bo
);
1810 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1814 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1816 static inline uint32_t
1817 radv_get_layerCount(const struct radv_image
*image
,
1818 const VkImageSubresourceRange
*range
)
1820 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1821 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1824 static inline uint32_t
1825 radv_get_levelCount(const struct radv_image
*image
,
1826 const VkImageSubresourceRange
*range
)
1828 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1829 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1832 struct radeon_bo_metadata
;
1834 radv_init_metadata(struct radv_device
*device
,
1835 struct radv_image
*image
,
1836 struct radeon_bo_metadata
*metadata
);
1839 radv_image_override_offset_stride(struct radv_device
*device
,
1840 struct radv_image
*image
,
1841 uint64_t offset
, uint32_t stride
);
1843 union radv_descriptor
{
1845 uint32_t plane0_descriptor
[8];
1846 uint32_t fmask_descriptor
[8];
1849 uint32_t plane_descriptors
[3][8];
1853 struct radv_image_view
{
1854 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1855 struct radeon_winsys_bo
*bo
;
1857 VkImageViewType type
;
1858 VkImageAspectFlags aspect_mask
;
1861 bool multiple_planes
;
1862 uint32_t base_layer
;
1863 uint32_t layer_count
;
1865 uint32_t level_count
;
1866 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1868 union radv_descriptor descriptor
;
1870 /* Descriptor for use as a storage image as opposed to a sampled image.
1871 * This has a few differences for cube maps (e.g. type).
1873 union radv_descriptor storage_descriptor
;
1876 struct radv_image_create_info
{
1877 const VkImageCreateInfo
*vk_info
;
1879 bool no_metadata_planes
;
1880 const struct radeon_bo_metadata
*bo_metadata
;
1883 VkResult
radv_image_create(VkDevice _device
,
1884 const struct radv_image_create_info
*info
,
1885 const VkAllocationCallbacks
* alloc
,
1889 radv_image_from_gralloc(VkDevice device_h
,
1890 const VkImageCreateInfo
*base_info
,
1891 const VkNativeBufferANDROID
*gralloc_info
,
1892 const VkAllocationCallbacks
*alloc
,
1893 VkImage
*out_image_h
);
1895 struct radv_image_view_extra_create_info
{
1896 bool disable_compression
;
1899 void radv_image_view_init(struct radv_image_view
*view
,
1900 struct radv_device
*device
,
1901 const VkImageViewCreateInfo
*pCreateInfo
,
1902 const struct radv_image_view_extra_create_info
* extra_create_info
);
1904 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1906 struct radv_sampler_ycbcr_conversion
{
1908 VkSamplerYcbcrModelConversion ycbcr_model
;
1909 VkSamplerYcbcrRange ycbcr_range
;
1910 VkComponentMapping components
;
1911 VkChromaLocation chroma_offsets
[2];
1912 VkFilter chroma_filter
;
1915 struct radv_buffer_view
{
1916 struct radeon_winsys_bo
*bo
;
1918 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1921 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1922 struct radv_device
*device
,
1923 const VkBufferViewCreateInfo
* pCreateInfo
);
1925 static inline struct VkExtent3D
1926 radv_sanitize_image_extent(const VkImageType imageType
,
1927 const struct VkExtent3D imageExtent
)
1929 switch (imageType
) {
1930 case VK_IMAGE_TYPE_1D
:
1931 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1932 case VK_IMAGE_TYPE_2D
:
1933 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1934 case VK_IMAGE_TYPE_3D
:
1937 unreachable("invalid image type");
1941 static inline struct VkOffset3D
1942 radv_sanitize_image_offset(const VkImageType imageType
,
1943 const struct VkOffset3D imageOffset
)
1945 switch (imageType
) {
1946 case VK_IMAGE_TYPE_1D
:
1947 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1948 case VK_IMAGE_TYPE_2D
:
1949 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1950 case VK_IMAGE_TYPE_3D
:
1953 unreachable("invalid image type");
1958 radv_image_extent_compare(const struct radv_image
*image
,
1959 const VkExtent3D
*extent
)
1961 if (extent
->width
!= image
->info
.width
||
1962 extent
->height
!= image
->info
.height
||
1963 extent
->depth
!= image
->info
.depth
)
1968 struct radv_sampler
{
1970 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
1973 struct radv_framebuffer
{
1978 uint32_t attachment_count
;
1979 struct radv_image_view
*attachments
[0];
1982 struct radv_subpass_barrier
{
1983 VkPipelineStageFlags src_stage_mask
;
1984 VkAccessFlags src_access_mask
;
1985 VkAccessFlags dst_access_mask
;
1988 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
1989 const struct radv_subpass_barrier
*barrier
);
1991 struct radv_subpass_attachment
{
1992 uint32_t attachment
;
1993 VkImageLayout layout
;
1994 bool in_render_loop
;
1997 struct radv_subpass
{
1998 uint32_t attachment_count
;
1999 struct radv_subpass_attachment
* attachments
;
2001 uint32_t input_count
;
2002 uint32_t color_count
;
2003 struct radv_subpass_attachment
* input_attachments
;
2004 struct radv_subpass_attachment
* color_attachments
;
2005 struct radv_subpass_attachment
* resolve_attachments
;
2006 struct radv_subpass_attachment
* depth_stencil_attachment
;
2007 struct radv_subpass_attachment
* ds_resolve_attachment
;
2008 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2009 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2011 /** Subpass has at least one color resolve attachment */
2012 bool has_color_resolve
;
2014 /** Subpass has at least one color attachment */
2017 struct radv_subpass_barrier start_barrier
;
2020 VkSampleCountFlagBits max_sample_count
;
2024 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2026 struct radv_render_pass_attachment
{
2029 VkAttachmentLoadOp load_op
;
2030 VkAttachmentLoadOp stencil_load_op
;
2031 VkImageLayout initial_layout
;
2032 VkImageLayout final_layout
;
2034 /* The subpass id in which the attachment will be used first/last. */
2035 uint32_t first_subpass_idx
;
2036 uint32_t last_subpass_idx
;
2039 struct radv_render_pass
{
2040 uint32_t attachment_count
;
2041 uint32_t subpass_count
;
2042 struct radv_subpass_attachment
* subpass_attachments
;
2043 struct radv_render_pass_attachment
* attachments
;
2044 struct radv_subpass_barrier end_barrier
;
2045 struct radv_subpass subpasses
[0];
2048 VkResult
radv_device_init_meta(struct radv_device
*device
);
2049 void radv_device_finish_meta(struct radv_device
*device
);
2051 struct radv_query_pool
{
2052 struct radeon_winsys_bo
*bo
;
2054 uint32_t availability_offset
;
2058 uint32_t pipeline_stats_mask
;
2061 struct radv_semaphore
{
2062 /* use a winsys sem for non-exportable */
2063 struct radeon_winsys_sem
*sem
;
2065 uint32_t temp_syncobj
;
2068 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2069 VkPipelineBindPoint bind_point
,
2070 struct radv_descriptor_set
*set
,
2074 radv_update_descriptor_sets(struct radv_device
*device
,
2075 struct radv_cmd_buffer
*cmd_buffer
,
2076 VkDescriptorSet overrideSet
,
2077 uint32_t descriptorWriteCount
,
2078 const VkWriteDescriptorSet
*pDescriptorWrites
,
2079 uint32_t descriptorCopyCount
,
2080 const VkCopyDescriptorSet
*pDescriptorCopies
);
2083 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2084 struct radv_cmd_buffer
*cmd_buffer
,
2085 struct radv_descriptor_set
*set
,
2086 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2089 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2090 VkPipelineBindPoint pipelineBindPoint
,
2091 VkPipelineLayout _layout
,
2093 uint32_t descriptorWriteCount
,
2094 const VkWriteDescriptorSet
*pDescriptorWrites
);
2096 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2097 struct radv_image
*image
,
2098 const VkImageSubresourceRange
*range
, uint32_t value
);
2100 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2101 struct radv_image
*image
,
2102 const VkImageSubresourceRange
*range
);
2105 struct radeon_winsys_fence
*fence
;
2106 struct wsi_fence
*fence_wsi
;
2109 uint32_t temp_syncobj
;
2112 /* radv_nir_to_llvm.c */
2113 struct radv_shader_variant_info
;
2114 struct radv_nir_compiler_options
;
2116 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2117 struct nir_shader
*geom_shader
,
2118 struct radv_shader_binary
**rbinary
,
2119 struct radv_shader_variant_info
*shader_info
,
2120 const struct radv_nir_compiler_options
*option
);
2122 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2123 struct radv_shader_binary
**rbinary
,
2124 struct radv_shader_variant_info
*shader_info
,
2125 struct nir_shader
*const *nir
,
2127 const struct radv_nir_compiler_options
*options
);
2129 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2130 gl_shader_stage stage
,
2131 const struct nir_shader
*nir
);
2133 /* radv_shader_info.h */
2134 struct radv_shader_info
;
2136 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2137 const struct radv_nir_compiler_options
*options
,
2138 struct radv_shader_info
*info
);
2140 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2142 struct radeon_winsys_sem
;
2144 uint64_t radv_get_current_time(void);
2146 static inline uint32_t
2147 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2150 case 0: /* GL_POINTS */
2152 case 1: /* GL_LINES */
2153 case 3: /* GL_LINE_STRIP */
2155 case 4: /* GL_TRIANGLES */
2156 case 5: /* GL_TRIANGLE_STRIP */
2158 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2160 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2162 case 7: /* GL_QUADS */
2163 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2170 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2172 static inline struct __radv_type * \
2173 __radv_type ## _from_handle(__VkType _handle) \
2175 return (struct __radv_type *) _handle; \
2178 static inline __VkType \
2179 __radv_type ## _to_handle(struct __radv_type *_obj) \
2181 return (__VkType) _obj; \
2184 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2186 static inline struct __radv_type * \
2187 __radv_type ## _from_handle(__VkType _handle) \
2189 return (struct __radv_type *)(uintptr_t) _handle; \
2192 static inline __VkType \
2193 __radv_type ## _to_handle(struct __radv_type *_obj) \
2195 return (__VkType)(uintptr_t) _obj; \
2198 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2199 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2201 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2202 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2203 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2204 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2205 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2208 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2209 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2210 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2211 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2212 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2213 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2214 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2215 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2216 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2217 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2218 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2219 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2220 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2221 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2222 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2223 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2224 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2225 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2226 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2227 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2228 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2230 #endif /* RADV_PRIVATE_H */