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radv: rework the error function helpers a bit
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorv(struct radv_instance *instance, VkResult error,
198 const char *file, int line, const char *format,
199 va_list args);
200
201 VkResult __vk_errorf(struct radv_instance *instance, VkResult error,
202 const char *file, int line, const char *format, ...)
203 radv_printflike(5, 6);
204
205 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
207
208 void __radv_finishme(const char *file, int line, const char *format, ...)
209 radv_printflike(3, 4);
210 void radv_loge(const char *format, ...) radv_printflike(1, 2);
211 void radv_loge_v(const char *format, va_list va);
212 void radv_logi(const char *format, ...) radv_printflike(1, 2);
213 void radv_logi_v(const char *format, va_list va);
214
215 /**
216 * Print a FINISHME message, including its source location.
217 */
218 #define radv_finishme(format, ...) \
219 do { \
220 static bool reported = false; \
221 if (!reported) { \
222 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
223 reported = true; \
224 } \
225 } while (0)
226
227 /* A non-fatal assert. Useful for debugging. */
228 #ifdef DEBUG
229 #define radv_assert(x) ({ \
230 if (unlikely(!(x))) \
231 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
232 })
233 #else
234 #define radv_assert(x) do {} while(0)
235 #endif
236
237 #define stub_return(v) \
238 do { \
239 radv_finishme("stub %s", __func__); \
240 return (v); \
241 } while (0)
242
243 #define stub() \
244 do { \
245 radv_finishme("stub %s", __func__); \
246 return; \
247 } while (0)
248
249 int radv_get_instance_entrypoint_index(const char *name);
250 int radv_get_device_entrypoint_index(const char *name);
251 int radv_get_physical_device_entrypoint_index(const char *name);
252
253 const char *radv_get_instance_entry_name(int index);
254 const char *radv_get_physical_device_entry_name(int index);
255 const char *radv_get_device_entry_name(int index);
256
257 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
258 const struct radv_instance_extension_table *instance);
259 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
260 const struct radv_instance_extension_table *instance);
261 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
262 const struct radv_instance_extension_table *instance,
263 const struct radv_device_extension_table *device);
264
265 void *radv_lookup_entrypoint(const char *name);
266
267 struct radv_physical_device {
268 VK_LOADER_DATA _loader_data;
269
270 /* Link in radv_instance::physical_devices */
271 struct list_head link;
272
273 struct radv_instance * instance;
274
275 struct radeon_winsys *ws;
276 struct radeon_info rad_info;
277 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
278 uint8_t driver_uuid[VK_UUID_SIZE];
279 uint8_t device_uuid[VK_UUID_SIZE];
280 uint8_t cache_uuid[VK_UUID_SIZE];
281
282 int local_fd;
283 int master_fd;
284 struct wsi_device wsi_device;
285
286 bool out_of_order_rast_allowed;
287
288 /* Whether DCC should be enabled for MSAA textures. */
289 bool dcc_msaa_allowed;
290
291 /* Whether to enable NGG. */
292 bool use_ngg;
293
294 /* Whether to enable NGG GS. */
295 bool use_ngg_gs;
296
297 /* Whether to enable NGG streamout. */
298 bool use_ngg_streamout;
299
300 /* Number of threads per wave. */
301 uint8_t ps_wave_size;
302 uint8_t cs_wave_size;
303 uint8_t ge_wave_size;
304
305 /* Whether to use the LLVM compiler backend */
306 bool use_llvm;
307
308 /* This is the drivers on-disk cache used as a fallback as opposed to
309 * the pipeline cache defined by apps.
310 */
311 struct disk_cache * disk_cache;
312
313 VkPhysicalDeviceMemoryProperties memory_properties;
314 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
315 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
316
317 drmPciBusInfo bus_info;
318
319 struct radv_device_extension_table supported_extensions;
320 };
321
322 struct radv_instance {
323 struct vk_object_base base;
324
325 VkAllocationCallbacks alloc;
326
327 uint32_t apiVersion;
328
329 char * engineName;
330 uint32_t engineVersion;
331
332 uint64_t debug_flags;
333 uint64_t perftest_flags;
334
335 struct vk_debug_report_instance debug_report_callbacks;
336
337 struct radv_instance_extension_table enabled_extensions;
338 struct radv_instance_dispatch_table dispatch;
339 struct radv_physical_device_dispatch_table physical_device_dispatch;
340 struct radv_device_dispatch_table device_dispatch;
341
342 bool physical_devices_enumerated;
343 struct list_head physical_devices;
344
345 struct driOptionCache dri_options;
346 struct driOptionCache available_dri_options;
347
348 /**
349 * Workarounds for game bugs.
350 */
351 bool enable_mrt_output_nan_fixup;
352 };
353
354 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
355 void radv_finish_wsi(struct radv_physical_device *physical_device);
356
357 bool radv_instance_extension_supported(const char *name);
358 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
359 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
360 const char *name);
361
362 struct cache_entry;
363
364 struct radv_pipeline_cache {
365 struct vk_object_base base;
366 struct radv_device * device;
367 pthread_mutex_t mutex;
368 VkPipelineCacheCreateFlags flags;
369
370 uint32_t total_size;
371 uint32_t table_size;
372 uint32_t kernel_count;
373 struct cache_entry ** hash_table;
374 bool modified;
375
376 VkAllocationCallbacks alloc;
377 };
378
379 struct radv_pipeline_key {
380 uint32_t instance_rate_inputs;
381 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
382 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
383 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
384 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
385 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
386 uint64_t vertex_alpha_adjust;
387 uint32_t vertex_post_shuffle;
388 unsigned tess_input_vertices;
389 uint32_t col_format;
390 uint32_t is_int8;
391 uint32_t is_int10;
392 uint8_t log2_ps_iter_samples;
393 uint8_t num_samples;
394 bool is_dual_src;
395 uint32_t has_multiview_view_index : 1;
396 uint32_t optimisations_disabled : 1;
397 uint8_t topology;
398
399 /* Non-zero if a required subgroup size is specified via
400 * VK_EXT_subgroup_size_control.
401 */
402 uint8_t compute_subgroup_size;
403 };
404
405 struct radv_shader_binary;
406 struct radv_shader_variant;
407
408 void
409 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
410 struct radv_device *device);
411 void
412 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
413 bool
414 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
415 const void *data, size_t size);
416
417 bool
418 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
419 struct radv_pipeline_cache *cache,
420 const unsigned char *sha1,
421 struct radv_shader_variant **variants,
422 bool *found_in_application_cache);
423
424 void
425 radv_pipeline_cache_insert_shaders(struct radv_device *device,
426 struct radv_pipeline_cache *cache,
427 const unsigned char *sha1,
428 struct radv_shader_variant **variants,
429 struct radv_shader_binary *const *binaries);
430
431 enum radv_blit_ds_layout {
432 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
433 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
434 RADV_BLIT_DS_LAYOUT_COUNT,
435 };
436
437 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
438 {
439 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
440 }
441
442 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
443 {
444 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
445 }
446
447 enum radv_meta_dst_layout {
448 RADV_META_DST_LAYOUT_GENERAL,
449 RADV_META_DST_LAYOUT_OPTIMAL,
450 RADV_META_DST_LAYOUT_COUNT,
451 };
452
453 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
454 {
455 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
456 }
457
458 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
459 {
460 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
461 }
462
463 struct radv_meta_state {
464 VkAllocationCallbacks alloc;
465
466 struct radv_pipeline_cache cache;
467
468 /*
469 * For on-demand pipeline creation, makes sure that
470 * only one thread tries to build a pipeline at the same time.
471 */
472 mtx_t mtx;
473
474 /**
475 * Use array element `i` for images with `2^i` samples.
476 */
477 struct {
478 VkRenderPass render_pass[NUM_META_FS_KEYS];
479 VkPipeline color_pipelines[NUM_META_FS_KEYS];
480
481 VkRenderPass depthstencil_rp;
482 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
483 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
484 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
485
486 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
487 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
488 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
489 } clear[MAX_SAMPLES_LOG2];
490
491 VkPipelineLayout clear_color_p_layout;
492 VkPipelineLayout clear_depth_p_layout;
493 VkPipelineLayout clear_depth_unrestricted_p_layout;
494
495 /* Optimized compute fast HTILE clear for stencil or depth only. */
496 VkPipeline clear_htile_mask_pipeline;
497 VkPipelineLayout clear_htile_mask_p_layout;
498 VkDescriptorSetLayout clear_htile_mask_ds_layout;
499
500 struct {
501 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
502
503 /** Pipeline that blits from a 1D image. */
504 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
505
506 /** Pipeline that blits from a 2D image. */
507 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
508
509 /** Pipeline that blits from a 3D image. */
510 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
511
512 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
513 VkPipeline depth_only_1d_pipeline;
514 VkPipeline depth_only_2d_pipeline;
515 VkPipeline depth_only_3d_pipeline;
516
517 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
518 VkPipeline stencil_only_1d_pipeline;
519 VkPipeline stencil_only_2d_pipeline;
520 VkPipeline stencil_only_3d_pipeline;
521 VkPipelineLayout pipeline_layout;
522 VkDescriptorSetLayout ds_layout;
523 } blit;
524
525 struct {
526 VkPipelineLayout p_layouts[5];
527 VkDescriptorSetLayout ds_layouts[5];
528 VkPipeline pipelines[5][NUM_META_FS_KEYS];
529
530 VkPipeline depth_only_pipeline[5];
531
532 VkPipeline stencil_only_pipeline[5];
533 } blit2d[MAX_SAMPLES_LOG2];
534
535 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
536 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
537 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
538
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 VkPipeline pipeline_3d;
544 } itob;
545 struct {
546 VkPipelineLayout img_p_layout;
547 VkDescriptorSetLayout img_ds_layout;
548 VkPipeline pipeline;
549 VkPipeline pipeline_3d;
550 } btoi;
551 struct {
552 VkPipelineLayout img_p_layout;
553 VkDescriptorSetLayout img_ds_layout;
554 VkPipeline pipeline;
555 } btoi_r32g32b32;
556 struct {
557 VkPipelineLayout img_p_layout;
558 VkDescriptorSetLayout img_ds_layout;
559 VkPipeline pipeline;
560 VkPipeline pipeline_3d;
561 } itoi;
562 struct {
563 VkPipelineLayout img_p_layout;
564 VkDescriptorSetLayout img_ds_layout;
565 VkPipeline pipeline;
566 } itoi_r32g32b32;
567 struct {
568 VkPipelineLayout img_p_layout;
569 VkDescriptorSetLayout img_ds_layout;
570 VkPipeline pipeline;
571 VkPipeline pipeline_3d;
572 } cleari;
573 struct {
574 VkPipelineLayout img_p_layout;
575 VkDescriptorSetLayout img_ds_layout;
576 VkPipeline pipeline;
577 } cleari_r32g32b32;
578
579 struct {
580 VkPipelineLayout p_layout;
581 VkPipeline pipeline[NUM_META_FS_KEYS];
582 VkRenderPass pass[NUM_META_FS_KEYS];
583 } resolve;
584
585 struct {
586 VkDescriptorSetLayout ds_layout;
587 VkPipelineLayout p_layout;
588 struct {
589 VkPipeline pipeline;
590 VkPipeline i_pipeline;
591 VkPipeline srgb_pipeline;
592 } rc[MAX_SAMPLES_LOG2];
593
594 VkPipeline depth_zero_pipeline;
595 struct {
596 VkPipeline average_pipeline;
597 VkPipeline max_pipeline;
598 VkPipeline min_pipeline;
599 } depth[MAX_SAMPLES_LOG2];
600
601 VkPipeline stencil_zero_pipeline;
602 struct {
603 VkPipeline max_pipeline;
604 VkPipeline min_pipeline;
605 } stencil[MAX_SAMPLES_LOG2];
606 } resolve_compute;
607
608 struct {
609 VkDescriptorSetLayout ds_layout;
610 VkPipelineLayout p_layout;
611
612 struct {
613 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
614 VkPipeline pipeline[NUM_META_FS_KEYS];
615 } rc[MAX_SAMPLES_LOG2];
616
617 VkRenderPass depth_render_pass;
618 VkPipeline depth_zero_pipeline;
619 struct {
620 VkPipeline average_pipeline;
621 VkPipeline max_pipeline;
622 VkPipeline min_pipeline;
623 } depth[MAX_SAMPLES_LOG2];
624
625 VkRenderPass stencil_render_pass;
626 VkPipeline stencil_zero_pipeline;
627 struct {
628 VkPipeline max_pipeline;
629 VkPipeline min_pipeline;
630 } stencil[MAX_SAMPLES_LOG2];
631 } resolve_fragment;
632
633 struct {
634 VkPipelineLayout p_layout;
635 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
636 VkPipeline resummarize_pipeline;
637 VkRenderPass pass;
638 } depth_decomp[MAX_SAMPLES_LOG2];
639
640 struct {
641 VkPipelineLayout p_layout;
642 VkPipeline cmask_eliminate_pipeline;
643 VkPipeline fmask_decompress_pipeline;
644 VkPipeline dcc_decompress_pipeline;
645 VkRenderPass pass;
646
647 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
648 VkPipelineLayout dcc_decompress_compute_p_layout;
649 VkPipeline dcc_decompress_compute_pipeline;
650 } fast_clear_flush;
651
652 struct {
653 VkPipelineLayout fill_p_layout;
654 VkPipelineLayout copy_p_layout;
655 VkDescriptorSetLayout fill_ds_layout;
656 VkDescriptorSetLayout copy_ds_layout;
657 VkPipeline fill_pipeline;
658 VkPipeline copy_pipeline;
659 } buffer;
660
661 struct {
662 VkDescriptorSetLayout ds_layout;
663 VkPipelineLayout p_layout;
664 VkPipeline occlusion_query_pipeline;
665 VkPipeline pipeline_statistics_query_pipeline;
666 VkPipeline tfb_query_pipeline;
667 VkPipeline timestamp_query_pipeline;
668 } query;
669
670 struct {
671 VkDescriptorSetLayout ds_layout;
672 VkPipelineLayout p_layout;
673 VkPipeline pipeline[MAX_SAMPLES_LOG2];
674 } fmask_expand;
675 };
676
677 /* queue types */
678 #define RADV_QUEUE_GENERAL 0
679 #define RADV_QUEUE_COMPUTE 1
680 #define RADV_QUEUE_TRANSFER 2
681
682 #define RADV_MAX_QUEUE_FAMILIES 3
683
684 struct radv_deferred_queue_submission;
685
686 enum ring_type radv_queue_family_to_ring(int f);
687
688 struct radv_queue {
689 VK_LOADER_DATA _loader_data;
690 struct radv_device * device;
691 struct radeon_winsys_ctx *hw_ctx;
692 enum radeon_ctx_priority priority;
693 uint32_t queue_family_index;
694 int queue_idx;
695 VkDeviceQueueCreateFlags flags;
696
697 uint32_t scratch_size_per_wave;
698 uint32_t scratch_waves;
699 uint32_t compute_scratch_size_per_wave;
700 uint32_t compute_scratch_waves;
701 uint32_t esgs_ring_size;
702 uint32_t gsvs_ring_size;
703 bool has_tess_rings;
704 bool has_gds;
705 bool has_gds_oa;
706 bool has_sample_positions;
707
708 struct radeon_winsys_bo *scratch_bo;
709 struct radeon_winsys_bo *descriptor_bo;
710 struct radeon_winsys_bo *compute_scratch_bo;
711 struct radeon_winsys_bo *esgs_ring_bo;
712 struct radeon_winsys_bo *gsvs_ring_bo;
713 struct radeon_winsys_bo *tess_rings_bo;
714 struct radeon_winsys_bo *gds_bo;
715 struct radeon_winsys_bo *gds_oa_bo;
716 struct radeon_cmdbuf *initial_preamble_cs;
717 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
718 struct radeon_cmdbuf *continue_preamble_cs;
719
720 struct list_head pending_submissions;
721 pthread_mutex_t pending_mutex;
722
723 pthread_mutex_t thread_mutex;
724 pthread_cond_t thread_cond;
725 struct radv_deferred_queue_submission *thread_submission;
726 pthread_t submission_thread;
727 bool thread_exit;
728 bool thread_running;
729 };
730
731 struct radv_bo_list {
732 struct radv_winsys_bo_list list;
733 unsigned capacity;
734 pthread_mutex_t mutex;
735 };
736
737 VkResult radv_bo_list_add(struct radv_device *device,
738 struct radeon_winsys_bo *bo);
739 void radv_bo_list_remove(struct radv_device *device,
740 struct radeon_winsys_bo *bo);
741
742 #define RADV_BORDER_COLOR_COUNT 4096
743 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
744
745 struct radv_device_border_color_data {
746 bool used[RADV_BORDER_COLOR_COUNT];
747
748 struct radeon_winsys_bo *bo;
749 VkClearColorValue *colors_gpu_ptr;
750
751 /* Mutex is required to guarantee vkCreateSampler thread safety
752 * given that we are writing to a buffer and checking color occupation */
753 pthread_mutex_t mutex;
754 };
755
756 struct radv_device {
757 struct vk_device vk;
758
759 struct radv_instance * instance;
760 struct radeon_winsys *ws;
761
762 struct radv_meta_state meta_state;
763
764 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
765 int queue_count[RADV_MAX_QUEUE_FAMILIES];
766 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
767
768 bool always_use_syncobj;
769 bool pbb_allowed;
770 bool dfsm_allowed;
771 uint32_t tess_offchip_block_dw_size;
772 uint32_t scratch_waves;
773 uint32_t dispatch_initiator;
774
775 uint32_t gs_table_depth;
776
777 /* MSAA sample locations.
778 * The first index is the sample index.
779 * The second index is the coordinate: X, Y. */
780 float sample_locations_1x[1][2];
781 float sample_locations_2x[2][2];
782 float sample_locations_4x[4][2];
783 float sample_locations_8x[8][2];
784
785 /* GFX7 and later */
786 uint32_t gfx_init_size_dw;
787 struct radeon_winsys_bo *gfx_init;
788
789 struct radeon_winsys_bo *trace_bo;
790 uint32_t *trace_id_ptr;
791
792 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
793 bool keep_shader_info;
794
795 struct radv_physical_device *physical_device;
796
797 /* Backup in-memory cache to be used if the app doesn't provide one */
798 struct radv_pipeline_cache * mem_cache;
799
800 /*
801 * use different counters so MSAA MRTs get consecutive surface indices,
802 * even if MASK is allocated in between.
803 */
804 uint32_t image_mrt_offset_counter;
805 uint32_t fmask_mrt_offset_counter;
806 struct list_head shader_slabs;
807 mtx_t shader_slab_mutex;
808
809 /* For detecting VM faults reported by dmesg. */
810 uint64_t dmesg_timestamp;
811
812 struct radv_device_extension_table enabled_extensions;
813 struct radv_device_dispatch_table dispatch;
814
815 /* Whether the app has enabled the robustBufferAccess feature. */
816 bool robust_buffer_access;
817
818 /* Whether the driver uses a global BO list. */
819 bool use_global_bo_list;
820
821 struct radv_bo_list bo_list;
822
823 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
824 int force_aniso;
825
826 struct radv_device_border_color_data border_color_data;
827
828 /* Condition variable for legacy timelines, to notify waiters when a
829 * new point gets submitted. */
830 pthread_cond_t timeline_cond;
831
832 /* Thread trace. */
833 struct radeon_cmdbuf *thread_trace_start_cs[2];
834 struct radeon_cmdbuf *thread_trace_stop_cs[2];
835 struct radeon_winsys_bo *thread_trace_bo;
836 void *thread_trace_ptr;
837 uint32_t thread_trace_buffer_size;
838 int thread_trace_start_frame;
839
840 /* Overallocation. */
841 bool overallocation_disallowed;
842 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
843 mtx_t overallocation_mutex;
844 };
845
846 struct radv_device_memory {
847 struct vk_object_base base;
848 struct radeon_winsys_bo *bo;
849 /* for dedicated allocations */
850 struct radv_image *image;
851 struct radv_buffer *buffer;
852 uint32_t heap_index;
853 uint64_t alloc_size;
854 void * map;
855 void * user_ptr;
856
857 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
858 struct AHardwareBuffer * android_hardware_buffer;
859 #endif
860 };
861
862
863 struct radv_descriptor_range {
864 uint64_t va;
865 uint32_t size;
866 };
867
868 struct radv_descriptor_set {
869 struct vk_object_base base;
870 const struct radv_descriptor_set_layout *layout;
871 uint32_t size;
872 uint32_t buffer_count;
873
874 struct radeon_winsys_bo *bo;
875 uint64_t va;
876 uint32_t *mapped_ptr;
877 struct radv_descriptor_range *dynamic_descriptors;
878
879 struct radeon_winsys_bo *descriptors[0];
880 };
881
882 struct radv_push_descriptor_set
883 {
884 struct radv_descriptor_set set;
885 uint32_t capacity;
886 };
887
888 struct radv_descriptor_pool_entry {
889 uint32_t offset;
890 uint32_t size;
891 struct radv_descriptor_set *set;
892 };
893
894 struct radv_descriptor_pool {
895 struct vk_object_base base;
896 struct radeon_winsys_bo *bo;
897 uint8_t *mapped_ptr;
898 uint64_t current_offset;
899 uint64_t size;
900
901 uint8_t *host_memory_base;
902 uint8_t *host_memory_ptr;
903 uint8_t *host_memory_end;
904
905 uint32_t entry_count;
906 uint32_t max_entry_count;
907 struct radv_descriptor_pool_entry entries[0];
908 };
909
910 struct radv_descriptor_update_template_entry {
911 VkDescriptorType descriptor_type;
912
913 /* The number of descriptors to update */
914 uint32_t descriptor_count;
915
916 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
917 uint32_t dst_offset;
918
919 /* In dwords. Not valid/used for dynamic descriptors */
920 uint32_t dst_stride;
921
922 uint32_t buffer_offset;
923
924 /* Only valid for combined image samplers and samplers */
925 uint8_t has_sampler;
926 uint8_t sampler_offset;
927
928 /* In bytes */
929 size_t src_offset;
930 size_t src_stride;
931
932 /* For push descriptors */
933 const uint32_t *immutable_samplers;
934 };
935
936 struct radv_descriptor_update_template {
937 struct vk_object_base base;
938 uint32_t entry_count;
939 VkPipelineBindPoint bind_point;
940 struct radv_descriptor_update_template_entry entry[0];
941 };
942
943 struct radv_buffer {
944 struct vk_object_base base;
945 VkDeviceSize size;
946
947 VkBufferUsageFlags usage;
948 VkBufferCreateFlags flags;
949
950 /* Set when bound */
951 struct radeon_winsys_bo * bo;
952 VkDeviceSize offset;
953
954 bool shareable;
955 };
956
957 enum radv_dynamic_state_bits {
958 RADV_DYNAMIC_VIEWPORT = 1 << 0,
959 RADV_DYNAMIC_SCISSOR = 1 << 1,
960 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
961 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
962 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
963 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
964 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
965 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
966 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
967 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
968 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
969 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
970 RADV_DYNAMIC_CULL_MODE = 1 << 12,
971 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
972 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
973 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
974 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
975 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
976 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
977 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
978 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
979 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
980 RADV_DYNAMIC_ALL = (1 << 22) - 1,
981 };
982
983 enum radv_cmd_dirty_bits {
984 /* Keep the dynamic state dirty bits in sync with
985 * enum radv_dynamic_state_bits */
986 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
987 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
988 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
989 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
990 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
991 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
992 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
993 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
994 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
995 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
996 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
997 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
998 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
999 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
1000 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
1001 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
1002 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
1003 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
1004 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
1005 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1006 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
1007 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1008 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
1009 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
1010 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
1011 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
1012 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
1013 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
1014 };
1015
1016 enum radv_cmd_flush_bits {
1017 /* Instruction cache. */
1018 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1019 /* Scalar L1 cache. */
1020 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1021 /* Vector L1 cache. */
1022 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1023 /* L2 cache + L2 metadata cache writeback & invalidate.
1024 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1025 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1026 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1027 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1028 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1029 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1030 /* Framebuffer caches */
1031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1032 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1033 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1034 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1035 /* Engine synchronization. */
1036 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1037 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1038 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1039 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1040 /* Pipeline query controls. */
1041 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1042 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1043 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1044
1045 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1046 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1047 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1048 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1049 };
1050
1051 struct radv_vertex_binding {
1052 struct radv_buffer * buffer;
1053 VkDeviceSize offset;
1054 VkDeviceSize size;
1055 VkDeviceSize stride;
1056 };
1057
1058 struct radv_streamout_binding {
1059 struct radv_buffer *buffer;
1060 VkDeviceSize offset;
1061 VkDeviceSize size;
1062 };
1063
1064 struct radv_streamout_state {
1065 /* Mask of bound streamout buffers. */
1066 uint8_t enabled_mask;
1067
1068 /* External state that comes from the last vertex stage, it must be
1069 * set explicitely when binding a new graphics pipeline.
1070 */
1071 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1072 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1073
1074 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1075 uint32_t hw_enabled_mask;
1076
1077 /* State of VGT_STRMOUT_(CONFIG|EN) */
1078 bool streamout_enabled;
1079 };
1080
1081 struct radv_viewport_state {
1082 uint32_t count;
1083 VkViewport viewports[MAX_VIEWPORTS];
1084 };
1085
1086 struct radv_scissor_state {
1087 uint32_t count;
1088 VkRect2D scissors[MAX_SCISSORS];
1089 };
1090
1091 struct radv_discard_rectangle_state {
1092 uint32_t count;
1093 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1094 };
1095
1096 struct radv_sample_locations_state {
1097 VkSampleCountFlagBits per_pixel;
1098 VkExtent2D grid_size;
1099 uint32_t count;
1100 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1101 };
1102
1103 struct radv_dynamic_state {
1104 /**
1105 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1106 * Defines the set of saved dynamic state.
1107 */
1108 uint32_t mask;
1109
1110 struct radv_viewport_state viewport;
1111
1112 struct radv_scissor_state scissor;
1113
1114 float line_width;
1115
1116 struct {
1117 float bias;
1118 float clamp;
1119 float slope;
1120 } depth_bias;
1121
1122 float blend_constants[4];
1123
1124 struct {
1125 float min;
1126 float max;
1127 } depth_bounds;
1128
1129 struct {
1130 uint32_t front;
1131 uint32_t back;
1132 } stencil_compare_mask;
1133
1134 struct {
1135 uint32_t front;
1136 uint32_t back;
1137 } stencil_write_mask;
1138
1139 struct {
1140 struct {
1141 VkStencilOp fail_op;
1142 VkStencilOp pass_op;
1143 VkStencilOp depth_fail_op;
1144 VkCompareOp compare_op;
1145 } front;
1146
1147 struct {
1148 VkStencilOp fail_op;
1149 VkStencilOp pass_op;
1150 VkStencilOp depth_fail_op;
1151 VkCompareOp compare_op;
1152 } back;
1153 } stencil_op;
1154
1155 struct {
1156 uint32_t front;
1157 uint32_t back;
1158 } stencil_reference;
1159
1160 struct radv_discard_rectangle_state discard_rectangle;
1161
1162 struct radv_sample_locations_state sample_location;
1163
1164 struct {
1165 uint32_t factor;
1166 uint16_t pattern;
1167 } line_stipple;
1168
1169 VkCullModeFlags cull_mode;
1170 VkFrontFace front_face;
1171 unsigned primitive_topology;
1172
1173 bool depth_test_enable;
1174 bool depth_write_enable;
1175 VkCompareOp depth_compare_op;
1176 bool depth_bounds_test_enable;
1177 bool stencil_test_enable;
1178 };
1179
1180 extern const struct radv_dynamic_state default_dynamic_state;
1181
1182 const char *
1183 radv_get_debug_option_name(int id);
1184
1185 const char *
1186 radv_get_perftest_option_name(int id);
1187
1188 struct radv_color_buffer_info {
1189 uint64_t cb_color_base;
1190 uint64_t cb_color_cmask;
1191 uint64_t cb_color_fmask;
1192 uint64_t cb_dcc_base;
1193 uint32_t cb_color_slice;
1194 uint32_t cb_color_view;
1195 uint32_t cb_color_info;
1196 uint32_t cb_color_attrib;
1197 uint32_t cb_color_attrib2; /* GFX9 and later */
1198 uint32_t cb_color_attrib3; /* GFX10 and later */
1199 uint32_t cb_dcc_control;
1200 uint32_t cb_color_cmask_slice;
1201 uint32_t cb_color_fmask_slice;
1202 union {
1203 uint32_t cb_color_pitch; // GFX6-GFX8
1204 uint32_t cb_mrt_epitch; // GFX9+
1205 };
1206 };
1207
1208 struct radv_ds_buffer_info {
1209 uint64_t db_z_read_base;
1210 uint64_t db_stencil_read_base;
1211 uint64_t db_z_write_base;
1212 uint64_t db_stencil_write_base;
1213 uint64_t db_htile_data_base;
1214 uint32_t db_depth_info;
1215 uint32_t db_z_info;
1216 uint32_t db_stencil_info;
1217 uint32_t db_depth_view;
1218 uint32_t db_depth_size;
1219 uint32_t db_depth_slice;
1220 uint32_t db_htile_surface;
1221 uint32_t pa_su_poly_offset_db_fmt_cntl;
1222 uint32_t db_z_info2; /* GFX9 only */
1223 uint32_t db_stencil_info2; /* GFX9 only */
1224 float offset_scale;
1225 };
1226
1227 void
1228 radv_initialise_color_surface(struct radv_device *device,
1229 struct radv_color_buffer_info *cb,
1230 struct radv_image_view *iview);
1231 void
1232 radv_initialise_ds_surface(struct radv_device *device,
1233 struct radv_ds_buffer_info *ds,
1234 struct radv_image_view *iview);
1235
1236 /**
1237 * Attachment state when recording a renderpass instance.
1238 *
1239 * The clear value is valid only if there exists a pending clear.
1240 */
1241 struct radv_attachment_state {
1242 VkImageAspectFlags pending_clear_aspects;
1243 uint32_t cleared_views;
1244 VkClearValue clear_value;
1245 VkImageLayout current_layout;
1246 VkImageLayout current_stencil_layout;
1247 bool current_in_render_loop;
1248 struct radv_sample_locations_state sample_location;
1249
1250 union {
1251 struct radv_color_buffer_info cb;
1252 struct radv_ds_buffer_info ds;
1253 };
1254 struct radv_image_view *iview;
1255 };
1256
1257 struct radv_descriptor_state {
1258 struct radv_descriptor_set *sets[MAX_SETS];
1259 uint32_t dirty;
1260 uint32_t valid;
1261 struct radv_push_descriptor_set push_set;
1262 bool push_dirty;
1263 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1264 };
1265
1266 struct radv_subpass_sample_locs_state {
1267 uint32_t subpass_idx;
1268 struct radv_sample_locations_state sample_location;
1269 };
1270
1271 struct radv_cmd_state {
1272 /* Vertex descriptors */
1273 uint64_t vb_va;
1274 unsigned vb_size;
1275
1276 bool predicating;
1277 uint32_t dirty;
1278
1279 uint32_t prefetch_L2_mask;
1280
1281 struct radv_pipeline * pipeline;
1282 struct radv_pipeline * emitted_pipeline;
1283 struct radv_pipeline * compute_pipeline;
1284 struct radv_pipeline * emitted_compute_pipeline;
1285 struct radv_framebuffer * framebuffer;
1286 struct radv_render_pass * pass;
1287 const struct radv_subpass * subpass;
1288 struct radv_dynamic_state dynamic;
1289 struct radv_attachment_state * attachments;
1290 struct radv_streamout_state streamout;
1291 VkRect2D render_area;
1292
1293 uint32_t num_subpass_sample_locs;
1294 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1295
1296 /* Index buffer */
1297 struct radv_buffer *index_buffer;
1298 uint64_t index_offset;
1299 uint32_t index_type;
1300 uint32_t max_index_count;
1301 uint64_t index_va;
1302 int32_t last_index_type;
1303
1304 int32_t last_primitive_reset_en;
1305 uint32_t last_primitive_reset_index;
1306 enum radv_cmd_flush_bits flush_bits;
1307 unsigned active_occlusion_queries;
1308 bool perfect_occlusion_queries_enabled;
1309 unsigned active_pipeline_queries;
1310 unsigned active_pipeline_gds_queries;
1311 float offset_scale;
1312 uint32_t trace_id;
1313 uint32_t last_ia_multi_vgt_param;
1314
1315 uint32_t last_num_instances;
1316 uint32_t last_first_instance;
1317 uint32_t last_vertex_offset;
1318
1319 uint32_t last_sx_ps_downconvert;
1320 uint32_t last_sx_blend_opt_epsilon;
1321 uint32_t last_sx_blend_opt_control;
1322
1323 /* Whether CP DMA is busy/idle. */
1324 bool dma_is_busy;
1325
1326 /* Conditional rendering info. */
1327 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1328 uint64_t predication_va;
1329
1330 /* Inheritance info. */
1331 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1332
1333 bool context_roll_without_scissor_emitted;
1334
1335 /* SQTT related state. */
1336 uint32_t current_event_type;
1337 uint32_t num_events;
1338 uint32_t num_layout_transitions;
1339 };
1340
1341 struct radv_cmd_pool {
1342 struct vk_object_base base;
1343 VkAllocationCallbacks alloc;
1344 struct list_head cmd_buffers;
1345 struct list_head free_cmd_buffers;
1346 uint32_t queue_family_index;
1347 };
1348
1349 struct radv_cmd_buffer_upload {
1350 uint8_t *map;
1351 unsigned offset;
1352 uint64_t size;
1353 struct radeon_winsys_bo *upload_bo;
1354 struct list_head list;
1355 };
1356
1357 enum radv_cmd_buffer_status {
1358 RADV_CMD_BUFFER_STATUS_INVALID,
1359 RADV_CMD_BUFFER_STATUS_INITIAL,
1360 RADV_CMD_BUFFER_STATUS_RECORDING,
1361 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1362 RADV_CMD_BUFFER_STATUS_PENDING,
1363 };
1364
1365 struct radv_cmd_buffer {
1366 struct vk_object_base base;
1367
1368 struct radv_device * device;
1369
1370 struct radv_cmd_pool * pool;
1371 struct list_head pool_link;
1372
1373 VkCommandBufferUsageFlags usage_flags;
1374 VkCommandBufferLevel level;
1375 enum radv_cmd_buffer_status status;
1376 struct radeon_cmdbuf *cs;
1377 struct radv_cmd_state state;
1378 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1379 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1380 uint32_t queue_family_index;
1381
1382 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1383 VkShaderStageFlags push_constant_stages;
1384 struct radv_descriptor_set meta_push_descriptors;
1385
1386 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1387
1388 struct radv_cmd_buffer_upload upload;
1389
1390 uint32_t scratch_size_per_wave_needed;
1391 uint32_t scratch_waves_wanted;
1392 uint32_t compute_scratch_size_per_wave_needed;
1393 uint32_t compute_scratch_waves_wanted;
1394 uint32_t esgs_ring_size_needed;
1395 uint32_t gsvs_ring_size_needed;
1396 bool tess_rings_needed;
1397 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1398 bool gds_oa_needed; /* for GFX10 streamout */
1399 bool sample_positions_needed;
1400
1401 VkResult record_result;
1402
1403 uint64_t gfx9_fence_va;
1404 uint32_t gfx9_fence_idx;
1405 uint64_t gfx9_eop_bug_va;
1406
1407 /**
1408 * Whether a query pool has been resetted and we have to flush caches.
1409 */
1410 bool pending_reset_query;
1411
1412 /**
1413 * Bitmask of pending active query flushes.
1414 */
1415 enum radv_cmd_flush_bits active_query_flush_bits;
1416 };
1417
1418 struct radv_image;
1419 struct radv_image_view;
1420
1421 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1422
1423 void si_emit_graphics(struct radv_device *device,
1424 struct radeon_cmdbuf *cs);
1425 void si_emit_compute(struct radv_physical_device *physical_device,
1426 struct radeon_cmdbuf *cs);
1427
1428 void cik_create_gfx_config(struct radv_device *device);
1429
1430 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1431 int count, const VkViewport *viewports);
1432 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1433 int count, const VkRect2D *scissors,
1434 const VkViewport *viewports, bool can_use_guardband);
1435 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1436 bool instanced_draw, bool indirect_draw,
1437 bool count_from_stream_output,
1438 uint32_t draw_vertex_count,
1439 unsigned topology);
1440 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1441 enum chip_class chip_class,
1442 bool is_mec,
1443 unsigned event, unsigned event_flags,
1444 unsigned dst_sel, unsigned data_sel,
1445 uint64_t va,
1446 uint32_t new_fence,
1447 uint64_t gfx9_eop_bug_va);
1448
1449 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1450 uint32_t ref, uint32_t mask);
1451 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1452 enum chip_class chip_class,
1453 uint32_t *fence_ptr, uint64_t va,
1454 bool is_mec,
1455 enum radv_cmd_flush_bits flush_bits,
1456 uint64_t gfx9_eop_bug_va);
1457 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1458 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1459 bool inverted, uint64_t va);
1460 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1461 uint64_t src_va, uint64_t dest_va,
1462 uint64_t size);
1463 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1464 unsigned size);
1465 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1466 uint64_t size, unsigned value);
1467 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1468
1469 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1470 bool
1471 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1472 unsigned size,
1473 unsigned alignment,
1474 unsigned *out_offset,
1475 void **ptr);
1476 void
1477 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1478 const struct radv_subpass *subpass);
1479 bool
1480 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1481 unsigned size, unsigned alignmnet,
1482 const void *data, unsigned *out_offset);
1483
1484 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1485 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1486 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1487 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1488 VkImageAspectFlags aspects,
1489 VkResolveModeFlagBits resolve_mode);
1490 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1491 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1492 VkImageAspectFlags aspects,
1493 VkResolveModeFlagBits resolve_mode);
1494 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1495 unsigned radv_get_default_max_sample_dist(int log_samples);
1496 void radv_device_init_msaa(struct radv_device *device);
1497
1498 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1499 const struct radv_image_view *iview,
1500 VkClearDepthStencilValue ds_clear_value,
1501 VkImageAspectFlags aspects);
1502
1503 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1504 const struct radv_image_view *iview,
1505 int cb_idx,
1506 uint32_t color_values[2]);
1507
1508 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1509 struct radv_image *image,
1510 const VkImageSubresourceRange *range, bool value);
1511
1512 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1513 struct radv_image *image,
1514 const VkImageSubresourceRange *range, bool value);
1515
1516 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1517 struct radeon_winsys_bo *bo,
1518 uint64_t offset, uint64_t size, uint32_t value);
1519 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1520 bool radv_get_memory_fd(struct radv_device *device,
1521 struct radv_device_memory *memory,
1522 int *pFD);
1523 void radv_free_memory(struct radv_device *device,
1524 const VkAllocationCallbacks* pAllocator,
1525 struct radv_device_memory *mem);
1526
1527 static inline void
1528 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1529 unsigned sh_offset, unsigned pointer_count,
1530 bool use_32bit_pointers)
1531 {
1532 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1533 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1534 }
1535
1536 static inline void
1537 radv_emit_shader_pointer_body(struct radv_device *device,
1538 struct radeon_cmdbuf *cs,
1539 uint64_t va, bool use_32bit_pointers)
1540 {
1541 radeon_emit(cs, va);
1542
1543 if (use_32bit_pointers) {
1544 assert(va == 0 ||
1545 (va >> 32) == device->physical_device->rad_info.address32_hi);
1546 } else {
1547 radeon_emit(cs, va >> 32);
1548 }
1549 }
1550
1551 static inline void
1552 radv_emit_shader_pointer(struct radv_device *device,
1553 struct radeon_cmdbuf *cs,
1554 uint32_t sh_offset, uint64_t va, bool global)
1555 {
1556 bool use_32bit_pointers = !global;
1557
1558 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1559 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1560 }
1561
1562 static inline struct radv_descriptor_state *
1563 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1564 VkPipelineBindPoint bind_point)
1565 {
1566 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1567 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1568 return &cmd_buffer->descriptors[bind_point];
1569 }
1570
1571 /*
1572 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1573 *
1574 * Limitations: Can't call normal dispatch functions without binding or rebinding
1575 * the compute pipeline.
1576 */
1577 void radv_unaligned_dispatch(
1578 struct radv_cmd_buffer *cmd_buffer,
1579 uint32_t x,
1580 uint32_t y,
1581 uint32_t z);
1582
1583 struct radv_event {
1584 struct vk_object_base base;
1585 struct radeon_winsys_bo *bo;
1586 uint64_t *map;
1587 };
1588
1589 struct radv_shader_module;
1590
1591 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1592 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1593 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1594 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1595 #define RADV_HASH_SHADER_LLVM (1 << 4)
1596
1597 void
1598 radv_hash_shaders(unsigned char *hash,
1599 const VkPipelineShaderStageCreateInfo **stages,
1600 const struct radv_pipeline_layout *layout,
1601 const struct radv_pipeline_key *key,
1602 uint32_t flags);
1603
1604 static inline gl_shader_stage
1605 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1606 {
1607 assert(__builtin_popcount(vk_stage) == 1);
1608 return ffs(vk_stage) - 1;
1609 }
1610
1611 static inline VkShaderStageFlagBits
1612 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1613 {
1614 return (1 << mesa_stage);
1615 }
1616
1617 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1618
1619 #define radv_foreach_stage(stage, stage_bits) \
1620 for (gl_shader_stage stage, \
1621 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1622 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1623 __tmp &= ~(1 << (stage)))
1624
1625 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1626 unsigned radv_format_meta_fs_key(VkFormat format);
1627
1628 struct radv_multisample_state {
1629 uint32_t db_eqaa;
1630 uint32_t pa_sc_mode_cntl_0;
1631 uint32_t pa_sc_mode_cntl_1;
1632 uint32_t pa_sc_aa_config;
1633 uint32_t pa_sc_aa_mask[2];
1634 unsigned num_samples;
1635 };
1636
1637 struct radv_prim_vertex_count {
1638 uint8_t min;
1639 uint8_t incr;
1640 };
1641
1642 struct radv_ia_multi_vgt_param_helpers {
1643 uint32_t base;
1644 bool partial_es_wave;
1645 uint8_t primgroup_size;
1646 bool ia_switch_on_eoi;
1647 bool partial_vs_wave;
1648 };
1649
1650 struct radv_binning_state {
1651 uint32_t pa_sc_binner_cntl_0;
1652 uint32_t db_dfsm_control;
1653 };
1654
1655 #define SI_GS_PER_ES 128
1656
1657 struct radv_pipeline {
1658 struct vk_object_base base;
1659 struct radv_device * device;
1660 struct radv_dynamic_state dynamic_state;
1661
1662 struct radv_pipeline_layout * layout;
1663
1664 bool need_indirect_descriptor_sets;
1665 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1666 struct radv_shader_variant *gs_copy_shader;
1667 VkShaderStageFlags active_stages;
1668
1669 struct radeon_cmdbuf cs;
1670 uint32_t ctx_cs_hash;
1671 struct radeon_cmdbuf ctx_cs;
1672
1673 uint32_t binding_stride[MAX_VBS];
1674 uint8_t num_vertex_bindings;
1675
1676 uint32_t user_data_0[MESA_SHADER_STAGES];
1677 union {
1678 struct {
1679 struct radv_multisample_state ms;
1680 struct radv_binning_state binning;
1681 uint32_t spi_baryc_cntl;
1682 bool prim_restart_enable;
1683 unsigned esgs_ring_size;
1684 unsigned gsvs_ring_size;
1685 uint32_t vtx_base_sgpr;
1686 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1687 uint8_t vtx_emit_num;
1688 bool can_use_guardband;
1689 uint32_t needed_dynamic_state;
1690 bool disable_out_of_order_rast_for_occlusion;
1691 unsigned tess_patch_control_points;
1692 unsigned pa_su_sc_mode_cntl;
1693 unsigned db_depth_control;
1694 bool uses_dynamic_stride;
1695
1696 /* Used for rbplus */
1697 uint32_t col_format;
1698 uint32_t cb_target_mask;
1699 } graphics;
1700 };
1701
1702 unsigned max_waves;
1703 unsigned scratch_bytes_per_wave;
1704
1705 /* Not NULL if graphics pipeline uses streamout. */
1706 struct radv_shader_variant *streamout_shader;
1707 };
1708
1709 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1710 {
1711 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1712 }
1713
1714 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1715 {
1716 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1717 }
1718
1719 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1720
1721 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1722
1723 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1724
1725 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1726 gl_shader_stage stage,
1727 int idx);
1728
1729 struct radv_shader_variant *radv_get_shader(const struct radv_pipeline *pipeline,
1730 gl_shader_stage stage);
1731
1732 struct radv_graphics_pipeline_create_info {
1733 bool use_rectlist;
1734 bool db_depth_clear;
1735 bool db_stencil_clear;
1736 bool db_depth_disable_expclear;
1737 bool db_stencil_disable_expclear;
1738 bool depth_compress_disable;
1739 bool stencil_compress_disable;
1740 bool resummarize_enable;
1741 uint32_t custom_blend_mode;
1742 };
1743
1744 VkResult
1745 radv_graphics_pipeline_create(VkDevice device,
1746 VkPipelineCache cache,
1747 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1748 const struct radv_graphics_pipeline_create_info *extra,
1749 const VkAllocationCallbacks *alloc,
1750 VkPipeline *pPipeline);
1751
1752 struct radv_binning_settings {
1753 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1754 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1755 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1756 };
1757
1758 struct radv_binning_settings
1759 radv_get_binning_settings(const struct radv_physical_device *pdev);
1760
1761 struct vk_format_description;
1762 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1763 int first_non_void);
1764 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1765 int first_non_void);
1766 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1767 uint32_t radv_translate_colorformat(VkFormat format);
1768 uint32_t radv_translate_color_numformat(VkFormat format,
1769 const struct vk_format_description *desc,
1770 int first_non_void);
1771 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1772 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1773 uint32_t radv_translate_dbformat(VkFormat format);
1774 uint32_t radv_translate_tex_dataformat(VkFormat format,
1775 const struct vk_format_description *desc,
1776 int first_non_void);
1777 uint32_t radv_translate_tex_numformat(VkFormat format,
1778 const struct vk_format_description *desc,
1779 int first_non_void);
1780 bool radv_format_pack_clear_color(VkFormat format,
1781 uint32_t clear_vals[2],
1782 VkClearColorValue *value);
1783 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1784 bool radv_dcc_formats_compatible(VkFormat format1,
1785 VkFormat format2);
1786 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1787
1788 struct radv_image_plane {
1789 VkFormat format;
1790 struct radeon_surf surface;
1791 uint64_t offset;
1792 };
1793
1794 struct radv_image {
1795 struct vk_object_base base;
1796 VkImageType type;
1797 /* The original VkFormat provided by the client. This may not match any
1798 * of the actual surface formats.
1799 */
1800 VkFormat vk_format;
1801 VkImageAspectFlags aspects;
1802 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1803 struct ac_surf_info info;
1804 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1805 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1806
1807 VkDeviceSize size;
1808 uint32_t alignment;
1809
1810 unsigned queue_family_mask;
1811 bool exclusive;
1812 bool shareable;
1813
1814 /* Set when bound */
1815 struct radeon_winsys_bo *bo;
1816 VkDeviceSize offset;
1817 bool tc_compatible_htile;
1818 bool tc_compatible_cmask;
1819
1820 uint64_t clear_value_offset;
1821 uint64_t fce_pred_offset;
1822 uint64_t dcc_pred_offset;
1823
1824 /*
1825 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1826 * stored at this offset is UINT_MAX, the driver will emit
1827 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1828 * SET_CONTEXT_REG packet.
1829 */
1830 uint64_t tc_compat_zrange_offset;
1831
1832 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1833 VkDeviceMemory owned_memory;
1834
1835 unsigned plane_count;
1836 struct radv_image_plane planes[0];
1837 };
1838
1839 /* Whether the image has a htile that is known consistent with the contents of
1840 * the image and is allowed to be in compressed form.
1841 *
1842 * If this is false reads that don't use the htile should be able to return
1843 * correct results.
1844 */
1845 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1846 VkImageLayout layout,
1847 bool in_render_loop,
1848 unsigned queue_mask);
1849
1850 bool radv_layout_can_fast_clear(const struct radv_image *image,
1851 VkImageLayout layout,
1852 bool in_render_loop,
1853 unsigned queue_mask);
1854
1855 bool radv_layout_dcc_compressed(const struct radv_device *device,
1856 const struct radv_image *image,
1857 VkImageLayout layout,
1858 bool in_render_loop,
1859 unsigned queue_mask);
1860
1861 /**
1862 * Return whether the image has CMASK metadata for color surfaces.
1863 */
1864 static inline bool
1865 radv_image_has_cmask(const struct radv_image *image)
1866 {
1867 return image->planes[0].surface.cmask_offset;
1868 }
1869
1870 /**
1871 * Return whether the image has FMASK metadata for color surfaces.
1872 */
1873 static inline bool
1874 radv_image_has_fmask(const struct radv_image *image)
1875 {
1876 return image->planes[0].surface.fmask_offset;
1877 }
1878
1879 /**
1880 * Return whether the image has DCC metadata for color surfaces.
1881 */
1882 static inline bool
1883 radv_image_has_dcc(const struct radv_image *image)
1884 {
1885 return image->planes[0].surface.dcc_size;
1886 }
1887
1888 /**
1889 * Return whether the image is TC-compatible CMASK.
1890 */
1891 static inline bool
1892 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1893 {
1894 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1895 }
1896
1897 /**
1898 * Return whether DCC metadata is enabled for a level.
1899 */
1900 static inline bool
1901 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1902 {
1903 return radv_image_has_dcc(image) &&
1904 level < image->planes[0].surface.num_dcc_levels;
1905 }
1906
1907 /**
1908 * Return whether the image has CB metadata.
1909 */
1910 static inline bool
1911 radv_image_has_CB_metadata(const struct radv_image *image)
1912 {
1913 return radv_image_has_cmask(image) ||
1914 radv_image_has_fmask(image) ||
1915 radv_image_has_dcc(image);
1916 }
1917
1918 /**
1919 * Return whether the image has HTILE metadata for depth surfaces.
1920 */
1921 static inline bool
1922 radv_image_has_htile(const struct radv_image *image)
1923 {
1924 return image->planes[0].surface.htile_size;
1925 }
1926
1927 /**
1928 * Return whether HTILE metadata is enabled for a level.
1929 */
1930 static inline bool
1931 radv_htile_enabled(const struct radv_image *image, unsigned level)
1932 {
1933 return radv_image_has_htile(image) && level == 0;
1934 }
1935
1936 /**
1937 * Return whether the image is TC-compatible HTILE.
1938 */
1939 static inline bool
1940 radv_image_is_tc_compat_htile(const struct radv_image *image)
1941 {
1942 return radv_image_has_htile(image) && image->tc_compatible_htile;
1943 }
1944
1945 static inline uint64_t
1946 radv_image_get_fast_clear_va(const struct radv_image *image,
1947 uint32_t base_level)
1948 {
1949 uint64_t va = radv_buffer_get_va(image->bo);
1950 va += image->offset + image->clear_value_offset + base_level * 8;
1951 return va;
1952 }
1953
1954 static inline uint64_t
1955 radv_image_get_fce_pred_va(const struct radv_image *image,
1956 uint32_t base_level)
1957 {
1958 uint64_t va = radv_buffer_get_va(image->bo);
1959 va += image->offset + image->fce_pred_offset + base_level * 8;
1960 return va;
1961 }
1962
1963 static inline uint64_t
1964 radv_image_get_dcc_pred_va(const struct radv_image *image,
1965 uint32_t base_level)
1966 {
1967 uint64_t va = radv_buffer_get_va(image->bo);
1968 va += image->offset + image->dcc_pred_offset + base_level * 8;
1969 return va;
1970 }
1971
1972 static inline uint64_t
1973 radv_get_tc_compat_zrange_va(const struct radv_image *image,
1974 uint32_t base_level)
1975 {
1976 uint64_t va = radv_buffer_get_va(image->bo);
1977 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
1978 return va;
1979 }
1980
1981 static inline uint64_t
1982 radv_get_ds_clear_value_va(const struct radv_image *image,
1983 uint32_t base_level)
1984 {
1985 uint64_t va = radv_buffer_get_va(image->bo);
1986 va += image->offset + image->clear_value_offset + base_level * 8;
1987 return va;
1988 }
1989
1990 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1991
1992 static inline uint32_t
1993 radv_get_layerCount(const struct radv_image *image,
1994 const VkImageSubresourceRange *range)
1995 {
1996 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1997 image->info.array_size - range->baseArrayLayer : range->layerCount;
1998 }
1999
2000 static inline uint32_t
2001 radv_get_levelCount(const struct radv_image *image,
2002 const VkImageSubresourceRange *range)
2003 {
2004 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2005 image->info.levels - range->baseMipLevel : range->levelCount;
2006 }
2007
2008 struct radeon_bo_metadata;
2009 void
2010 radv_init_metadata(struct radv_device *device,
2011 struct radv_image *image,
2012 struct radeon_bo_metadata *metadata);
2013
2014 void
2015 radv_image_override_offset_stride(struct radv_device *device,
2016 struct radv_image *image,
2017 uint64_t offset, uint32_t stride);
2018
2019 union radv_descriptor {
2020 struct {
2021 uint32_t plane0_descriptor[8];
2022 uint32_t fmask_descriptor[8];
2023 };
2024 struct {
2025 uint32_t plane_descriptors[3][8];
2026 };
2027 };
2028
2029 struct radv_image_view {
2030 struct vk_object_base base;
2031 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2032 struct radeon_winsys_bo *bo;
2033
2034 VkImageViewType type;
2035 VkImageAspectFlags aspect_mask;
2036 VkFormat vk_format;
2037 unsigned plane_id;
2038 bool multiple_planes;
2039 uint32_t base_layer;
2040 uint32_t layer_count;
2041 uint32_t base_mip;
2042 uint32_t level_count;
2043 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2044
2045 union radv_descriptor descriptor;
2046
2047 /* Descriptor for use as a storage image as opposed to a sampled image.
2048 * This has a few differences for cube maps (e.g. type).
2049 */
2050 union radv_descriptor storage_descriptor;
2051 };
2052
2053 struct radv_image_create_info {
2054 const VkImageCreateInfo *vk_info;
2055 bool scanout;
2056 bool no_metadata_planes;
2057 const struct radeon_bo_metadata *bo_metadata;
2058 };
2059
2060 VkResult
2061 radv_image_create_layout(struct radv_device *device,
2062 struct radv_image_create_info create_info,
2063 struct radv_image *image);
2064
2065 VkResult radv_image_create(VkDevice _device,
2066 const struct radv_image_create_info *info,
2067 const VkAllocationCallbacks* alloc,
2068 VkImage *pImage);
2069
2070 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2071
2072 VkResult
2073 radv_image_from_gralloc(VkDevice device_h,
2074 const VkImageCreateInfo *base_info,
2075 const VkNativeBufferANDROID *gralloc_info,
2076 const VkAllocationCallbacks *alloc,
2077 VkImage *out_image_h);
2078 uint64_t
2079 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2080 const VkImageUsageFlags vk_usage);
2081 VkResult
2082 radv_import_ahb_memory(struct radv_device *device,
2083 struct radv_device_memory *mem,
2084 unsigned priority,
2085 const VkImportAndroidHardwareBufferInfoANDROID *info);
2086 VkResult
2087 radv_create_ahb_memory(struct radv_device *device,
2088 struct radv_device_memory *mem,
2089 unsigned priority,
2090 const VkMemoryAllocateInfo *pAllocateInfo);
2091
2092 VkFormat
2093 radv_select_android_external_format(const void *next, VkFormat default_format);
2094
2095 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2096
2097 struct radv_image_view_extra_create_info {
2098 bool disable_compression;
2099 };
2100
2101 void radv_image_view_init(struct radv_image_view *view,
2102 struct radv_device *device,
2103 const VkImageViewCreateInfo *pCreateInfo,
2104 const struct radv_image_view_extra_create_info* extra_create_info);
2105
2106 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2107
2108 struct radv_sampler_ycbcr_conversion {
2109 struct vk_object_base base;
2110 VkFormat format;
2111 VkSamplerYcbcrModelConversion ycbcr_model;
2112 VkSamplerYcbcrRange ycbcr_range;
2113 VkComponentMapping components;
2114 VkChromaLocation chroma_offsets[2];
2115 VkFilter chroma_filter;
2116 };
2117
2118 struct radv_buffer_view {
2119 struct vk_object_base base;
2120 struct radeon_winsys_bo *bo;
2121 VkFormat vk_format;
2122 uint64_t range; /**< VkBufferViewCreateInfo::range */
2123 uint32_t state[4];
2124 };
2125 void radv_buffer_view_init(struct radv_buffer_view *view,
2126 struct radv_device *device,
2127 const VkBufferViewCreateInfo* pCreateInfo);
2128
2129 static inline struct VkExtent3D
2130 radv_sanitize_image_extent(const VkImageType imageType,
2131 const struct VkExtent3D imageExtent)
2132 {
2133 switch (imageType) {
2134 case VK_IMAGE_TYPE_1D:
2135 return (VkExtent3D) { imageExtent.width, 1, 1 };
2136 case VK_IMAGE_TYPE_2D:
2137 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2138 case VK_IMAGE_TYPE_3D:
2139 return imageExtent;
2140 default:
2141 unreachable("invalid image type");
2142 }
2143 }
2144
2145 static inline struct VkOffset3D
2146 radv_sanitize_image_offset(const VkImageType imageType,
2147 const struct VkOffset3D imageOffset)
2148 {
2149 switch (imageType) {
2150 case VK_IMAGE_TYPE_1D:
2151 return (VkOffset3D) { imageOffset.x, 0, 0 };
2152 case VK_IMAGE_TYPE_2D:
2153 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2154 case VK_IMAGE_TYPE_3D:
2155 return imageOffset;
2156 default:
2157 unreachable("invalid image type");
2158 }
2159 }
2160
2161 static inline bool
2162 radv_image_extent_compare(const struct radv_image *image,
2163 const VkExtent3D *extent)
2164 {
2165 if (extent->width != image->info.width ||
2166 extent->height != image->info.height ||
2167 extent->depth != image->info.depth)
2168 return false;
2169 return true;
2170 }
2171
2172 struct radv_sampler {
2173 struct vk_object_base base;
2174 uint32_t state[4];
2175 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2176 uint32_t border_color_slot;
2177 };
2178
2179 struct radv_framebuffer {
2180 struct vk_object_base base;
2181 uint32_t width;
2182 uint32_t height;
2183 uint32_t layers;
2184
2185 uint32_t attachment_count;
2186 struct radv_image_view *attachments[0];
2187 };
2188
2189 struct radv_subpass_barrier {
2190 VkPipelineStageFlags src_stage_mask;
2191 VkAccessFlags src_access_mask;
2192 VkAccessFlags dst_access_mask;
2193 };
2194
2195 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2196 const struct radv_subpass_barrier *barrier);
2197
2198 struct radv_subpass_attachment {
2199 uint32_t attachment;
2200 VkImageLayout layout;
2201 VkImageLayout stencil_layout;
2202 bool in_render_loop;
2203 };
2204
2205 struct radv_subpass {
2206 uint32_t attachment_count;
2207 struct radv_subpass_attachment * attachments;
2208
2209 uint32_t input_count;
2210 uint32_t color_count;
2211 struct radv_subpass_attachment * input_attachments;
2212 struct radv_subpass_attachment * color_attachments;
2213 struct radv_subpass_attachment * resolve_attachments;
2214 struct radv_subpass_attachment * depth_stencil_attachment;
2215 struct radv_subpass_attachment * ds_resolve_attachment;
2216 VkResolveModeFlagBits depth_resolve_mode;
2217 VkResolveModeFlagBits stencil_resolve_mode;
2218
2219 /** Subpass has at least one color resolve attachment */
2220 bool has_color_resolve;
2221
2222 /** Subpass has at least one color attachment */
2223 bool has_color_att;
2224
2225 struct radv_subpass_barrier start_barrier;
2226
2227 uint32_t view_mask;
2228
2229 VkSampleCountFlagBits color_sample_count;
2230 VkSampleCountFlagBits depth_sample_count;
2231 VkSampleCountFlagBits max_sample_count;
2232 };
2233
2234 uint32_t
2235 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2236
2237 struct radv_render_pass_attachment {
2238 VkFormat format;
2239 uint32_t samples;
2240 VkAttachmentLoadOp load_op;
2241 VkAttachmentLoadOp stencil_load_op;
2242 VkImageLayout initial_layout;
2243 VkImageLayout final_layout;
2244 VkImageLayout stencil_initial_layout;
2245 VkImageLayout stencil_final_layout;
2246
2247 /* The subpass id in which the attachment will be used first/last. */
2248 uint32_t first_subpass_idx;
2249 uint32_t last_subpass_idx;
2250 };
2251
2252 struct radv_render_pass {
2253 struct vk_object_base base;
2254 uint32_t attachment_count;
2255 uint32_t subpass_count;
2256 struct radv_subpass_attachment * subpass_attachments;
2257 struct radv_render_pass_attachment * attachments;
2258 struct radv_subpass_barrier end_barrier;
2259 struct radv_subpass subpasses[0];
2260 };
2261
2262 VkResult radv_device_init_meta(struct radv_device *device);
2263 void radv_device_finish_meta(struct radv_device *device);
2264
2265 struct radv_query_pool {
2266 struct vk_object_base base;
2267 struct radeon_winsys_bo *bo;
2268 uint32_t stride;
2269 uint32_t availability_offset;
2270 uint64_t size;
2271 char *ptr;
2272 VkQueryType type;
2273 uint32_t pipeline_stats_mask;
2274 };
2275
2276 typedef enum {
2277 RADV_SEMAPHORE_NONE,
2278 RADV_SEMAPHORE_WINSYS,
2279 RADV_SEMAPHORE_SYNCOBJ,
2280 RADV_SEMAPHORE_TIMELINE_SYNCOBJ,
2281 RADV_SEMAPHORE_TIMELINE,
2282 } radv_semaphore_kind;
2283
2284 struct radv_deferred_queue_submission;
2285
2286 struct radv_timeline_waiter {
2287 struct list_head list;
2288 struct radv_deferred_queue_submission *submission;
2289 uint64_t value;
2290 };
2291
2292 struct radv_timeline_point {
2293 struct list_head list;
2294
2295 uint64_t value;
2296 uint32_t syncobj;
2297
2298 /* Separate from the list to accomodate CPU wait being async, as well
2299 * as prevent point deletion during submission. */
2300 unsigned wait_count;
2301 };
2302
2303 struct radv_timeline {
2304 /* Using a pthread mutex to be compatible with condition variables. */
2305 pthread_mutex_t mutex;
2306
2307 uint64_t highest_signaled;
2308 uint64_t highest_submitted;
2309
2310 struct list_head points;
2311
2312 /* Keep free points on hand so we do not have to recreate syncobjs all
2313 * the time. */
2314 struct list_head free_points;
2315
2316 /* Submissions that are deferred waiting for a specific value to be
2317 * submitted. */
2318 struct list_head waiters;
2319 };
2320
2321 struct radv_timeline_syncobj {
2322 /* Keep syncobj first, so common-code can just handle this as
2323 * non-timeline syncobj. */
2324 uint32_t syncobj;
2325 uint64_t max_point; /* max submitted point. */
2326 };
2327
2328 struct radv_semaphore_part {
2329 radv_semaphore_kind kind;
2330 union {
2331 uint32_t syncobj;
2332 struct radeon_winsys_sem *ws_sem;
2333 struct radv_timeline timeline;
2334 struct radv_timeline_syncobj timeline_syncobj;
2335 };
2336 };
2337
2338 struct radv_semaphore {
2339 struct vk_object_base base;
2340 struct radv_semaphore_part permanent;
2341 struct radv_semaphore_part temporary;
2342 };
2343
2344 bool radv_queue_internal_submit(struct radv_queue *queue,
2345 struct radeon_cmdbuf *cs);
2346
2347 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2348 VkPipelineBindPoint bind_point,
2349 struct radv_descriptor_set *set,
2350 unsigned idx);
2351
2352 void
2353 radv_update_descriptor_sets(struct radv_device *device,
2354 struct radv_cmd_buffer *cmd_buffer,
2355 VkDescriptorSet overrideSet,
2356 uint32_t descriptorWriteCount,
2357 const VkWriteDescriptorSet *pDescriptorWrites,
2358 uint32_t descriptorCopyCount,
2359 const VkCopyDescriptorSet *pDescriptorCopies);
2360
2361 void
2362 radv_update_descriptor_set_with_template(struct radv_device *device,
2363 struct radv_cmd_buffer *cmd_buffer,
2364 struct radv_descriptor_set *set,
2365 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2366 const void *pData);
2367
2368 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2369 VkPipelineBindPoint pipelineBindPoint,
2370 VkPipelineLayout _layout,
2371 uint32_t set,
2372 uint32_t descriptorWriteCount,
2373 const VkWriteDescriptorSet *pDescriptorWrites);
2374
2375 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2376 struct radv_image *image,
2377 const VkImageSubresourceRange *range, uint32_t value);
2378
2379 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2380 struct radv_image *image,
2381 const VkImageSubresourceRange *range);
2382
2383 typedef enum {
2384 RADV_FENCE_NONE,
2385 RADV_FENCE_WINSYS,
2386 RADV_FENCE_SYNCOBJ,
2387 RADV_FENCE_WSI,
2388 } radv_fence_kind;
2389
2390 struct radv_fence_part {
2391 radv_fence_kind kind;
2392
2393 union {
2394 /* AMDGPU winsys fence. */
2395 struct radeon_winsys_fence *fence;
2396
2397 /* DRM syncobj handle for syncobj-based fences. */
2398 uint32_t syncobj;
2399
2400 /* WSI fence. */
2401 struct wsi_fence *fence_wsi;
2402 };
2403 };
2404
2405 struct radv_fence {
2406 struct vk_object_base base;
2407 struct radv_fence_part permanent;
2408 struct radv_fence_part temporary;
2409 };
2410
2411 /* radv_nir_to_llvm.c */
2412 struct radv_shader_args;
2413
2414 void llvm_compile_shader(struct radv_device *device,
2415 unsigned shader_count,
2416 struct nir_shader *const *shaders,
2417 struct radv_shader_binary **binary,
2418 struct radv_shader_args *args);
2419
2420 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2421 gl_shader_stage stage,
2422 const struct nir_shader *nir);
2423
2424 /* radv_shader_info.h */
2425 struct radv_shader_info;
2426 struct radv_shader_variant_key;
2427
2428 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2429 const struct radv_pipeline_layout *layout,
2430 const struct radv_shader_variant_key *key,
2431 struct radv_shader_info *info,
2432 bool use_llvm);
2433
2434 void radv_nir_shader_info_init(struct radv_shader_info *info);
2435
2436 /* radv_sqtt.c */
2437 struct radv_thread_trace_info {
2438 uint32_t cur_offset;
2439 uint32_t trace_status;
2440 union {
2441 uint32_t gfx9_write_counter;
2442 uint32_t gfx10_dropped_cntr;
2443 };
2444 };
2445
2446 struct radv_thread_trace_se {
2447 struct radv_thread_trace_info info;
2448 void *data_ptr;
2449 uint32_t shader_engine;
2450 uint32_t compute_unit;
2451 };
2452
2453 struct radv_thread_trace {
2454 uint32_t num_traces;
2455 struct radv_thread_trace_se traces[4];
2456 };
2457
2458 bool radv_thread_trace_init(struct radv_device *device);
2459 void radv_thread_trace_finish(struct radv_device *device);
2460 bool radv_begin_thread_trace(struct radv_queue *queue);
2461 bool radv_end_thread_trace(struct radv_queue *queue);
2462 bool radv_get_thread_trace(struct radv_queue *queue,
2463 struct radv_thread_trace *thread_trace);
2464 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2465 const void *data, uint32_t num_dwords);
2466
2467 /* radv_rgp.c */
2468 int radv_dump_thread_trace(struct radv_device *device,
2469 const struct radv_thread_trace *trace);
2470
2471 /* radv_sqtt_layer_.c */
2472 struct radv_barrier_data {
2473 union {
2474 struct {
2475 uint16_t depth_stencil_expand : 1;
2476 uint16_t htile_hiz_range_expand : 1;
2477 uint16_t depth_stencil_resummarize : 1;
2478 uint16_t dcc_decompress : 1;
2479 uint16_t fmask_decompress : 1;
2480 uint16_t fast_clear_eliminate : 1;
2481 uint16_t fmask_color_expand : 1;
2482 uint16_t init_mask_ram : 1;
2483 uint16_t reserved : 8;
2484 };
2485 uint16_t all;
2486 } layout_transitions;
2487 };
2488
2489 /**
2490 * Value for the reason field of an RGP barrier start marker originating from
2491 * the Vulkan client (does not include PAL-defined values). (Table 15)
2492 */
2493 enum rgp_barrier_reason {
2494 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2495
2496 /* External app-generated barrier reasons, i.e. API synchronization
2497 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2498 */
2499 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2500 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2501 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2502
2503 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2504 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2505 */
2506 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2507 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2508 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2509 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2510 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2511 };
2512
2513 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2514 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2515 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2516 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2517 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2518 VkImageAspectFlagBits aspects);
2519 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2520 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2521 enum rgp_barrier_reason reason);
2522 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2523 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2524 const struct radv_barrier_data *barrier);
2525
2526 struct radeon_winsys_sem;
2527
2528 uint64_t radv_get_current_time(void);
2529
2530 static inline uint32_t
2531 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2532 {
2533 switch (gl_prim) {
2534 case 0: /* GL_POINTS */
2535 return 1;
2536 case 1: /* GL_LINES */
2537 case 3: /* GL_LINE_STRIP */
2538 return 2;
2539 case 4: /* GL_TRIANGLES */
2540 case 5: /* GL_TRIANGLE_STRIP */
2541 return 3;
2542 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2543 return 4;
2544 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2545 return 6;
2546 case 7: /* GL_QUADS */
2547 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2548 default:
2549 assert(0);
2550 return 0;
2551 }
2552 }
2553
2554 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2555 const VkRenderPassBeginInfo *pRenderPassBegin);
2556 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2557
2558 static inline uint32_t si_translate_prim(unsigned topology)
2559 {
2560 switch (topology) {
2561 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2562 return V_008958_DI_PT_POINTLIST;
2563 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2564 return V_008958_DI_PT_LINELIST;
2565 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2566 return V_008958_DI_PT_LINESTRIP;
2567 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2568 return V_008958_DI_PT_TRILIST;
2569 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2570 return V_008958_DI_PT_TRISTRIP;
2571 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2572 return V_008958_DI_PT_TRIFAN;
2573 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2574 return V_008958_DI_PT_LINELIST_ADJ;
2575 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2576 return V_008958_DI_PT_LINESTRIP_ADJ;
2577 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2578 return V_008958_DI_PT_TRILIST_ADJ;
2579 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2580 return V_008958_DI_PT_TRISTRIP_ADJ;
2581 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2582 return V_008958_DI_PT_PATCH;
2583 default:
2584 assert(0);
2585 return 0;
2586 }
2587 }
2588
2589 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2590 {
2591 switch (op) {
2592 case VK_STENCIL_OP_KEEP:
2593 return V_02842C_STENCIL_KEEP;
2594 case VK_STENCIL_OP_ZERO:
2595 return V_02842C_STENCIL_ZERO;
2596 case VK_STENCIL_OP_REPLACE:
2597 return V_02842C_STENCIL_REPLACE_TEST;
2598 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2599 return V_02842C_STENCIL_ADD_CLAMP;
2600 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2601 return V_02842C_STENCIL_SUB_CLAMP;
2602 case VK_STENCIL_OP_INVERT:
2603 return V_02842C_STENCIL_INVERT;
2604 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2605 return V_02842C_STENCIL_ADD_WRAP;
2606 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2607 return V_02842C_STENCIL_SUB_WRAP;
2608 default:
2609 return 0;
2610 }
2611 }
2612
2613 /**
2614 * Helper used for debugging compiler issues by enabling/disabling LLVM for a
2615 * specific shader stage (developers only).
2616 */
2617 static inline bool
2618 radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage)
2619 {
2620 return device->physical_device->use_llvm;
2621 }
2622
2623 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2624 \
2625 static inline struct __radv_type * \
2626 __radv_type ## _from_handle(__VkType _handle) \
2627 { \
2628 return (struct __radv_type *) _handle; \
2629 } \
2630 \
2631 static inline __VkType \
2632 __radv_type ## _to_handle(struct __radv_type *_obj) \
2633 { \
2634 return (__VkType) _obj; \
2635 }
2636
2637 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2638 \
2639 static inline struct __radv_type * \
2640 __radv_type ## _from_handle(__VkType _handle) \
2641 { \
2642 return (struct __radv_type *)(uintptr_t) _handle; \
2643 } \
2644 \
2645 static inline __VkType \
2646 __radv_type ## _to_handle(struct __radv_type *_obj) \
2647 { \
2648 return (__VkType)(uintptr_t) _obj; \
2649 }
2650
2651 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2652 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2653
2654 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2655 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2656 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2657 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2658 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2659
2660 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2661 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2662 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2663 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2664 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2665 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2666 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2667 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2668 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2669 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2670 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2671 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2672 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2673 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2674 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2675 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2676 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2677 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2678 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2679 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2680 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2681 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2682
2683 #endif /* RADV_PRIVATE_H */