2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vulkan_android.h>
80 #include <vulkan/vk_icd.h>
81 #include <vulkan/vk_android_native_buffer.h>
83 #include "radv_entrypoints.h"
85 #include "wsi_common.h"
86 #include "wsi_common_display.h"
88 /* Helper to determine if we should compile
89 * any of the Android AHB support.
91 * To actually enable the ext we also need
92 * the necessary kernel support.
94 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
97 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
101 struct gfx10_format
{
102 unsigned img_format
:9;
104 /* Various formats are only supported with workarounds for vertex fetch,
105 * and some 32_32_32 formats are supported natively, but only for buffers
106 * (possibly with some image support, actually, but no filtering). */
110 #include "gfx10_format_table.h"
114 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
121 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
122 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
123 RADV_MEM_TYPE_GTT_CACHED
,
127 enum radv_secure_compile_type
{
128 RADV_SC_TYPE_INIT_SUCCESS
,
129 RADV_SC_TYPE_INIT_FAILURE
,
130 RADV_SC_TYPE_COMPILE_PIPELINE
,
131 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
132 RADV_SC_TYPE_READ_DISK_CACHE
,
133 RADV_SC_TYPE_WRITE_DISK_CACHE
,
134 RADV_SC_TYPE_DESTROY_DEVICE
,
138 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
140 static inline uint32_t
141 align_u32(uint32_t v
, uint32_t a
)
143 assert(a
!= 0 && a
== (a
& -a
));
144 return (v
+ a
- 1) & ~(a
- 1);
147 static inline uint32_t
148 align_u32_npot(uint32_t v
, uint32_t a
)
150 return (v
+ a
- 1) / a
* a
;
153 static inline uint64_t
154 align_u64(uint64_t v
, uint64_t a
)
156 assert(a
!= 0 && a
== (a
& -a
));
157 return (v
+ a
- 1) & ~(a
- 1);
160 static inline int32_t
161 align_i32(int32_t v
, int32_t a
)
163 assert(a
!= 0 && a
== (a
& -a
));
164 return (v
+ a
- 1) & ~(a
- 1);
167 /** Alignment must be a power of 2. */
169 radv_is_aligned(uintmax_t n
, uintmax_t a
)
171 assert(a
== (a
& -a
));
172 return (n
& (a
- 1)) == 0;
175 static inline uint32_t
176 round_up_u32(uint32_t v
, uint32_t a
)
178 return (v
+ a
- 1) / a
;
181 static inline uint64_t
182 round_up_u64(uint64_t v
, uint64_t a
)
184 return (v
+ a
- 1) / a
;
187 static inline uint32_t
188 radv_minify(uint32_t n
, uint32_t levels
)
190 if (unlikely(n
== 0))
193 return MAX2(n
>> levels
, 1);
196 radv_clamp_f(float f
, float min
, float max
)
209 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
211 if (*inout_mask
& clear_mask
) {
212 *inout_mask
&= ~clear_mask
;
219 #define for_each_bit(b, dword) \
220 for (uint32_t __dword = (dword); \
221 (b) = __builtin_ffs(__dword) - 1, __dword; \
222 __dword &= ~(1 << (b)))
224 #define typed_memcpy(dest, src, count) ({ \
225 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
226 memcpy((dest), (src), (count) * sizeof(*(src))); \
229 /* Whenever we generate an error, pass it through this function. Useful for
230 * debugging, where we can break on it. Only call at error site, not when
231 * propagating errors. Might be useful to plug in a stack trace here.
234 struct radv_image_view
;
235 struct radv_instance
;
237 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
239 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
240 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
242 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
243 radv_printflike(3, 4);
244 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
245 void radv_loge_v(const char *format
, va_list va
);
246 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
247 void radv_logi_v(const char *format
, va_list va
);
250 * Print a FINISHME message, including its source location.
252 #define radv_finishme(format, ...) \
254 static bool reported = false; \
256 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 /* A non-fatal assert. Useful for debugging. */
263 #define radv_assert(x) ({ \
264 if (unlikely(!(x))) \
265 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
268 #define radv_assert(x)
271 #define stub_return(v) \
273 radv_finishme("stub %s", __func__); \
279 radv_finishme("stub %s", __func__); \
283 void *radv_lookup_entrypoint_unchecked(const char *name
);
284 void *radv_lookup_entrypoint_checked(const char *name
,
285 uint32_t core_version
,
286 const struct radv_instance_extension_table
*instance
,
287 const struct radv_device_extension_table
*device
);
288 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
289 uint32_t core_version
,
290 const struct radv_instance_extension_table
*instance
);
292 struct radv_physical_device
{
293 VK_LOADER_DATA _loader_data
;
295 struct radv_instance
* instance
;
297 struct radeon_winsys
*ws
;
298 struct radeon_info rad_info
;
299 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
300 uint8_t driver_uuid
[VK_UUID_SIZE
];
301 uint8_t device_uuid
[VK_UUID_SIZE
];
302 uint8_t cache_uuid
[VK_UUID_SIZE
];
306 struct wsi_device wsi_device
;
308 bool out_of_order_rast_allowed
;
310 /* Whether DCC should be enabled for MSAA textures. */
311 bool dcc_msaa_allowed
;
313 /* Whether to enable the AMD_shader_ballot extension */
314 bool use_shader_ballot
;
316 /* Whether to enable NGG. */
319 /* Whether to enable NGG streamout. */
320 bool use_ngg_streamout
;
322 /* Number of threads per wave. */
323 uint8_t ps_wave_size
;
324 uint8_t cs_wave_size
;
325 uint8_t ge_wave_size
;
327 /* Whether to use the experimental compiler backend */
330 /* This is the drivers on-disk cache used as a fallback as opposed to
331 * the pipeline cache defined by apps.
333 struct disk_cache
* disk_cache
;
335 VkPhysicalDeviceMemoryProperties memory_properties
;
336 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
338 drmPciBusInfo bus_info
;
340 struct radv_device_extension_table supported_extensions
;
343 struct radv_instance
{
344 VK_LOADER_DATA _loader_data
;
346 VkAllocationCallbacks alloc
;
349 int physicalDeviceCount
;
350 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
353 uint32_t engineVersion
;
355 uint64_t debug_flags
;
356 uint64_t perftest_flags
;
357 uint8_t num_sc_threads
;
359 struct vk_debug_report_instance debug_report_callbacks
;
361 struct radv_instance_extension_table enabled_extensions
;
363 struct driOptionCache dri_options
;
364 struct driOptionCache available_dri_options
;
367 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
368 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
370 bool radv_instance_extension_supported(const char *name
);
371 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
372 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
377 struct radv_pipeline_cache
{
378 struct radv_device
* device
;
379 pthread_mutex_t mutex
;
383 uint32_t kernel_count
;
384 struct cache_entry
** hash_table
;
387 VkAllocationCallbacks alloc
;
390 struct radv_pipeline_key
{
391 uint32_t instance_rate_inputs
;
392 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
393 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
394 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
395 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
396 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
397 uint64_t vertex_alpha_adjust
;
398 uint32_t vertex_post_shuffle
;
399 unsigned tess_input_vertices
;
403 uint8_t log2_ps_iter_samples
;
405 uint32_t has_multiview_view_index
: 1;
406 uint32_t optimisations_disabled
: 1;
410 struct radv_shader_binary
;
411 struct radv_shader_variant
;
414 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
415 struct radv_device
*device
);
417 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
419 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
420 const void *data
, size_t size
);
423 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
424 struct radv_pipeline_cache
*cache
,
425 const unsigned char *sha1
,
426 struct radv_shader_variant
**variants
,
427 bool *found_in_application_cache
);
430 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
431 struct radv_pipeline_cache
*cache
,
432 const unsigned char *sha1
,
433 struct radv_shader_variant
**variants
,
434 struct radv_shader_binary
*const *binaries
);
436 enum radv_blit_ds_layout
{
437 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
438 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
439 RADV_BLIT_DS_LAYOUT_COUNT
,
442 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
444 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
447 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
449 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
452 enum radv_meta_dst_layout
{
453 RADV_META_DST_LAYOUT_GENERAL
,
454 RADV_META_DST_LAYOUT_OPTIMAL
,
455 RADV_META_DST_LAYOUT_COUNT
,
458 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
460 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
463 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
465 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
468 struct radv_meta_state
{
469 VkAllocationCallbacks alloc
;
471 struct radv_pipeline_cache cache
;
474 * For on-demand pipeline creation, makes sure that
475 * only one thread tries to build a pipeline at the same time.
480 * Use array element `i` for images with `2^i` samples.
483 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
484 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
486 VkRenderPass depthstencil_rp
;
487 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
488 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
489 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
491 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
492 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
493 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
494 } clear
[MAX_SAMPLES_LOG2
];
496 VkPipelineLayout clear_color_p_layout
;
497 VkPipelineLayout clear_depth_p_layout
;
498 VkPipelineLayout clear_depth_unrestricted_p_layout
;
500 /* Optimized compute fast HTILE clear for stencil or depth only. */
501 VkPipeline clear_htile_mask_pipeline
;
502 VkPipelineLayout clear_htile_mask_p_layout
;
503 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
506 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
508 /** Pipeline that blits from a 1D image. */
509 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
511 /** Pipeline that blits from a 2D image. */
512 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
514 /** Pipeline that blits from a 3D image. */
515 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
517 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
518 VkPipeline depth_only_1d_pipeline
;
519 VkPipeline depth_only_2d_pipeline
;
520 VkPipeline depth_only_3d_pipeline
;
522 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
523 VkPipeline stencil_only_1d_pipeline
;
524 VkPipeline stencil_only_2d_pipeline
;
525 VkPipeline stencil_only_3d_pipeline
;
526 VkPipelineLayout pipeline_layout
;
527 VkDescriptorSetLayout ds_layout
;
531 VkPipelineLayout p_layouts
[5];
532 VkDescriptorSetLayout ds_layouts
[5];
533 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
535 VkPipeline depth_only_pipeline
[5];
537 VkPipeline stencil_only_pipeline
[5];
538 } blit2d
[MAX_SAMPLES_LOG2
];
540 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
541 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
542 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
545 VkPipelineLayout img_p_layout
;
546 VkDescriptorSetLayout img_ds_layout
;
548 VkPipeline pipeline_3d
;
551 VkPipelineLayout img_p_layout
;
552 VkDescriptorSetLayout img_ds_layout
;
554 VkPipeline pipeline_3d
;
557 VkPipelineLayout img_p_layout
;
558 VkDescriptorSetLayout img_ds_layout
;
562 VkPipelineLayout img_p_layout
;
563 VkDescriptorSetLayout img_ds_layout
;
565 VkPipeline pipeline_3d
;
568 VkPipelineLayout img_p_layout
;
569 VkDescriptorSetLayout img_ds_layout
;
573 VkPipelineLayout img_p_layout
;
574 VkDescriptorSetLayout img_ds_layout
;
576 VkPipeline pipeline_3d
;
579 VkPipelineLayout img_p_layout
;
580 VkDescriptorSetLayout img_ds_layout
;
585 VkPipelineLayout p_layout
;
586 VkPipeline pipeline
[NUM_META_FS_KEYS
];
587 VkRenderPass pass
[NUM_META_FS_KEYS
];
591 VkDescriptorSetLayout ds_layout
;
592 VkPipelineLayout p_layout
;
595 VkPipeline i_pipeline
;
596 VkPipeline srgb_pipeline
;
597 } rc
[MAX_SAMPLES_LOG2
];
599 VkPipeline depth_zero_pipeline
;
601 VkPipeline average_pipeline
;
602 VkPipeline max_pipeline
;
603 VkPipeline min_pipeline
;
604 } depth
[MAX_SAMPLES_LOG2
];
606 VkPipeline stencil_zero_pipeline
;
608 VkPipeline max_pipeline
;
609 VkPipeline min_pipeline
;
610 } stencil
[MAX_SAMPLES_LOG2
];
614 VkDescriptorSetLayout ds_layout
;
615 VkPipelineLayout p_layout
;
618 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
619 VkPipeline pipeline
[NUM_META_FS_KEYS
];
620 } rc
[MAX_SAMPLES_LOG2
];
622 VkRenderPass depth_render_pass
;
623 VkPipeline depth_zero_pipeline
;
625 VkPipeline average_pipeline
;
626 VkPipeline max_pipeline
;
627 VkPipeline min_pipeline
;
628 } depth
[MAX_SAMPLES_LOG2
];
630 VkRenderPass stencil_render_pass
;
631 VkPipeline stencil_zero_pipeline
;
633 VkPipeline max_pipeline
;
634 VkPipeline min_pipeline
;
635 } stencil
[MAX_SAMPLES_LOG2
];
639 VkPipelineLayout p_layout
;
640 VkPipeline decompress_pipeline
;
641 VkPipeline resummarize_pipeline
;
643 } depth_decomp
[MAX_SAMPLES_LOG2
];
646 VkPipelineLayout p_layout
;
647 VkPipeline cmask_eliminate_pipeline
;
648 VkPipeline fmask_decompress_pipeline
;
649 VkPipeline dcc_decompress_pipeline
;
652 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
653 VkPipelineLayout dcc_decompress_compute_p_layout
;
654 VkPipeline dcc_decompress_compute_pipeline
;
658 VkPipelineLayout fill_p_layout
;
659 VkPipelineLayout copy_p_layout
;
660 VkDescriptorSetLayout fill_ds_layout
;
661 VkDescriptorSetLayout copy_ds_layout
;
662 VkPipeline fill_pipeline
;
663 VkPipeline copy_pipeline
;
667 VkDescriptorSetLayout ds_layout
;
668 VkPipelineLayout p_layout
;
669 VkPipeline occlusion_query_pipeline
;
670 VkPipeline pipeline_statistics_query_pipeline
;
671 VkPipeline tfb_query_pipeline
;
672 VkPipeline timestamp_query_pipeline
;
676 VkDescriptorSetLayout ds_layout
;
677 VkPipelineLayout p_layout
;
678 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
683 #define RADV_QUEUE_GENERAL 0
684 #define RADV_QUEUE_COMPUTE 1
685 #define RADV_QUEUE_TRANSFER 2
687 #define RADV_MAX_QUEUE_FAMILIES 3
689 enum ring_type
radv_queue_family_to_ring(int f
);
692 VK_LOADER_DATA _loader_data
;
693 struct radv_device
* device
;
694 struct radeon_winsys_ctx
*hw_ctx
;
695 enum radeon_ctx_priority priority
;
696 uint32_t queue_family_index
;
698 VkDeviceQueueCreateFlags flags
;
700 uint32_t scratch_size
;
701 uint32_t compute_scratch_size
;
702 uint32_t esgs_ring_size
;
703 uint32_t gsvs_ring_size
;
706 bool has_sample_positions
;
708 struct radeon_winsys_bo
*scratch_bo
;
709 struct radeon_winsys_bo
*descriptor_bo
;
710 struct radeon_winsys_bo
*compute_scratch_bo
;
711 struct radeon_winsys_bo
*esgs_ring_bo
;
712 struct radeon_winsys_bo
*gsvs_ring_bo
;
713 struct radeon_winsys_bo
*tess_rings_bo
;
714 struct radeon_winsys_bo
*gds_bo
;
715 struct radeon_winsys_bo
*gds_oa_bo
;
716 struct radeon_cmdbuf
*initial_preamble_cs
;
717 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
718 struct radeon_cmdbuf
*continue_preamble_cs
;
721 struct radv_bo_list
{
722 struct radv_winsys_bo_list list
;
724 pthread_mutex_t mutex
;
727 struct radv_secure_compile_process
{
728 /* Secure process file descriptors */
730 int fd_secure_output
;
732 /* Secure compile process id */
735 /* Is the secure compile process currently in use by a thread */
739 struct radv_secure_compile_state
{
740 struct radv_secure_compile_process
*secure_compile_processes
;
741 uint32_t secure_compile_thread_counter
;
742 mtx_t secure_compile_mutex
;
746 VK_LOADER_DATA _loader_data
;
748 VkAllocationCallbacks alloc
;
750 struct radv_instance
* instance
;
751 struct radeon_winsys
*ws
;
753 struct radv_meta_state meta_state
;
755 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
756 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
757 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
759 bool always_use_syncobj
;
762 uint32_t tess_offchip_block_dw_size
;
763 uint32_t scratch_waves
;
764 uint32_t dispatch_initiator
;
766 uint32_t gs_table_depth
;
768 /* MSAA sample locations.
769 * The first index is the sample index.
770 * The second index is the coordinate: X, Y. */
771 float sample_locations_1x
[1][2];
772 float sample_locations_2x
[2][2];
773 float sample_locations_4x
[4][2];
774 float sample_locations_8x
[8][2];
777 uint32_t gfx_init_size_dw
;
778 struct radeon_winsys_bo
*gfx_init
;
780 struct radeon_winsys_bo
*trace_bo
;
781 uint32_t *trace_id_ptr
;
783 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
784 bool keep_shader_info
;
786 struct radv_physical_device
*physical_device
;
788 /* Backup in-memory cache to be used if the app doesn't provide one */
789 struct radv_pipeline_cache
* mem_cache
;
792 * use different counters so MSAA MRTs get consecutive surface indices,
793 * even if MASK is allocated in between.
795 uint32_t image_mrt_offset_counter
;
796 uint32_t fmask_mrt_offset_counter
;
797 struct list_head shader_slabs
;
798 mtx_t shader_slab_mutex
;
800 /* For detecting VM faults reported by dmesg. */
801 uint64_t dmesg_timestamp
;
803 struct radv_device_extension_table enabled_extensions
;
805 /* Whether the app has enabled the robustBufferAccess feature. */
806 bool robust_buffer_access
;
808 /* Whether the driver uses a global BO list. */
809 bool use_global_bo_list
;
811 struct radv_bo_list bo_list
;
813 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
816 struct radv_secure_compile_state
*sc_state
;
819 struct radv_device_memory
{
820 struct radeon_winsys_bo
*bo
;
821 /* for dedicated allocations */
822 struct radv_image
*image
;
823 struct radv_buffer
*buffer
;
825 VkDeviceSize map_size
;
829 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
830 struct AHardwareBuffer
* android_hardware_buffer
;
835 struct radv_descriptor_range
{
840 struct radv_descriptor_set
{
841 const struct radv_descriptor_set_layout
*layout
;
844 struct radeon_winsys_bo
*bo
;
846 uint32_t *mapped_ptr
;
847 struct radv_descriptor_range
*dynamic_descriptors
;
849 struct radeon_winsys_bo
*descriptors
[0];
852 struct radv_push_descriptor_set
854 struct radv_descriptor_set set
;
858 struct radv_descriptor_pool_entry
{
861 struct radv_descriptor_set
*set
;
864 struct radv_descriptor_pool
{
865 struct radeon_winsys_bo
*bo
;
867 uint64_t current_offset
;
870 uint8_t *host_memory_base
;
871 uint8_t *host_memory_ptr
;
872 uint8_t *host_memory_end
;
874 uint32_t entry_count
;
875 uint32_t max_entry_count
;
876 struct radv_descriptor_pool_entry entries
[0];
879 struct radv_descriptor_update_template_entry
{
880 VkDescriptorType descriptor_type
;
882 /* The number of descriptors to update */
883 uint32_t descriptor_count
;
885 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
888 /* In dwords. Not valid/used for dynamic descriptors */
891 uint32_t buffer_offset
;
893 /* Only valid for combined image samplers and samplers */
895 uint8_t sampler_offset
;
901 /* For push descriptors */
902 const uint32_t *immutable_samplers
;
905 struct radv_descriptor_update_template
{
906 uint32_t entry_count
;
907 VkPipelineBindPoint bind_point
;
908 struct radv_descriptor_update_template_entry entry
[0];
914 VkBufferUsageFlags usage
;
915 VkBufferCreateFlags flags
;
918 struct radeon_winsys_bo
* bo
;
924 enum radv_dynamic_state_bits
{
925 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
926 RADV_DYNAMIC_SCISSOR
= 1 << 1,
927 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
928 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
929 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
930 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
931 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
932 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
933 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
934 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
935 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
936 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
939 enum radv_cmd_dirty_bits
{
940 /* Keep the dynamic state dirty bits in sync with
941 * enum radv_dynamic_state_bits */
942 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
943 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
944 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
945 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
946 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
947 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
948 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
949 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
950 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
951 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
952 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
953 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
954 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
955 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
956 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
957 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
958 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
961 enum radv_cmd_flush_bits
{
962 /* Instruction cache. */
963 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
964 /* Scalar L1 cache. */
965 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
966 /* Vector L1 cache. */
967 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
968 /* L2 cache + L2 metadata cache writeback & invalidate.
969 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
970 RADV_CMD_FLAG_INV_L2
= 1 << 3,
971 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
972 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
973 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
974 RADV_CMD_FLAG_WB_L2
= 1 << 4,
975 /* Framebuffer caches */
976 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
977 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
978 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
979 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
980 /* Engine synchronization. */
981 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
982 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
983 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
984 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
985 /* Pipeline query controls. */
986 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
987 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
988 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
990 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
991 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
992 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
993 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
996 struct radv_vertex_binding
{
997 struct radv_buffer
* buffer
;
1001 struct radv_streamout_binding
{
1002 struct radv_buffer
*buffer
;
1003 VkDeviceSize offset
;
1007 struct radv_streamout_state
{
1008 /* Mask of bound streamout buffers. */
1009 uint8_t enabled_mask
;
1011 /* External state that comes from the last vertex stage, it must be
1012 * set explicitely when binding a new graphics pipeline.
1014 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1015 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1017 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1018 uint32_t hw_enabled_mask
;
1020 /* State of VGT_STRMOUT_(CONFIG|EN) */
1021 bool streamout_enabled
;
1024 struct radv_viewport_state
{
1026 VkViewport viewports
[MAX_VIEWPORTS
];
1029 struct radv_scissor_state
{
1031 VkRect2D scissors
[MAX_SCISSORS
];
1034 struct radv_discard_rectangle_state
{
1036 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1039 struct radv_sample_locations_state
{
1040 VkSampleCountFlagBits per_pixel
;
1041 VkExtent2D grid_size
;
1043 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1046 struct radv_dynamic_state
{
1048 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1049 * Defines the set of saved dynamic state.
1053 struct radv_viewport_state viewport
;
1055 struct radv_scissor_state scissor
;
1065 float blend_constants
[4];
1075 } stencil_compare_mask
;
1080 } stencil_write_mask
;
1085 } stencil_reference
;
1087 struct radv_discard_rectangle_state discard_rectangle
;
1089 struct radv_sample_locations_state sample_location
;
1092 extern const struct radv_dynamic_state default_dynamic_state
;
1095 radv_get_debug_option_name(int id
);
1098 radv_get_perftest_option_name(int id
);
1100 struct radv_color_buffer_info
{
1101 uint64_t cb_color_base
;
1102 uint64_t cb_color_cmask
;
1103 uint64_t cb_color_fmask
;
1104 uint64_t cb_dcc_base
;
1105 uint32_t cb_color_slice
;
1106 uint32_t cb_color_view
;
1107 uint32_t cb_color_info
;
1108 uint32_t cb_color_attrib
;
1109 uint32_t cb_color_attrib2
; /* GFX9 and later */
1110 uint32_t cb_color_attrib3
; /* GFX10 and later */
1111 uint32_t cb_dcc_control
;
1112 uint32_t cb_color_cmask_slice
;
1113 uint32_t cb_color_fmask_slice
;
1115 uint32_t cb_color_pitch
; // GFX6-GFX8
1116 uint32_t cb_mrt_epitch
; // GFX9+
1120 struct radv_ds_buffer_info
{
1121 uint64_t db_z_read_base
;
1122 uint64_t db_stencil_read_base
;
1123 uint64_t db_z_write_base
;
1124 uint64_t db_stencil_write_base
;
1125 uint64_t db_htile_data_base
;
1126 uint32_t db_depth_info
;
1128 uint32_t db_stencil_info
;
1129 uint32_t db_depth_view
;
1130 uint32_t db_depth_size
;
1131 uint32_t db_depth_slice
;
1132 uint32_t db_htile_surface
;
1133 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1134 uint32_t db_z_info2
; /* GFX9 only */
1135 uint32_t db_stencil_info2
; /* GFX9 only */
1140 radv_initialise_color_surface(struct radv_device
*device
,
1141 struct radv_color_buffer_info
*cb
,
1142 struct radv_image_view
*iview
);
1144 radv_initialise_ds_surface(struct radv_device
*device
,
1145 struct radv_ds_buffer_info
*ds
,
1146 struct radv_image_view
*iview
);
1149 * Attachment state when recording a renderpass instance.
1151 * The clear value is valid only if there exists a pending clear.
1153 struct radv_attachment_state
{
1154 VkImageAspectFlags pending_clear_aspects
;
1155 uint32_t cleared_views
;
1156 VkClearValue clear_value
;
1157 VkImageLayout current_layout
;
1158 bool current_in_render_loop
;
1159 struct radv_sample_locations_state sample_location
;
1162 struct radv_color_buffer_info cb
;
1163 struct radv_ds_buffer_info ds
;
1165 struct radv_image_view
*iview
;
1168 struct radv_descriptor_state
{
1169 struct radv_descriptor_set
*sets
[MAX_SETS
];
1172 struct radv_push_descriptor_set push_set
;
1174 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1177 struct radv_subpass_sample_locs_state
{
1178 uint32_t subpass_idx
;
1179 struct radv_sample_locations_state sample_location
;
1182 struct radv_cmd_state
{
1183 /* Vertex descriptors */
1190 uint32_t prefetch_L2_mask
;
1192 struct radv_pipeline
* pipeline
;
1193 struct radv_pipeline
* emitted_pipeline
;
1194 struct radv_pipeline
* compute_pipeline
;
1195 struct radv_pipeline
* emitted_compute_pipeline
;
1196 struct radv_framebuffer
* framebuffer
;
1197 struct radv_render_pass
* pass
;
1198 const struct radv_subpass
* subpass
;
1199 struct radv_dynamic_state dynamic
;
1200 struct radv_attachment_state
* attachments
;
1201 struct radv_streamout_state streamout
;
1202 VkRect2D render_area
;
1204 uint32_t num_subpass_sample_locs
;
1205 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1208 struct radv_buffer
*index_buffer
;
1209 uint64_t index_offset
;
1210 uint32_t index_type
;
1211 uint32_t max_index_count
;
1213 int32_t last_index_type
;
1215 int32_t last_primitive_reset_en
;
1216 uint32_t last_primitive_reset_index
;
1217 enum radv_cmd_flush_bits flush_bits
;
1218 unsigned active_occlusion_queries
;
1219 bool perfect_occlusion_queries_enabled
;
1220 unsigned active_pipeline_queries
;
1223 uint32_t last_ia_multi_vgt_param
;
1225 uint32_t last_num_instances
;
1226 uint32_t last_first_instance
;
1227 uint32_t last_vertex_offset
;
1229 /* Whether CP DMA is busy/idle. */
1232 /* Conditional rendering info. */
1233 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1234 uint64_t predication_va
;
1236 bool context_roll_without_scissor_emitted
;
1239 struct radv_cmd_pool
{
1240 VkAllocationCallbacks alloc
;
1241 struct list_head cmd_buffers
;
1242 struct list_head free_cmd_buffers
;
1243 uint32_t queue_family_index
;
1246 struct radv_cmd_buffer_upload
{
1250 struct radeon_winsys_bo
*upload_bo
;
1251 struct list_head list
;
1254 enum radv_cmd_buffer_status
{
1255 RADV_CMD_BUFFER_STATUS_INVALID
,
1256 RADV_CMD_BUFFER_STATUS_INITIAL
,
1257 RADV_CMD_BUFFER_STATUS_RECORDING
,
1258 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1259 RADV_CMD_BUFFER_STATUS_PENDING
,
1262 struct radv_cmd_buffer
{
1263 VK_LOADER_DATA _loader_data
;
1265 struct radv_device
* device
;
1267 struct radv_cmd_pool
* pool
;
1268 struct list_head pool_link
;
1270 VkCommandBufferUsageFlags usage_flags
;
1271 VkCommandBufferLevel level
;
1272 enum radv_cmd_buffer_status status
;
1273 struct radeon_cmdbuf
*cs
;
1274 struct radv_cmd_state state
;
1275 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1276 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1277 uint32_t queue_family_index
;
1279 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1280 VkShaderStageFlags push_constant_stages
;
1281 struct radv_descriptor_set meta_push_descriptors
;
1283 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1285 struct radv_cmd_buffer_upload upload
;
1287 uint32_t scratch_size_needed
;
1288 uint32_t compute_scratch_size_needed
;
1289 uint32_t esgs_ring_size_needed
;
1290 uint32_t gsvs_ring_size_needed
;
1291 bool tess_rings_needed
;
1292 bool gds_needed
; /* for GFX10 streamout */
1293 bool sample_positions_needed
;
1295 VkResult record_result
;
1297 uint64_t gfx9_fence_va
;
1298 uint32_t gfx9_fence_idx
;
1299 uint64_t gfx9_eop_bug_va
;
1302 * Whether a query pool has been resetted and we have to flush caches.
1304 bool pending_reset_query
;
1307 * Bitmask of pending active query flushes.
1309 enum radv_cmd_flush_bits active_query_flush_bits
;
1313 struct radv_image_view
;
1315 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1317 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1318 struct radeon_cmdbuf
*cs
);
1319 void si_emit_compute(struct radv_physical_device
*physical_device
,
1320 struct radeon_cmdbuf
*cs
);
1322 void cik_create_gfx_config(struct radv_device
*device
);
1324 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1325 int count
, const VkViewport
*viewports
);
1326 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1327 int count
, const VkRect2D
*scissors
,
1328 const VkViewport
*viewports
, bool can_use_guardband
);
1329 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1330 bool instanced_draw
, bool indirect_draw
,
1331 bool count_from_stream_output
,
1332 uint32_t draw_vertex_count
);
1333 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1334 enum chip_class chip_class
,
1336 unsigned event
, unsigned event_flags
,
1337 unsigned dst_sel
, unsigned data_sel
,
1340 uint64_t gfx9_eop_bug_va
);
1342 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1343 uint32_t ref
, uint32_t mask
);
1344 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1345 enum chip_class chip_class
,
1346 uint32_t *fence_ptr
, uint64_t va
,
1348 enum radv_cmd_flush_bits flush_bits
,
1349 uint64_t gfx9_eop_bug_va
);
1350 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1351 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1352 bool inverted
, uint64_t va
);
1353 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1354 uint64_t src_va
, uint64_t dest_va
,
1356 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1358 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1359 uint64_t size
, unsigned value
);
1360 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1362 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1364 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1367 unsigned *out_offset
,
1370 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1371 const struct radv_subpass
*subpass
);
1373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1374 unsigned size
, unsigned alignmnet
,
1375 const void *data
, unsigned *out_offset
);
1377 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1378 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1379 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1380 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1381 VkImageAspectFlags aspects
,
1382 VkResolveModeFlagBitsKHR resolve_mode
);
1383 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1384 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1385 VkImageAspectFlags aspects
,
1386 VkResolveModeFlagBitsKHR resolve_mode
);
1387 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1388 unsigned radv_get_default_max_sample_dist(int log_samples
);
1389 void radv_device_init_msaa(struct radv_device
*device
);
1391 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1392 const struct radv_image_view
*iview
,
1393 VkClearDepthStencilValue ds_clear_value
,
1394 VkImageAspectFlags aspects
);
1396 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1397 const struct radv_image_view
*iview
,
1399 uint32_t color_values
[2]);
1401 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1402 struct radv_image
*image
,
1403 const VkImageSubresourceRange
*range
, bool value
);
1405 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1406 struct radv_image
*image
,
1407 const VkImageSubresourceRange
*range
, bool value
);
1409 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1410 struct radeon_winsys_bo
*bo
,
1411 uint64_t offset
, uint64_t size
, uint32_t value
);
1412 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1413 bool radv_get_memory_fd(struct radv_device
*device
,
1414 struct radv_device_memory
*memory
,
1418 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1419 unsigned sh_offset
, unsigned pointer_count
,
1420 bool use_32bit_pointers
)
1422 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1423 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1427 radv_emit_shader_pointer_body(struct radv_device
*device
,
1428 struct radeon_cmdbuf
*cs
,
1429 uint64_t va
, bool use_32bit_pointers
)
1431 radeon_emit(cs
, va
);
1433 if (use_32bit_pointers
) {
1435 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1437 radeon_emit(cs
, va
>> 32);
1442 radv_emit_shader_pointer(struct radv_device
*device
,
1443 struct radeon_cmdbuf
*cs
,
1444 uint32_t sh_offset
, uint64_t va
, bool global
)
1446 bool use_32bit_pointers
= !global
;
1448 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1449 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1452 static inline struct radv_descriptor_state
*
1453 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1454 VkPipelineBindPoint bind_point
)
1456 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1457 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1458 return &cmd_buffer
->descriptors
[bind_point
];
1462 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1464 * Limitations: Can't call normal dispatch functions without binding or rebinding
1465 * the compute pipeline.
1467 void radv_unaligned_dispatch(
1468 struct radv_cmd_buffer
*cmd_buffer
,
1474 struct radeon_winsys_bo
*bo
;
1478 struct radv_shader_module
;
1480 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1481 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1482 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1483 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1484 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1485 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1486 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1487 #define RADV_HASH_SHADER_ACO (1 << 7)
1490 radv_hash_shaders(unsigned char *hash
,
1491 const VkPipelineShaderStageCreateInfo
**stages
,
1492 const struct radv_pipeline_layout
*layout
,
1493 const struct radv_pipeline_key
*key
,
1496 static inline gl_shader_stage
1497 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1499 assert(__builtin_popcount(vk_stage
) == 1);
1500 return ffs(vk_stage
) - 1;
1503 static inline VkShaderStageFlagBits
1504 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1506 return (1 << mesa_stage
);
1509 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1511 #define radv_foreach_stage(stage, stage_bits) \
1512 for (gl_shader_stage stage, \
1513 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1514 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1515 __tmp &= ~(1 << (stage)))
1517 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1518 unsigned radv_format_meta_fs_key(VkFormat format
);
1520 struct radv_multisample_state
{
1522 uint32_t pa_sc_line_cntl
;
1523 uint32_t pa_sc_mode_cntl_0
;
1524 uint32_t pa_sc_mode_cntl_1
;
1525 uint32_t pa_sc_aa_config
;
1526 uint32_t pa_sc_aa_mask
[2];
1527 unsigned num_samples
;
1530 struct radv_prim_vertex_count
{
1535 struct radv_vertex_elements_info
{
1536 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1539 struct radv_ia_multi_vgt_param_helpers
{
1541 bool partial_es_wave
;
1542 uint8_t primgroup_size
;
1543 bool wd_switch_on_eop
;
1544 bool ia_switch_on_eoi
;
1545 bool partial_vs_wave
;
1548 struct radv_binning_state
{
1549 uint32_t pa_sc_binner_cntl_0
;
1550 uint32_t db_dfsm_control
;
1553 #define SI_GS_PER_ES 128
1555 struct radv_pipeline
{
1556 struct radv_device
* device
;
1557 struct radv_dynamic_state dynamic_state
;
1559 struct radv_pipeline_layout
* layout
;
1561 bool need_indirect_descriptor_sets
;
1562 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1563 struct radv_shader_variant
*gs_copy_shader
;
1564 VkShaderStageFlags active_stages
;
1566 struct radeon_cmdbuf cs
;
1567 uint32_t ctx_cs_hash
;
1568 struct radeon_cmdbuf ctx_cs
;
1570 struct radv_vertex_elements_info vertex_elements
;
1572 uint32_t binding_stride
[MAX_VBS
];
1573 uint8_t num_vertex_bindings
;
1575 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1578 struct radv_multisample_state ms
;
1579 struct radv_binning_state binning
;
1580 uint32_t spi_baryc_cntl
;
1581 bool prim_restart_enable
;
1582 unsigned esgs_ring_size
;
1583 unsigned gsvs_ring_size
;
1584 uint32_t vtx_base_sgpr
;
1585 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1586 uint8_t vtx_emit_num
;
1587 struct radv_prim_vertex_count prim_vertex_count
;
1588 bool can_use_guardband
;
1589 uint32_t needed_dynamic_state
;
1590 bool disable_out_of_order_rast_for_occlusion
;
1592 /* Used for rbplus */
1593 uint32_t col_format
;
1594 uint32_t cb_target_mask
;
1599 unsigned scratch_bytes_per_wave
;
1601 /* Not NULL if graphics pipeline uses streamout. */
1602 struct radv_shader_variant
*streamout_shader
;
1605 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1607 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1610 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1612 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1615 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1617 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1619 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1620 gl_shader_stage stage
,
1623 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1624 gl_shader_stage stage
);
1626 struct radv_graphics_pipeline_create_info
{
1628 bool db_depth_clear
;
1629 bool db_stencil_clear
;
1630 bool db_depth_disable_expclear
;
1631 bool db_stencil_disable_expclear
;
1632 bool db_flush_depth_inplace
;
1633 bool db_flush_stencil_inplace
;
1634 bool db_resummarize
;
1635 uint32_t custom_blend_mode
;
1639 radv_graphics_pipeline_create(VkDevice device
,
1640 VkPipelineCache cache
,
1641 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1642 const struct radv_graphics_pipeline_create_info
*extra
,
1643 const VkAllocationCallbacks
*alloc
,
1644 VkPipeline
*pPipeline
);
1646 struct vk_format_description
;
1647 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1648 int first_non_void
);
1649 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1650 int first_non_void
);
1651 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1652 uint32_t radv_translate_colorformat(VkFormat format
);
1653 uint32_t radv_translate_color_numformat(VkFormat format
,
1654 const struct vk_format_description
*desc
,
1655 int first_non_void
);
1656 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1657 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1658 uint32_t radv_translate_dbformat(VkFormat format
);
1659 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1660 const struct vk_format_description
*desc
,
1661 int first_non_void
);
1662 uint32_t radv_translate_tex_numformat(VkFormat format
,
1663 const struct vk_format_description
*desc
,
1664 int first_non_void
);
1665 bool radv_format_pack_clear_color(VkFormat format
,
1666 uint32_t clear_vals
[2],
1667 VkClearColorValue
*value
);
1668 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1669 bool radv_dcc_formats_compatible(VkFormat format1
,
1671 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1673 struct radv_image_plane
{
1675 struct radeon_surf surface
;
1681 /* The original VkFormat provided by the client. This may not match any
1682 * of the actual surface formats.
1685 VkImageAspectFlags aspects
;
1686 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1687 struct ac_surf_info info
;
1688 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1689 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1694 unsigned queue_family_mask
;
1698 /* Set when bound */
1699 struct radeon_winsys_bo
*bo
;
1700 VkDeviceSize offset
;
1701 uint64_t dcc_offset
;
1702 uint64_t htile_offset
;
1703 bool tc_compatible_htile
;
1704 bool tc_compatible_cmask
;
1706 uint64_t cmask_offset
;
1707 uint64_t fmask_offset
;
1708 uint64_t clear_value_offset
;
1709 uint64_t fce_pred_offset
;
1710 uint64_t dcc_pred_offset
;
1713 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1714 * stored at this offset is UINT_MAX, the driver will emit
1715 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1716 * SET_CONTEXT_REG packet.
1718 uint64_t tc_compat_zrange_offset
;
1720 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1721 VkDeviceMemory owned_memory
;
1723 unsigned plane_count
;
1724 struct radv_image_plane planes
[0];
1727 /* Whether the image has a htile that is known consistent with the contents of
1729 bool radv_layout_has_htile(const struct radv_image
*image
,
1730 VkImageLayout layout
,
1731 bool in_render_loop
,
1732 unsigned queue_mask
);
1734 /* Whether the image has a htile that is known consistent with the contents of
1735 * the image and is allowed to be in compressed form.
1737 * If this is false reads that don't use the htile should be able to return
1740 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1741 VkImageLayout layout
,
1742 bool in_render_loop
,
1743 unsigned queue_mask
);
1745 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1746 VkImageLayout layout
,
1747 bool in_render_loop
,
1748 unsigned queue_mask
);
1750 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1751 const struct radv_image
*image
,
1752 VkImageLayout layout
,
1753 bool in_render_loop
,
1754 unsigned queue_mask
);
1757 * Return whether the image has CMASK metadata for color surfaces.
1760 radv_image_has_cmask(const struct radv_image
*image
)
1762 return image
->cmask_offset
;
1766 * Return whether the image has FMASK metadata for color surfaces.
1769 radv_image_has_fmask(const struct radv_image
*image
)
1771 return image
->fmask_offset
;
1775 * Return whether the image has DCC metadata for color surfaces.
1778 radv_image_has_dcc(const struct radv_image
*image
)
1780 return image
->planes
[0].surface
.dcc_size
;
1784 * Return whether the image is TC-compatible CMASK.
1787 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1789 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1793 * Return whether DCC metadata is enabled for a level.
1796 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1798 return radv_image_has_dcc(image
) &&
1799 level
< image
->planes
[0].surface
.num_dcc_levels
;
1803 * Return whether the image has CB metadata.
1806 radv_image_has_CB_metadata(const struct radv_image
*image
)
1808 return radv_image_has_cmask(image
) ||
1809 radv_image_has_fmask(image
) ||
1810 radv_image_has_dcc(image
);
1814 * Return whether the image has HTILE metadata for depth surfaces.
1817 radv_image_has_htile(const struct radv_image
*image
)
1819 return image
->planes
[0].surface
.htile_size
;
1823 * Return whether HTILE metadata is enabled for a level.
1826 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1828 return radv_image_has_htile(image
) && level
== 0;
1832 * Return whether the image is TC-compatible HTILE.
1835 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1837 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1840 static inline uint64_t
1841 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1842 uint32_t base_level
)
1844 uint64_t va
= radv_buffer_get_va(image
->bo
);
1845 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1849 static inline uint64_t
1850 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1851 uint32_t base_level
)
1853 uint64_t va
= radv_buffer_get_va(image
->bo
);
1854 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1858 static inline uint64_t
1859 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1860 uint32_t base_level
)
1862 uint64_t va
= radv_buffer_get_va(image
->bo
);
1863 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1867 static inline uint64_t
1868 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1869 uint32_t base_level
)
1871 uint64_t va
= radv_buffer_get_va(image
->bo
);
1872 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1876 static inline uint64_t
1877 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1878 uint32_t base_level
)
1880 uint64_t va
= radv_buffer_get_va(image
->bo
);
1881 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1885 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1887 static inline uint32_t
1888 radv_get_layerCount(const struct radv_image
*image
,
1889 const VkImageSubresourceRange
*range
)
1891 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1892 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1895 static inline uint32_t
1896 radv_get_levelCount(const struct radv_image
*image
,
1897 const VkImageSubresourceRange
*range
)
1899 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1900 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1903 struct radeon_bo_metadata
;
1905 radv_init_metadata(struct radv_device
*device
,
1906 struct radv_image
*image
,
1907 struct radeon_bo_metadata
*metadata
);
1910 radv_image_override_offset_stride(struct radv_device
*device
,
1911 struct radv_image
*image
,
1912 uint64_t offset
, uint32_t stride
);
1914 union radv_descriptor
{
1916 uint32_t plane0_descriptor
[8];
1917 uint32_t fmask_descriptor
[8];
1920 uint32_t plane_descriptors
[3][8];
1924 struct radv_image_view
{
1925 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1926 struct radeon_winsys_bo
*bo
;
1928 VkImageViewType type
;
1929 VkImageAspectFlags aspect_mask
;
1932 bool multiple_planes
;
1933 uint32_t base_layer
;
1934 uint32_t layer_count
;
1936 uint32_t level_count
;
1937 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1939 union radv_descriptor descriptor
;
1941 /* Descriptor for use as a storage image as opposed to a sampled image.
1942 * This has a few differences for cube maps (e.g. type).
1944 union radv_descriptor storage_descriptor
;
1947 struct radv_image_create_info
{
1948 const VkImageCreateInfo
*vk_info
;
1950 bool no_metadata_planes
;
1951 const struct radeon_bo_metadata
*bo_metadata
;
1955 radv_image_create_layout(struct radv_device
*device
,
1956 struct radv_image_create_info create_info
,
1957 struct radv_image
*image
);
1959 VkResult
radv_image_create(VkDevice _device
,
1960 const struct radv_image_create_info
*info
,
1961 const VkAllocationCallbacks
* alloc
,
1964 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
1967 radv_image_from_gralloc(VkDevice device_h
,
1968 const VkImageCreateInfo
*base_info
,
1969 const VkNativeBufferANDROID
*gralloc_info
,
1970 const VkAllocationCallbacks
*alloc
,
1971 VkImage
*out_image_h
);
1973 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
1974 const VkImageUsageFlags vk_usage
);
1976 radv_import_ahb_memory(struct radv_device
*device
,
1977 struct radv_device_memory
*mem
,
1979 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
1981 radv_create_ahb_memory(struct radv_device
*device
,
1982 struct radv_device_memory
*mem
,
1984 const VkMemoryAllocateInfo
*pAllocateInfo
);
1987 radv_select_android_external_format(const void *next
, VkFormat default_format
);
1989 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
1991 struct radv_image_view_extra_create_info
{
1992 bool disable_compression
;
1995 void radv_image_view_init(struct radv_image_view
*view
,
1996 struct radv_device
*device
,
1997 const VkImageViewCreateInfo
*pCreateInfo
,
1998 const struct radv_image_view_extra_create_info
* extra_create_info
);
2000 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2002 struct radv_sampler_ycbcr_conversion
{
2004 VkSamplerYcbcrModelConversion ycbcr_model
;
2005 VkSamplerYcbcrRange ycbcr_range
;
2006 VkComponentMapping components
;
2007 VkChromaLocation chroma_offsets
[2];
2008 VkFilter chroma_filter
;
2011 struct radv_buffer_view
{
2012 struct radeon_winsys_bo
*bo
;
2014 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2017 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2018 struct radv_device
*device
,
2019 const VkBufferViewCreateInfo
* pCreateInfo
);
2021 static inline struct VkExtent3D
2022 radv_sanitize_image_extent(const VkImageType imageType
,
2023 const struct VkExtent3D imageExtent
)
2025 switch (imageType
) {
2026 case VK_IMAGE_TYPE_1D
:
2027 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2028 case VK_IMAGE_TYPE_2D
:
2029 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2030 case VK_IMAGE_TYPE_3D
:
2033 unreachable("invalid image type");
2037 static inline struct VkOffset3D
2038 radv_sanitize_image_offset(const VkImageType imageType
,
2039 const struct VkOffset3D imageOffset
)
2041 switch (imageType
) {
2042 case VK_IMAGE_TYPE_1D
:
2043 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2044 case VK_IMAGE_TYPE_2D
:
2045 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2046 case VK_IMAGE_TYPE_3D
:
2049 unreachable("invalid image type");
2054 radv_image_extent_compare(const struct radv_image
*image
,
2055 const VkExtent3D
*extent
)
2057 if (extent
->width
!= image
->info
.width
||
2058 extent
->height
!= image
->info
.height
||
2059 extent
->depth
!= image
->info
.depth
)
2064 struct radv_sampler
{
2066 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2069 struct radv_framebuffer
{
2074 uint32_t attachment_count
;
2075 struct radv_image_view
*attachments
[0];
2078 struct radv_subpass_barrier
{
2079 VkPipelineStageFlags src_stage_mask
;
2080 VkAccessFlags src_access_mask
;
2081 VkAccessFlags dst_access_mask
;
2084 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2085 const struct radv_subpass_barrier
*barrier
);
2087 struct radv_subpass_attachment
{
2088 uint32_t attachment
;
2089 VkImageLayout layout
;
2090 bool in_render_loop
;
2093 struct radv_subpass
{
2094 uint32_t attachment_count
;
2095 struct radv_subpass_attachment
* attachments
;
2097 uint32_t input_count
;
2098 uint32_t color_count
;
2099 struct radv_subpass_attachment
* input_attachments
;
2100 struct radv_subpass_attachment
* color_attachments
;
2101 struct radv_subpass_attachment
* resolve_attachments
;
2102 struct radv_subpass_attachment
* depth_stencil_attachment
;
2103 struct radv_subpass_attachment
* ds_resolve_attachment
;
2104 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2105 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2107 /** Subpass has at least one color resolve attachment */
2108 bool has_color_resolve
;
2110 /** Subpass has at least one color attachment */
2113 struct radv_subpass_barrier start_barrier
;
2116 VkSampleCountFlagBits max_sample_count
;
2120 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2122 struct radv_render_pass_attachment
{
2125 VkAttachmentLoadOp load_op
;
2126 VkAttachmentLoadOp stencil_load_op
;
2127 VkImageLayout initial_layout
;
2128 VkImageLayout final_layout
;
2130 /* The subpass id in which the attachment will be used first/last. */
2131 uint32_t first_subpass_idx
;
2132 uint32_t last_subpass_idx
;
2135 struct radv_render_pass
{
2136 uint32_t attachment_count
;
2137 uint32_t subpass_count
;
2138 struct radv_subpass_attachment
* subpass_attachments
;
2139 struct radv_render_pass_attachment
* attachments
;
2140 struct radv_subpass_barrier end_barrier
;
2141 struct radv_subpass subpasses
[0];
2144 VkResult
radv_device_init_meta(struct radv_device
*device
);
2145 void radv_device_finish_meta(struct radv_device
*device
);
2147 struct radv_query_pool
{
2148 struct radeon_winsys_bo
*bo
;
2150 uint32_t availability_offset
;
2154 uint32_t pipeline_stats_mask
;
2157 struct radv_semaphore
{
2158 /* use a winsys sem for non-exportable */
2159 struct radeon_winsys_sem
*sem
;
2161 uint32_t temp_syncobj
;
2164 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2165 VkPipelineBindPoint bind_point
,
2166 struct radv_descriptor_set
*set
,
2170 radv_update_descriptor_sets(struct radv_device
*device
,
2171 struct radv_cmd_buffer
*cmd_buffer
,
2172 VkDescriptorSet overrideSet
,
2173 uint32_t descriptorWriteCount
,
2174 const VkWriteDescriptorSet
*pDescriptorWrites
,
2175 uint32_t descriptorCopyCount
,
2176 const VkCopyDescriptorSet
*pDescriptorCopies
);
2179 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2180 struct radv_cmd_buffer
*cmd_buffer
,
2181 struct radv_descriptor_set
*set
,
2182 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2185 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2186 VkPipelineBindPoint pipelineBindPoint
,
2187 VkPipelineLayout _layout
,
2189 uint32_t descriptorWriteCount
,
2190 const VkWriteDescriptorSet
*pDescriptorWrites
);
2192 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2193 struct radv_image
*image
,
2194 const VkImageSubresourceRange
*range
, uint32_t value
);
2196 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2197 struct radv_image
*image
,
2198 const VkImageSubresourceRange
*range
);
2201 struct radeon_winsys_fence
*fence
;
2202 struct wsi_fence
*fence_wsi
;
2205 uint32_t temp_syncobj
;
2208 /* radv_nir_to_llvm.c */
2209 struct radv_shader_info
;
2210 struct radv_nir_compiler_options
;
2212 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2213 struct nir_shader
*geom_shader
,
2214 struct radv_shader_binary
**rbinary
,
2215 struct radv_shader_info
*info
,
2216 const struct radv_nir_compiler_options
*option
);
2218 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2219 struct radv_shader_binary
**rbinary
,
2220 struct radv_shader_info
*info
,
2221 struct nir_shader
*const *nir
,
2223 const struct radv_nir_compiler_options
*options
);
2225 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2226 gl_shader_stage stage
,
2227 const struct nir_shader
*nir
);
2229 /* radv_shader_info.h */
2230 struct radv_shader_info
;
2231 struct radv_shader_variant_key
;
2233 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2234 const struct radv_pipeline_layout
*layout
,
2235 const struct radv_shader_variant_key
*key
,
2236 struct radv_shader_info
*info
);
2238 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2240 struct radeon_winsys_sem
;
2242 uint64_t radv_get_current_time(void);
2244 static inline uint32_t
2245 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2248 case 0: /* GL_POINTS */
2250 case 1: /* GL_LINES */
2251 case 3: /* GL_LINE_STRIP */
2253 case 4: /* GL_TRIANGLES */
2254 case 5: /* GL_TRIANGLE_STRIP */
2256 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2258 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2260 case 7: /* GL_QUADS */
2261 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2268 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2270 static inline struct __radv_type * \
2271 __radv_type ## _from_handle(__VkType _handle) \
2273 return (struct __radv_type *) _handle; \
2276 static inline __VkType \
2277 __radv_type ## _to_handle(struct __radv_type *_obj) \
2279 return (__VkType) _obj; \
2282 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2284 static inline struct __radv_type * \
2285 __radv_type ## _from_handle(__VkType _handle) \
2287 return (struct __radv_type *)(uintptr_t) _handle; \
2290 static inline __VkType \
2291 __radv_type ## _to_handle(struct __radv_type *_obj) \
2293 return (__VkType)(uintptr_t) _obj; \
2296 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2297 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2299 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2300 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2301 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2302 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2303 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2305 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2306 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2307 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2308 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2309 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2310 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2311 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2312 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2313 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2314 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2315 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2316 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2317 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2318 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2319 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2320 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2321 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2322 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2323 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2324 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2325 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2326 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2328 #endif /* RADV_PRIVATE_H */