2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vulkan_android.h>
80 #include <vulkan/vk_icd.h>
81 #include <vulkan/vk_android_native_buffer.h>
83 #include "radv_entrypoints.h"
85 #include "wsi_common.h"
86 #include "wsi_common_display.h"
88 /* Helper to determine if we should compile
89 * any of the Android AHB support.
91 * To actually enable the ext we also need
92 * the necessary kernel support.
94 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
97 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
101 struct gfx10_format
{
102 unsigned img_format
:9;
104 /* Various formats are only supported with workarounds for vertex fetch,
105 * and some 32_32_32 formats are supported natively, but only for buffers
106 * (possibly with some image support, actually, but no filtering). */
110 #include "gfx10_format_table.h"
114 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
121 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
122 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
123 RADV_MEM_TYPE_GTT_CACHED
,
127 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129 static inline uint32_t
130 align_u32(uint32_t v
, uint32_t a
)
132 assert(a
!= 0 && a
== (a
& -a
));
133 return (v
+ a
- 1) & ~(a
- 1);
136 static inline uint32_t
137 align_u32_npot(uint32_t v
, uint32_t a
)
139 return (v
+ a
- 1) / a
* a
;
142 static inline uint64_t
143 align_u64(uint64_t v
, uint64_t a
)
145 assert(a
!= 0 && a
== (a
& -a
));
146 return (v
+ a
- 1) & ~(a
- 1);
149 static inline int32_t
150 align_i32(int32_t v
, int32_t a
)
152 assert(a
!= 0 && a
== (a
& -a
));
153 return (v
+ a
- 1) & ~(a
- 1);
156 /** Alignment must be a power of 2. */
158 radv_is_aligned(uintmax_t n
, uintmax_t a
)
160 assert(a
== (a
& -a
));
161 return (n
& (a
- 1)) == 0;
164 static inline uint32_t
165 round_up_u32(uint32_t v
, uint32_t a
)
167 return (v
+ a
- 1) / a
;
170 static inline uint64_t
171 round_up_u64(uint64_t v
, uint64_t a
)
173 return (v
+ a
- 1) / a
;
176 static inline uint32_t
177 radv_minify(uint32_t n
, uint32_t levels
)
179 if (unlikely(n
== 0))
182 return MAX2(n
>> levels
, 1);
185 radv_clamp_f(float f
, float min
, float max
)
198 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
200 if (*inout_mask
& clear_mask
) {
201 *inout_mask
&= ~clear_mask
;
208 #define for_each_bit(b, dword) \
209 for (uint32_t __dword = (dword); \
210 (b) = __builtin_ffs(__dword) - 1, __dword; \
211 __dword &= ~(1 << (b)))
213 #define typed_memcpy(dest, src, count) ({ \
214 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
215 memcpy((dest), (src), (count) * sizeof(*(src))); \
218 /* Whenever we generate an error, pass it through this function. Useful for
219 * debugging, where we can break on it. Only call at error site, not when
220 * propagating errors. Might be useful to plug in a stack trace here.
223 struct radv_image_view
;
224 struct radv_instance
;
226 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
228 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
229 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
231 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
232 radv_printflike(3, 4);
233 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
234 void radv_loge_v(const char *format
, va_list va
);
235 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
236 void radv_logi_v(const char *format
, va_list va
);
239 * Print a FINISHME message, including its source location.
241 #define radv_finishme(format, ...) \
243 static bool reported = false; \
245 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
250 /* A non-fatal assert. Useful for debugging. */
252 #define radv_assert(x) ({ \
253 if (unlikely(!(x))) \
254 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
257 #define radv_assert(x)
260 #define stub_return(v) \
262 radv_finishme("stub %s", __func__); \
268 radv_finishme("stub %s", __func__); \
272 void *radv_lookup_entrypoint_unchecked(const char *name
);
273 void *radv_lookup_entrypoint_checked(const char *name
,
274 uint32_t core_version
,
275 const struct radv_instance_extension_table
*instance
,
276 const struct radv_device_extension_table
*device
);
277 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
278 uint32_t core_version
,
279 const struct radv_instance_extension_table
*instance
);
281 struct radv_physical_device
{
282 VK_LOADER_DATA _loader_data
;
284 struct radv_instance
* instance
;
286 struct radeon_winsys
*ws
;
287 struct radeon_info rad_info
;
288 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
289 uint8_t driver_uuid
[VK_UUID_SIZE
];
290 uint8_t device_uuid
[VK_UUID_SIZE
];
291 uint8_t cache_uuid
[VK_UUID_SIZE
];
295 struct wsi_device wsi_device
;
297 bool out_of_order_rast_allowed
;
299 /* Whether DCC should be enabled for MSAA textures. */
300 bool dcc_msaa_allowed
;
302 /* Whether to enable the AMD_shader_ballot extension */
303 bool use_shader_ballot
;
305 /* Whether to enable NGG. */
308 /* Whether to enable NGG streamout. */
309 bool use_ngg_streamout
;
311 /* Number of threads per wave. */
312 uint8_t ps_wave_size
;
313 uint8_t cs_wave_size
;
314 uint8_t ge_wave_size
;
316 /* Whether to use the experimental compiler backend */
319 /* This is the drivers on-disk cache used as a fallback as opposed to
320 * the pipeline cache defined by apps.
322 struct disk_cache
* disk_cache
;
324 VkPhysicalDeviceMemoryProperties memory_properties
;
325 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
327 drmPciBusInfo bus_info
;
329 struct radv_device_extension_table supported_extensions
;
332 struct radv_instance
{
333 VK_LOADER_DATA _loader_data
;
335 VkAllocationCallbacks alloc
;
338 int physicalDeviceCount
;
339 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
342 uint32_t engineVersion
;
344 uint64_t debug_flags
;
345 uint64_t perftest_flags
;
347 struct vk_debug_report_instance debug_report_callbacks
;
349 struct radv_instance_extension_table enabled_extensions
;
351 struct driOptionCache dri_options
;
352 struct driOptionCache available_dri_options
;
355 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
356 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
358 bool radv_instance_extension_supported(const char *name
);
359 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
360 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
365 struct radv_pipeline_cache
{
366 struct radv_device
* device
;
367 pthread_mutex_t mutex
;
371 uint32_t kernel_count
;
372 struct cache_entry
** hash_table
;
375 VkAllocationCallbacks alloc
;
378 struct radv_pipeline_key
{
379 uint32_t instance_rate_inputs
;
380 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
381 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
382 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
383 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
384 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
385 uint64_t vertex_alpha_adjust
;
386 uint32_t vertex_post_shuffle
;
387 unsigned tess_input_vertices
;
391 uint8_t log2_ps_iter_samples
;
393 uint32_t has_multiview_view_index
: 1;
394 uint32_t optimisations_disabled
: 1;
398 struct radv_shader_binary
;
399 struct radv_shader_variant
;
402 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
403 struct radv_device
*device
);
405 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
407 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
408 const void *data
, size_t size
);
411 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
412 struct radv_pipeline_cache
*cache
,
413 const unsigned char *sha1
,
414 struct radv_shader_variant
**variants
,
415 bool *found_in_application_cache
);
418 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
419 struct radv_pipeline_cache
*cache
,
420 const unsigned char *sha1
,
421 struct radv_shader_variant
**variants
,
422 struct radv_shader_binary
*const *binaries
);
424 enum radv_blit_ds_layout
{
425 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
426 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
427 RADV_BLIT_DS_LAYOUT_COUNT
,
430 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
432 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
435 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
437 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
440 enum radv_meta_dst_layout
{
441 RADV_META_DST_LAYOUT_GENERAL
,
442 RADV_META_DST_LAYOUT_OPTIMAL
,
443 RADV_META_DST_LAYOUT_COUNT
,
446 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
448 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
451 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
453 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
456 struct radv_meta_state
{
457 VkAllocationCallbacks alloc
;
459 struct radv_pipeline_cache cache
;
462 * For on-demand pipeline creation, makes sure that
463 * only one thread tries to build a pipeline at the same time.
468 * Use array element `i` for images with `2^i` samples.
471 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
472 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
474 VkRenderPass depthstencil_rp
;
475 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
476 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
477 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
478 } clear
[MAX_SAMPLES_LOG2
];
480 VkPipelineLayout clear_color_p_layout
;
481 VkPipelineLayout clear_depth_p_layout
;
483 /* Optimized compute fast HTILE clear for stencil or depth only. */
484 VkPipeline clear_htile_mask_pipeline
;
485 VkPipelineLayout clear_htile_mask_p_layout
;
486 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
489 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
491 /** Pipeline that blits from a 1D image. */
492 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
494 /** Pipeline that blits from a 2D image. */
495 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
497 /** Pipeline that blits from a 3D image. */
498 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
500 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
501 VkPipeline depth_only_1d_pipeline
;
502 VkPipeline depth_only_2d_pipeline
;
503 VkPipeline depth_only_3d_pipeline
;
505 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
506 VkPipeline stencil_only_1d_pipeline
;
507 VkPipeline stencil_only_2d_pipeline
;
508 VkPipeline stencil_only_3d_pipeline
;
509 VkPipelineLayout pipeline_layout
;
510 VkDescriptorSetLayout ds_layout
;
514 VkPipelineLayout p_layouts
[5];
515 VkDescriptorSetLayout ds_layouts
[5];
516 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
518 VkPipeline depth_only_pipeline
[5];
520 VkPipeline stencil_only_pipeline
[5];
521 } blit2d
[MAX_SAMPLES_LOG2
];
523 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
524 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
525 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
528 VkPipelineLayout img_p_layout
;
529 VkDescriptorSetLayout img_ds_layout
;
531 VkPipeline pipeline_3d
;
534 VkPipelineLayout img_p_layout
;
535 VkDescriptorSetLayout img_ds_layout
;
537 VkPipeline pipeline_3d
;
540 VkPipelineLayout img_p_layout
;
541 VkDescriptorSetLayout img_ds_layout
;
545 VkPipelineLayout img_p_layout
;
546 VkDescriptorSetLayout img_ds_layout
;
548 VkPipeline pipeline_3d
;
551 VkPipelineLayout img_p_layout
;
552 VkDescriptorSetLayout img_ds_layout
;
556 VkPipelineLayout img_p_layout
;
557 VkDescriptorSetLayout img_ds_layout
;
559 VkPipeline pipeline_3d
;
562 VkPipelineLayout img_p_layout
;
563 VkDescriptorSetLayout img_ds_layout
;
568 VkPipelineLayout p_layout
;
569 VkPipeline pipeline
[NUM_META_FS_KEYS
];
570 VkRenderPass pass
[NUM_META_FS_KEYS
];
574 VkDescriptorSetLayout ds_layout
;
575 VkPipelineLayout p_layout
;
578 VkPipeline i_pipeline
;
579 VkPipeline srgb_pipeline
;
580 } rc
[MAX_SAMPLES_LOG2
];
582 VkPipeline depth_zero_pipeline
;
584 VkPipeline average_pipeline
;
585 VkPipeline max_pipeline
;
586 VkPipeline min_pipeline
;
587 } depth
[MAX_SAMPLES_LOG2
];
589 VkPipeline stencil_zero_pipeline
;
591 VkPipeline max_pipeline
;
592 VkPipeline min_pipeline
;
593 } stencil
[MAX_SAMPLES_LOG2
];
597 VkDescriptorSetLayout ds_layout
;
598 VkPipelineLayout p_layout
;
601 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
602 VkPipeline pipeline
[NUM_META_FS_KEYS
];
603 } rc
[MAX_SAMPLES_LOG2
];
605 VkRenderPass depth_render_pass
;
606 VkPipeline depth_zero_pipeline
;
608 VkPipeline average_pipeline
;
609 VkPipeline max_pipeline
;
610 VkPipeline min_pipeline
;
611 } depth
[MAX_SAMPLES_LOG2
];
613 VkRenderPass stencil_render_pass
;
614 VkPipeline stencil_zero_pipeline
;
616 VkPipeline max_pipeline
;
617 VkPipeline min_pipeline
;
618 } stencil
[MAX_SAMPLES_LOG2
];
622 VkPipelineLayout p_layout
;
623 VkPipeline decompress_pipeline
;
624 VkPipeline resummarize_pipeline
;
626 } depth_decomp
[MAX_SAMPLES_LOG2
];
629 VkPipelineLayout p_layout
;
630 VkPipeline cmask_eliminate_pipeline
;
631 VkPipeline fmask_decompress_pipeline
;
632 VkPipeline dcc_decompress_pipeline
;
635 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
636 VkPipelineLayout dcc_decompress_compute_p_layout
;
637 VkPipeline dcc_decompress_compute_pipeline
;
641 VkPipelineLayout fill_p_layout
;
642 VkPipelineLayout copy_p_layout
;
643 VkDescriptorSetLayout fill_ds_layout
;
644 VkDescriptorSetLayout copy_ds_layout
;
645 VkPipeline fill_pipeline
;
646 VkPipeline copy_pipeline
;
650 VkDescriptorSetLayout ds_layout
;
651 VkPipelineLayout p_layout
;
652 VkPipeline occlusion_query_pipeline
;
653 VkPipeline pipeline_statistics_query_pipeline
;
654 VkPipeline tfb_query_pipeline
;
655 VkPipeline timestamp_query_pipeline
;
659 VkDescriptorSetLayout ds_layout
;
660 VkPipelineLayout p_layout
;
661 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
666 #define RADV_QUEUE_GENERAL 0
667 #define RADV_QUEUE_COMPUTE 1
668 #define RADV_QUEUE_TRANSFER 2
670 #define RADV_MAX_QUEUE_FAMILIES 3
672 enum ring_type
radv_queue_family_to_ring(int f
);
675 VK_LOADER_DATA _loader_data
;
676 struct radv_device
* device
;
677 struct radeon_winsys_ctx
*hw_ctx
;
678 enum radeon_ctx_priority priority
;
679 uint32_t queue_family_index
;
681 VkDeviceQueueCreateFlags flags
;
683 uint32_t scratch_size
;
684 uint32_t compute_scratch_size
;
685 uint32_t esgs_ring_size
;
686 uint32_t gsvs_ring_size
;
689 bool has_sample_positions
;
691 struct radeon_winsys_bo
*scratch_bo
;
692 struct radeon_winsys_bo
*descriptor_bo
;
693 struct radeon_winsys_bo
*compute_scratch_bo
;
694 struct radeon_winsys_bo
*esgs_ring_bo
;
695 struct radeon_winsys_bo
*gsvs_ring_bo
;
696 struct radeon_winsys_bo
*tess_rings_bo
;
697 struct radeon_winsys_bo
*gds_bo
;
698 struct radeon_winsys_bo
*gds_oa_bo
;
699 struct radeon_cmdbuf
*initial_preamble_cs
;
700 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
701 struct radeon_cmdbuf
*continue_preamble_cs
;
704 struct radv_bo_list
{
705 struct radv_winsys_bo_list list
;
707 pthread_mutex_t mutex
;
711 VK_LOADER_DATA _loader_data
;
713 VkAllocationCallbacks alloc
;
715 struct radv_instance
* instance
;
716 struct radeon_winsys
*ws
;
718 struct radv_meta_state meta_state
;
720 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
721 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
722 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
724 bool always_use_syncobj
;
727 uint32_t tess_offchip_block_dw_size
;
728 uint32_t scratch_waves
;
729 uint32_t dispatch_initiator
;
731 uint32_t gs_table_depth
;
733 /* MSAA sample locations.
734 * The first index is the sample index.
735 * The second index is the coordinate: X, Y. */
736 float sample_locations_1x
[1][2];
737 float sample_locations_2x
[2][2];
738 float sample_locations_4x
[4][2];
739 float sample_locations_8x
[8][2];
742 uint32_t gfx_init_size_dw
;
743 struct radeon_winsys_bo
*gfx_init
;
745 struct radeon_winsys_bo
*trace_bo
;
746 uint32_t *trace_id_ptr
;
748 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
749 bool keep_shader_info
;
751 struct radv_physical_device
*physical_device
;
753 /* Backup in-memory cache to be used if the app doesn't provide one */
754 struct radv_pipeline_cache
* mem_cache
;
757 * use different counters so MSAA MRTs get consecutive surface indices,
758 * even if MASK is allocated in between.
760 uint32_t image_mrt_offset_counter
;
761 uint32_t fmask_mrt_offset_counter
;
762 struct list_head shader_slabs
;
763 mtx_t shader_slab_mutex
;
765 /* For detecting VM faults reported by dmesg. */
766 uint64_t dmesg_timestamp
;
768 struct radv_device_extension_table enabled_extensions
;
770 /* Whether the app has enabled the robustBufferAccess feature. */
771 bool robust_buffer_access
;
773 /* Whether the driver uses a global BO list. */
774 bool use_global_bo_list
;
776 struct radv_bo_list bo_list
;
778 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
782 struct radv_device_memory
{
783 struct radeon_winsys_bo
*bo
;
784 /* for dedicated allocations */
785 struct radv_image
*image
;
786 struct radv_buffer
*buffer
;
788 VkDeviceSize map_size
;
792 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
793 struct AHardwareBuffer
* android_hardware_buffer
;
798 struct radv_descriptor_range
{
803 struct radv_descriptor_set
{
804 const struct radv_descriptor_set_layout
*layout
;
807 struct radeon_winsys_bo
*bo
;
809 uint32_t *mapped_ptr
;
810 struct radv_descriptor_range
*dynamic_descriptors
;
812 struct radeon_winsys_bo
*descriptors
[0];
815 struct radv_push_descriptor_set
817 struct radv_descriptor_set set
;
821 struct radv_descriptor_pool_entry
{
824 struct radv_descriptor_set
*set
;
827 struct radv_descriptor_pool
{
828 struct radeon_winsys_bo
*bo
;
830 uint64_t current_offset
;
833 uint8_t *host_memory_base
;
834 uint8_t *host_memory_ptr
;
835 uint8_t *host_memory_end
;
837 uint32_t entry_count
;
838 uint32_t max_entry_count
;
839 struct radv_descriptor_pool_entry entries
[0];
842 struct radv_descriptor_update_template_entry
{
843 VkDescriptorType descriptor_type
;
845 /* The number of descriptors to update */
846 uint32_t descriptor_count
;
848 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
851 /* In dwords. Not valid/used for dynamic descriptors */
854 uint32_t buffer_offset
;
856 /* Only valid for combined image samplers and samplers */
858 uint8_t sampler_offset
;
864 /* For push descriptors */
865 const uint32_t *immutable_samplers
;
868 struct radv_descriptor_update_template
{
869 uint32_t entry_count
;
870 VkPipelineBindPoint bind_point
;
871 struct radv_descriptor_update_template_entry entry
[0];
877 VkBufferUsageFlags usage
;
878 VkBufferCreateFlags flags
;
881 struct radeon_winsys_bo
* bo
;
887 enum radv_dynamic_state_bits
{
888 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
889 RADV_DYNAMIC_SCISSOR
= 1 << 1,
890 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
891 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
892 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
893 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
894 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
895 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
896 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
897 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
898 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
899 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
902 enum radv_cmd_dirty_bits
{
903 /* Keep the dynamic state dirty bits in sync with
904 * enum radv_dynamic_state_bits */
905 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
906 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
907 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
908 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
909 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
910 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
911 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
912 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
913 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
914 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
915 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
916 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
917 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
918 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
919 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
920 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
921 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
924 enum radv_cmd_flush_bits
{
925 /* Instruction cache. */
926 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
927 /* Scalar L1 cache. */
928 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
929 /* Vector L1 cache. */
930 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
931 /* L2 cache + L2 metadata cache writeback & invalidate.
932 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
933 RADV_CMD_FLAG_INV_L2
= 1 << 3,
934 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
935 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
936 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
937 RADV_CMD_FLAG_WB_L2
= 1 << 4,
938 /* Framebuffer caches */
939 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
940 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
941 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
942 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
943 /* Engine synchronization. */
944 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
945 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
946 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
947 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
948 /* Pipeline query controls. */
949 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
950 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
951 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
953 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
954 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
955 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
956 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
959 struct radv_vertex_binding
{
960 struct radv_buffer
* buffer
;
964 struct radv_streamout_binding
{
965 struct radv_buffer
*buffer
;
970 struct radv_streamout_state
{
971 /* Mask of bound streamout buffers. */
972 uint8_t enabled_mask
;
974 /* External state that comes from the last vertex stage, it must be
975 * set explicitely when binding a new graphics pipeline.
977 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
978 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
980 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
981 uint32_t hw_enabled_mask
;
983 /* State of VGT_STRMOUT_(CONFIG|EN) */
984 bool streamout_enabled
;
987 struct radv_viewport_state
{
989 VkViewport viewports
[MAX_VIEWPORTS
];
992 struct radv_scissor_state
{
994 VkRect2D scissors
[MAX_SCISSORS
];
997 struct radv_discard_rectangle_state
{
999 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1002 struct radv_sample_locations_state
{
1003 VkSampleCountFlagBits per_pixel
;
1004 VkExtent2D grid_size
;
1006 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1009 struct radv_dynamic_state
{
1011 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1012 * Defines the set of saved dynamic state.
1016 struct radv_viewport_state viewport
;
1018 struct radv_scissor_state scissor
;
1028 float blend_constants
[4];
1038 } stencil_compare_mask
;
1043 } stencil_write_mask
;
1048 } stencil_reference
;
1050 struct radv_discard_rectangle_state discard_rectangle
;
1052 struct radv_sample_locations_state sample_location
;
1055 extern const struct radv_dynamic_state default_dynamic_state
;
1058 radv_get_debug_option_name(int id
);
1061 radv_get_perftest_option_name(int id
);
1063 struct radv_color_buffer_info
{
1064 uint64_t cb_color_base
;
1065 uint64_t cb_color_cmask
;
1066 uint64_t cb_color_fmask
;
1067 uint64_t cb_dcc_base
;
1068 uint32_t cb_color_slice
;
1069 uint32_t cb_color_view
;
1070 uint32_t cb_color_info
;
1071 uint32_t cb_color_attrib
;
1072 uint32_t cb_color_attrib2
; /* GFX9 and later */
1073 uint32_t cb_color_attrib3
; /* GFX10 and later */
1074 uint32_t cb_dcc_control
;
1075 uint32_t cb_color_cmask_slice
;
1076 uint32_t cb_color_fmask_slice
;
1078 uint32_t cb_color_pitch
; // GFX6-GFX8
1079 uint32_t cb_mrt_epitch
; // GFX9+
1083 struct radv_ds_buffer_info
{
1084 uint64_t db_z_read_base
;
1085 uint64_t db_stencil_read_base
;
1086 uint64_t db_z_write_base
;
1087 uint64_t db_stencil_write_base
;
1088 uint64_t db_htile_data_base
;
1089 uint32_t db_depth_info
;
1091 uint32_t db_stencil_info
;
1092 uint32_t db_depth_view
;
1093 uint32_t db_depth_size
;
1094 uint32_t db_depth_slice
;
1095 uint32_t db_htile_surface
;
1096 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1097 uint32_t db_z_info2
; /* GFX9 only */
1098 uint32_t db_stencil_info2
; /* GFX9 only */
1103 radv_initialise_color_surface(struct radv_device
*device
,
1104 struct radv_color_buffer_info
*cb
,
1105 struct radv_image_view
*iview
);
1107 radv_initialise_ds_surface(struct radv_device
*device
,
1108 struct radv_ds_buffer_info
*ds
,
1109 struct radv_image_view
*iview
);
1112 * Attachment state when recording a renderpass instance.
1114 * The clear value is valid only if there exists a pending clear.
1116 struct radv_attachment_state
{
1117 VkImageAspectFlags pending_clear_aspects
;
1118 uint32_t cleared_views
;
1119 VkClearValue clear_value
;
1120 VkImageLayout current_layout
;
1121 bool current_in_render_loop
;
1122 struct radv_sample_locations_state sample_location
;
1125 struct radv_color_buffer_info cb
;
1126 struct radv_ds_buffer_info ds
;
1128 struct radv_image_view
*iview
;
1131 struct radv_descriptor_state
{
1132 struct radv_descriptor_set
*sets
[MAX_SETS
];
1135 struct radv_push_descriptor_set push_set
;
1137 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1140 struct radv_subpass_sample_locs_state
{
1141 uint32_t subpass_idx
;
1142 struct radv_sample_locations_state sample_location
;
1145 struct radv_cmd_state
{
1146 /* Vertex descriptors */
1153 uint32_t prefetch_L2_mask
;
1155 struct radv_pipeline
* pipeline
;
1156 struct radv_pipeline
* emitted_pipeline
;
1157 struct radv_pipeline
* compute_pipeline
;
1158 struct radv_pipeline
* emitted_compute_pipeline
;
1159 struct radv_framebuffer
* framebuffer
;
1160 struct radv_render_pass
* pass
;
1161 const struct radv_subpass
* subpass
;
1162 struct radv_dynamic_state dynamic
;
1163 struct radv_attachment_state
* attachments
;
1164 struct radv_streamout_state streamout
;
1165 VkRect2D render_area
;
1167 uint32_t num_subpass_sample_locs
;
1168 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1171 struct radv_buffer
*index_buffer
;
1172 uint64_t index_offset
;
1173 uint32_t index_type
;
1174 uint32_t max_index_count
;
1176 int32_t last_index_type
;
1178 int32_t last_primitive_reset_en
;
1179 uint32_t last_primitive_reset_index
;
1180 enum radv_cmd_flush_bits flush_bits
;
1181 unsigned active_occlusion_queries
;
1182 bool perfect_occlusion_queries_enabled
;
1183 unsigned active_pipeline_queries
;
1186 uint32_t last_ia_multi_vgt_param
;
1188 uint32_t last_num_instances
;
1189 uint32_t last_first_instance
;
1190 uint32_t last_vertex_offset
;
1192 /* Whether CP DMA is busy/idle. */
1195 /* Conditional rendering info. */
1196 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1197 uint64_t predication_va
;
1199 bool context_roll_without_scissor_emitted
;
1202 struct radv_cmd_pool
{
1203 VkAllocationCallbacks alloc
;
1204 struct list_head cmd_buffers
;
1205 struct list_head free_cmd_buffers
;
1206 uint32_t queue_family_index
;
1209 struct radv_cmd_buffer_upload
{
1213 struct radeon_winsys_bo
*upload_bo
;
1214 struct list_head list
;
1217 enum radv_cmd_buffer_status
{
1218 RADV_CMD_BUFFER_STATUS_INVALID
,
1219 RADV_CMD_BUFFER_STATUS_INITIAL
,
1220 RADV_CMD_BUFFER_STATUS_RECORDING
,
1221 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1222 RADV_CMD_BUFFER_STATUS_PENDING
,
1225 struct radv_cmd_buffer
{
1226 VK_LOADER_DATA _loader_data
;
1228 struct radv_device
* device
;
1230 struct radv_cmd_pool
* pool
;
1231 struct list_head pool_link
;
1233 VkCommandBufferUsageFlags usage_flags
;
1234 VkCommandBufferLevel level
;
1235 enum radv_cmd_buffer_status status
;
1236 struct radeon_cmdbuf
*cs
;
1237 struct radv_cmd_state state
;
1238 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1239 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1240 uint32_t queue_family_index
;
1242 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1243 VkShaderStageFlags push_constant_stages
;
1244 struct radv_descriptor_set meta_push_descriptors
;
1246 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1248 struct radv_cmd_buffer_upload upload
;
1250 uint32_t scratch_size_needed
;
1251 uint32_t compute_scratch_size_needed
;
1252 uint32_t esgs_ring_size_needed
;
1253 uint32_t gsvs_ring_size_needed
;
1254 bool tess_rings_needed
;
1255 bool gds_needed
; /* for GFX10 streamout */
1256 bool sample_positions_needed
;
1258 VkResult record_result
;
1260 uint64_t gfx9_fence_va
;
1261 uint32_t gfx9_fence_idx
;
1262 uint64_t gfx9_eop_bug_va
;
1265 * Whether a query pool has been resetted and we have to flush caches.
1267 bool pending_reset_query
;
1270 * Bitmask of pending active query flushes.
1272 enum radv_cmd_flush_bits active_query_flush_bits
;
1276 struct radv_image_view
;
1278 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1280 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1281 struct radeon_cmdbuf
*cs
);
1282 void si_emit_compute(struct radv_physical_device
*physical_device
,
1283 struct radeon_cmdbuf
*cs
);
1285 void cik_create_gfx_config(struct radv_device
*device
);
1287 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1288 int count
, const VkViewport
*viewports
);
1289 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1290 int count
, const VkRect2D
*scissors
,
1291 const VkViewport
*viewports
, bool can_use_guardband
);
1292 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1293 bool instanced_draw
, bool indirect_draw
,
1294 bool count_from_stream_output
,
1295 uint32_t draw_vertex_count
);
1296 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1297 enum chip_class chip_class
,
1299 unsigned event
, unsigned event_flags
,
1300 unsigned dst_sel
, unsigned data_sel
,
1303 uint64_t gfx9_eop_bug_va
);
1305 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1306 uint32_t ref
, uint32_t mask
);
1307 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1308 enum chip_class chip_class
,
1309 uint32_t *fence_ptr
, uint64_t va
,
1311 enum radv_cmd_flush_bits flush_bits
,
1312 uint64_t gfx9_eop_bug_va
);
1313 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1314 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1315 bool inverted
, uint64_t va
);
1316 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1317 uint64_t src_va
, uint64_t dest_va
,
1319 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1321 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1322 uint64_t size
, unsigned value
);
1323 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1325 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1327 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1330 unsigned *out_offset
,
1333 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1334 const struct radv_subpass
*subpass
);
1336 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1337 unsigned size
, unsigned alignmnet
,
1338 const void *data
, unsigned *out_offset
);
1340 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1341 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1342 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1343 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1344 VkImageAspectFlags aspects
,
1345 VkResolveModeFlagBitsKHR resolve_mode
);
1346 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1347 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1348 VkImageAspectFlags aspects
,
1349 VkResolveModeFlagBitsKHR resolve_mode
);
1350 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1351 unsigned radv_get_default_max_sample_dist(int log_samples
);
1352 void radv_device_init_msaa(struct radv_device
*device
);
1354 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1355 const struct radv_image_view
*iview
,
1356 VkClearDepthStencilValue ds_clear_value
,
1357 VkImageAspectFlags aspects
);
1359 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1360 const struct radv_image_view
*iview
,
1362 uint32_t color_values
[2]);
1364 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1365 struct radv_image
*image
,
1366 const VkImageSubresourceRange
*range
, bool value
);
1368 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1369 struct radv_image
*image
,
1370 const VkImageSubresourceRange
*range
, bool value
);
1372 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1373 struct radeon_winsys_bo
*bo
,
1374 uint64_t offset
, uint64_t size
, uint32_t value
);
1375 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1376 bool radv_get_memory_fd(struct radv_device
*device
,
1377 struct radv_device_memory
*memory
,
1381 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1382 unsigned sh_offset
, unsigned pointer_count
,
1383 bool use_32bit_pointers
)
1385 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1386 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1390 radv_emit_shader_pointer_body(struct radv_device
*device
,
1391 struct radeon_cmdbuf
*cs
,
1392 uint64_t va
, bool use_32bit_pointers
)
1394 radeon_emit(cs
, va
);
1396 if (use_32bit_pointers
) {
1398 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1400 radeon_emit(cs
, va
>> 32);
1405 radv_emit_shader_pointer(struct radv_device
*device
,
1406 struct radeon_cmdbuf
*cs
,
1407 uint32_t sh_offset
, uint64_t va
, bool global
)
1409 bool use_32bit_pointers
= !global
;
1411 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1412 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1415 static inline struct radv_descriptor_state
*
1416 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1417 VkPipelineBindPoint bind_point
)
1419 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1420 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1421 return &cmd_buffer
->descriptors
[bind_point
];
1425 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1427 * Limitations: Can't call normal dispatch functions without binding or rebinding
1428 * the compute pipeline.
1430 void radv_unaligned_dispatch(
1431 struct radv_cmd_buffer
*cmd_buffer
,
1437 struct radeon_winsys_bo
*bo
;
1441 struct radv_shader_module
;
1443 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1444 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1445 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1446 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1447 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1448 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1449 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1450 #define RADV_HASH_SHADER_ACO (1 << 7)
1453 radv_hash_shaders(unsigned char *hash
,
1454 const VkPipelineShaderStageCreateInfo
**stages
,
1455 const struct radv_pipeline_layout
*layout
,
1456 const struct radv_pipeline_key
*key
,
1459 static inline gl_shader_stage
1460 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1462 assert(__builtin_popcount(vk_stage
) == 1);
1463 return ffs(vk_stage
) - 1;
1466 static inline VkShaderStageFlagBits
1467 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1469 return (1 << mesa_stage
);
1472 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1474 #define radv_foreach_stage(stage, stage_bits) \
1475 for (gl_shader_stage stage, \
1476 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1477 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1478 __tmp &= ~(1 << (stage)))
1480 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1481 unsigned radv_format_meta_fs_key(VkFormat format
);
1483 struct radv_multisample_state
{
1485 uint32_t pa_sc_line_cntl
;
1486 uint32_t pa_sc_mode_cntl_0
;
1487 uint32_t pa_sc_mode_cntl_1
;
1488 uint32_t pa_sc_aa_config
;
1489 uint32_t pa_sc_aa_mask
[2];
1490 unsigned num_samples
;
1493 struct radv_prim_vertex_count
{
1498 struct radv_vertex_elements_info
{
1499 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1502 struct radv_ia_multi_vgt_param_helpers
{
1504 bool partial_es_wave
;
1505 uint8_t primgroup_size
;
1506 bool wd_switch_on_eop
;
1507 bool ia_switch_on_eoi
;
1508 bool partial_vs_wave
;
1511 struct radv_binning_state
{
1512 uint32_t pa_sc_binner_cntl_0
;
1513 uint32_t db_dfsm_control
;
1516 #define SI_GS_PER_ES 128
1518 struct radv_pipeline
{
1519 struct radv_device
* device
;
1520 struct radv_dynamic_state dynamic_state
;
1522 struct radv_pipeline_layout
* layout
;
1524 bool need_indirect_descriptor_sets
;
1525 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1526 struct radv_shader_variant
*gs_copy_shader
;
1527 VkShaderStageFlags active_stages
;
1529 struct radeon_cmdbuf cs
;
1530 uint32_t ctx_cs_hash
;
1531 struct radeon_cmdbuf ctx_cs
;
1533 struct radv_vertex_elements_info vertex_elements
;
1535 uint32_t binding_stride
[MAX_VBS
];
1536 uint8_t num_vertex_bindings
;
1538 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1541 struct radv_multisample_state ms
;
1542 struct radv_binning_state binning
;
1543 uint32_t spi_baryc_cntl
;
1544 bool prim_restart_enable
;
1545 unsigned esgs_ring_size
;
1546 unsigned gsvs_ring_size
;
1547 uint32_t vtx_base_sgpr
;
1548 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1549 uint8_t vtx_emit_num
;
1550 struct radv_prim_vertex_count prim_vertex_count
;
1551 bool can_use_guardband
;
1552 uint32_t needed_dynamic_state
;
1553 bool disable_out_of_order_rast_for_occlusion
;
1555 /* Used for rbplus */
1556 uint32_t col_format
;
1557 uint32_t cb_target_mask
;
1562 unsigned scratch_bytes_per_wave
;
1564 /* Not NULL if graphics pipeline uses streamout. */
1565 struct radv_shader_variant
*streamout_shader
;
1568 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1570 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1573 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1575 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1578 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1580 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1582 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1583 gl_shader_stage stage
,
1586 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1587 gl_shader_stage stage
);
1589 struct radv_graphics_pipeline_create_info
{
1591 bool db_depth_clear
;
1592 bool db_stencil_clear
;
1593 bool db_depth_disable_expclear
;
1594 bool db_stencil_disable_expclear
;
1595 bool db_flush_depth_inplace
;
1596 bool db_flush_stencil_inplace
;
1597 bool db_resummarize
;
1598 uint32_t custom_blend_mode
;
1602 radv_graphics_pipeline_create(VkDevice device
,
1603 VkPipelineCache cache
,
1604 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1605 const struct radv_graphics_pipeline_create_info
*extra
,
1606 const VkAllocationCallbacks
*alloc
,
1607 VkPipeline
*pPipeline
);
1609 struct vk_format_description
;
1610 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1611 int first_non_void
);
1612 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1613 int first_non_void
);
1614 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1615 uint32_t radv_translate_colorformat(VkFormat format
);
1616 uint32_t radv_translate_color_numformat(VkFormat format
,
1617 const struct vk_format_description
*desc
,
1618 int first_non_void
);
1619 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1620 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1621 uint32_t radv_translate_dbformat(VkFormat format
);
1622 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1623 const struct vk_format_description
*desc
,
1624 int first_non_void
);
1625 uint32_t radv_translate_tex_numformat(VkFormat format
,
1626 const struct vk_format_description
*desc
,
1627 int first_non_void
);
1628 bool radv_format_pack_clear_color(VkFormat format
,
1629 uint32_t clear_vals
[2],
1630 VkClearColorValue
*value
);
1631 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1632 bool radv_dcc_formats_compatible(VkFormat format1
,
1634 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1636 struct radv_image_plane
{
1638 struct radeon_surf surface
;
1644 /* The original VkFormat provided by the client. This may not match any
1645 * of the actual surface formats.
1648 VkImageAspectFlags aspects
;
1649 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1650 struct ac_surf_info info
;
1651 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1652 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1657 unsigned queue_family_mask
;
1661 /* Set when bound */
1662 struct radeon_winsys_bo
*bo
;
1663 VkDeviceSize offset
;
1664 uint64_t dcc_offset
;
1665 uint64_t htile_offset
;
1666 bool tc_compatible_htile
;
1667 bool tc_compatible_cmask
;
1669 uint64_t cmask_offset
;
1670 uint64_t fmask_offset
;
1671 uint64_t clear_value_offset
;
1672 uint64_t fce_pred_offset
;
1673 uint64_t dcc_pred_offset
;
1676 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1677 * stored at this offset is UINT_MAX, the driver will emit
1678 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1679 * SET_CONTEXT_REG packet.
1681 uint64_t tc_compat_zrange_offset
;
1683 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1684 VkDeviceMemory owned_memory
;
1686 unsigned plane_count
;
1687 struct radv_image_plane planes
[0];
1690 /* Whether the image has a htile that is known consistent with the contents of
1692 bool radv_layout_has_htile(const struct radv_image
*image
,
1693 VkImageLayout layout
,
1694 bool in_render_loop
,
1695 unsigned queue_mask
);
1697 /* Whether the image has a htile that is known consistent with the contents of
1698 * the image and is allowed to be in compressed form.
1700 * If this is false reads that don't use the htile should be able to return
1703 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1704 VkImageLayout layout
,
1705 bool in_render_loop
,
1706 unsigned queue_mask
);
1708 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1709 VkImageLayout layout
,
1710 bool in_render_loop
,
1711 unsigned queue_mask
);
1713 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1714 const struct radv_image
*image
,
1715 VkImageLayout layout
,
1716 bool in_render_loop
,
1717 unsigned queue_mask
);
1720 * Return whether the image has CMASK metadata for color surfaces.
1723 radv_image_has_cmask(const struct radv_image
*image
)
1725 return image
->cmask_offset
;
1729 * Return whether the image has FMASK metadata for color surfaces.
1732 radv_image_has_fmask(const struct radv_image
*image
)
1734 return image
->fmask_offset
;
1738 * Return whether the image has DCC metadata for color surfaces.
1741 radv_image_has_dcc(const struct radv_image
*image
)
1743 return image
->planes
[0].surface
.dcc_size
;
1747 * Return whether the image is TC-compatible CMASK.
1750 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1752 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1756 * Return whether DCC metadata is enabled for a level.
1759 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1761 return radv_image_has_dcc(image
) &&
1762 level
< image
->planes
[0].surface
.num_dcc_levels
;
1766 * Return whether the image has CB metadata.
1769 radv_image_has_CB_metadata(const struct radv_image
*image
)
1771 return radv_image_has_cmask(image
) ||
1772 radv_image_has_fmask(image
) ||
1773 radv_image_has_dcc(image
);
1777 * Return whether the image has HTILE metadata for depth surfaces.
1780 radv_image_has_htile(const struct radv_image
*image
)
1782 return image
->planes
[0].surface
.htile_size
;
1786 * Return whether HTILE metadata is enabled for a level.
1789 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1791 return radv_image_has_htile(image
) && level
== 0;
1795 * Return whether the image is TC-compatible HTILE.
1798 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1800 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1803 static inline uint64_t
1804 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1805 uint32_t base_level
)
1807 uint64_t va
= radv_buffer_get_va(image
->bo
);
1808 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1812 static inline uint64_t
1813 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1814 uint32_t base_level
)
1816 uint64_t va
= radv_buffer_get_va(image
->bo
);
1817 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1821 static inline uint64_t
1822 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1823 uint32_t base_level
)
1825 uint64_t va
= radv_buffer_get_va(image
->bo
);
1826 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1830 static inline uint64_t
1831 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1832 uint32_t base_level
)
1834 uint64_t va
= radv_buffer_get_va(image
->bo
);
1835 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1839 static inline uint64_t
1840 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1841 uint32_t base_level
)
1843 uint64_t va
= radv_buffer_get_va(image
->bo
);
1844 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1848 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1850 static inline uint32_t
1851 radv_get_layerCount(const struct radv_image
*image
,
1852 const VkImageSubresourceRange
*range
)
1854 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1855 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1858 static inline uint32_t
1859 radv_get_levelCount(const struct radv_image
*image
,
1860 const VkImageSubresourceRange
*range
)
1862 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1863 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1866 struct radeon_bo_metadata
;
1868 radv_init_metadata(struct radv_device
*device
,
1869 struct radv_image
*image
,
1870 struct radeon_bo_metadata
*metadata
);
1873 radv_image_override_offset_stride(struct radv_device
*device
,
1874 struct radv_image
*image
,
1875 uint64_t offset
, uint32_t stride
);
1877 union radv_descriptor
{
1879 uint32_t plane0_descriptor
[8];
1880 uint32_t fmask_descriptor
[8];
1883 uint32_t plane_descriptors
[3][8];
1887 struct radv_image_view
{
1888 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1889 struct radeon_winsys_bo
*bo
;
1891 VkImageViewType type
;
1892 VkImageAspectFlags aspect_mask
;
1895 bool multiple_planes
;
1896 uint32_t base_layer
;
1897 uint32_t layer_count
;
1899 uint32_t level_count
;
1900 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1902 union radv_descriptor descriptor
;
1904 /* Descriptor for use as a storage image as opposed to a sampled image.
1905 * This has a few differences for cube maps (e.g. type).
1907 union radv_descriptor storage_descriptor
;
1910 struct radv_image_create_info
{
1911 const VkImageCreateInfo
*vk_info
;
1913 bool no_metadata_planes
;
1914 const struct radeon_bo_metadata
*bo_metadata
;
1918 radv_image_create_layout(struct radv_device
*device
,
1919 struct radv_image_create_info create_info
,
1920 struct radv_image
*image
);
1922 VkResult
radv_image_create(VkDevice _device
,
1923 const struct radv_image_create_info
*info
,
1924 const VkAllocationCallbacks
* alloc
,
1927 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
1930 radv_image_from_gralloc(VkDevice device_h
,
1931 const VkImageCreateInfo
*base_info
,
1932 const VkNativeBufferANDROID
*gralloc_info
,
1933 const VkAllocationCallbacks
*alloc
,
1934 VkImage
*out_image_h
);
1936 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
1937 const VkImageUsageFlags vk_usage
);
1939 radv_import_ahb_memory(struct radv_device
*device
,
1940 struct radv_device_memory
*mem
,
1942 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
1944 radv_create_ahb_memory(struct radv_device
*device
,
1945 struct radv_device_memory
*mem
,
1947 const VkMemoryAllocateInfo
*pAllocateInfo
);
1950 radv_select_android_external_format(const void *next
, VkFormat default_format
);
1952 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
1954 struct radv_image_view_extra_create_info
{
1955 bool disable_compression
;
1958 void radv_image_view_init(struct radv_image_view
*view
,
1959 struct radv_device
*device
,
1960 const VkImageViewCreateInfo
*pCreateInfo
,
1961 const struct radv_image_view_extra_create_info
* extra_create_info
);
1963 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1965 struct radv_sampler_ycbcr_conversion
{
1967 VkSamplerYcbcrModelConversion ycbcr_model
;
1968 VkSamplerYcbcrRange ycbcr_range
;
1969 VkComponentMapping components
;
1970 VkChromaLocation chroma_offsets
[2];
1971 VkFilter chroma_filter
;
1974 struct radv_buffer_view
{
1975 struct radeon_winsys_bo
*bo
;
1977 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1980 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1981 struct radv_device
*device
,
1982 const VkBufferViewCreateInfo
* pCreateInfo
);
1984 static inline struct VkExtent3D
1985 radv_sanitize_image_extent(const VkImageType imageType
,
1986 const struct VkExtent3D imageExtent
)
1988 switch (imageType
) {
1989 case VK_IMAGE_TYPE_1D
:
1990 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1991 case VK_IMAGE_TYPE_2D
:
1992 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1993 case VK_IMAGE_TYPE_3D
:
1996 unreachable("invalid image type");
2000 static inline struct VkOffset3D
2001 radv_sanitize_image_offset(const VkImageType imageType
,
2002 const struct VkOffset3D imageOffset
)
2004 switch (imageType
) {
2005 case VK_IMAGE_TYPE_1D
:
2006 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2007 case VK_IMAGE_TYPE_2D
:
2008 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2009 case VK_IMAGE_TYPE_3D
:
2012 unreachable("invalid image type");
2017 radv_image_extent_compare(const struct radv_image
*image
,
2018 const VkExtent3D
*extent
)
2020 if (extent
->width
!= image
->info
.width
||
2021 extent
->height
!= image
->info
.height
||
2022 extent
->depth
!= image
->info
.depth
)
2027 struct radv_sampler
{
2029 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2032 struct radv_framebuffer
{
2037 uint32_t attachment_count
;
2038 struct radv_image_view
*attachments
[0];
2041 struct radv_subpass_barrier
{
2042 VkPipelineStageFlags src_stage_mask
;
2043 VkAccessFlags src_access_mask
;
2044 VkAccessFlags dst_access_mask
;
2047 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2048 const struct radv_subpass_barrier
*barrier
);
2050 struct radv_subpass_attachment
{
2051 uint32_t attachment
;
2052 VkImageLayout layout
;
2053 bool in_render_loop
;
2056 struct radv_subpass
{
2057 uint32_t attachment_count
;
2058 struct radv_subpass_attachment
* attachments
;
2060 uint32_t input_count
;
2061 uint32_t color_count
;
2062 struct radv_subpass_attachment
* input_attachments
;
2063 struct radv_subpass_attachment
* color_attachments
;
2064 struct radv_subpass_attachment
* resolve_attachments
;
2065 struct radv_subpass_attachment
* depth_stencil_attachment
;
2066 struct radv_subpass_attachment
* ds_resolve_attachment
;
2067 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2068 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2070 /** Subpass has at least one color resolve attachment */
2071 bool has_color_resolve
;
2073 /** Subpass has at least one color attachment */
2076 struct radv_subpass_barrier start_barrier
;
2079 VkSampleCountFlagBits max_sample_count
;
2083 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2085 struct radv_render_pass_attachment
{
2088 VkAttachmentLoadOp load_op
;
2089 VkAttachmentLoadOp stencil_load_op
;
2090 VkImageLayout initial_layout
;
2091 VkImageLayout final_layout
;
2093 /* The subpass id in which the attachment will be used first/last. */
2094 uint32_t first_subpass_idx
;
2095 uint32_t last_subpass_idx
;
2098 struct radv_render_pass
{
2099 uint32_t attachment_count
;
2100 uint32_t subpass_count
;
2101 struct radv_subpass_attachment
* subpass_attachments
;
2102 struct radv_render_pass_attachment
* attachments
;
2103 struct radv_subpass_barrier end_barrier
;
2104 struct radv_subpass subpasses
[0];
2107 VkResult
radv_device_init_meta(struct radv_device
*device
);
2108 void radv_device_finish_meta(struct radv_device
*device
);
2110 struct radv_query_pool
{
2111 struct radeon_winsys_bo
*bo
;
2113 uint32_t availability_offset
;
2117 uint32_t pipeline_stats_mask
;
2120 struct radv_semaphore
{
2121 /* use a winsys sem for non-exportable */
2122 struct radeon_winsys_sem
*sem
;
2124 uint32_t temp_syncobj
;
2127 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2128 VkPipelineBindPoint bind_point
,
2129 struct radv_descriptor_set
*set
,
2133 radv_update_descriptor_sets(struct radv_device
*device
,
2134 struct radv_cmd_buffer
*cmd_buffer
,
2135 VkDescriptorSet overrideSet
,
2136 uint32_t descriptorWriteCount
,
2137 const VkWriteDescriptorSet
*pDescriptorWrites
,
2138 uint32_t descriptorCopyCount
,
2139 const VkCopyDescriptorSet
*pDescriptorCopies
);
2142 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2143 struct radv_cmd_buffer
*cmd_buffer
,
2144 struct radv_descriptor_set
*set
,
2145 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2148 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2149 VkPipelineBindPoint pipelineBindPoint
,
2150 VkPipelineLayout _layout
,
2152 uint32_t descriptorWriteCount
,
2153 const VkWriteDescriptorSet
*pDescriptorWrites
);
2155 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2156 struct radv_image
*image
,
2157 const VkImageSubresourceRange
*range
, uint32_t value
);
2159 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2160 struct radv_image
*image
,
2161 const VkImageSubresourceRange
*range
);
2164 struct radeon_winsys_fence
*fence
;
2165 struct wsi_fence
*fence_wsi
;
2168 uint32_t temp_syncobj
;
2171 /* radv_nir_to_llvm.c */
2172 struct radv_shader_info
;
2173 struct radv_nir_compiler_options
;
2175 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2176 struct nir_shader
*geom_shader
,
2177 struct radv_shader_binary
**rbinary
,
2178 struct radv_shader_info
*info
,
2179 const struct radv_nir_compiler_options
*option
);
2181 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2182 struct radv_shader_binary
**rbinary
,
2183 struct radv_shader_info
*info
,
2184 struct nir_shader
*const *nir
,
2186 const struct radv_nir_compiler_options
*options
);
2188 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2189 gl_shader_stage stage
,
2190 const struct nir_shader
*nir
);
2192 /* radv_shader_info.h */
2193 struct radv_shader_info
;
2194 struct radv_shader_variant_key
;
2196 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2197 const struct radv_pipeline_layout
*layout
,
2198 const struct radv_shader_variant_key
*key
,
2199 struct radv_shader_info
*info
);
2201 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2203 struct radeon_winsys_sem
;
2205 uint64_t radv_get_current_time(void);
2207 static inline uint32_t
2208 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2211 case 0: /* GL_POINTS */
2213 case 1: /* GL_LINES */
2214 case 3: /* GL_LINE_STRIP */
2216 case 4: /* GL_TRIANGLES */
2217 case 5: /* GL_TRIANGLE_STRIP */
2219 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2221 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2223 case 7: /* GL_QUADS */
2224 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2231 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2233 static inline struct __radv_type * \
2234 __radv_type ## _from_handle(__VkType _handle) \
2236 return (struct __radv_type *) _handle; \
2239 static inline __VkType \
2240 __radv_type ## _to_handle(struct __radv_type *_obj) \
2242 return (__VkType) _obj; \
2245 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2247 static inline struct __radv_type * \
2248 __radv_type ## _from_handle(__VkType _handle) \
2250 return (struct __radv_type *)(uintptr_t) _handle; \
2253 static inline __VkType \
2254 __radv_type ## _to_handle(struct __radv_type *_obj) \
2256 return (__VkType)(uintptr_t) _obj; \
2259 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2260 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2262 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2263 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2264 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2265 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2266 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2268 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2269 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2270 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2271 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2272 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2273 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2274 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2275 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2276 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2277 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2278 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2279 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2280 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2281 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2282 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2283 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2284 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2285 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2286 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2287 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2288 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2289 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2291 #endif /* RADV_PRIVATE_H */