2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
43 #define VG(x) ((void)0)
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vulkan_android.h>
80 #include <vulkan/vk_icd.h>
81 #include <vulkan/vk_android_native_buffer.h>
83 #include "radv_entrypoints.h"
85 #include "wsi_common.h"
86 #include "wsi_common_display.h"
88 /* Helper to determine if we should compile
89 * any of the Android AHB support.
91 * To actually enable the ext we also need
92 * the necessary kernel support.
94 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
97 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
101 struct gfx10_format
{
102 unsigned img_format
:9;
104 /* Various formats are only supported with workarounds for vertex fetch,
105 * and some 32_32_32 formats are supported natively, but only for buffers
106 * (possibly with some image support, actually, but no filtering). */
110 #include "gfx10_format_table.h"
114 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
121 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
122 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
123 RADV_MEM_TYPE_GTT_CACHED
,
127 enum radv_secure_compile_type
{
128 RADV_SC_TYPE_INIT_SUCCESS
,
129 RADV_SC_TYPE_INIT_FAILURE
,
130 RADV_SC_TYPE_COMPILE_PIPELINE
,
131 RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
,
132 RADV_SC_TYPE_READ_DISK_CACHE
,
133 RADV_SC_TYPE_WRITE_DISK_CACHE
,
134 RADV_SC_TYPE_DESTROY_DEVICE
,
138 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
140 static inline uint32_t
141 align_u32(uint32_t v
, uint32_t a
)
143 assert(a
!= 0 && a
== (a
& -a
));
144 return (v
+ a
- 1) & ~(a
- 1);
147 static inline uint32_t
148 align_u32_npot(uint32_t v
, uint32_t a
)
150 return (v
+ a
- 1) / a
* a
;
153 static inline uint64_t
154 align_u64(uint64_t v
, uint64_t a
)
156 assert(a
!= 0 && a
== (a
& -a
));
157 return (v
+ a
- 1) & ~(a
- 1);
160 static inline int32_t
161 align_i32(int32_t v
, int32_t a
)
163 assert(a
!= 0 && a
== (a
& -a
));
164 return (v
+ a
- 1) & ~(a
- 1);
167 /** Alignment must be a power of 2. */
169 radv_is_aligned(uintmax_t n
, uintmax_t a
)
171 assert(a
== (a
& -a
));
172 return (n
& (a
- 1)) == 0;
175 static inline uint32_t
176 round_up_u32(uint32_t v
, uint32_t a
)
178 return (v
+ a
- 1) / a
;
181 static inline uint64_t
182 round_up_u64(uint64_t v
, uint64_t a
)
184 return (v
+ a
- 1) / a
;
187 static inline uint32_t
188 radv_minify(uint32_t n
, uint32_t levels
)
190 if (unlikely(n
== 0))
193 return MAX2(n
>> levels
, 1);
196 radv_clamp_f(float f
, float min
, float max
)
209 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
211 if (*inout_mask
& clear_mask
) {
212 *inout_mask
&= ~clear_mask
;
219 #define for_each_bit(b, dword) \
220 for (uint32_t __dword = (dword); \
221 (b) = __builtin_ffs(__dword) - 1, __dword; \
222 __dword &= ~(1 << (b)))
224 #define typed_memcpy(dest, src, count) ({ \
225 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
226 memcpy((dest), (src), (count) * sizeof(*(src))); \
229 /* Whenever we generate an error, pass it through this function. Useful for
230 * debugging, where we can break on it. Only call at error site, not when
231 * propagating errors. Might be useful to plug in a stack trace here.
234 struct radv_image_view
;
235 struct radv_instance
;
237 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
239 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
240 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
242 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
243 radv_printflike(3, 4);
244 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
245 void radv_loge_v(const char *format
, va_list va
);
246 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
247 void radv_logi_v(const char *format
, va_list va
);
250 * Print a FINISHME message, including its source location.
252 #define radv_finishme(format, ...) \
254 static bool reported = false; \
256 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
261 /* A non-fatal assert. Useful for debugging. */
263 #define radv_assert(x) ({ \
264 if (unlikely(!(x))) \
265 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
268 #define radv_assert(x)
271 #define stub_return(v) \
273 radv_finishme("stub %s", __func__); \
279 radv_finishme("stub %s", __func__); \
283 void *radv_lookup_entrypoint_unchecked(const char *name
);
284 void *radv_lookup_entrypoint_checked(const char *name
,
285 uint32_t core_version
,
286 const struct radv_instance_extension_table
*instance
,
287 const struct radv_device_extension_table
*device
);
288 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
289 uint32_t core_version
,
290 const struct radv_instance_extension_table
*instance
);
292 struct radv_physical_device
{
293 VK_LOADER_DATA _loader_data
;
295 struct radv_instance
* instance
;
297 struct radeon_winsys
*ws
;
298 struct radeon_info rad_info
;
299 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
300 uint8_t driver_uuid
[VK_UUID_SIZE
];
301 uint8_t device_uuid
[VK_UUID_SIZE
];
302 uint8_t cache_uuid
[VK_UUID_SIZE
];
306 struct wsi_device wsi_device
;
308 bool out_of_order_rast_allowed
;
310 /* Whether DCC should be enabled for MSAA textures. */
311 bool dcc_msaa_allowed
;
313 /* Whether to enable the AMD_shader_ballot extension */
314 bool use_shader_ballot
;
316 /* Whether to enable NGG. */
319 /* Whether to enable NGG streamout. */
320 bool use_ngg_streamout
;
322 /* Number of threads per wave. */
323 uint8_t ps_wave_size
;
324 uint8_t cs_wave_size
;
325 uint8_t ge_wave_size
;
327 /* Whether to use the experimental compiler backend */
330 /* This is the drivers on-disk cache used as a fallback as opposed to
331 * the pipeline cache defined by apps.
333 struct disk_cache
* disk_cache
;
335 VkPhysicalDeviceMemoryProperties memory_properties
;
336 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
338 drmPciBusInfo bus_info
;
340 struct radv_device_extension_table supported_extensions
;
343 struct radv_instance
{
344 VK_LOADER_DATA _loader_data
;
346 VkAllocationCallbacks alloc
;
349 int physicalDeviceCount
;
350 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
353 uint32_t engineVersion
;
355 uint64_t debug_flags
;
356 uint64_t perftest_flags
;
357 uint8_t num_sc_threads
;
359 struct vk_debug_report_instance debug_report_callbacks
;
361 struct radv_instance_extension_table enabled_extensions
;
363 struct driOptionCache dri_options
;
364 struct driOptionCache available_dri_options
;
368 bool radv_device_use_secure_compile(struct radv_instance
*instance
)
370 return instance
->num_sc_threads
;
373 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
374 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
376 bool radv_instance_extension_supported(const char *name
);
377 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
378 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
383 struct radv_pipeline_cache
{
384 struct radv_device
* device
;
385 pthread_mutex_t mutex
;
389 uint32_t kernel_count
;
390 struct cache_entry
** hash_table
;
393 VkAllocationCallbacks alloc
;
396 struct radv_pipeline_key
{
397 uint32_t instance_rate_inputs
;
398 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
399 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
400 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
401 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
402 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
403 uint64_t vertex_alpha_adjust
;
404 uint32_t vertex_post_shuffle
;
405 unsigned tess_input_vertices
;
409 uint8_t log2_ps_iter_samples
;
411 uint32_t has_multiview_view_index
: 1;
412 uint32_t optimisations_disabled
: 1;
415 /* Non-zero if a required subgroup size is specified via
416 * VK_EXT_subgroup_size_control.
418 uint8_t compute_subgroup_size
;
421 struct radv_shader_binary
;
422 struct radv_shader_variant
;
425 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
426 struct radv_device
*device
);
428 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
430 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
431 const void *data
, size_t size
);
434 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
435 struct radv_pipeline_cache
*cache
,
436 const unsigned char *sha1
,
437 struct radv_shader_variant
**variants
,
438 bool *found_in_application_cache
);
441 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
442 struct radv_pipeline_cache
*cache
,
443 const unsigned char *sha1
,
444 struct radv_shader_variant
**variants
,
445 struct radv_shader_binary
*const *binaries
);
447 enum radv_blit_ds_layout
{
448 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
449 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
450 RADV_BLIT_DS_LAYOUT_COUNT
,
453 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
455 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
458 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
460 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
463 enum radv_meta_dst_layout
{
464 RADV_META_DST_LAYOUT_GENERAL
,
465 RADV_META_DST_LAYOUT_OPTIMAL
,
466 RADV_META_DST_LAYOUT_COUNT
,
469 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
471 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
474 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
476 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
479 struct radv_meta_state
{
480 VkAllocationCallbacks alloc
;
482 struct radv_pipeline_cache cache
;
485 * For on-demand pipeline creation, makes sure that
486 * only one thread tries to build a pipeline at the same time.
491 * Use array element `i` for images with `2^i` samples.
494 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
495 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
497 VkRenderPass depthstencil_rp
;
498 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
499 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
500 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
502 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
503 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
504 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
505 } clear
[MAX_SAMPLES_LOG2
];
507 VkPipelineLayout clear_color_p_layout
;
508 VkPipelineLayout clear_depth_p_layout
;
509 VkPipelineLayout clear_depth_unrestricted_p_layout
;
511 /* Optimized compute fast HTILE clear for stencil or depth only. */
512 VkPipeline clear_htile_mask_pipeline
;
513 VkPipelineLayout clear_htile_mask_p_layout
;
514 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
517 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
519 /** Pipeline that blits from a 1D image. */
520 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
522 /** Pipeline that blits from a 2D image. */
523 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
525 /** Pipeline that blits from a 3D image. */
526 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
528 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
529 VkPipeline depth_only_1d_pipeline
;
530 VkPipeline depth_only_2d_pipeline
;
531 VkPipeline depth_only_3d_pipeline
;
533 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
534 VkPipeline stencil_only_1d_pipeline
;
535 VkPipeline stencil_only_2d_pipeline
;
536 VkPipeline stencil_only_3d_pipeline
;
537 VkPipelineLayout pipeline_layout
;
538 VkDescriptorSetLayout ds_layout
;
542 VkPipelineLayout p_layouts
[5];
543 VkDescriptorSetLayout ds_layouts
[5];
544 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
546 VkPipeline depth_only_pipeline
[5];
548 VkPipeline stencil_only_pipeline
[5];
549 } blit2d
[MAX_SAMPLES_LOG2
];
551 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
552 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
553 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
556 VkPipelineLayout img_p_layout
;
557 VkDescriptorSetLayout img_ds_layout
;
559 VkPipeline pipeline_3d
;
562 VkPipelineLayout img_p_layout
;
563 VkDescriptorSetLayout img_ds_layout
;
565 VkPipeline pipeline_3d
;
568 VkPipelineLayout img_p_layout
;
569 VkDescriptorSetLayout img_ds_layout
;
573 VkPipelineLayout img_p_layout
;
574 VkDescriptorSetLayout img_ds_layout
;
576 VkPipeline pipeline_3d
;
579 VkPipelineLayout img_p_layout
;
580 VkDescriptorSetLayout img_ds_layout
;
584 VkPipelineLayout img_p_layout
;
585 VkDescriptorSetLayout img_ds_layout
;
587 VkPipeline pipeline_3d
;
590 VkPipelineLayout img_p_layout
;
591 VkDescriptorSetLayout img_ds_layout
;
596 VkPipelineLayout p_layout
;
597 VkPipeline pipeline
[NUM_META_FS_KEYS
];
598 VkRenderPass pass
[NUM_META_FS_KEYS
];
602 VkDescriptorSetLayout ds_layout
;
603 VkPipelineLayout p_layout
;
606 VkPipeline i_pipeline
;
607 VkPipeline srgb_pipeline
;
608 } rc
[MAX_SAMPLES_LOG2
];
610 VkPipeline depth_zero_pipeline
;
612 VkPipeline average_pipeline
;
613 VkPipeline max_pipeline
;
614 VkPipeline min_pipeline
;
615 } depth
[MAX_SAMPLES_LOG2
];
617 VkPipeline stencil_zero_pipeline
;
619 VkPipeline max_pipeline
;
620 VkPipeline min_pipeline
;
621 } stencil
[MAX_SAMPLES_LOG2
];
625 VkDescriptorSetLayout ds_layout
;
626 VkPipelineLayout p_layout
;
629 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
630 VkPipeline pipeline
[NUM_META_FS_KEYS
];
631 } rc
[MAX_SAMPLES_LOG2
];
633 VkRenderPass depth_render_pass
;
634 VkPipeline depth_zero_pipeline
;
636 VkPipeline average_pipeline
;
637 VkPipeline max_pipeline
;
638 VkPipeline min_pipeline
;
639 } depth
[MAX_SAMPLES_LOG2
];
641 VkRenderPass stencil_render_pass
;
642 VkPipeline stencil_zero_pipeline
;
644 VkPipeline max_pipeline
;
645 VkPipeline min_pipeline
;
646 } stencil
[MAX_SAMPLES_LOG2
];
650 VkPipelineLayout p_layout
;
651 VkPipeline decompress_pipeline
;
652 VkPipeline resummarize_pipeline
;
654 } depth_decomp
[MAX_SAMPLES_LOG2
];
657 VkPipelineLayout p_layout
;
658 VkPipeline cmask_eliminate_pipeline
;
659 VkPipeline fmask_decompress_pipeline
;
660 VkPipeline dcc_decompress_pipeline
;
663 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
664 VkPipelineLayout dcc_decompress_compute_p_layout
;
665 VkPipeline dcc_decompress_compute_pipeline
;
669 VkPipelineLayout fill_p_layout
;
670 VkPipelineLayout copy_p_layout
;
671 VkDescriptorSetLayout fill_ds_layout
;
672 VkDescriptorSetLayout copy_ds_layout
;
673 VkPipeline fill_pipeline
;
674 VkPipeline copy_pipeline
;
678 VkDescriptorSetLayout ds_layout
;
679 VkPipelineLayout p_layout
;
680 VkPipeline occlusion_query_pipeline
;
681 VkPipeline pipeline_statistics_query_pipeline
;
682 VkPipeline tfb_query_pipeline
;
683 VkPipeline timestamp_query_pipeline
;
687 VkDescriptorSetLayout ds_layout
;
688 VkPipelineLayout p_layout
;
689 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
694 #define RADV_QUEUE_GENERAL 0
695 #define RADV_QUEUE_COMPUTE 1
696 #define RADV_QUEUE_TRANSFER 2
698 #define RADV_MAX_QUEUE_FAMILIES 3
700 enum ring_type
radv_queue_family_to_ring(int f
);
703 VK_LOADER_DATA _loader_data
;
704 struct radv_device
* device
;
705 struct radeon_winsys_ctx
*hw_ctx
;
706 enum radeon_ctx_priority priority
;
707 uint32_t queue_family_index
;
709 VkDeviceQueueCreateFlags flags
;
711 uint32_t scratch_size
;
712 uint32_t compute_scratch_size
;
713 uint32_t esgs_ring_size
;
714 uint32_t gsvs_ring_size
;
717 bool has_sample_positions
;
719 struct radeon_winsys_bo
*scratch_bo
;
720 struct radeon_winsys_bo
*descriptor_bo
;
721 struct radeon_winsys_bo
*compute_scratch_bo
;
722 struct radeon_winsys_bo
*esgs_ring_bo
;
723 struct radeon_winsys_bo
*gsvs_ring_bo
;
724 struct radeon_winsys_bo
*tess_rings_bo
;
725 struct radeon_winsys_bo
*gds_bo
;
726 struct radeon_winsys_bo
*gds_oa_bo
;
727 struct radeon_cmdbuf
*initial_preamble_cs
;
728 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
729 struct radeon_cmdbuf
*continue_preamble_cs
;
731 struct list_head pending_submissions
;
732 pthread_mutex_t pending_mutex
;
735 struct radv_bo_list
{
736 struct radv_winsys_bo_list list
;
738 pthread_mutex_t mutex
;
741 struct radv_secure_compile_process
{
742 /* Secure process file descriptors */
744 int fd_secure_output
;
746 /* Secure compile process id */
749 /* Is the secure compile process currently in use by a thread */
753 struct radv_secure_compile_state
{
754 struct radv_secure_compile_process
*secure_compile_processes
;
755 uint32_t secure_compile_thread_counter
;
756 mtx_t secure_compile_mutex
;
760 VK_LOADER_DATA _loader_data
;
762 VkAllocationCallbacks alloc
;
764 struct radv_instance
* instance
;
765 struct radeon_winsys
*ws
;
767 struct radv_meta_state meta_state
;
769 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
770 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
771 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
773 bool always_use_syncobj
;
776 uint32_t tess_offchip_block_dw_size
;
777 uint32_t scratch_waves
;
778 uint32_t dispatch_initiator
;
780 uint32_t gs_table_depth
;
782 /* MSAA sample locations.
783 * The first index is the sample index.
784 * The second index is the coordinate: X, Y. */
785 float sample_locations_1x
[1][2];
786 float sample_locations_2x
[2][2];
787 float sample_locations_4x
[4][2];
788 float sample_locations_8x
[8][2];
791 uint32_t gfx_init_size_dw
;
792 struct radeon_winsys_bo
*gfx_init
;
794 struct radeon_winsys_bo
*trace_bo
;
795 uint32_t *trace_id_ptr
;
797 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
798 bool keep_shader_info
;
800 struct radv_physical_device
*physical_device
;
802 /* Backup in-memory cache to be used if the app doesn't provide one */
803 struct radv_pipeline_cache
* mem_cache
;
806 * use different counters so MSAA MRTs get consecutive surface indices,
807 * even if MASK is allocated in between.
809 uint32_t image_mrt_offset_counter
;
810 uint32_t fmask_mrt_offset_counter
;
811 struct list_head shader_slabs
;
812 mtx_t shader_slab_mutex
;
814 /* For detecting VM faults reported by dmesg. */
815 uint64_t dmesg_timestamp
;
817 struct radv_device_extension_table enabled_extensions
;
819 /* Whether the app has enabled the robustBufferAccess feature. */
820 bool robust_buffer_access
;
822 /* Whether the driver uses a global BO list. */
823 bool use_global_bo_list
;
825 struct radv_bo_list bo_list
;
827 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
830 struct radv_secure_compile_state
*sc_state
;
832 /* Condition variable for legacy timelines, to notify waiters when a
833 * new point gets submitted. */
834 pthread_cond_t timeline_cond
;
837 struct radv_device_memory
{
838 struct radeon_winsys_bo
*bo
;
839 /* for dedicated allocations */
840 struct radv_image
*image
;
841 struct radv_buffer
*buffer
;
843 VkDeviceSize map_size
;
847 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
848 struct AHardwareBuffer
* android_hardware_buffer
;
853 struct radv_descriptor_range
{
858 struct radv_descriptor_set
{
859 const struct radv_descriptor_set_layout
*layout
;
862 struct radeon_winsys_bo
*bo
;
864 uint32_t *mapped_ptr
;
865 struct radv_descriptor_range
*dynamic_descriptors
;
867 struct radeon_winsys_bo
*descriptors
[0];
870 struct radv_push_descriptor_set
872 struct radv_descriptor_set set
;
876 struct radv_descriptor_pool_entry
{
879 struct radv_descriptor_set
*set
;
882 struct radv_descriptor_pool
{
883 struct radeon_winsys_bo
*bo
;
885 uint64_t current_offset
;
888 uint8_t *host_memory_base
;
889 uint8_t *host_memory_ptr
;
890 uint8_t *host_memory_end
;
892 uint32_t entry_count
;
893 uint32_t max_entry_count
;
894 struct radv_descriptor_pool_entry entries
[0];
897 struct radv_descriptor_update_template_entry
{
898 VkDescriptorType descriptor_type
;
900 /* The number of descriptors to update */
901 uint32_t descriptor_count
;
903 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
906 /* In dwords. Not valid/used for dynamic descriptors */
909 uint32_t buffer_offset
;
911 /* Only valid for combined image samplers and samplers */
913 uint8_t sampler_offset
;
919 /* For push descriptors */
920 const uint32_t *immutable_samplers
;
923 struct radv_descriptor_update_template
{
924 uint32_t entry_count
;
925 VkPipelineBindPoint bind_point
;
926 struct radv_descriptor_update_template_entry entry
[0];
932 VkBufferUsageFlags usage
;
933 VkBufferCreateFlags flags
;
936 struct radeon_winsys_bo
* bo
;
942 enum radv_dynamic_state_bits
{
943 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
944 RADV_DYNAMIC_SCISSOR
= 1 << 1,
945 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
946 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
947 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
948 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
949 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
950 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
951 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
952 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
953 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
954 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
957 enum radv_cmd_dirty_bits
{
958 /* Keep the dynamic state dirty bits in sync with
959 * enum radv_dynamic_state_bits */
960 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
961 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
962 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
963 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
964 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
965 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
966 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
967 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
968 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
969 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
970 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
971 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
972 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
973 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
974 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
975 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
976 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
979 enum radv_cmd_flush_bits
{
980 /* Instruction cache. */
981 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
982 /* Scalar L1 cache. */
983 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
984 /* Vector L1 cache. */
985 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
986 /* L2 cache + L2 metadata cache writeback & invalidate.
987 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
988 RADV_CMD_FLAG_INV_L2
= 1 << 3,
989 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
990 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
991 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
992 RADV_CMD_FLAG_WB_L2
= 1 << 4,
993 /* Framebuffer caches */
994 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
995 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
996 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
997 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
998 /* Engine synchronization. */
999 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
1000 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
1001 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
1002 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
1003 /* Pipeline query controls. */
1004 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
1005 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
1006 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
1008 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1009 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
1010 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
1011 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
1014 struct radv_vertex_binding
{
1015 struct radv_buffer
* buffer
;
1016 VkDeviceSize offset
;
1019 struct radv_streamout_binding
{
1020 struct radv_buffer
*buffer
;
1021 VkDeviceSize offset
;
1025 struct radv_streamout_state
{
1026 /* Mask of bound streamout buffers. */
1027 uint8_t enabled_mask
;
1029 /* External state that comes from the last vertex stage, it must be
1030 * set explicitely when binding a new graphics pipeline.
1032 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
1033 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
1035 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1036 uint32_t hw_enabled_mask
;
1038 /* State of VGT_STRMOUT_(CONFIG|EN) */
1039 bool streamout_enabled
;
1042 struct radv_viewport_state
{
1044 VkViewport viewports
[MAX_VIEWPORTS
];
1047 struct radv_scissor_state
{
1049 VkRect2D scissors
[MAX_SCISSORS
];
1052 struct radv_discard_rectangle_state
{
1054 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1057 struct radv_sample_locations_state
{
1058 VkSampleCountFlagBits per_pixel
;
1059 VkExtent2D grid_size
;
1061 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1064 struct radv_dynamic_state
{
1066 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1067 * Defines the set of saved dynamic state.
1071 struct radv_viewport_state viewport
;
1073 struct radv_scissor_state scissor
;
1083 float blend_constants
[4];
1093 } stencil_compare_mask
;
1098 } stencil_write_mask
;
1103 } stencil_reference
;
1105 struct radv_discard_rectangle_state discard_rectangle
;
1107 struct radv_sample_locations_state sample_location
;
1110 extern const struct radv_dynamic_state default_dynamic_state
;
1113 radv_get_debug_option_name(int id
);
1116 radv_get_perftest_option_name(int id
);
1118 struct radv_color_buffer_info
{
1119 uint64_t cb_color_base
;
1120 uint64_t cb_color_cmask
;
1121 uint64_t cb_color_fmask
;
1122 uint64_t cb_dcc_base
;
1123 uint32_t cb_color_slice
;
1124 uint32_t cb_color_view
;
1125 uint32_t cb_color_info
;
1126 uint32_t cb_color_attrib
;
1127 uint32_t cb_color_attrib2
; /* GFX9 and later */
1128 uint32_t cb_color_attrib3
; /* GFX10 and later */
1129 uint32_t cb_dcc_control
;
1130 uint32_t cb_color_cmask_slice
;
1131 uint32_t cb_color_fmask_slice
;
1133 uint32_t cb_color_pitch
; // GFX6-GFX8
1134 uint32_t cb_mrt_epitch
; // GFX9+
1138 struct radv_ds_buffer_info
{
1139 uint64_t db_z_read_base
;
1140 uint64_t db_stencil_read_base
;
1141 uint64_t db_z_write_base
;
1142 uint64_t db_stencil_write_base
;
1143 uint64_t db_htile_data_base
;
1144 uint32_t db_depth_info
;
1146 uint32_t db_stencil_info
;
1147 uint32_t db_depth_view
;
1148 uint32_t db_depth_size
;
1149 uint32_t db_depth_slice
;
1150 uint32_t db_htile_surface
;
1151 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1152 uint32_t db_z_info2
; /* GFX9 only */
1153 uint32_t db_stencil_info2
; /* GFX9 only */
1158 radv_initialise_color_surface(struct radv_device
*device
,
1159 struct radv_color_buffer_info
*cb
,
1160 struct radv_image_view
*iview
);
1162 radv_initialise_ds_surface(struct radv_device
*device
,
1163 struct radv_ds_buffer_info
*ds
,
1164 struct radv_image_view
*iview
);
1167 radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
);
1170 * Attachment state when recording a renderpass instance.
1172 * The clear value is valid only if there exists a pending clear.
1174 struct radv_attachment_state
{
1175 VkImageAspectFlags pending_clear_aspects
;
1176 uint32_t cleared_views
;
1177 VkClearValue clear_value
;
1178 VkImageLayout current_layout
;
1179 bool current_in_render_loop
;
1180 struct radv_sample_locations_state sample_location
;
1183 struct radv_color_buffer_info cb
;
1184 struct radv_ds_buffer_info ds
;
1186 struct radv_image_view
*iview
;
1189 struct radv_descriptor_state
{
1190 struct radv_descriptor_set
*sets
[MAX_SETS
];
1193 struct radv_push_descriptor_set push_set
;
1195 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1198 struct radv_subpass_sample_locs_state
{
1199 uint32_t subpass_idx
;
1200 struct radv_sample_locations_state sample_location
;
1203 struct radv_cmd_state
{
1204 /* Vertex descriptors */
1211 uint32_t prefetch_L2_mask
;
1213 struct radv_pipeline
* pipeline
;
1214 struct radv_pipeline
* emitted_pipeline
;
1215 struct radv_pipeline
* compute_pipeline
;
1216 struct radv_pipeline
* emitted_compute_pipeline
;
1217 struct radv_framebuffer
* framebuffer
;
1218 struct radv_render_pass
* pass
;
1219 const struct radv_subpass
* subpass
;
1220 struct radv_dynamic_state dynamic
;
1221 struct radv_attachment_state
* attachments
;
1222 struct radv_streamout_state streamout
;
1223 VkRect2D render_area
;
1225 uint32_t num_subpass_sample_locs
;
1226 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1229 struct radv_buffer
*index_buffer
;
1230 uint64_t index_offset
;
1231 uint32_t index_type
;
1232 uint32_t max_index_count
;
1234 int32_t last_index_type
;
1236 int32_t last_primitive_reset_en
;
1237 uint32_t last_primitive_reset_index
;
1238 enum radv_cmd_flush_bits flush_bits
;
1239 unsigned active_occlusion_queries
;
1240 bool perfect_occlusion_queries_enabled
;
1241 unsigned active_pipeline_queries
;
1244 uint32_t last_ia_multi_vgt_param
;
1246 uint32_t last_num_instances
;
1247 uint32_t last_first_instance
;
1248 uint32_t last_vertex_offset
;
1250 /* Whether CP DMA is busy/idle. */
1253 /* Conditional rendering info. */
1254 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1255 uint64_t predication_va
;
1257 bool context_roll_without_scissor_emitted
;
1260 struct radv_cmd_pool
{
1261 VkAllocationCallbacks alloc
;
1262 struct list_head cmd_buffers
;
1263 struct list_head free_cmd_buffers
;
1264 uint32_t queue_family_index
;
1267 struct radv_cmd_buffer_upload
{
1271 struct radeon_winsys_bo
*upload_bo
;
1272 struct list_head list
;
1275 enum radv_cmd_buffer_status
{
1276 RADV_CMD_BUFFER_STATUS_INVALID
,
1277 RADV_CMD_BUFFER_STATUS_INITIAL
,
1278 RADV_CMD_BUFFER_STATUS_RECORDING
,
1279 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1280 RADV_CMD_BUFFER_STATUS_PENDING
,
1283 struct radv_cmd_buffer
{
1284 VK_LOADER_DATA _loader_data
;
1286 struct radv_device
* device
;
1288 struct radv_cmd_pool
* pool
;
1289 struct list_head pool_link
;
1291 VkCommandBufferUsageFlags usage_flags
;
1292 VkCommandBufferLevel level
;
1293 enum radv_cmd_buffer_status status
;
1294 struct radeon_cmdbuf
*cs
;
1295 struct radv_cmd_state state
;
1296 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1297 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1298 uint32_t queue_family_index
;
1300 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1301 VkShaderStageFlags push_constant_stages
;
1302 struct radv_descriptor_set meta_push_descriptors
;
1304 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1306 struct radv_cmd_buffer_upload upload
;
1308 uint32_t scratch_size_needed
;
1309 uint32_t compute_scratch_size_needed
;
1310 uint32_t esgs_ring_size_needed
;
1311 uint32_t gsvs_ring_size_needed
;
1312 bool tess_rings_needed
;
1313 bool gds_needed
; /* for GFX10 streamout */
1314 bool sample_positions_needed
;
1316 VkResult record_result
;
1318 uint64_t gfx9_fence_va
;
1319 uint32_t gfx9_fence_idx
;
1320 uint64_t gfx9_eop_bug_va
;
1323 * Whether a query pool has been resetted and we have to flush caches.
1325 bool pending_reset_query
;
1328 * Bitmask of pending active query flushes.
1330 enum radv_cmd_flush_bits active_query_flush_bits
;
1334 struct radv_image_view
;
1336 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1338 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1339 struct radeon_cmdbuf
*cs
);
1340 void si_emit_compute(struct radv_physical_device
*physical_device
,
1341 struct radeon_cmdbuf
*cs
);
1343 void cik_create_gfx_config(struct radv_device
*device
);
1345 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1346 int count
, const VkViewport
*viewports
);
1347 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1348 int count
, const VkRect2D
*scissors
,
1349 const VkViewport
*viewports
, bool can_use_guardband
);
1350 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1351 bool instanced_draw
, bool indirect_draw
,
1352 bool count_from_stream_output
,
1353 uint32_t draw_vertex_count
);
1354 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1355 enum chip_class chip_class
,
1357 unsigned event
, unsigned event_flags
,
1358 unsigned dst_sel
, unsigned data_sel
,
1361 uint64_t gfx9_eop_bug_va
);
1363 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1364 uint32_t ref
, uint32_t mask
);
1365 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1366 enum chip_class chip_class
,
1367 uint32_t *fence_ptr
, uint64_t va
,
1369 enum radv_cmd_flush_bits flush_bits
,
1370 uint64_t gfx9_eop_bug_va
);
1371 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1372 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1373 bool inverted
, uint64_t va
);
1374 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1375 uint64_t src_va
, uint64_t dest_va
,
1377 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1379 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1380 uint64_t size
, unsigned value
);
1381 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1383 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1388 unsigned *out_offset
,
1391 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1392 const struct radv_subpass
*subpass
);
1394 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1395 unsigned size
, unsigned alignmnet
,
1396 const void *data
, unsigned *out_offset
);
1398 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1399 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1400 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1401 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1402 VkImageAspectFlags aspects
,
1403 VkResolveModeFlagBitsKHR resolve_mode
);
1404 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1405 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1406 VkImageAspectFlags aspects
,
1407 VkResolveModeFlagBitsKHR resolve_mode
);
1408 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1409 unsigned radv_get_default_max_sample_dist(int log_samples
);
1410 void radv_device_init_msaa(struct radv_device
*device
);
1412 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1413 const struct radv_image_view
*iview
,
1414 VkClearDepthStencilValue ds_clear_value
,
1415 VkImageAspectFlags aspects
);
1417 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1418 const struct radv_image_view
*iview
,
1420 uint32_t color_values
[2]);
1422 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1423 struct radv_image
*image
,
1424 const VkImageSubresourceRange
*range
, bool value
);
1426 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1427 struct radv_image
*image
,
1428 const VkImageSubresourceRange
*range
, bool value
);
1430 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1431 struct radeon_winsys_bo
*bo
,
1432 uint64_t offset
, uint64_t size
, uint32_t value
);
1433 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1434 bool radv_get_memory_fd(struct radv_device
*device
,
1435 struct radv_device_memory
*memory
,
1439 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1440 unsigned sh_offset
, unsigned pointer_count
,
1441 bool use_32bit_pointers
)
1443 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1444 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1448 radv_emit_shader_pointer_body(struct radv_device
*device
,
1449 struct radeon_cmdbuf
*cs
,
1450 uint64_t va
, bool use_32bit_pointers
)
1452 radeon_emit(cs
, va
);
1454 if (use_32bit_pointers
) {
1456 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1458 radeon_emit(cs
, va
>> 32);
1463 radv_emit_shader_pointer(struct radv_device
*device
,
1464 struct radeon_cmdbuf
*cs
,
1465 uint32_t sh_offset
, uint64_t va
, bool global
)
1467 bool use_32bit_pointers
= !global
;
1469 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1470 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1473 static inline struct radv_descriptor_state
*
1474 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1475 VkPipelineBindPoint bind_point
)
1477 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1478 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1479 return &cmd_buffer
->descriptors
[bind_point
];
1483 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1485 * Limitations: Can't call normal dispatch functions without binding or rebinding
1486 * the compute pipeline.
1488 void radv_unaligned_dispatch(
1489 struct radv_cmd_buffer
*cmd_buffer
,
1495 struct radeon_winsys_bo
*bo
;
1499 struct radv_shader_module
;
1501 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1502 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1503 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1504 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1505 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1506 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1507 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1508 #define RADV_HASH_SHADER_ACO (1 << 7)
1511 radv_hash_shaders(unsigned char *hash
,
1512 const VkPipelineShaderStageCreateInfo
**stages
,
1513 const struct radv_pipeline_layout
*layout
,
1514 const struct radv_pipeline_key
*key
,
1517 static inline gl_shader_stage
1518 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1520 assert(__builtin_popcount(vk_stage
) == 1);
1521 return ffs(vk_stage
) - 1;
1524 static inline VkShaderStageFlagBits
1525 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1527 return (1 << mesa_stage
);
1530 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1532 #define radv_foreach_stage(stage, stage_bits) \
1533 for (gl_shader_stage stage, \
1534 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1535 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1536 __tmp &= ~(1 << (stage)))
1538 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1539 unsigned radv_format_meta_fs_key(VkFormat format
);
1541 struct radv_multisample_state
{
1543 uint32_t pa_sc_line_cntl
;
1544 uint32_t pa_sc_mode_cntl_0
;
1545 uint32_t pa_sc_mode_cntl_1
;
1546 uint32_t pa_sc_aa_config
;
1547 uint32_t pa_sc_aa_mask
[2];
1548 unsigned num_samples
;
1551 struct radv_prim_vertex_count
{
1556 struct radv_vertex_elements_info
{
1557 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1560 struct radv_ia_multi_vgt_param_helpers
{
1562 bool partial_es_wave
;
1563 uint8_t primgroup_size
;
1564 bool wd_switch_on_eop
;
1565 bool ia_switch_on_eoi
;
1566 bool partial_vs_wave
;
1569 struct radv_binning_state
{
1570 uint32_t pa_sc_binner_cntl_0
;
1571 uint32_t db_dfsm_control
;
1574 #define SI_GS_PER_ES 128
1576 struct radv_pipeline
{
1577 struct radv_device
* device
;
1578 struct radv_dynamic_state dynamic_state
;
1580 struct radv_pipeline_layout
* layout
;
1582 bool need_indirect_descriptor_sets
;
1583 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1584 struct radv_shader_variant
*gs_copy_shader
;
1585 VkShaderStageFlags active_stages
;
1587 struct radeon_cmdbuf cs
;
1588 uint32_t ctx_cs_hash
;
1589 struct radeon_cmdbuf ctx_cs
;
1591 struct radv_vertex_elements_info vertex_elements
;
1593 uint32_t binding_stride
[MAX_VBS
];
1594 uint8_t num_vertex_bindings
;
1596 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1599 struct radv_multisample_state ms
;
1600 struct radv_binning_state binning
;
1601 uint32_t spi_baryc_cntl
;
1602 bool prim_restart_enable
;
1603 unsigned esgs_ring_size
;
1604 unsigned gsvs_ring_size
;
1605 uint32_t vtx_base_sgpr
;
1606 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1607 uint8_t vtx_emit_num
;
1608 struct radv_prim_vertex_count prim_vertex_count
;
1609 bool can_use_guardband
;
1610 uint32_t needed_dynamic_state
;
1611 bool disable_out_of_order_rast_for_occlusion
;
1613 /* Used for rbplus */
1614 uint32_t col_format
;
1615 uint32_t cb_target_mask
;
1620 unsigned scratch_bytes_per_wave
;
1622 /* Not NULL if graphics pipeline uses streamout. */
1623 struct radv_shader_variant
*streamout_shader
;
1626 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1628 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1631 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1633 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1636 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1638 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1640 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1641 gl_shader_stage stage
,
1644 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1645 gl_shader_stage stage
);
1647 struct radv_graphics_pipeline_create_info
{
1649 bool db_depth_clear
;
1650 bool db_stencil_clear
;
1651 bool db_depth_disable_expclear
;
1652 bool db_stencil_disable_expclear
;
1653 bool db_flush_depth_inplace
;
1654 bool db_flush_stencil_inplace
;
1655 bool db_resummarize
;
1656 uint32_t custom_blend_mode
;
1660 radv_graphics_pipeline_create(VkDevice device
,
1661 VkPipelineCache cache
,
1662 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1663 const struct radv_graphics_pipeline_create_info
*extra
,
1664 const VkAllocationCallbacks
*alloc
,
1665 VkPipeline
*pPipeline
);
1667 struct vk_format_description
;
1668 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1669 int first_non_void
);
1670 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1671 int first_non_void
);
1672 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1673 uint32_t radv_translate_colorformat(VkFormat format
);
1674 uint32_t radv_translate_color_numformat(VkFormat format
,
1675 const struct vk_format_description
*desc
,
1676 int first_non_void
);
1677 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1678 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1679 uint32_t radv_translate_dbformat(VkFormat format
);
1680 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1681 const struct vk_format_description
*desc
,
1682 int first_non_void
);
1683 uint32_t radv_translate_tex_numformat(VkFormat format
,
1684 const struct vk_format_description
*desc
,
1685 int first_non_void
);
1686 bool radv_format_pack_clear_color(VkFormat format
,
1687 uint32_t clear_vals
[2],
1688 VkClearColorValue
*value
);
1689 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1690 bool radv_dcc_formats_compatible(VkFormat format1
,
1692 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1694 struct radv_image_plane
{
1696 struct radeon_surf surface
;
1702 /* The original VkFormat provided by the client. This may not match any
1703 * of the actual surface formats.
1706 VkImageAspectFlags aspects
;
1707 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1708 struct ac_surf_info info
;
1709 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1710 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1715 unsigned queue_family_mask
;
1719 /* Set when bound */
1720 struct radeon_winsys_bo
*bo
;
1721 VkDeviceSize offset
;
1722 uint64_t dcc_offset
;
1723 uint64_t htile_offset
;
1724 bool tc_compatible_htile
;
1725 bool tc_compatible_cmask
;
1727 uint64_t cmask_offset
;
1728 uint64_t fmask_offset
;
1729 uint64_t clear_value_offset
;
1730 uint64_t fce_pred_offset
;
1731 uint64_t dcc_pred_offset
;
1734 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1735 * stored at this offset is UINT_MAX, the driver will emit
1736 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1737 * SET_CONTEXT_REG packet.
1739 uint64_t tc_compat_zrange_offset
;
1741 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1742 VkDeviceMemory owned_memory
;
1744 unsigned plane_count
;
1745 struct radv_image_plane planes
[0];
1748 /* Whether the image has a htile that is known consistent with the contents of
1750 bool radv_layout_has_htile(const struct radv_image
*image
,
1751 VkImageLayout layout
,
1752 bool in_render_loop
,
1753 unsigned queue_mask
);
1755 /* Whether the image has a htile that is known consistent with the contents of
1756 * the image and is allowed to be in compressed form.
1758 * If this is false reads that don't use the htile should be able to return
1761 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1762 VkImageLayout layout
,
1763 bool in_render_loop
,
1764 unsigned queue_mask
);
1766 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1767 VkImageLayout layout
,
1768 bool in_render_loop
,
1769 unsigned queue_mask
);
1771 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1772 const struct radv_image
*image
,
1773 VkImageLayout layout
,
1774 bool in_render_loop
,
1775 unsigned queue_mask
);
1778 * Return whether the image has CMASK metadata for color surfaces.
1781 radv_image_has_cmask(const struct radv_image
*image
)
1783 return image
->cmask_offset
;
1787 * Return whether the image has FMASK metadata for color surfaces.
1790 radv_image_has_fmask(const struct radv_image
*image
)
1792 return image
->fmask_offset
;
1796 * Return whether the image has DCC metadata for color surfaces.
1799 radv_image_has_dcc(const struct radv_image
*image
)
1801 return image
->planes
[0].surface
.dcc_size
;
1805 * Return whether the image is TC-compatible CMASK.
1808 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1810 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1814 * Return whether DCC metadata is enabled for a level.
1817 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1819 return radv_image_has_dcc(image
) &&
1820 level
< image
->planes
[0].surface
.num_dcc_levels
;
1824 * Return whether the image has CB metadata.
1827 radv_image_has_CB_metadata(const struct radv_image
*image
)
1829 return radv_image_has_cmask(image
) ||
1830 radv_image_has_fmask(image
) ||
1831 radv_image_has_dcc(image
);
1835 * Return whether the image has HTILE metadata for depth surfaces.
1838 radv_image_has_htile(const struct radv_image
*image
)
1840 return image
->planes
[0].surface
.htile_size
;
1844 * Return whether HTILE metadata is enabled for a level.
1847 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1849 return radv_image_has_htile(image
) && level
== 0;
1853 * Return whether the image is TC-compatible HTILE.
1856 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1858 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1861 static inline uint64_t
1862 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1863 uint32_t base_level
)
1865 uint64_t va
= radv_buffer_get_va(image
->bo
);
1866 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1870 static inline uint64_t
1871 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1872 uint32_t base_level
)
1874 uint64_t va
= radv_buffer_get_va(image
->bo
);
1875 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1879 static inline uint64_t
1880 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1881 uint32_t base_level
)
1883 uint64_t va
= radv_buffer_get_va(image
->bo
);
1884 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1888 static inline uint64_t
1889 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1890 uint32_t base_level
)
1892 uint64_t va
= radv_buffer_get_va(image
->bo
);
1893 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1897 static inline uint64_t
1898 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1899 uint32_t base_level
)
1901 uint64_t va
= radv_buffer_get_va(image
->bo
);
1902 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1906 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1908 static inline uint32_t
1909 radv_get_layerCount(const struct radv_image
*image
,
1910 const VkImageSubresourceRange
*range
)
1912 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1913 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1916 static inline uint32_t
1917 radv_get_levelCount(const struct radv_image
*image
,
1918 const VkImageSubresourceRange
*range
)
1920 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1921 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1924 struct radeon_bo_metadata
;
1926 radv_init_metadata(struct radv_device
*device
,
1927 struct radv_image
*image
,
1928 struct radeon_bo_metadata
*metadata
);
1931 radv_image_override_offset_stride(struct radv_device
*device
,
1932 struct radv_image
*image
,
1933 uint64_t offset
, uint32_t stride
);
1935 union radv_descriptor
{
1937 uint32_t plane0_descriptor
[8];
1938 uint32_t fmask_descriptor
[8];
1941 uint32_t plane_descriptors
[3][8];
1945 struct radv_image_view
{
1946 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1947 struct radeon_winsys_bo
*bo
;
1949 VkImageViewType type
;
1950 VkImageAspectFlags aspect_mask
;
1953 bool multiple_planes
;
1954 uint32_t base_layer
;
1955 uint32_t layer_count
;
1957 uint32_t level_count
;
1958 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1960 union radv_descriptor descriptor
;
1962 /* Descriptor for use as a storage image as opposed to a sampled image.
1963 * This has a few differences for cube maps (e.g. type).
1965 union radv_descriptor storage_descriptor
;
1968 struct radv_image_create_info
{
1969 const VkImageCreateInfo
*vk_info
;
1971 bool no_metadata_planes
;
1972 const struct radeon_bo_metadata
*bo_metadata
;
1976 radv_image_create_layout(struct radv_device
*device
,
1977 struct radv_image_create_info create_info
,
1978 struct radv_image
*image
);
1980 VkResult
radv_image_create(VkDevice _device
,
1981 const struct radv_image_create_info
*info
,
1982 const VkAllocationCallbacks
* alloc
,
1985 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
1988 radv_image_from_gralloc(VkDevice device_h
,
1989 const VkImageCreateInfo
*base_info
,
1990 const VkNativeBufferANDROID
*gralloc_info
,
1991 const VkAllocationCallbacks
*alloc
,
1992 VkImage
*out_image_h
);
1994 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
1995 const VkImageUsageFlags vk_usage
);
1997 radv_import_ahb_memory(struct radv_device
*device
,
1998 struct radv_device_memory
*mem
,
2000 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
2002 radv_create_ahb_memory(struct radv_device
*device
,
2003 struct radv_device_memory
*mem
,
2005 const VkMemoryAllocateInfo
*pAllocateInfo
);
2008 radv_select_android_external_format(const void *next
, VkFormat default_format
);
2010 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
2012 struct radv_image_view_extra_create_info
{
2013 bool disable_compression
;
2016 void radv_image_view_init(struct radv_image_view
*view
,
2017 struct radv_device
*device
,
2018 const VkImageViewCreateInfo
*pCreateInfo
,
2019 const struct radv_image_view_extra_create_info
* extra_create_info
);
2021 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
2023 struct radv_sampler_ycbcr_conversion
{
2025 VkSamplerYcbcrModelConversion ycbcr_model
;
2026 VkSamplerYcbcrRange ycbcr_range
;
2027 VkComponentMapping components
;
2028 VkChromaLocation chroma_offsets
[2];
2029 VkFilter chroma_filter
;
2032 struct radv_buffer_view
{
2033 struct radeon_winsys_bo
*bo
;
2035 uint64_t range
; /**< VkBufferViewCreateInfo::range */
2038 void radv_buffer_view_init(struct radv_buffer_view
*view
,
2039 struct radv_device
*device
,
2040 const VkBufferViewCreateInfo
* pCreateInfo
);
2042 static inline struct VkExtent3D
2043 radv_sanitize_image_extent(const VkImageType imageType
,
2044 const struct VkExtent3D imageExtent
)
2046 switch (imageType
) {
2047 case VK_IMAGE_TYPE_1D
:
2048 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
2049 case VK_IMAGE_TYPE_2D
:
2050 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
2051 case VK_IMAGE_TYPE_3D
:
2054 unreachable("invalid image type");
2058 static inline struct VkOffset3D
2059 radv_sanitize_image_offset(const VkImageType imageType
,
2060 const struct VkOffset3D imageOffset
)
2062 switch (imageType
) {
2063 case VK_IMAGE_TYPE_1D
:
2064 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2065 case VK_IMAGE_TYPE_2D
:
2066 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2067 case VK_IMAGE_TYPE_3D
:
2070 unreachable("invalid image type");
2075 radv_image_extent_compare(const struct radv_image
*image
,
2076 const VkExtent3D
*extent
)
2078 if (extent
->width
!= image
->info
.width
||
2079 extent
->height
!= image
->info
.height
||
2080 extent
->depth
!= image
->info
.depth
)
2085 struct radv_sampler
{
2087 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2090 struct radv_framebuffer
{
2095 uint32_t attachment_count
;
2096 struct radv_image_view
*attachments
[0];
2099 struct radv_subpass_barrier
{
2100 VkPipelineStageFlags src_stage_mask
;
2101 VkAccessFlags src_access_mask
;
2102 VkAccessFlags dst_access_mask
;
2105 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2106 const struct radv_subpass_barrier
*barrier
);
2108 struct radv_subpass_attachment
{
2109 uint32_t attachment
;
2110 VkImageLayout layout
;
2111 bool in_render_loop
;
2114 struct radv_subpass
{
2115 uint32_t attachment_count
;
2116 struct radv_subpass_attachment
* attachments
;
2118 uint32_t input_count
;
2119 uint32_t color_count
;
2120 struct radv_subpass_attachment
* input_attachments
;
2121 struct radv_subpass_attachment
* color_attachments
;
2122 struct radv_subpass_attachment
* resolve_attachments
;
2123 struct radv_subpass_attachment
* depth_stencil_attachment
;
2124 struct radv_subpass_attachment
* ds_resolve_attachment
;
2125 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2126 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2128 /** Subpass has at least one color resolve attachment */
2129 bool has_color_resolve
;
2131 /** Subpass has at least one color attachment */
2134 struct radv_subpass_barrier start_barrier
;
2137 VkSampleCountFlagBits max_sample_count
;
2141 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2143 struct radv_render_pass_attachment
{
2146 VkAttachmentLoadOp load_op
;
2147 VkAttachmentLoadOp stencil_load_op
;
2148 VkImageLayout initial_layout
;
2149 VkImageLayout final_layout
;
2151 /* The subpass id in which the attachment will be used first/last. */
2152 uint32_t first_subpass_idx
;
2153 uint32_t last_subpass_idx
;
2156 struct radv_render_pass
{
2157 uint32_t attachment_count
;
2158 uint32_t subpass_count
;
2159 struct radv_subpass_attachment
* subpass_attachments
;
2160 struct radv_render_pass_attachment
* attachments
;
2161 struct radv_subpass_barrier end_barrier
;
2162 struct radv_subpass subpasses
[0];
2165 VkResult
radv_device_init_meta(struct radv_device
*device
);
2166 void radv_device_finish_meta(struct radv_device
*device
);
2168 struct radv_query_pool
{
2169 struct radeon_winsys_bo
*bo
;
2171 uint32_t availability_offset
;
2175 uint32_t pipeline_stats_mask
;
2179 RADV_SEMAPHORE_NONE
,
2180 RADV_SEMAPHORE_WINSYS
,
2181 RADV_SEMAPHORE_SYNCOBJ
,
2182 RADV_SEMAPHORE_TIMELINE
,
2183 } radv_semaphore_kind
;
2185 struct radv_deferred_queue_submission
;
2187 struct radv_timeline_waiter
{
2188 struct list_head list
;
2189 struct radv_deferred_queue_submission
*submission
;
2193 struct radv_timeline_point
{
2194 struct list_head list
;
2199 /* Separate from the list to accomodate CPU wait being async, as well
2200 * as prevent point deletion during submission. */
2201 unsigned wait_count
;
2204 struct radv_timeline
{
2205 /* Using a pthread mutex to be compatible with condition variables. */
2206 pthread_mutex_t mutex
;
2208 uint64_t highest_signaled
;
2209 uint64_t highest_submitted
;
2211 struct list_head points
;
2213 /* Keep free points on hand so we do not have to recreate syncobjs all
2215 struct list_head free_points
;
2217 /* Submissions that are deferred waiting for a specific value to be
2219 struct list_head waiters
;
2222 struct radv_semaphore_part
{
2223 radv_semaphore_kind kind
;
2226 struct radeon_winsys_sem
*ws_sem
;
2227 struct radv_timeline timeline
;
2231 struct radv_semaphore
{
2232 struct radv_semaphore_part permanent
;
2233 struct radv_semaphore_part temporary
;
2236 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2237 VkPipelineBindPoint bind_point
,
2238 struct radv_descriptor_set
*set
,
2242 radv_update_descriptor_sets(struct radv_device
*device
,
2243 struct radv_cmd_buffer
*cmd_buffer
,
2244 VkDescriptorSet overrideSet
,
2245 uint32_t descriptorWriteCount
,
2246 const VkWriteDescriptorSet
*pDescriptorWrites
,
2247 uint32_t descriptorCopyCount
,
2248 const VkCopyDescriptorSet
*pDescriptorCopies
);
2251 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2252 struct radv_cmd_buffer
*cmd_buffer
,
2253 struct radv_descriptor_set
*set
,
2254 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2257 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2258 VkPipelineBindPoint pipelineBindPoint
,
2259 VkPipelineLayout _layout
,
2261 uint32_t descriptorWriteCount
,
2262 const VkWriteDescriptorSet
*pDescriptorWrites
);
2264 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2265 struct radv_image
*image
,
2266 const VkImageSubresourceRange
*range
, uint32_t value
);
2268 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2269 struct radv_image
*image
,
2270 const VkImageSubresourceRange
*range
);
2273 struct radeon_winsys_fence
*fence
;
2274 struct wsi_fence
*fence_wsi
;
2277 uint32_t temp_syncobj
;
2280 /* radv_nir_to_llvm.c */
2281 struct radv_shader_info
;
2282 struct radv_nir_compiler_options
;
2284 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2285 struct nir_shader
*geom_shader
,
2286 struct radv_shader_binary
**rbinary
,
2287 struct radv_shader_info
*info
,
2288 const struct radv_nir_compiler_options
*option
);
2290 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2291 struct radv_shader_binary
**rbinary
,
2292 struct radv_shader_info
*info
,
2293 struct nir_shader
*const *nir
,
2295 const struct radv_nir_compiler_options
*options
);
2297 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2298 gl_shader_stage stage
,
2299 const struct nir_shader
*nir
);
2301 /* radv_shader_info.h */
2302 struct radv_shader_info
;
2303 struct radv_shader_variant_key
;
2305 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2306 const struct radv_pipeline_layout
*layout
,
2307 const struct radv_shader_variant_key
*key
,
2308 struct radv_shader_info
*info
);
2310 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2312 struct radeon_winsys_sem
;
2314 uint64_t radv_get_current_time(void);
2316 static inline uint32_t
2317 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2320 case 0: /* GL_POINTS */
2322 case 1: /* GL_LINES */
2323 case 3: /* GL_LINE_STRIP */
2325 case 4: /* GL_TRIANGLES */
2326 case 5: /* GL_TRIANGLE_STRIP */
2328 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2330 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2332 case 7: /* GL_QUADS */
2333 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2340 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2342 static inline struct __radv_type * \
2343 __radv_type ## _from_handle(__VkType _handle) \
2345 return (struct __radv_type *) _handle; \
2348 static inline __VkType \
2349 __radv_type ## _to_handle(struct __radv_type *_obj) \
2351 return (__VkType) _obj; \
2354 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2356 static inline struct __radv_type * \
2357 __radv_type ## _from_handle(__VkType _handle) \
2359 return (struct __radv_type *)(uintptr_t) _handle; \
2362 static inline __VkType \
2363 __radv_type ## _to_handle(struct __radv_type *_obj) \
2365 return (__VkType)(uintptr_t) _obj; \
2368 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2369 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2371 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2372 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2373 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2374 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2375 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2377 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2378 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2379 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2380 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2381 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2382 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2383 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2384 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2385 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2386 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2387 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2388 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2389 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2390 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2391 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2392 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2393 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2394 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2395 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2396 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2397 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2398 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2400 #endif /* RADV_PRIVATE_H */