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radv: Add thread for timeline syncobj submission.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
198
199 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
200 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
201
202 void __radv_finishme(const char *file, int line, const char *format, ...)
203 radv_printflike(3, 4);
204 void radv_loge(const char *format, ...) radv_printflike(1, 2);
205 void radv_loge_v(const char *format, va_list va);
206 void radv_logi(const char *format, ...) radv_printflike(1, 2);
207 void radv_logi_v(const char *format, va_list va);
208
209 /**
210 * Print a FINISHME message, including its source location.
211 */
212 #define radv_finishme(format, ...) \
213 do { \
214 static bool reported = false; \
215 if (!reported) { \
216 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
217 reported = true; \
218 } \
219 } while (0)
220
221 /* A non-fatal assert. Useful for debugging. */
222 #ifdef DEBUG
223 #define radv_assert(x) ({ \
224 if (unlikely(!(x))) \
225 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
226 })
227 #else
228 #define radv_assert(x) do {} while(0)
229 #endif
230
231 #define stub_return(v) \
232 do { \
233 radv_finishme("stub %s", __func__); \
234 return (v); \
235 } while (0)
236
237 #define stub() \
238 do { \
239 radv_finishme("stub %s", __func__); \
240 return; \
241 } while (0)
242
243 int radv_get_instance_entrypoint_index(const char *name);
244 int radv_get_device_entrypoint_index(const char *name);
245 int radv_get_physical_device_entrypoint_index(const char *name);
246
247 const char *radv_get_instance_entry_name(int index);
248 const char *radv_get_physical_device_entry_name(int index);
249 const char *radv_get_device_entry_name(int index);
250
251 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
252 const struct radv_instance_extension_table *instance);
253 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
254 const struct radv_instance_extension_table *instance);
255 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
256 const struct radv_instance_extension_table *instance,
257 const struct radv_device_extension_table *device);
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 /* Link in radv_instance::physical_devices */
265 struct list_head link;
266
267 struct radv_instance * instance;
268
269 struct radeon_winsys *ws;
270 struct radeon_info rad_info;
271 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
272 uint8_t driver_uuid[VK_UUID_SIZE];
273 uint8_t device_uuid[VK_UUID_SIZE];
274 uint8_t cache_uuid[VK_UUID_SIZE];
275
276 int local_fd;
277 int master_fd;
278 struct wsi_device wsi_device;
279
280 bool out_of_order_rast_allowed;
281
282 /* Whether DCC should be enabled for MSAA textures. */
283 bool dcc_msaa_allowed;
284
285 /* Whether to enable NGG. */
286 bool use_ngg;
287
288 /* Whether to enable NGG GS. */
289 bool use_ngg_gs;
290
291 /* Whether to enable NGG streamout. */
292 bool use_ngg_streamout;
293
294 /* Number of threads per wave. */
295 uint8_t ps_wave_size;
296 uint8_t cs_wave_size;
297 uint8_t ge_wave_size;
298
299 /* Whether to use the LLVM compiler backend */
300 bool use_llvm;
301
302 /* This is the drivers on-disk cache used as a fallback as opposed to
303 * the pipeline cache defined by apps.
304 */
305 struct disk_cache * disk_cache;
306
307 VkPhysicalDeviceMemoryProperties memory_properties;
308 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
309 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
310
311 drmPciBusInfo bus_info;
312
313 struct radv_device_extension_table supported_extensions;
314 };
315
316 struct radv_instance {
317 struct vk_object_base base;
318
319 VkAllocationCallbacks alloc;
320
321 uint32_t apiVersion;
322
323 char * engineName;
324 uint32_t engineVersion;
325
326 uint64_t debug_flags;
327 uint64_t perftest_flags;
328
329 struct vk_debug_report_instance debug_report_callbacks;
330
331 struct radv_instance_extension_table enabled_extensions;
332 struct radv_instance_dispatch_table dispatch;
333 struct radv_physical_device_dispatch_table physical_device_dispatch;
334 struct radv_device_dispatch_table device_dispatch;
335
336 bool physical_devices_enumerated;
337 struct list_head physical_devices;
338
339 struct driOptionCache dri_options;
340 struct driOptionCache available_dri_options;
341
342 /**
343 * Workarounds for game bugs.
344 */
345 bool enable_mrt_output_nan_fixup;
346 };
347
348 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
349 void radv_finish_wsi(struct radv_physical_device *physical_device);
350
351 bool radv_instance_extension_supported(const char *name);
352 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
353 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
354 const char *name);
355
356 struct cache_entry;
357
358 struct radv_pipeline_cache {
359 struct vk_object_base base;
360 struct radv_device * device;
361 pthread_mutex_t mutex;
362 VkPipelineCacheCreateFlags flags;
363
364 uint32_t total_size;
365 uint32_t table_size;
366 uint32_t kernel_count;
367 struct cache_entry ** hash_table;
368 bool modified;
369
370 VkAllocationCallbacks alloc;
371 };
372
373 struct radv_pipeline_key {
374 uint32_t instance_rate_inputs;
375 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
376 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
377 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
378 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
379 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
380 uint64_t vertex_alpha_adjust;
381 uint32_t vertex_post_shuffle;
382 unsigned tess_input_vertices;
383 uint32_t col_format;
384 uint32_t is_int8;
385 uint32_t is_int10;
386 uint8_t log2_ps_iter_samples;
387 uint8_t num_samples;
388 bool is_dual_src;
389 uint32_t has_multiview_view_index : 1;
390 uint32_t optimisations_disabled : 1;
391 uint8_t topology;
392
393 /* Non-zero if a required subgroup size is specified via
394 * VK_EXT_subgroup_size_control.
395 */
396 uint8_t compute_subgroup_size;
397 };
398
399 struct radv_shader_binary;
400 struct radv_shader_variant;
401
402 void
403 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
404 struct radv_device *device);
405 void
406 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
407 bool
408 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
409 const void *data, size_t size);
410
411 bool
412 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
413 struct radv_pipeline_cache *cache,
414 const unsigned char *sha1,
415 struct radv_shader_variant **variants,
416 bool *found_in_application_cache);
417
418 void
419 radv_pipeline_cache_insert_shaders(struct radv_device *device,
420 struct radv_pipeline_cache *cache,
421 const unsigned char *sha1,
422 struct radv_shader_variant **variants,
423 struct radv_shader_binary *const *binaries);
424
425 enum radv_blit_ds_layout {
426 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
427 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
428 RADV_BLIT_DS_LAYOUT_COUNT,
429 };
430
431 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
432 {
433 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
434 }
435
436 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
437 {
438 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
439 }
440
441 enum radv_meta_dst_layout {
442 RADV_META_DST_LAYOUT_GENERAL,
443 RADV_META_DST_LAYOUT_OPTIMAL,
444 RADV_META_DST_LAYOUT_COUNT,
445 };
446
447 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
448 {
449 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
450 }
451
452 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
453 {
454 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
455 }
456
457 struct radv_meta_state {
458 VkAllocationCallbacks alloc;
459
460 struct radv_pipeline_cache cache;
461
462 /*
463 * For on-demand pipeline creation, makes sure that
464 * only one thread tries to build a pipeline at the same time.
465 */
466 mtx_t mtx;
467
468 /**
469 * Use array element `i` for images with `2^i` samples.
470 */
471 struct {
472 VkRenderPass render_pass[NUM_META_FS_KEYS];
473 VkPipeline color_pipelines[NUM_META_FS_KEYS];
474
475 VkRenderPass depthstencil_rp;
476 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
477 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
478 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
479
480 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
481 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
482 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
483 } clear[MAX_SAMPLES_LOG2];
484
485 VkPipelineLayout clear_color_p_layout;
486 VkPipelineLayout clear_depth_p_layout;
487 VkPipelineLayout clear_depth_unrestricted_p_layout;
488
489 /* Optimized compute fast HTILE clear for stencil or depth only. */
490 VkPipeline clear_htile_mask_pipeline;
491 VkPipelineLayout clear_htile_mask_p_layout;
492 VkDescriptorSetLayout clear_htile_mask_ds_layout;
493
494 struct {
495 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496
497 /** Pipeline that blits from a 1D image. */
498 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
499
500 /** Pipeline that blits from a 2D image. */
501 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
502
503 /** Pipeline that blits from a 3D image. */
504 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
505
506 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
507 VkPipeline depth_only_1d_pipeline;
508 VkPipeline depth_only_2d_pipeline;
509 VkPipeline depth_only_3d_pipeline;
510
511 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
512 VkPipeline stencil_only_1d_pipeline;
513 VkPipeline stencil_only_2d_pipeline;
514 VkPipeline stencil_only_3d_pipeline;
515 VkPipelineLayout pipeline_layout;
516 VkDescriptorSetLayout ds_layout;
517 } blit;
518
519 struct {
520 VkPipelineLayout p_layouts[5];
521 VkDescriptorSetLayout ds_layouts[5];
522 VkPipeline pipelines[5][NUM_META_FS_KEYS];
523
524 VkPipeline depth_only_pipeline[5];
525
526 VkPipeline stencil_only_pipeline[5];
527 } blit2d[MAX_SAMPLES_LOG2];
528
529 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
530 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
531 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
532
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 VkPipeline pipeline_3d;
538 } itob;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 VkPipeline pipeline_3d;
544 } btoi;
545 struct {
546 VkPipelineLayout img_p_layout;
547 VkDescriptorSetLayout img_ds_layout;
548 VkPipeline pipeline;
549 } btoi_r32g32b32;
550 struct {
551 VkPipelineLayout img_p_layout;
552 VkDescriptorSetLayout img_ds_layout;
553 VkPipeline pipeline;
554 VkPipeline pipeline_3d;
555 } itoi;
556 struct {
557 VkPipelineLayout img_p_layout;
558 VkDescriptorSetLayout img_ds_layout;
559 VkPipeline pipeline;
560 } itoi_r32g32b32;
561 struct {
562 VkPipelineLayout img_p_layout;
563 VkDescriptorSetLayout img_ds_layout;
564 VkPipeline pipeline;
565 VkPipeline pipeline_3d;
566 } cleari;
567 struct {
568 VkPipelineLayout img_p_layout;
569 VkDescriptorSetLayout img_ds_layout;
570 VkPipeline pipeline;
571 } cleari_r32g32b32;
572
573 struct {
574 VkPipelineLayout p_layout;
575 VkPipeline pipeline[NUM_META_FS_KEYS];
576 VkRenderPass pass[NUM_META_FS_KEYS];
577 } resolve;
578
579 struct {
580 VkDescriptorSetLayout ds_layout;
581 VkPipelineLayout p_layout;
582 struct {
583 VkPipeline pipeline;
584 VkPipeline i_pipeline;
585 VkPipeline srgb_pipeline;
586 } rc[MAX_SAMPLES_LOG2];
587
588 VkPipeline depth_zero_pipeline;
589 struct {
590 VkPipeline average_pipeline;
591 VkPipeline max_pipeline;
592 VkPipeline min_pipeline;
593 } depth[MAX_SAMPLES_LOG2];
594
595 VkPipeline stencil_zero_pipeline;
596 struct {
597 VkPipeline max_pipeline;
598 VkPipeline min_pipeline;
599 } stencil[MAX_SAMPLES_LOG2];
600 } resolve_compute;
601
602 struct {
603 VkDescriptorSetLayout ds_layout;
604 VkPipelineLayout p_layout;
605
606 struct {
607 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
608 VkPipeline pipeline[NUM_META_FS_KEYS];
609 } rc[MAX_SAMPLES_LOG2];
610
611 VkRenderPass depth_render_pass;
612 VkPipeline depth_zero_pipeline;
613 struct {
614 VkPipeline average_pipeline;
615 VkPipeline max_pipeline;
616 VkPipeline min_pipeline;
617 } depth[MAX_SAMPLES_LOG2];
618
619 VkRenderPass stencil_render_pass;
620 VkPipeline stencil_zero_pipeline;
621 struct {
622 VkPipeline max_pipeline;
623 VkPipeline min_pipeline;
624 } stencil[MAX_SAMPLES_LOG2];
625 } resolve_fragment;
626
627 struct {
628 VkPipelineLayout p_layout;
629 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
630 VkPipeline resummarize_pipeline;
631 VkRenderPass pass;
632 } depth_decomp[MAX_SAMPLES_LOG2];
633
634 struct {
635 VkPipelineLayout p_layout;
636 VkPipeline cmask_eliminate_pipeline;
637 VkPipeline fmask_decompress_pipeline;
638 VkPipeline dcc_decompress_pipeline;
639 VkRenderPass pass;
640
641 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
642 VkPipelineLayout dcc_decompress_compute_p_layout;
643 VkPipeline dcc_decompress_compute_pipeline;
644 } fast_clear_flush;
645
646 struct {
647 VkPipelineLayout fill_p_layout;
648 VkPipelineLayout copy_p_layout;
649 VkDescriptorSetLayout fill_ds_layout;
650 VkDescriptorSetLayout copy_ds_layout;
651 VkPipeline fill_pipeline;
652 VkPipeline copy_pipeline;
653 } buffer;
654
655 struct {
656 VkDescriptorSetLayout ds_layout;
657 VkPipelineLayout p_layout;
658 VkPipeline occlusion_query_pipeline;
659 VkPipeline pipeline_statistics_query_pipeline;
660 VkPipeline tfb_query_pipeline;
661 VkPipeline timestamp_query_pipeline;
662 } query;
663
664 struct {
665 VkDescriptorSetLayout ds_layout;
666 VkPipelineLayout p_layout;
667 VkPipeline pipeline[MAX_SAMPLES_LOG2];
668 } fmask_expand;
669 };
670
671 /* queue types */
672 #define RADV_QUEUE_GENERAL 0
673 #define RADV_QUEUE_COMPUTE 1
674 #define RADV_QUEUE_TRANSFER 2
675
676 #define RADV_MAX_QUEUE_FAMILIES 3
677
678 struct radv_deferred_queue_submission;
679
680 enum ring_type radv_queue_family_to_ring(int f);
681
682 struct radv_queue {
683 VK_LOADER_DATA _loader_data;
684 struct radv_device * device;
685 struct radeon_winsys_ctx *hw_ctx;
686 enum radeon_ctx_priority priority;
687 uint32_t queue_family_index;
688 int queue_idx;
689 VkDeviceQueueCreateFlags flags;
690
691 uint32_t scratch_size_per_wave;
692 uint32_t scratch_waves;
693 uint32_t compute_scratch_size_per_wave;
694 uint32_t compute_scratch_waves;
695 uint32_t esgs_ring_size;
696 uint32_t gsvs_ring_size;
697 bool has_tess_rings;
698 bool has_gds;
699 bool has_gds_oa;
700 bool has_sample_positions;
701
702 struct radeon_winsys_bo *scratch_bo;
703 struct radeon_winsys_bo *descriptor_bo;
704 struct radeon_winsys_bo *compute_scratch_bo;
705 struct radeon_winsys_bo *esgs_ring_bo;
706 struct radeon_winsys_bo *gsvs_ring_bo;
707 struct radeon_winsys_bo *tess_rings_bo;
708 struct radeon_winsys_bo *gds_bo;
709 struct radeon_winsys_bo *gds_oa_bo;
710 struct radeon_cmdbuf *initial_preamble_cs;
711 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
712 struct radeon_cmdbuf *continue_preamble_cs;
713
714 struct list_head pending_submissions;
715 pthread_mutex_t pending_mutex;
716
717 pthread_mutex_t thread_mutex;
718 pthread_cond_t thread_cond;
719 struct radv_deferred_queue_submission *thread_submission;
720 pthread_t submission_thread;
721 bool thread_exit;
722 bool thread_running;
723 };
724
725 struct radv_bo_list {
726 struct radv_winsys_bo_list list;
727 unsigned capacity;
728 pthread_mutex_t mutex;
729 };
730
731 VkResult radv_bo_list_add(struct radv_device *device,
732 struct radeon_winsys_bo *bo);
733 void radv_bo_list_remove(struct radv_device *device,
734 struct radeon_winsys_bo *bo);
735
736 #define RADV_BORDER_COLOR_COUNT 4096
737 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
738
739 struct radv_device_border_color_data {
740 bool used[RADV_BORDER_COLOR_COUNT];
741
742 struct radeon_winsys_bo *bo;
743 VkClearColorValue *colors_gpu_ptr;
744
745 /* Mutex is required to guarantee vkCreateSampler thread safety
746 * given that we are writing to a buffer and checking color occupation */
747 pthread_mutex_t mutex;
748 };
749
750 struct radv_device {
751 struct vk_device vk;
752
753 struct radv_instance * instance;
754 struct radeon_winsys *ws;
755
756 struct radv_meta_state meta_state;
757
758 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
759 int queue_count[RADV_MAX_QUEUE_FAMILIES];
760 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
761
762 bool always_use_syncobj;
763 bool pbb_allowed;
764 bool dfsm_allowed;
765 uint32_t tess_offchip_block_dw_size;
766 uint32_t scratch_waves;
767 uint32_t dispatch_initiator;
768
769 uint32_t gs_table_depth;
770
771 /* MSAA sample locations.
772 * The first index is the sample index.
773 * The second index is the coordinate: X, Y. */
774 float sample_locations_1x[1][2];
775 float sample_locations_2x[2][2];
776 float sample_locations_4x[4][2];
777 float sample_locations_8x[8][2];
778
779 /* GFX7 and later */
780 uint32_t gfx_init_size_dw;
781 struct radeon_winsys_bo *gfx_init;
782
783 struct radeon_winsys_bo *trace_bo;
784 uint32_t *trace_id_ptr;
785
786 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
787 bool keep_shader_info;
788
789 struct radv_physical_device *physical_device;
790
791 /* Backup in-memory cache to be used if the app doesn't provide one */
792 struct radv_pipeline_cache * mem_cache;
793
794 /*
795 * use different counters so MSAA MRTs get consecutive surface indices,
796 * even if MASK is allocated in between.
797 */
798 uint32_t image_mrt_offset_counter;
799 uint32_t fmask_mrt_offset_counter;
800 struct list_head shader_slabs;
801 mtx_t shader_slab_mutex;
802
803 /* For detecting VM faults reported by dmesg. */
804 uint64_t dmesg_timestamp;
805
806 struct radv_device_extension_table enabled_extensions;
807 struct radv_device_dispatch_table dispatch;
808
809 /* Whether the app has enabled the robustBufferAccess feature. */
810 bool robust_buffer_access;
811
812 /* Whether the driver uses a global BO list. */
813 bool use_global_bo_list;
814
815 struct radv_bo_list bo_list;
816
817 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
818 int force_aniso;
819
820 struct radv_device_border_color_data border_color_data;
821
822 /* Condition variable for legacy timelines, to notify waiters when a
823 * new point gets submitted. */
824 pthread_cond_t timeline_cond;
825
826 /* Thread trace. */
827 struct radeon_cmdbuf *thread_trace_start_cs[2];
828 struct radeon_cmdbuf *thread_trace_stop_cs[2];
829 struct radeon_winsys_bo *thread_trace_bo;
830 void *thread_trace_ptr;
831 uint32_t thread_trace_buffer_size;
832 int thread_trace_start_frame;
833
834 /* Overallocation. */
835 bool overallocation_disallowed;
836 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
837 mtx_t overallocation_mutex;
838 };
839
840 struct radv_device_memory {
841 struct vk_object_base base;
842 struct radeon_winsys_bo *bo;
843 /* for dedicated allocations */
844 struct radv_image *image;
845 struct radv_buffer *buffer;
846 uint32_t heap_index;
847 uint64_t alloc_size;
848 void * map;
849 void * user_ptr;
850
851 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
852 struct AHardwareBuffer * android_hardware_buffer;
853 #endif
854 };
855
856
857 struct radv_descriptor_range {
858 uint64_t va;
859 uint32_t size;
860 };
861
862 struct radv_descriptor_set {
863 struct vk_object_base base;
864 const struct radv_descriptor_set_layout *layout;
865 uint32_t size;
866 uint32_t buffer_count;
867
868 struct radeon_winsys_bo *bo;
869 uint64_t va;
870 uint32_t *mapped_ptr;
871 struct radv_descriptor_range *dynamic_descriptors;
872
873 struct radeon_winsys_bo *descriptors[0];
874 };
875
876 struct radv_push_descriptor_set
877 {
878 struct radv_descriptor_set set;
879 uint32_t capacity;
880 };
881
882 struct radv_descriptor_pool_entry {
883 uint32_t offset;
884 uint32_t size;
885 struct radv_descriptor_set *set;
886 };
887
888 struct radv_descriptor_pool {
889 struct vk_object_base base;
890 struct radeon_winsys_bo *bo;
891 uint8_t *mapped_ptr;
892 uint64_t current_offset;
893 uint64_t size;
894
895 uint8_t *host_memory_base;
896 uint8_t *host_memory_ptr;
897 uint8_t *host_memory_end;
898
899 uint32_t entry_count;
900 uint32_t max_entry_count;
901 struct radv_descriptor_pool_entry entries[0];
902 };
903
904 struct radv_descriptor_update_template_entry {
905 VkDescriptorType descriptor_type;
906
907 /* The number of descriptors to update */
908 uint32_t descriptor_count;
909
910 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
911 uint32_t dst_offset;
912
913 /* In dwords. Not valid/used for dynamic descriptors */
914 uint32_t dst_stride;
915
916 uint32_t buffer_offset;
917
918 /* Only valid for combined image samplers and samplers */
919 uint8_t has_sampler;
920 uint8_t sampler_offset;
921
922 /* In bytes */
923 size_t src_offset;
924 size_t src_stride;
925
926 /* For push descriptors */
927 const uint32_t *immutable_samplers;
928 };
929
930 struct radv_descriptor_update_template {
931 struct vk_object_base base;
932 uint32_t entry_count;
933 VkPipelineBindPoint bind_point;
934 struct radv_descriptor_update_template_entry entry[0];
935 };
936
937 struct radv_buffer {
938 struct vk_object_base base;
939 VkDeviceSize size;
940
941 VkBufferUsageFlags usage;
942 VkBufferCreateFlags flags;
943
944 /* Set when bound */
945 struct radeon_winsys_bo * bo;
946 VkDeviceSize offset;
947
948 bool shareable;
949 };
950
951 enum radv_dynamic_state_bits {
952 RADV_DYNAMIC_VIEWPORT = 1 << 0,
953 RADV_DYNAMIC_SCISSOR = 1 << 1,
954 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
955 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
956 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
957 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
958 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
959 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
960 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
961 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
962 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
963 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
964 RADV_DYNAMIC_CULL_MODE = 1 << 12,
965 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
966 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
967 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
968 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
969 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
970 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
971 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
972 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
973 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
974 RADV_DYNAMIC_ALL = (1 << 22) - 1,
975 };
976
977 enum radv_cmd_dirty_bits {
978 /* Keep the dynamic state dirty bits in sync with
979 * enum radv_dynamic_state_bits */
980 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
981 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
982 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
983 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
984 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
985 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
986 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
987 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
988 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
989 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
990 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
991 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
992 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
993 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
994 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
995 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
996 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
997 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
998 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
999 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
1000 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
1001 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
1002 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
1003 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
1004 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
1005 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
1006 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
1007 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
1008 };
1009
1010 enum radv_cmd_flush_bits {
1011 /* Instruction cache. */
1012 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1013 /* Scalar L1 cache. */
1014 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1015 /* Vector L1 cache. */
1016 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1017 /* L2 cache + L2 metadata cache writeback & invalidate.
1018 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1019 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1020 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1021 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1022 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1023 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1024 /* Framebuffer caches */
1025 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1026 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1027 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1028 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1029 /* Engine synchronization. */
1030 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1031 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1032 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1033 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1034 /* Pipeline query controls. */
1035 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1036 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1037 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1038
1039 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1040 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1041 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1042 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1043 };
1044
1045 struct radv_vertex_binding {
1046 struct radv_buffer * buffer;
1047 VkDeviceSize offset;
1048 VkDeviceSize size;
1049 VkDeviceSize stride;
1050 };
1051
1052 struct radv_streamout_binding {
1053 struct radv_buffer *buffer;
1054 VkDeviceSize offset;
1055 VkDeviceSize size;
1056 };
1057
1058 struct radv_streamout_state {
1059 /* Mask of bound streamout buffers. */
1060 uint8_t enabled_mask;
1061
1062 /* External state that comes from the last vertex stage, it must be
1063 * set explicitely when binding a new graphics pipeline.
1064 */
1065 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1066 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1067
1068 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1069 uint32_t hw_enabled_mask;
1070
1071 /* State of VGT_STRMOUT_(CONFIG|EN) */
1072 bool streamout_enabled;
1073 };
1074
1075 struct radv_viewport_state {
1076 uint32_t count;
1077 VkViewport viewports[MAX_VIEWPORTS];
1078 };
1079
1080 struct radv_scissor_state {
1081 uint32_t count;
1082 VkRect2D scissors[MAX_SCISSORS];
1083 };
1084
1085 struct radv_discard_rectangle_state {
1086 uint32_t count;
1087 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1088 };
1089
1090 struct radv_sample_locations_state {
1091 VkSampleCountFlagBits per_pixel;
1092 VkExtent2D grid_size;
1093 uint32_t count;
1094 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1095 };
1096
1097 struct radv_dynamic_state {
1098 /**
1099 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1100 * Defines the set of saved dynamic state.
1101 */
1102 uint32_t mask;
1103
1104 struct radv_viewport_state viewport;
1105
1106 struct radv_scissor_state scissor;
1107
1108 float line_width;
1109
1110 struct {
1111 float bias;
1112 float clamp;
1113 float slope;
1114 } depth_bias;
1115
1116 float blend_constants[4];
1117
1118 struct {
1119 float min;
1120 float max;
1121 } depth_bounds;
1122
1123 struct {
1124 uint32_t front;
1125 uint32_t back;
1126 } stencil_compare_mask;
1127
1128 struct {
1129 uint32_t front;
1130 uint32_t back;
1131 } stencil_write_mask;
1132
1133 struct {
1134 struct {
1135 VkStencilOp fail_op;
1136 VkStencilOp pass_op;
1137 VkStencilOp depth_fail_op;
1138 VkCompareOp compare_op;
1139 } front;
1140
1141 struct {
1142 VkStencilOp fail_op;
1143 VkStencilOp pass_op;
1144 VkStencilOp depth_fail_op;
1145 VkCompareOp compare_op;
1146 } back;
1147 } stencil_op;
1148
1149 struct {
1150 uint32_t front;
1151 uint32_t back;
1152 } stencil_reference;
1153
1154 struct radv_discard_rectangle_state discard_rectangle;
1155
1156 struct radv_sample_locations_state sample_location;
1157
1158 struct {
1159 uint32_t factor;
1160 uint16_t pattern;
1161 } line_stipple;
1162
1163 VkCullModeFlags cull_mode;
1164 VkFrontFace front_face;
1165 unsigned primitive_topology;
1166
1167 bool depth_test_enable;
1168 bool depth_write_enable;
1169 VkCompareOp depth_compare_op;
1170 bool depth_bounds_test_enable;
1171 bool stencil_test_enable;
1172 };
1173
1174 extern const struct radv_dynamic_state default_dynamic_state;
1175
1176 const char *
1177 radv_get_debug_option_name(int id);
1178
1179 const char *
1180 radv_get_perftest_option_name(int id);
1181
1182 struct radv_color_buffer_info {
1183 uint64_t cb_color_base;
1184 uint64_t cb_color_cmask;
1185 uint64_t cb_color_fmask;
1186 uint64_t cb_dcc_base;
1187 uint32_t cb_color_slice;
1188 uint32_t cb_color_view;
1189 uint32_t cb_color_info;
1190 uint32_t cb_color_attrib;
1191 uint32_t cb_color_attrib2; /* GFX9 and later */
1192 uint32_t cb_color_attrib3; /* GFX10 and later */
1193 uint32_t cb_dcc_control;
1194 uint32_t cb_color_cmask_slice;
1195 uint32_t cb_color_fmask_slice;
1196 union {
1197 uint32_t cb_color_pitch; // GFX6-GFX8
1198 uint32_t cb_mrt_epitch; // GFX9+
1199 };
1200 };
1201
1202 struct radv_ds_buffer_info {
1203 uint64_t db_z_read_base;
1204 uint64_t db_stencil_read_base;
1205 uint64_t db_z_write_base;
1206 uint64_t db_stencil_write_base;
1207 uint64_t db_htile_data_base;
1208 uint32_t db_depth_info;
1209 uint32_t db_z_info;
1210 uint32_t db_stencil_info;
1211 uint32_t db_depth_view;
1212 uint32_t db_depth_size;
1213 uint32_t db_depth_slice;
1214 uint32_t db_htile_surface;
1215 uint32_t pa_su_poly_offset_db_fmt_cntl;
1216 uint32_t db_z_info2; /* GFX9 only */
1217 uint32_t db_stencil_info2; /* GFX9 only */
1218 float offset_scale;
1219 };
1220
1221 void
1222 radv_initialise_color_surface(struct radv_device *device,
1223 struct radv_color_buffer_info *cb,
1224 struct radv_image_view *iview);
1225 void
1226 radv_initialise_ds_surface(struct radv_device *device,
1227 struct radv_ds_buffer_info *ds,
1228 struct radv_image_view *iview);
1229
1230 /**
1231 * Attachment state when recording a renderpass instance.
1232 *
1233 * The clear value is valid only if there exists a pending clear.
1234 */
1235 struct radv_attachment_state {
1236 VkImageAspectFlags pending_clear_aspects;
1237 uint32_t cleared_views;
1238 VkClearValue clear_value;
1239 VkImageLayout current_layout;
1240 VkImageLayout current_stencil_layout;
1241 bool current_in_render_loop;
1242 struct radv_sample_locations_state sample_location;
1243
1244 union {
1245 struct radv_color_buffer_info cb;
1246 struct radv_ds_buffer_info ds;
1247 };
1248 struct radv_image_view *iview;
1249 };
1250
1251 struct radv_descriptor_state {
1252 struct radv_descriptor_set *sets[MAX_SETS];
1253 uint32_t dirty;
1254 uint32_t valid;
1255 struct radv_push_descriptor_set push_set;
1256 bool push_dirty;
1257 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1258 };
1259
1260 struct radv_subpass_sample_locs_state {
1261 uint32_t subpass_idx;
1262 struct radv_sample_locations_state sample_location;
1263 };
1264
1265 struct radv_cmd_state {
1266 /* Vertex descriptors */
1267 uint64_t vb_va;
1268 unsigned vb_size;
1269
1270 bool predicating;
1271 uint32_t dirty;
1272
1273 uint32_t prefetch_L2_mask;
1274
1275 struct radv_pipeline * pipeline;
1276 struct radv_pipeline * emitted_pipeline;
1277 struct radv_pipeline * compute_pipeline;
1278 struct radv_pipeline * emitted_compute_pipeline;
1279 struct radv_framebuffer * framebuffer;
1280 struct radv_render_pass * pass;
1281 const struct radv_subpass * subpass;
1282 struct radv_dynamic_state dynamic;
1283 struct radv_attachment_state * attachments;
1284 struct radv_streamout_state streamout;
1285 VkRect2D render_area;
1286
1287 uint32_t num_subpass_sample_locs;
1288 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1289
1290 /* Index buffer */
1291 struct radv_buffer *index_buffer;
1292 uint64_t index_offset;
1293 uint32_t index_type;
1294 uint32_t max_index_count;
1295 uint64_t index_va;
1296 int32_t last_index_type;
1297
1298 int32_t last_primitive_reset_en;
1299 uint32_t last_primitive_reset_index;
1300 enum radv_cmd_flush_bits flush_bits;
1301 unsigned active_occlusion_queries;
1302 bool perfect_occlusion_queries_enabled;
1303 unsigned active_pipeline_queries;
1304 unsigned active_pipeline_gds_queries;
1305 float offset_scale;
1306 uint32_t trace_id;
1307 uint32_t last_ia_multi_vgt_param;
1308
1309 uint32_t last_num_instances;
1310 uint32_t last_first_instance;
1311 uint32_t last_vertex_offset;
1312
1313 uint32_t last_sx_ps_downconvert;
1314 uint32_t last_sx_blend_opt_epsilon;
1315 uint32_t last_sx_blend_opt_control;
1316
1317 /* Whether CP DMA is busy/idle. */
1318 bool dma_is_busy;
1319
1320 /* Conditional rendering info. */
1321 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1322 uint64_t predication_va;
1323
1324 /* Inheritance info. */
1325 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1326
1327 bool context_roll_without_scissor_emitted;
1328
1329 /* SQTT related state. */
1330 uint32_t current_event_type;
1331 uint32_t num_events;
1332 uint32_t num_layout_transitions;
1333 };
1334
1335 struct radv_cmd_pool {
1336 struct vk_object_base base;
1337 VkAllocationCallbacks alloc;
1338 struct list_head cmd_buffers;
1339 struct list_head free_cmd_buffers;
1340 uint32_t queue_family_index;
1341 };
1342
1343 struct radv_cmd_buffer_upload {
1344 uint8_t *map;
1345 unsigned offset;
1346 uint64_t size;
1347 struct radeon_winsys_bo *upload_bo;
1348 struct list_head list;
1349 };
1350
1351 enum radv_cmd_buffer_status {
1352 RADV_CMD_BUFFER_STATUS_INVALID,
1353 RADV_CMD_BUFFER_STATUS_INITIAL,
1354 RADV_CMD_BUFFER_STATUS_RECORDING,
1355 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1356 RADV_CMD_BUFFER_STATUS_PENDING,
1357 };
1358
1359 struct radv_cmd_buffer {
1360 struct vk_object_base base;
1361
1362 struct radv_device * device;
1363
1364 struct radv_cmd_pool * pool;
1365 struct list_head pool_link;
1366
1367 VkCommandBufferUsageFlags usage_flags;
1368 VkCommandBufferLevel level;
1369 enum radv_cmd_buffer_status status;
1370 struct radeon_cmdbuf *cs;
1371 struct radv_cmd_state state;
1372 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1373 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1374 uint32_t queue_family_index;
1375
1376 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1377 VkShaderStageFlags push_constant_stages;
1378 struct radv_descriptor_set meta_push_descriptors;
1379
1380 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1381
1382 struct radv_cmd_buffer_upload upload;
1383
1384 uint32_t scratch_size_per_wave_needed;
1385 uint32_t scratch_waves_wanted;
1386 uint32_t compute_scratch_size_per_wave_needed;
1387 uint32_t compute_scratch_waves_wanted;
1388 uint32_t esgs_ring_size_needed;
1389 uint32_t gsvs_ring_size_needed;
1390 bool tess_rings_needed;
1391 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1392 bool gds_oa_needed; /* for GFX10 streamout */
1393 bool sample_positions_needed;
1394
1395 VkResult record_result;
1396
1397 uint64_t gfx9_fence_va;
1398 uint32_t gfx9_fence_idx;
1399 uint64_t gfx9_eop_bug_va;
1400
1401 /**
1402 * Whether a query pool has been resetted and we have to flush caches.
1403 */
1404 bool pending_reset_query;
1405
1406 /**
1407 * Bitmask of pending active query flushes.
1408 */
1409 enum radv_cmd_flush_bits active_query_flush_bits;
1410 };
1411
1412 struct radv_image;
1413 struct radv_image_view;
1414
1415 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1416
1417 void si_emit_graphics(struct radv_device *device,
1418 struct radeon_cmdbuf *cs);
1419 void si_emit_compute(struct radv_physical_device *physical_device,
1420 struct radeon_cmdbuf *cs);
1421
1422 void cik_create_gfx_config(struct radv_device *device);
1423
1424 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1425 int count, const VkViewport *viewports);
1426 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1427 int count, const VkRect2D *scissors,
1428 const VkViewport *viewports, bool can_use_guardband);
1429 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1430 bool instanced_draw, bool indirect_draw,
1431 bool count_from_stream_output,
1432 uint32_t draw_vertex_count,
1433 unsigned topology);
1434 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1435 enum chip_class chip_class,
1436 bool is_mec,
1437 unsigned event, unsigned event_flags,
1438 unsigned dst_sel, unsigned data_sel,
1439 uint64_t va,
1440 uint32_t new_fence,
1441 uint64_t gfx9_eop_bug_va);
1442
1443 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1444 uint32_t ref, uint32_t mask);
1445 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1446 enum chip_class chip_class,
1447 uint32_t *fence_ptr, uint64_t va,
1448 bool is_mec,
1449 enum radv_cmd_flush_bits flush_bits,
1450 uint64_t gfx9_eop_bug_va);
1451 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1452 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1453 bool inverted, uint64_t va);
1454 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1455 uint64_t src_va, uint64_t dest_va,
1456 uint64_t size);
1457 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1458 unsigned size);
1459 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1460 uint64_t size, unsigned value);
1461 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1462
1463 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1464 bool
1465 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1466 unsigned size,
1467 unsigned alignment,
1468 unsigned *out_offset,
1469 void **ptr);
1470 void
1471 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1472 const struct radv_subpass *subpass);
1473 bool
1474 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1475 unsigned size, unsigned alignmnet,
1476 const void *data, unsigned *out_offset);
1477
1478 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1479 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1480 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1481 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1482 VkImageAspectFlags aspects,
1483 VkResolveModeFlagBits resolve_mode);
1484 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1485 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1486 VkImageAspectFlags aspects,
1487 VkResolveModeFlagBits resolve_mode);
1488 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1489 unsigned radv_get_default_max_sample_dist(int log_samples);
1490 void radv_device_init_msaa(struct radv_device *device);
1491
1492 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1493 const struct radv_image_view *iview,
1494 VkClearDepthStencilValue ds_clear_value,
1495 VkImageAspectFlags aspects);
1496
1497 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1498 const struct radv_image_view *iview,
1499 int cb_idx,
1500 uint32_t color_values[2]);
1501
1502 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1503 struct radv_image *image,
1504 const VkImageSubresourceRange *range, bool value);
1505
1506 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1507 struct radv_image *image,
1508 const VkImageSubresourceRange *range, bool value);
1509
1510 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1511 struct radeon_winsys_bo *bo,
1512 uint64_t offset, uint64_t size, uint32_t value);
1513 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1514 bool radv_get_memory_fd(struct radv_device *device,
1515 struct radv_device_memory *memory,
1516 int *pFD);
1517 void radv_free_memory(struct radv_device *device,
1518 const VkAllocationCallbacks* pAllocator,
1519 struct radv_device_memory *mem);
1520
1521 static inline void
1522 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1523 unsigned sh_offset, unsigned pointer_count,
1524 bool use_32bit_pointers)
1525 {
1526 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1527 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1528 }
1529
1530 static inline void
1531 radv_emit_shader_pointer_body(struct radv_device *device,
1532 struct radeon_cmdbuf *cs,
1533 uint64_t va, bool use_32bit_pointers)
1534 {
1535 radeon_emit(cs, va);
1536
1537 if (use_32bit_pointers) {
1538 assert(va == 0 ||
1539 (va >> 32) == device->physical_device->rad_info.address32_hi);
1540 } else {
1541 radeon_emit(cs, va >> 32);
1542 }
1543 }
1544
1545 static inline void
1546 radv_emit_shader_pointer(struct radv_device *device,
1547 struct radeon_cmdbuf *cs,
1548 uint32_t sh_offset, uint64_t va, bool global)
1549 {
1550 bool use_32bit_pointers = !global;
1551
1552 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1553 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1554 }
1555
1556 static inline struct radv_descriptor_state *
1557 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1558 VkPipelineBindPoint bind_point)
1559 {
1560 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1561 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1562 return &cmd_buffer->descriptors[bind_point];
1563 }
1564
1565 /*
1566 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1567 *
1568 * Limitations: Can't call normal dispatch functions without binding or rebinding
1569 * the compute pipeline.
1570 */
1571 void radv_unaligned_dispatch(
1572 struct radv_cmd_buffer *cmd_buffer,
1573 uint32_t x,
1574 uint32_t y,
1575 uint32_t z);
1576
1577 struct radv_event {
1578 struct vk_object_base base;
1579 struct radeon_winsys_bo *bo;
1580 uint64_t *map;
1581 };
1582
1583 struct radv_shader_module;
1584
1585 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1586 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1587 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1588 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1589 #define RADV_HASH_SHADER_LLVM (1 << 4)
1590
1591 void
1592 radv_hash_shaders(unsigned char *hash,
1593 const VkPipelineShaderStageCreateInfo **stages,
1594 const struct radv_pipeline_layout *layout,
1595 const struct radv_pipeline_key *key,
1596 uint32_t flags);
1597
1598 static inline gl_shader_stage
1599 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1600 {
1601 assert(__builtin_popcount(vk_stage) == 1);
1602 return ffs(vk_stage) - 1;
1603 }
1604
1605 static inline VkShaderStageFlagBits
1606 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1607 {
1608 return (1 << mesa_stage);
1609 }
1610
1611 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1612
1613 #define radv_foreach_stage(stage, stage_bits) \
1614 for (gl_shader_stage stage, \
1615 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1616 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1617 __tmp &= ~(1 << (stage)))
1618
1619 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1620 unsigned radv_format_meta_fs_key(VkFormat format);
1621
1622 struct radv_multisample_state {
1623 uint32_t db_eqaa;
1624 uint32_t pa_sc_line_cntl;
1625 uint32_t pa_sc_mode_cntl_0;
1626 uint32_t pa_sc_mode_cntl_1;
1627 uint32_t pa_sc_aa_config;
1628 uint32_t pa_sc_aa_mask[2];
1629 unsigned num_samples;
1630 };
1631
1632 struct radv_prim_vertex_count {
1633 uint8_t min;
1634 uint8_t incr;
1635 };
1636
1637 struct radv_vertex_elements_info {
1638 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1639 };
1640
1641 struct radv_ia_multi_vgt_param_helpers {
1642 uint32_t base;
1643 bool partial_es_wave;
1644 uint8_t primgroup_size;
1645 bool ia_switch_on_eoi;
1646 bool partial_vs_wave;
1647 };
1648
1649 struct radv_binning_state {
1650 uint32_t pa_sc_binner_cntl_0;
1651 uint32_t db_dfsm_control;
1652 };
1653
1654 #define SI_GS_PER_ES 128
1655
1656 struct radv_pipeline {
1657 struct vk_object_base base;
1658 struct radv_device * device;
1659 struct radv_dynamic_state dynamic_state;
1660
1661 struct radv_pipeline_layout * layout;
1662
1663 bool need_indirect_descriptor_sets;
1664 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1665 struct radv_shader_variant *gs_copy_shader;
1666 VkShaderStageFlags active_stages;
1667
1668 struct radeon_cmdbuf cs;
1669 uint32_t ctx_cs_hash;
1670 struct radeon_cmdbuf ctx_cs;
1671
1672 struct radv_vertex_elements_info vertex_elements;
1673
1674 uint32_t binding_stride[MAX_VBS];
1675 uint8_t num_vertex_bindings;
1676
1677 uint32_t user_data_0[MESA_SHADER_STAGES];
1678 union {
1679 struct {
1680 struct radv_multisample_state ms;
1681 struct radv_binning_state binning;
1682 uint32_t spi_baryc_cntl;
1683 bool prim_restart_enable;
1684 unsigned esgs_ring_size;
1685 unsigned gsvs_ring_size;
1686 uint32_t vtx_base_sgpr;
1687 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1688 uint8_t vtx_emit_num;
1689 bool can_use_guardband;
1690 uint32_t needed_dynamic_state;
1691 bool disable_out_of_order_rast_for_occlusion;
1692 unsigned tess_patch_control_points;
1693 unsigned pa_su_sc_mode_cntl;
1694 unsigned db_depth_control;
1695 bool uses_dynamic_stride;
1696
1697 /* Used for rbplus */
1698 uint32_t col_format;
1699 uint32_t cb_target_mask;
1700 bool is_dual_src;
1701 } graphics;
1702 };
1703
1704 unsigned max_waves;
1705 unsigned scratch_bytes_per_wave;
1706
1707 /* Not NULL if graphics pipeline uses streamout. */
1708 struct radv_shader_variant *streamout_shader;
1709 };
1710
1711 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1712 {
1713 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1714 }
1715
1716 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1717 {
1718 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1719 }
1720
1721 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1722
1723 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1724
1725 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1726
1727 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1728 gl_shader_stage stage,
1729 int idx);
1730
1731 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1732 gl_shader_stage stage);
1733
1734 struct radv_graphics_pipeline_create_info {
1735 bool use_rectlist;
1736 bool db_depth_clear;
1737 bool db_stencil_clear;
1738 bool db_depth_disable_expclear;
1739 bool db_stencil_disable_expclear;
1740 bool depth_compress_disable;
1741 bool stencil_compress_disable;
1742 bool resummarize_enable;
1743 uint32_t custom_blend_mode;
1744 };
1745
1746 VkResult
1747 radv_graphics_pipeline_create(VkDevice device,
1748 VkPipelineCache cache,
1749 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1750 const struct radv_graphics_pipeline_create_info *extra,
1751 const VkAllocationCallbacks *alloc,
1752 VkPipeline *pPipeline);
1753
1754 struct radv_binning_settings {
1755 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1756 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1757 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1758 };
1759
1760 struct radv_binning_settings
1761 radv_get_binning_settings(const struct radv_physical_device *pdev);
1762
1763 struct vk_format_description;
1764 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1765 int first_non_void);
1766 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1767 int first_non_void);
1768 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1769 uint32_t radv_translate_colorformat(VkFormat format);
1770 uint32_t radv_translate_color_numformat(VkFormat format,
1771 const struct vk_format_description *desc,
1772 int first_non_void);
1773 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1774 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1775 uint32_t radv_translate_dbformat(VkFormat format);
1776 uint32_t radv_translate_tex_dataformat(VkFormat format,
1777 const struct vk_format_description *desc,
1778 int first_non_void);
1779 uint32_t radv_translate_tex_numformat(VkFormat format,
1780 const struct vk_format_description *desc,
1781 int first_non_void);
1782 bool radv_format_pack_clear_color(VkFormat format,
1783 uint32_t clear_vals[2],
1784 VkClearColorValue *value);
1785 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1786 bool radv_dcc_formats_compatible(VkFormat format1,
1787 VkFormat format2);
1788 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1789
1790 struct radv_image_plane {
1791 VkFormat format;
1792 struct radeon_surf surface;
1793 uint64_t offset;
1794 };
1795
1796 struct radv_image {
1797 struct vk_object_base base;
1798 VkImageType type;
1799 /* The original VkFormat provided by the client. This may not match any
1800 * of the actual surface formats.
1801 */
1802 VkFormat vk_format;
1803 VkImageAspectFlags aspects;
1804 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1805 struct ac_surf_info info;
1806 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1807 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1808
1809 VkDeviceSize size;
1810 uint32_t alignment;
1811
1812 unsigned queue_family_mask;
1813 bool exclusive;
1814 bool shareable;
1815
1816 /* Set when bound */
1817 struct radeon_winsys_bo *bo;
1818 VkDeviceSize offset;
1819 bool tc_compatible_htile;
1820 bool tc_compatible_cmask;
1821
1822 uint64_t clear_value_offset;
1823 uint64_t fce_pred_offset;
1824 uint64_t dcc_pred_offset;
1825
1826 /*
1827 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1828 * stored at this offset is UINT_MAX, the driver will emit
1829 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1830 * SET_CONTEXT_REG packet.
1831 */
1832 uint64_t tc_compat_zrange_offset;
1833
1834 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1835 VkDeviceMemory owned_memory;
1836
1837 unsigned plane_count;
1838 struct radv_image_plane planes[0];
1839 };
1840
1841 /* Whether the image has a htile that is known consistent with the contents of
1842 * the image and is allowed to be in compressed form.
1843 *
1844 * If this is false reads that don't use the htile should be able to return
1845 * correct results.
1846 */
1847 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1848 VkImageLayout layout,
1849 bool in_render_loop,
1850 unsigned queue_mask);
1851
1852 bool radv_layout_can_fast_clear(const struct radv_image *image,
1853 VkImageLayout layout,
1854 bool in_render_loop,
1855 unsigned queue_mask);
1856
1857 bool radv_layout_dcc_compressed(const struct radv_device *device,
1858 const struct radv_image *image,
1859 VkImageLayout layout,
1860 bool in_render_loop,
1861 unsigned queue_mask);
1862
1863 /**
1864 * Return whether the image has CMASK metadata for color surfaces.
1865 */
1866 static inline bool
1867 radv_image_has_cmask(const struct radv_image *image)
1868 {
1869 return image->planes[0].surface.cmask_offset;
1870 }
1871
1872 /**
1873 * Return whether the image has FMASK metadata for color surfaces.
1874 */
1875 static inline bool
1876 radv_image_has_fmask(const struct radv_image *image)
1877 {
1878 return image->planes[0].surface.fmask_offset;
1879 }
1880
1881 /**
1882 * Return whether the image has DCC metadata for color surfaces.
1883 */
1884 static inline bool
1885 radv_image_has_dcc(const struct radv_image *image)
1886 {
1887 return image->planes[0].surface.dcc_size;
1888 }
1889
1890 /**
1891 * Return whether the image is TC-compatible CMASK.
1892 */
1893 static inline bool
1894 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1895 {
1896 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1897 }
1898
1899 /**
1900 * Return whether DCC metadata is enabled for a level.
1901 */
1902 static inline bool
1903 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1904 {
1905 return radv_image_has_dcc(image) &&
1906 level < image->planes[0].surface.num_dcc_levels;
1907 }
1908
1909 /**
1910 * Return whether the image has CB metadata.
1911 */
1912 static inline bool
1913 radv_image_has_CB_metadata(const struct radv_image *image)
1914 {
1915 return radv_image_has_cmask(image) ||
1916 radv_image_has_fmask(image) ||
1917 radv_image_has_dcc(image);
1918 }
1919
1920 /**
1921 * Return whether the image has HTILE metadata for depth surfaces.
1922 */
1923 static inline bool
1924 radv_image_has_htile(const struct radv_image *image)
1925 {
1926 return image->planes[0].surface.htile_size;
1927 }
1928
1929 /**
1930 * Return whether HTILE metadata is enabled for a level.
1931 */
1932 static inline bool
1933 radv_htile_enabled(const struct radv_image *image, unsigned level)
1934 {
1935 return radv_image_has_htile(image) && level == 0;
1936 }
1937
1938 /**
1939 * Return whether the image is TC-compatible HTILE.
1940 */
1941 static inline bool
1942 radv_image_is_tc_compat_htile(const struct radv_image *image)
1943 {
1944 return radv_image_has_htile(image) && image->tc_compatible_htile;
1945 }
1946
1947 static inline uint64_t
1948 radv_image_get_fast_clear_va(const struct radv_image *image,
1949 uint32_t base_level)
1950 {
1951 uint64_t va = radv_buffer_get_va(image->bo);
1952 va += image->offset + image->clear_value_offset + base_level * 8;
1953 return va;
1954 }
1955
1956 static inline uint64_t
1957 radv_image_get_fce_pred_va(const struct radv_image *image,
1958 uint32_t base_level)
1959 {
1960 uint64_t va = radv_buffer_get_va(image->bo);
1961 va += image->offset + image->fce_pred_offset + base_level * 8;
1962 return va;
1963 }
1964
1965 static inline uint64_t
1966 radv_image_get_dcc_pred_va(const struct radv_image *image,
1967 uint32_t base_level)
1968 {
1969 uint64_t va = radv_buffer_get_va(image->bo);
1970 va += image->offset + image->dcc_pred_offset + base_level * 8;
1971 return va;
1972 }
1973
1974 static inline uint64_t
1975 radv_get_tc_compat_zrange_va(const struct radv_image *image,
1976 uint32_t base_level)
1977 {
1978 uint64_t va = radv_buffer_get_va(image->bo);
1979 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
1980 return va;
1981 }
1982
1983 static inline uint64_t
1984 radv_get_ds_clear_value_va(const struct radv_image *image,
1985 uint32_t base_level)
1986 {
1987 uint64_t va = radv_buffer_get_va(image->bo);
1988 va += image->offset + image->clear_value_offset + base_level * 8;
1989 return va;
1990 }
1991
1992 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1993
1994 static inline uint32_t
1995 radv_get_layerCount(const struct radv_image *image,
1996 const VkImageSubresourceRange *range)
1997 {
1998 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1999 image->info.array_size - range->baseArrayLayer : range->layerCount;
2000 }
2001
2002 static inline uint32_t
2003 radv_get_levelCount(const struct radv_image *image,
2004 const VkImageSubresourceRange *range)
2005 {
2006 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
2007 image->info.levels - range->baseMipLevel : range->levelCount;
2008 }
2009
2010 struct radeon_bo_metadata;
2011 void
2012 radv_init_metadata(struct radv_device *device,
2013 struct radv_image *image,
2014 struct radeon_bo_metadata *metadata);
2015
2016 void
2017 radv_image_override_offset_stride(struct radv_device *device,
2018 struct radv_image *image,
2019 uint64_t offset, uint32_t stride);
2020
2021 union radv_descriptor {
2022 struct {
2023 uint32_t plane0_descriptor[8];
2024 uint32_t fmask_descriptor[8];
2025 };
2026 struct {
2027 uint32_t plane_descriptors[3][8];
2028 };
2029 };
2030
2031 struct radv_image_view {
2032 struct vk_object_base base;
2033 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2034 struct radeon_winsys_bo *bo;
2035
2036 VkImageViewType type;
2037 VkImageAspectFlags aspect_mask;
2038 VkFormat vk_format;
2039 unsigned plane_id;
2040 bool multiple_planes;
2041 uint32_t base_layer;
2042 uint32_t layer_count;
2043 uint32_t base_mip;
2044 uint32_t level_count;
2045 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2046
2047 union radv_descriptor descriptor;
2048
2049 /* Descriptor for use as a storage image as opposed to a sampled image.
2050 * This has a few differences for cube maps (e.g. type).
2051 */
2052 union radv_descriptor storage_descriptor;
2053 };
2054
2055 struct radv_image_create_info {
2056 const VkImageCreateInfo *vk_info;
2057 bool scanout;
2058 bool no_metadata_planes;
2059 const struct radeon_bo_metadata *bo_metadata;
2060 };
2061
2062 VkResult
2063 radv_image_create_layout(struct radv_device *device,
2064 struct radv_image_create_info create_info,
2065 struct radv_image *image);
2066
2067 VkResult radv_image_create(VkDevice _device,
2068 const struct radv_image_create_info *info,
2069 const VkAllocationCallbacks* alloc,
2070 VkImage *pImage);
2071
2072 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2073
2074 VkResult
2075 radv_image_from_gralloc(VkDevice device_h,
2076 const VkImageCreateInfo *base_info,
2077 const VkNativeBufferANDROID *gralloc_info,
2078 const VkAllocationCallbacks *alloc,
2079 VkImage *out_image_h);
2080 uint64_t
2081 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2082 const VkImageUsageFlags vk_usage);
2083 VkResult
2084 radv_import_ahb_memory(struct radv_device *device,
2085 struct radv_device_memory *mem,
2086 unsigned priority,
2087 const VkImportAndroidHardwareBufferInfoANDROID *info);
2088 VkResult
2089 radv_create_ahb_memory(struct radv_device *device,
2090 struct radv_device_memory *mem,
2091 unsigned priority,
2092 const VkMemoryAllocateInfo *pAllocateInfo);
2093
2094 VkFormat
2095 radv_select_android_external_format(const void *next, VkFormat default_format);
2096
2097 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2098
2099 struct radv_image_view_extra_create_info {
2100 bool disable_compression;
2101 };
2102
2103 void radv_image_view_init(struct radv_image_view *view,
2104 struct radv_device *device,
2105 const VkImageViewCreateInfo *pCreateInfo,
2106 const struct radv_image_view_extra_create_info* extra_create_info);
2107
2108 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2109
2110 struct radv_sampler_ycbcr_conversion {
2111 struct vk_object_base base;
2112 VkFormat format;
2113 VkSamplerYcbcrModelConversion ycbcr_model;
2114 VkSamplerYcbcrRange ycbcr_range;
2115 VkComponentMapping components;
2116 VkChromaLocation chroma_offsets[2];
2117 VkFilter chroma_filter;
2118 };
2119
2120 struct radv_buffer_view {
2121 struct vk_object_base base;
2122 struct radeon_winsys_bo *bo;
2123 VkFormat vk_format;
2124 uint64_t range; /**< VkBufferViewCreateInfo::range */
2125 uint32_t state[4];
2126 };
2127 void radv_buffer_view_init(struct radv_buffer_view *view,
2128 struct radv_device *device,
2129 const VkBufferViewCreateInfo* pCreateInfo);
2130
2131 static inline struct VkExtent3D
2132 radv_sanitize_image_extent(const VkImageType imageType,
2133 const struct VkExtent3D imageExtent)
2134 {
2135 switch (imageType) {
2136 case VK_IMAGE_TYPE_1D:
2137 return (VkExtent3D) { imageExtent.width, 1, 1 };
2138 case VK_IMAGE_TYPE_2D:
2139 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2140 case VK_IMAGE_TYPE_3D:
2141 return imageExtent;
2142 default:
2143 unreachable("invalid image type");
2144 }
2145 }
2146
2147 static inline struct VkOffset3D
2148 radv_sanitize_image_offset(const VkImageType imageType,
2149 const struct VkOffset3D imageOffset)
2150 {
2151 switch (imageType) {
2152 case VK_IMAGE_TYPE_1D:
2153 return (VkOffset3D) { imageOffset.x, 0, 0 };
2154 case VK_IMAGE_TYPE_2D:
2155 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2156 case VK_IMAGE_TYPE_3D:
2157 return imageOffset;
2158 default:
2159 unreachable("invalid image type");
2160 }
2161 }
2162
2163 static inline bool
2164 radv_image_extent_compare(const struct radv_image *image,
2165 const VkExtent3D *extent)
2166 {
2167 if (extent->width != image->info.width ||
2168 extent->height != image->info.height ||
2169 extent->depth != image->info.depth)
2170 return false;
2171 return true;
2172 }
2173
2174 struct radv_sampler {
2175 struct vk_object_base base;
2176 uint32_t state[4];
2177 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2178 uint32_t border_color_slot;
2179 };
2180
2181 struct radv_framebuffer {
2182 struct vk_object_base base;
2183 uint32_t width;
2184 uint32_t height;
2185 uint32_t layers;
2186
2187 uint32_t attachment_count;
2188 struct radv_image_view *attachments[0];
2189 };
2190
2191 struct radv_subpass_barrier {
2192 VkPipelineStageFlags src_stage_mask;
2193 VkAccessFlags src_access_mask;
2194 VkAccessFlags dst_access_mask;
2195 };
2196
2197 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2198 const struct radv_subpass_barrier *barrier);
2199
2200 struct radv_subpass_attachment {
2201 uint32_t attachment;
2202 VkImageLayout layout;
2203 VkImageLayout stencil_layout;
2204 bool in_render_loop;
2205 };
2206
2207 struct radv_subpass {
2208 uint32_t attachment_count;
2209 struct radv_subpass_attachment * attachments;
2210
2211 uint32_t input_count;
2212 uint32_t color_count;
2213 struct radv_subpass_attachment * input_attachments;
2214 struct radv_subpass_attachment * color_attachments;
2215 struct radv_subpass_attachment * resolve_attachments;
2216 struct radv_subpass_attachment * depth_stencil_attachment;
2217 struct radv_subpass_attachment * ds_resolve_attachment;
2218 VkResolveModeFlagBits depth_resolve_mode;
2219 VkResolveModeFlagBits stencil_resolve_mode;
2220
2221 /** Subpass has at least one color resolve attachment */
2222 bool has_color_resolve;
2223
2224 /** Subpass has at least one color attachment */
2225 bool has_color_att;
2226
2227 struct radv_subpass_barrier start_barrier;
2228
2229 uint32_t view_mask;
2230
2231 VkSampleCountFlagBits color_sample_count;
2232 VkSampleCountFlagBits depth_sample_count;
2233 VkSampleCountFlagBits max_sample_count;
2234 };
2235
2236 uint32_t
2237 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2238
2239 struct radv_render_pass_attachment {
2240 VkFormat format;
2241 uint32_t samples;
2242 VkAttachmentLoadOp load_op;
2243 VkAttachmentLoadOp stencil_load_op;
2244 VkImageLayout initial_layout;
2245 VkImageLayout final_layout;
2246 VkImageLayout stencil_initial_layout;
2247 VkImageLayout stencil_final_layout;
2248
2249 /* The subpass id in which the attachment will be used first/last. */
2250 uint32_t first_subpass_idx;
2251 uint32_t last_subpass_idx;
2252 };
2253
2254 struct radv_render_pass {
2255 struct vk_object_base base;
2256 uint32_t attachment_count;
2257 uint32_t subpass_count;
2258 struct radv_subpass_attachment * subpass_attachments;
2259 struct radv_render_pass_attachment * attachments;
2260 struct radv_subpass_barrier end_barrier;
2261 struct radv_subpass subpasses[0];
2262 };
2263
2264 VkResult radv_device_init_meta(struct radv_device *device);
2265 void radv_device_finish_meta(struct radv_device *device);
2266
2267 struct radv_query_pool {
2268 struct vk_object_base base;
2269 struct radeon_winsys_bo *bo;
2270 uint32_t stride;
2271 uint32_t availability_offset;
2272 uint64_t size;
2273 char *ptr;
2274 VkQueryType type;
2275 uint32_t pipeline_stats_mask;
2276 };
2277
2278 typedef enum {
2279 RADV_SEMAPHORE_NONE,
2280 RADV_SEMAPHORE_WINSYS,
2281 RADV_SEMAPHORE_SYNCOBJ,
2282 RADV_SEMAPHORE_TIMELINE,
2283 } radv_semaphore_kind;
2284
2285 struct radv_deferred_queue_submission;
2286
2287 struct radv_timeline_waiter {
2288 struct list_head list;
2289 struct radv_deferred_queue_submission *submission;
2290 uint64_t value;
2291 };
2292
2293 struct radv_timeline_point {
2294 struct list_head list;
2295
2296 uint64_t value;
2297 uint32_t syncobj;
2298
2299 /* Separate from the list to accomodate CPU wait being async, as well
2300 * as prevent point deletion during submission. */
2301 unsigned wait_count;
2302 };
2303
2304 struct radv_timeline {
2305 /* Using a pthread mutex to be compatible with condition variables. */
2306 pthread_mutex_t mutex;
2307
2308 uint64_t highest_signaled;
2309 uint64_t highest_submitted;
2310
2311 struct list_head points;
2312
2313 /* Keep free points on hand so we do not have to recreate syncobjs all
2314 * the time. */
2315 struct list_head free_points;
2316
2317 /* Submissions that are deferred waiting for a specific value to be
2318 * submitted. */
2319 struct list_head waiters;
2320 };
2321
2322 struct radv_semaphore_part {
2323 radv_semaphore_kind kind;
2324 union {
2325 uint32_t syncobj;
2326 struct radeon_winsys_sem *ws_sem;
2327 struct radv_timeline timeline;
2328 };
2329 };
2330
2331 struct radv_semaphore {
2332 struct vk_object_base base;
2333 struct radv_semaphore_part permanent;
2334 struct radv_semaphore_part temporary;
2335 };
2336
2337 bool radv_queue_internal_submit(struct radv_queue *queue,
2338 struct radeon_cmdbuf *cs);
2339
2340 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2341 VkPipelineBindPoint bind_point,
2342 struct radv_descriptor_set *set,
2343 unsigned idx);
2344
2345 void
2346 radv_update_descriptor_sets(struct radv_device *device,
2347 struct radv_cmd_buffer *cmd_buffer,
2348 VkDescriptorSet overrideSet,
2349 uint32_t descriptorWriteCount,
2350 const VkWriteDescriptorSet *pDescriptorWrites,
2351 uint32_t descriptorCopyCount,
2352 const VkCopyDescriptorSet *pDescriptorCopies);
2353
2354 void
2355 radv_update_descriptor_set_with_template(struct radv_device *device,
2356 struct radv_cmd_buffer *cmd_buffer,
2357 struct radv_descriptor_set *set,
2358 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2359 const void *pData);
2360
2361 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2362 VkPipelineBindPoint pipelineBindPoint,
2363 VkPipelineLayout _layout,
2364 uint32_t set,
2365 uint32_t descriptorWriteCount,
2366 const VkWriteDescriptorSet *pDescriptorWrites);
2367
2368 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2369 struct radv_image *image,
2370 const VkImageSubresourceRange *range, uint32_t value);
2371
2372 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2373 struct radv_image *image,
2374 const VkImageSubresourceRange *range);
2375
2376 typedef enum {
2377 RADV_FENCE_NONE,
2378 RADV_FENCE_WINSYS,
2379 RADV_FENCE_SYNCOBJ,
2380 RADV_FENCE_WSI,
2381 } radv_fence_kind;
2382
2383 struct radv_fence_part {
2384 radv_fence_kind kind;
2385
2386 union {
2387 /* AMDGPU winsys fence. */
2388 struct radeon_winsys_fence *fence;
2389
2390 /* DRM syncobj handle for syncobj-based fences. */
2391 uint32_t syncobj;
2392
2393 /* WSI fence. */
2394 struct wsi_fence *fence_wsi;
2395 };
2396 };
2397
2398 struct radv_fence {
2399 struct vk_object_base base;
2400 struct radv_fence_part permanent;
2401 struct radv_fence_part temporary;
2402 };
2403
2404 /* radv_nir_to_llvm.c */
2405 struct radv_shader_args;
2406
2407 void llvm_compile_shader(struct radv_device *device,
2408 unsigned shader_count,
2409 struct nir_shader *const *shaders,
2410 struct radv_shader_binary **binary,
2411 struct radv_shader_args *args);
2412
2413 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2414 gl_shader_stage stage,
2415 const struct nir_shader *nir);
2416
2417 /* radv_shader_info.h */
2418 struct radv_shader_info;
2419 struct radv_shader_variant_key;
2420
2421 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2422 const struct radv_pipeline_layout *layout,
2423 const struct radv_shader_variant_key *key,
2424 struct radv_shader_info *info,
2425 bool use_llvm);
2426
2427 void radv_nir_shader_info_init(struct radv_shader_info *info);
2428
2429 /* radv_sqtt.c */
2430 struct radv_thread_trace_info {
2431 uint32_t cur_offset;
2432 uint32_t trace_status;
2433 union {
2434 uint32_t gfx9_write_counter;
2435 uint32_t gfx10_dropped_cntr;
2436 };
2437 };
2438
2439 struct radv_thread_trace_se {
2440 struct radv_thread_trace_info info;
2441 void *data_ptr;
2442 uint32_t shader_engine;
2443 uint32_t compute_unit;
2444 };
2445
2446 struct radv_thread_trace {
2447 uint32_t num_traces;
2448 struct radv_thread_trace_se traces[4];
2449 };
2450
2451 bool radv_thread_trace_init(struct radv_device *device);
2452 void radv_thread_trace_finish(struct radv_device *device);
2453 bool radv_begin_thread_trace(struct radv_queue *queue);
2454 bool radv_end_thread_trace(struct radv_queue *queue);
2455 bool radv_get_thread_trace(struct radv_queue *queue,
2456 struct radv_thread_trace *thread_trace);
2457 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2458 const void *data, uint32_t num_dwords);
2459
2460 /* radv_rgp.c */
2461 int radv_dump_thread_trace(struct radv_device *device,
2462 const struct radv_thread_trace *trace);
2463
2464 /* radv_sqtt_layer_.c */
2465 struct radv_barrier_data {
2466 union {
2467 struct {
2468 uint16_t depth_stencil_expand : 1;
2469 uint16_t htile_hiz_range_expand : 1;
2470 uint16_t depth_stencil_resummarize : 1;
2471 uint16_t dcc_decompress : 1;
2472 uint16_t fmask_decompress : 1;
2473 uint16_t fast_clear_eliminate : 1;
2474 uint16_t fmask_color_expand : 1;
2475 uint16_t init_mask_ram : 1;
2476 uint16_t reserved : 8;
2477 };
2478 uint16_t all;
2479 } layout_transitions;
2480 };
2481
2482 /**
2483 * Value for the reason field of an RGP barrier start marker originating from
2484 * the Vulkan client (does not include PAL-defined values). (Table 15)
2485 */
2486 enum rgp_barrier_reason {
2487 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2488
2489 /* External app-generated barrier reasons, i.e. API synchronization
2490 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2491 */
2492 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2493 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2494 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2495
2496 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2497 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2498 */
2499 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2500 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2501 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2502 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2503 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2504 };
2505
2506 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2507 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2508 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2509 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2510 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2511 VkImageAspectFlagBits aspects);
2512 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2513 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2514 enum rgp_barrier_reason reason);
2515 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2516 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2517 const struct radv_barrier_data *barrier);
2518
2519 struct radeon_winsys_sem;
2520
2521 uint64_t radv_get_current_time(void);
2522
2523 static inline uint32_t
2524 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2525 {
2526 switch (gl_prim) {
2527 case 0: /* GL_POINTS */
2528 return 1;
2529 case 1: /* GL_LINES */
2530 case 3: /* GL_LINE_STRIP */
2531 return 2;
2532 case 4: /* GL_TRIANGLES */
2533 case 5: /* GL_TRIANGLE_STRIP */
2534 return 3;
2535 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2536 return 4;
2537 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2538 return 6;
2539 case 7: /* GL_QUADS */
2540 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2541 default:
2542 assert(0);
2543 return 0;
2544 }
2545 }
2546
2547 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2548 const VkRenderPassBeginInfo *pRenderPassBegin);
2549 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2550
2551 static inline uint32_t si_translate_prim(unsigned topology)
2552 {
2553 switch (topology) {
2554 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2555 return V_008958_DI_PT_POINTLIST;
2556 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2557 return V_008958_DI_PT_LINELIST;
2558 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2559 return V_008958_DI_PT_LINESTRIP;
2560 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2561 return V_008958_DI_PT_TRILIST;
2562 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2563 return V_008958_DI_PT_TRISTRIP;
2564 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2565 return V_008958_DI_PT_TRIFAN;
2566 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2567 return V_008958_DI_PT_LINELIST_ADJ;
2568 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2569 return V_008958_DI_PT_LINESTRIP_ADJ;
2570 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2571 return V_008958_DI_PT_TRILIST_ADJ;
2572 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2573 return V_008958_DI_PT_TRISTRIP_ADJ;
2574 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2575 return V_008958_DI_PT_PATCH;
2576 default:
2577 assert(0);
2578 return 0;
2579 }
2580 }
2581
2582 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2583 {
2584 switch (op) {
2585 case VK_STENCIL_OP_KEEP:
2586 return V_02842C_STENCIL_KEEP;
2587 case VK_STENCIL_OP_ZERO:
2588 return V_02842C_STENCIL_ZERO;
2589 case VK_STENCIL_OP_REPLACE:
2590 return V_02842C_STENCIL_REPLACE_TEST;
2591 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2592 return V_02842C_STENCIL_ADD_CLAMP;
2593 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2594 return V_02842C_STENCIL_SUB_CLAMP;
2595 case VK_STENCIL_OP_INVERT:
2596 return V_02842C_STENCIL_INVERT;
2597 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2598 return V_02842C_STENCIL_ADD_WRAP;
2599 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2600 return V_02842C_STENCIL_SUB_WRAP;
2601 default:
2602 return 0;
2603 }
2604 }
2605
2606 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2607 \
2608 static inline struct __radv_type * \
2609 __radv_type ## _from_handle(__VkType _handle) \
2610 { \
2611 return (struct __radv_type *) _handle; \
2612 } \
2613 \
2614 static inline __VkType \
2615 __radv_type ## _to_handle(struct __radv_type *_obj) \
2616 { \
2617 return (__VkType) _obj; \
2618 }
2619
2620 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2621 \
2622 static inline struct __radv_type * \
2623 __radv_type ## _from_handle(__VkType _handle) \
2624 { \
2625 return (struct __radv_type *)(uintptr_t) _handle; \
2626 } \
2627 \
2628 static inline __VkType \
2629 __radv_type ## _to_handle(struct __radv_type *_obj) \
2630 { \
2631 return (__VkType)(uintptr_t) _obj; \
2632 }
2633
2634 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2635 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2636
2637 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2638 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2639 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2640 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2641 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2642
2643 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2644 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2645 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2646 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2656 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2657 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2658 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2659 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2660 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2661 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2662 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2663 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2664 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2665
2666 #endif /* RADV_PRIVATE_H */