src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 struct radeon_info;
  39 struct ac_surf_info;
  40 struct radeon_surf;
  41
  42 #define FREE(x) free(x)
  43
  44 enum radeon_bo_domain { /* bitfield */
  45         RADEON_DOMAIN_GTT  = 2,
  46         RADEON_DOMAIN_VRAM = 4,
  47         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51         RADEON_FLAG_GTT_WC =        (1 << 0),
  52         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54         RADEON_FLAG_VIRTUAL =       (1 << 3),
  55         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59         RADEON_USAGE_READ = 2,
  60         RADEON_USAGE_WRITE = 4,
  61         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  62 };
  63
  64 enum ring_type {
  65         RING_GFX = 0,
  66         RING_COMPUTE,
  67         RING_DMA,
  68         RING_UVD,
  69         RING_VCE,
  70         RING_LAST,
  71 };
  72
  73 struct radeon_winsys_cs {
  74         unsigned cdw;  /* Number of used dwords. */
  75         unsigned max_dw; /* Maximum number of dwords. */
  76         uint32_t *buf; /* The base pointer of the chunk. */
  77 };
  78
  79 #define RADEON_SURF_TYPE_MASK                   0xFF
  80 #define RADEON_SURF_TYPE_SHIFT                  0
  81 #define     RADEON_SURF_TYPE_1D                     0
  82 #define     RADEON_SURF_TYPE_2D                     1
  83 #define     RADEON_SURF_TYPE_3D                     2
  84 #define     RADEON_SURF_TYPE_CUBEMAP                3
  85 #define     RADEON_SURF_TYPE_1D_ARRAY               4
  86 #define     RADEON_SURF_TYPE_2D_ARRAY               5
  87 #define RADEON_SURF_MODE_MASK                   0xFF
  88 #define RADEON_SURF_MODE_SHIFT                  8
  89
  90 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
  91 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
  92 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
  93
  94 enum radeon_bo_layout {
  95         RADEON_LAYOUT_LINEAR = 0,
  96         RADEON_LAYOUT_TILED,
  97         RADEON_LAYOUT_SQUARETILED,
  98
  99         RADEON_LAYOUT_UNKNOWN
 100 };
 101
 102 /* Tiling info for display code, DRI sharing, and other data. */
 103 struct radeon_bo_metadata {
 104         /* Tiling flags describing the texture layout for display code
 105          * and DRI sharing.
 106          */
 107         union {
 108                 struct {
 109                         enum radeon_bo_layout   microtile;
 110                         enum radeon_bo_layout   macrotile;
 111                         unsigned                pipe_config;
 112                         unsigned                bankw;
 113                         unsigned                bankh;
 114                         unsigned                tile_split;
 115                         unsigned                mtilea;
 116                         unsigned                num_banks;
 117                         unsigned                stride;
 118                         bool                    scanout;
 119                 } legacy;
 120
 121                 struct {
 122                         /* surface flags */
 123                         unsigned swizzle_mode:5;
 124                 } gfx9;
 125         } u;
 126
 127         /* Additional metadata associated with the buffer, in bytes.
 128          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 129          * Supported by amdgpu only.
 130          */
 131         uint32_t                size_metadata;
 132         uint32_t                metadata[64];
 133 };
 134
 135 uint32_t syncobj_handle;
 136 struct radeon_winsys_bo;
 137 struct radeon_winsys_fence;
 138
 139 struct radv_winsys_sem_counts {
 140         uint32_t syncobj_count;
 141         uint32_t sem_count;
 142         uint32_t *syncobj;
 143         struct radeon_winsys_sem **sem;
 144 };
 145
 146 struct radv_winsys_sem_info {
 147         bool cs_emit_signal;
 148         bool cs_emit_wait;
 149         struct radv_winsys_sem_counts wait;
 150         struct radv_winsys_sem_counts signal;
 151 };
 152
 153 struct radeon_winsys {
 154         void (*destroy)(struct radeon_winsys *ws);
 155
 156         void (*query_info)(struct radeon_winsys *ws,
 157                            struct radeon_info *info);
 158
 159         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 160                                unsigned num_registers, uint32_t *out);
 161
 162         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 163                                                   uint64_t size,
 164                                                   unsigned alignment,
 165                                                   enum radeon_bo_domain domain,
 166                                                   enum radeon_bo_flag flags);
 167
 168         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 169         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 170
 171         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 172                                                    int fd,
 173                                                    unsigned *stride, unsigned *offset);
 174
 175         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 176                               struct radeon_winsys_bo *bo,
 177                               int *fd);
 178
 179         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 180
 181         uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
 182
 183         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 184                                     struct radeon_bo_metadata *md);
 185
 186         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 187                                     uint64_t offset, uint64_t size,
 188                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 189         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 190         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 191
 192         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 193                               enum ring_type ring_type, int ring_index);
 194
 195         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 196                                               enum ring_type ring_type);
 197
 198         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 199
 200         void (*cs_reset)(struct radeon_winsys_cs *cs);
 201
 202         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 203
 204         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 205
 206         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 207                          int queue_index,
 208                          struct radeon_winsys_cs **cs_array,
 209                          unsigned cs_count,
 210                          struct radeon_winsys_cs *initial_preamble_cs,
 211                          struct radeon_winsys_cs *continue_preamble_cs,
 212                          struct radv_winsys_sem_info *sem_info,
 213                          bool can_patch,
 214                          struct radeon_winsys_fence *fence);
 215
 216         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 217                               struct radeon_winsys_bo *bo,
 218                               uint8_t priority);
 219
 220         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 221                                     struct radeon_winsys_cs *child);
 222
 223         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
 224
 225         int (*surface_init)(struct radeon_winsys *ws,
 226                             const struct ac_surf_info *surf_info,
 227                             struct radeon_surf *surf);
 228
 229         int (*surface_best)(struct radeon_winsys *ws,
 230                             struct radeon_surf *surf);
 231
 232         struct radeon_winsys_fence *(*create_fence)();
 233         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 234         bool (*fence_wait)(struct radeon_winsys *ws,
 235                            struct radeon_winsys_fence *fence,
 236                            bool absolute,
 237                            uint64_t timeout);
 238
 239         /* old semaphores - non shareable */
 240         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 241         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 242
 243         /* new shareable sync objects */
 244         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 245         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 246
 247         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 248         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 249
 250 };
 251
 252 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 253 {
 254         cs->buf[cs->cdw++] = value;
 255 }
 256
 257 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 258                                      const uint32_t *values, unsigned count)
 259 {
 260         memcpy(cs->buf + cs->cdw, values, count * 4);
 261         cs->cdw += count;
 262 }
 263
 264 #endif /* RADV_RADEON_WINSYS_H */