src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include "main/macros.h"
  37 #include "amd_family.h"
  38
  39 struct radeon_info;
  40 struct ac_surf_info;
  41 struct radeon_surf;
  42
  43 #define FREE(x) free(x)
  44
  45 enum radeon_bo_domain { /* bitfield */
  46         RADEON_DOMAIN_GTT  = 2,
  47         RADEON_DOMAIN_VRAM = 4,
  48         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52         RADEON_FLAG_GTT_WC =        (1 << 0),
  53         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55         RADEON_FLAG_VIRTUAL =       (1 << 3),
  56         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  57         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  58         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  59         RADEON_FLAG_READ_ONLY =     (1 << 7),
  60 };
  61
  62 enum radeon_bo_usage { /* bitfield */
  63         RADEON_USAGE_READ = 2,
  64         RADEON_USAGE_WRITE = 4,
  65         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  66 };
  67
  68 enum ring_type {
  69         RING_GFX = 0,
  70         RING_COMPUTE,
  71         RING_DMA,
  72         RING_UVD,
  73         RING_VCE,
  74         RING_LAST,
  75 };
  76
  77 enum radeon_ctx_priority {
  78         RADEON_CTX_PRIORITY_INVALID = -1,
  79         RADEON_CTX_PRIORITY_LOW = 0,
  80         RADEON_CTX_PRIORITY_MEDIUM,
  81         RADEON_CTX_PRIORITY_HIGH,
  82         RADEON_CTX_PRIORITY_REALTIME,
  83 };
  84
  85 enum radeon_value_id {
  86         RADEON_TIMESTAMP,
  87         RADEON_NUM_BYTES_MOVED,
  88         RADEON_NUM_EVICTIONS,
  89         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  90         RADEON_VRAM_USAGE,
  91         RADEON_VRAM_VIS_USAGE,
  92         RADEON_GTT_USAGE,
  93         RADEON_GPU_TEMPERATURE,
  94         RADEON_CURRENT_SCLK,
  95         RADEON_CURRENT_MCLK,
  96 };
  97
  98 struct radeon_winsys_cs {
  99         unsigned cdw;  /* Number of used dwords. */
 100         unsigned max_dw; /* Maximum number of dwords. */
 101         uint32_t *buf; /* The base pointer of the chunk. */
 102 };
 103
 104 #define RADEON_SURF_TYPE_MASK                   0xFF
 105 #define RADEON_SURF_TYPE_SHIFT                  0
 106 #define     RADEON_SURF_TYPE_1D                     0
 107 #define     RADEON_SURF_TYPE_2D                     1
 108 #define     RADEON_SURF_TYPE_3D                     2
 109 #define     RADEON_SURF_TYPE_CUBEMAP                3
 110 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 111 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 112 #define RADEON_SURF_MODE_MASK                   0xFF
 113 #define RADEON_SURF_MODE_SHIFT                  8
 114
 115 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 116 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 117 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 118
 119 enum radeon_bo_layout {
 120         RADEON_LAYOUT_LINEAR = 0,
 121         RADEON_LAYOUT_TILED,
 122         RADEON_LAYOUT_SQUARETILED,
 123
 124         RADEON_LAYOUT_UNKNOWN
 125 };
 126
 127 /* Tiling info for display code, DRI sharing, and other data. */
 128 struct radeon_bo_metadata {
 129         /* Tiling flags describing the texture layout for display code
 130          * and DRI sharing.
 131          */
 132         union {
 133                 struct {
 134                         enum radeon_bo_layout   microtile;
 135                         enum radeon_bo_layout   macrotile;
 136                         unsigned                pipe_config;
 137                         unsigned                bankw;
 138                         unsigned                bankh;
 139                         unsigned                tile_split;
 140                         unsigned                mtilea;
 141                         unsigned                num_banks;
 142                         unsigned                stride;
 143                         bool                    scanout;
 144                 } legacy;
 145
 146                 struct {
 147                         /* surface flags */
 148                         unsigned swizzle_mode:5;
 149                 } gfx9;
 150         } u;
 151
 152         /* Additional metadata associated with the buffer, in bytes.
 153          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 154          * Supported by amdgpu only.
 155          */
 156         uint32_t                size_metadata;
 157         uint32_t                metadata[64];
 158 };
 159
 160 uint32_t syncobj_handle;
 161 struct radeon_winsys_fence;
 162
 163 struct radeon_winsys_bo {
 164         uint64_t va;
 165         bool is_local;
 166 };
 167 struct radv_winsys_sem_counts {
 168         uint32_t syncobj_count;
 169         uint32_t sem_count;
 170         uint32_t *syncobj;
 171         struct radeon_winsys_sem **sem;
 172 };
 173
 174 struct radv_winsys_sem_info {
 175         bool cs_emit_signal;
 176         bool cs_emit_wait;
 177         struct radv_winsys_sem_counts wait;
 178         struct radv_winsys_sem_counts signal;
 179 };
 180
 181 struct radeon_winsys {
 182         void (*destroy)(struct radeon_winsys *ws);
 183
 184         void (*query_info)(struct radeon_winsys *ws,
 185                            struct radeon_info *info);
 186
 187         uint64_t (*query_value)(struct radeon_winsys *ws,
 188                                 enum radeon_value_id value);
 189
 190         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 191                                unsigned num_registers, uint32_t *out);
 192
 193         const char *(*get_chip_name)(struct radeon_winsys *ws);
 194
 195         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 196                                                   uint64_t size,
 197                                                   unsigned alignment,
 198                                                   enum radeon_bo_domain domain,
 199                                                   enum radeon_bo_flag flags);
 200
 201         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 202         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 203
 204         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 205                                                     void *pointer,
 206                                                     uint64_t size);
 207
 208         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 209                                                    int fd,
 210                                                    unsigned *stride, unsigned *offset);
 211
 212         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 213                               struct radeon_winsys_bo *bo,
 214                               int *fd);
 215
 216         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 217
 218         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 219                                     struct radeon_bo_metadata *md);
 220
 221         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 222                                     uint64_t offset, uint64_t size,
 223                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 224         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 225                                                 enum radeon_ctx_priority priority);
 226         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 227
 228         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 229                               enum ring_type ring_type, int ring_index);
 230
 231         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 232                                               enum ring_type ring_type);
 233
 234         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 235
 236         void (*cs_reset)(struct radeon_winsys_cs *cs);
 237
 238         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 239
 240         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 241
 242         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 243                          int queue_index,
 244                          struct radeon_winsys_cs **cs_array,
 245                          unsigned cs_count,
 246                          struct radeon_winsys_cs *initial_preamble_cs,
 247                          struct radeon_winsys_cs *continue_preamble_cs,
 248                          struct radv_winsys_sem_info *sem_info,
 249                          bool can_patch,
 250                          struct radeon_winsys_fence *fence);
 251
 252         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 253                               struct radeon_winsys_bo *bo,
 254                               uint8_t priority);
 255
 256         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 257                                     struct radeon_winsys_cs *child);
 258
 259         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
 260
 261         int (*surface_init)(struct radeon_winsys *ws,
 262                             const struct ac_surf_info *surf_info,
 263                             struct radeon_surf *surf);
 264
 265         int (*surface_best)(struct radeon_winsys *ws,
 266                             struct radeon_surf *surf);
 267
 268         struct radeon_winsys_fence *(*create_fence)();
 269         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 270         bool (*fence_wait)(struct radeon_winsys *ws,
 271                            struct radeon_winsys_fence *fence,
 272                            bool absolute,
 273                            uint64_t timeout);
 274         bool (*fences_wait)(struct radeon_winsys *ws,
 275                             struct radeon_winsys_fence *const *fences,
 276                             uint32_t fence_count,
 277                             bool wait_all,
 278                             uint64_t timeout);
 279
 280         /* old semaphores - non shareable */
 281         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 282         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 283
 284         /* new shareable sync objects */
 285         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 286         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 287
 288         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 289         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 290         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 291                              bool wait_all, uint64_t timeout);
 292
 293         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 294         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 295
 296         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 297
 298         /* Note that this, unlike the normal import, uses an existing syncobj. */
 299         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 300
 301 };
 302
 303 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 304 {
 305         cs->buf[cs->cdw++] = value;
 306 }
 307
 308 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 309                                      const uint32_t *values, unsigned count)
 310 {
 311         memcpy(cs->buf + cs->cdw, values, count * 4);
 312         cs->cdw += count;
 313 }
 314
 315 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 316 {
 317         return bo->va;
 318 }
 319
 320 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 321                                       struct radeon_winsys_cs *cs,
 322                                       struct radeon_winsys_bo *bo,
 323                                       uint8_t priority)
 324 {
 325         if (bo->is_local)
 326                 return;
 327
 328         ws->cs_add_buffer(cs, bo, priority);
 329 }
 330
 331 #endif /* RADV_RADEON_WINSYS_H */