src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include "main/macros.h"
  37 #include "amd_family.h"
  38
  39 struct radeon_info;
  40 struct ac_surf_info;
  41 struct radeon_surf;
  42
  43 #define FREE(x) free(x)
  44
  45 enum radeon_bo_domain { /* bitfield */
  46         RADEON_DOMAIN_GTT  = 2,
  47         RADEON_DOMAIN_VRAM = 4,
  48         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52         RADEON_FLAG_GTT_WC =        (1 << 0),
  53         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55         RADEON_FLAG_VIRTUAL =       (1 << 3),
  56         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  57         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  58         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  59         RADEON_FLAG_READ_ONLY =     (1 << 7),
  60         RADEON_FLAG_32BIT =         (1 << 8),
  61 };
  62
  63 enum radeon_bo_usage { /* bitfield */
  64         RADEON_USAGE_READ = 2,
  65         RADEON_USAGE_WRITE = 4,
  66         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  67 };
  68
  69 enum ring_type {
  70         RING_GFX = 0,
  71         RING_COMPUTE,
  72         RING_DMA,
  73         RING_UVD,
  74         RING_VCE,
  75         RING_LAST,
  76 };
  77
  78 enum radeon_ctx_priority {
  79         RADEON_CTX_PRIORITY_INVALID = -1,
  80         RADEON_CTX_PRIORITY_LOW = 0,
  81         RADEON_CTX_PRIORITY_MEDIUM,
  82         RADEON_CTX_PRIORITY_HIGH,
  83         RADEON_CTX_PRIORITY_REALTIME,
  84 };
  85
  86 enum radeon_value_id {
  87         RADEON_ALLOCATED_VRAM,
  88         RADEON_ALLOCATED_VRAM_VIS,
  89         RADEON_ALLOCATED_GTT,
  90         RADEON_TIMESTAMP,
  91         RADEON_NUM_BYTES_MOVED,
  92         RADEON_NUM_EVICTIONS,
  93         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  94         RADEON_VRAM_USAGE,
  95         RADEON_VRAM_VIS_USAGE,
  96         RADEON_GTT_USAGE,
  97         RADEON_GPU_TEMPERATURE,
  98         RADEON_CURRENT_SCLK,
  99         RADEON_CURRENT_MCLK,
 100 };
 101
 102 struct radeon_cmdbuf {
 103         unsigned cdw;  /* Number of used dwords. */
 104         unsigned max_dw; /* Maximum number of dwords. */
 105         uint32_t *buf; /* The base pointer of the chunk. */
 106 };
 107
 108 #define RADEON_SURF_TYPE_MASK                   0xFF
 109 #define RADEON_SURF_TYPE_SHIFT                  0
 110 #define     RADEON_SURF_TYPE_1D                     0
 111 #define     RADEON_SURF_TYPE_2D                     1
 112 #define     RADEON_SURF_TYPE_3D                     2
 113 #define     RADEON_SURF_TYPE_CUBEMAP                3
 114 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 115 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 116 #define RADEON_SURF_MODE_MASK                   0xFF
 117 #define RADEON_SURF_MODE_SHIFT                  8
 118
 119 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 120 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 121 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 122
 123 enum radeon_bo_layout {
 124         RADEON_LAYOUT_LINEAR = 0,
 125         RADEON_LAYOUT_TILED,
 126         RADEON_LAYOUT_SQUARETILED,
 127
 128         RADEON_LAYOUT_UNKNOWN
 129 };
 130
 131 /* Tiling info for display code, DRI sharing, and other data. */
 132 struct radeon_bo_metadata {
 133         /* Tiling flags describing the texture layout for display code
 134          * and DRI sharing.
 135          */
 136         union {
 137                 struct {
 138                         enum radeon_bo_layout   microtile;
 139                         enum radeon_bo_layout   macrotile;
 140                         unsigned                pipe_config;
 141                         unsigned                bankw;
 142                         unsigned                bankh;
 143                         unsigned                tile_split;
 144                         unsigned                mtilea;
 145                         unsigned                num_banks;
 146                         unsigned                stride;
 147                         bool                    scanout;
 148                 } legacy;
 149
 150                 struct {
 151                         /* surface flags */
 152                         unsigned swizzle_mode:5;
 153                 } gfx9;
 154         } u;
 155
 156         /* Additional metadata associated with the buffer, in bytes.
 157          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 158          * Supported by amdgpu only.
 159          */
 160         uint32_t                size_metadata;
 161         uint32_t                metadata[64];
 162 };
 163
 164 uint32_t syncobj_handle;
 165 struct radeon_winsys_fence;
 166
 167 struct radeon_winsys_bo {
 168         uint64_t va;
 169         bool is_local;
 170         bool vram_cpu_access;
 171 };
 172 struct radv_winsys_sem_counts {
 173         uint32_t syncobj_count;
 174         uint32_t sem_count;
 175         uint32_t *syncobj;
 176         struct radeon_winsys_sem **sem;
 177 };
 178
 179 struct radv_winsys_sem_info {
 180         bool cs_emit_signal;
 181         bool cs_emit_wait;
 182         struct radv_winsys_sem_counts wait;
 183         struct radv_winsys_sem_counts signal;
 184 };
 185
 186 struct radv_winsys_bo_list {
 187         struct radeon_winsys_bo **bos;
 188         unsigned count;
 189 };
 190
 191 /* Kernel effectively allows 0-31. This sets some priorities for fixed
 192  * functionality buffers */
 193 enum {
 194         RADV_BO_PRIORITY_APPLICATION_MAX = 28,
 195
 196         /* virtual buffers have 0 priority since the priority is not used. */
 197         RADV_BO_PRIORITY_VIRTUAL = 0,
 198
 199         /* This should be considerably lower than most of the stuff below,
 200          * but how much lower is hard to say since we don't know application
 201          * assignments. Put it pretty high since it is GTT anyway. */
 202         RADV_BO_PRIORITY_QUERY_POOL = 29,
 203
 204         RADV_BO_PRIORITY_DESCRIPTOR = 30,
 205         RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
 206         RADV_BO_PRIORITY_FENCE = 30,
 207         RADV_BO_PRIORITY_SHADER = 31,
 208         RADV_BO_PRIORITY_SCRATCH = 31,
 209         RADV_BO_PRIORITY_CS = 31,
 210 };
 211
 212 struct radeon_winsys {
 213         void (*destroy)(struct radeon_winsys *ws);
 214
 215         void (*query_info)(struct radeon_winsys *ws,
 216                            struct radeon_info *info);
 217
 218         uint64_t (*query_value)(struct radeon_winsys *ws,
 219                                 enum radeon_value_id value);
 220
 221         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 222                                unsigned num_registers, uint32_t *out);
 223
 224         const char *(*get_chip_name)(struct radeon_winsys *ws);
 225
 226         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 227                                                   uint64_t size,
 228                                                   unsigned alignment,
 229                                                   enum radeon_bo_domain domain,
 230                                                   enum radeon_bo_flag flags,
 231                                                   unsigned priority);
 232
 233         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 234         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 235
 236         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 237                                                     void *pointer,
 238                                                     uint64_t size,
 239                                                     unsigned priority);
 240
 241         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 242                                                    int fd,
 243                                                    unsigned priority,
 244                                                    unsigned *stride, unsigned *offset);
 245
 246         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 247                               struct radeon_winsys_bo *bo,
 248                               int *fd);
 249
 250         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 251
 252         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 253                                     struct radeon_bo_metadata *md);
 254         void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
 255                                     struct radeon_bo_metadata *md);
 256
 257         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 258                                     uint64_t offset, uint64_t size,
 259                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 260         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 261                                                 enum radeon_ctx_priority priority);
 262         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 263
 264         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 265                               enum ring_type ring_type, int ring_index);
 266
 267         struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
 268                                               enum ring_type ring_type);
 269
 270         void (*cs_destroy)(struct radeon_cmdbuf *cs);
 271
 272         void (*cs_reset)(struct radeon_cmdbuf *cs);
 273
 274         bool (*cs_finalize)(struct radeon_cmdbuf *cs);
 275
 276         void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
 277
 278         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 279                          int queue_index,
 280                          struct radeon_cmdbuf **cs_array,
 281                          unsigned cs_count,
 282                          struct radeon_cmdbuf *initial_preamble_cs,
 283                          struct radeon_cmdbuf *continue_preamble_cs,
 284                          struct radv_winsys_sem_info *sem_info,
 285                          const struct radv_winsys_bo_list *bo_list, /* optional */
 286                          bool can_patch,
 287                          struct radeon_winsys_fence *fence);
 288
 289         void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 290                               struct radeon_winsys_bo *bo);
 291
 292         void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 293                                     struct radeon_cmdbuf *child);
 294
 295         void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
 296
 297         int (*surface_init)(struct radeon_winsys *ws,
 298                             const struct ac_surf_info *surf_info,
 299                             struct radeon_surf *surf);
 300
 301         struct radeon_winsys_fence *(*create_fence)();
 302         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 303         bool (*fence_wait)(struct radeon_winsys *ws,
 304                            struct radeon_winsys_fence *fence,
 305                            bool absolute,
 306                            uint64_t timeout);
 307         bool (*fences_wait)(struct radeon_winsys *ws,
 308                             struct radeon_winsys_fence *const *fences,
 309                             uint32_t fence_count,
 310                             bool wait_all,
 311                             uint64_t timeout);
 312
 313         /* old semaphores - non shareable */
 314         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 315         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 316
 317         /* new shareable sync objects */
 318         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 319         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 320
 321         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 322         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 323         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 324                              bool wait_all, uint64_t timeout);
 325
 326         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 327         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 328
 329         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 330
 331         /* Note that this, unlike the normal import, uses an existing syncobj. */
 332         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 333
 334 };
 335
 336 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 337 {
 338         cs->buf[cs->cdw++] = value;
 339 }
 340
 341 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 342                                      const uint32_t *values, unsigned count)
 343 {
 344         memcpy(cs->buf + cs->cdw, values, count * 4);
 345         cs->cdw += count;
 346 }
 347
 348 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 349 {
 350         return bo->va;
 351 }
 352
 353 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 354                                       struct radeon_cmdbuf *cs,
 355                                       struct radeon_winsys_bo *bo)
 356 {
 357         if (bo->is_local)
 358                 return;
 359
 360         ws->cs_add_buffer(cs, bo);
 361 }
 362
 363 #endif /* RADV_RADEON_WINSYS_H */