src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <vulkan/vulkan.h>
  38 #include "amd_family.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_math.h"
  41
  42 struct radeon_info;
  43 struct ac_surf_info;
  44 struct radeon_surf;
  45
  46 enum radeon_bo_domain { /* bitfield */
  47         RADEON_DOMAIN_GTT  = 2,
  48         RADEON_DOMAIN_VRAM = 4,
  49         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
  50         RADEON_DOMAIN_GDS = 8,
  51         RADEON_DOMAIN_OA = 16,
  52 };
  53
  54 enum radeon_bo_flag { /* bitfield */
  55         RADEON_FLAG_GTT_WC =        (1 << 0),
  56         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  57         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  58         RADEON_FLAG_VIRTUAL =       (1 << 3),
  59         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  60         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  61         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  62         RADEON_FLAG_READ_ONLY =     (1 << 7),
  63         RADEON_FLAG_32BIT =         (1 << 8),
  64         RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
  65         RADEON_FLAG_ZERO_VRAM = (1 << 10),
  66 };
  67
  68 enum radeon_bo_usage { /* bitfield */
  69         RADEON_USAGE_READ = 2,
  70         RADEON_USAGE_WRITE = 4,
  71         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  72 };
  73
  74 enum radeon_ctx_priority {
  75         RADEON_CTX_PRIORITY_INVALID = -1,
  76         RADEON_CTX_PRIORITY_LOW = 0,
  77         RADEON_CTX_PRIORITY_MEDIUM,
  78         RADEON_CTX_PRIORITY_HIGH,
  79         RADEON_CTX_PRIORITY_REALTIME,
  80 };
  81
  82 enum radeon_value_id {
  83         RADEON_ALLOCATED_VRAM,
  84         RADEON_ALLOCATED_VRAM_VIS,
  85         RADEON_ALLOCATED_GTT,
  86         RADEON_TIMESTAMP,
  87         RADEON_NUM_BYTES_MOVED,
  88         RADEON_NUM_EVICTIONS,
  89         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  90         RADEON_VRAM_USAGE,
  91         RADEON_VRAM_VIS_USAGE,
  92         RADEON_GTT_USAGE,
  93         RADEON_GPU_TEMPERATURE,
  94         RADEON_CURRENT_SCLK,
  95         RADEON_CURRENT_MCLK,
  96 };
  97
  98 struct radeon_cmdbuf {
  99         unsigned cdw;  /* Number of used dwords. */
 100         unsigned max_dw; /* Maximum number of dwords. */
 101         uint32_t *buf; /* The base pointer of the chunk. */
 102 };
 103
 104 #define RADEON_SURF_TYPE_MASK                   0xFF
 105 #define RADEON_SURF_TYPE_SHIFT                  0
 106 #define     RADEON_SURF_TYPE_1D                     0
 107 #define     RADEON_SURF_TYPE_2D                     1
 108 #define     RADEON_SURF_TYPE_3D                     2
 109 #define     RADEON_SURF_TYPE_CUBEMAP                3
 110 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 111 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 112 #define RADEON_SURF_MODE_MASK                   0xFF
 113 #define RADEON_SURF_MODE_SHIFT                  8
 114
 115 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 116 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 117 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 118
 119 enum radeon_bo_layout {
 120         RADEON_LAYOUT_LINEAR = 0,
 121         RADEON_LAYOUT_TILED,
 122         RADEON_LAYOUT_SQUARETILED,
 123
 124         RADEON_LAYOUT_UNKNOWN
 125 };
 126
 127 /* Tiling info for display code, DRI sharing, and other data. */
 128 struct radeon_bo_metadata {
 129         /* Tiling flags describing the texture layout for display code
 130          * and DRI sharing.
 131          */
 132         union {
 133                 struct {
 134                         enum radeon_bo_layout   microtile;
 135                         enum radeon_bo_layout   macrotile;
 136                         unsigned                pipe_config;
 137                         unsigned                bankw;
 138                         unsigned                bankh;
 139                         unsigned                tile_split;
 140                         unsigned                mtilea;
 141                         unsigned                num_banks;
 142                         unsigned                stride;
 143                         bool                    scanout;
 144                 } legacy;
 145
 146                 struct {
 147                         /* surface flags */
 148                         unsigned swizzle_mode:5;
 149                         bool scanout;
 150                 } gfx9;
 151         } u;
 152
 153         /* Additional metadata associated with the buffer, in bytes.
 154          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 155          * Supported by amdgpu only.
 156          */
 157         uint32_t                size_metadata;
 158         uint32_t                metadata[64];
 159 };
 160
 161 struct radeon_winsys_fence;
 162 struct radeon_winsys_ctx;
 163
 164 struct radeon_winsys_bo {
 165         uint64_t va;
 166         bool is_local;
 167         bool vram_no_cpu_access;
 168 };
 169 struct radv_winsys_sem_counts {
 170         uint32_t syncobj_count;
 171         uint32_t sem_count;
 172         uint32_t *syncobj;
 173         struct radeon_winsys_sem **sem;
 174 };
 175
 176 struct radv_winsys_sem_info {
 177         bool cs_emit_signal;
 178         bool cs_emit_wait;
 179         struct radv_winsys_sem_counts wait;
 180         struct radv_winsys_sem_counts signal;
 181 };
 182
 183 struct radv_winsys_bo_list {
 184         struct radeon_winsys_bo **bos;
 185         unsigned count;
 186 };
 187
 188 /* Kernel effectively allows 0-31. This sets some priorities for fixed
 189  * functionality buffers */
 190 enum {
 191         RADV_BO_PRIORITY_APPLICATION_MAX = 28,
 192
 193         /* virtual buffers have 0 priority since the priority is not used. */
 194         RADV_BO_PRIORITY_VIRTUAL = 0,
 195
 196         /* This should be considerably lower than most of the stuff below,
 197          * but how much lower is hard to say since we don't know application
 198          * assignments. Put it pretty high since it is GTT anyway. */
 199         RADV_BO_PRIORITY_QUERY_POOL = 29,
 200
 201         RADV_BO_PRIORITY_DESCRIPTOR = 30,
 202         RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
 203         RADV_BO_PRIORITY_FENCE = 30,
 204         RADV_BO_PRIORITY_SHADER = 31,
 205         RADV_BO_PRIORITY_SCRATCH = 31,
 206         RADV_BO_PRIORITY_CS = 31,
 207 };
 208
 209 struct radeon_winsys {
 210         void (*destroy)(struct radeon_winsys *ws);
 211
 212         void (*query_info)(struct radeon_winsys *ws,
 213                            struct radeon_info *info);
 214
 215         uint64_t (*query_value)(struct radeon_winsys *ws,
 216                                 enum radeon_value_id value);
 217
 218         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 219                                unsigned num_registers, uint32_t *out);
 220
 221         const char *(*get_chip_name)(struct radeon_winsys *ws);
 222
 223         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 224                                                   uint64_t size,
 225                                                   unsigned alignment,
 226                                                   enum radeon_bo_domain domain,
 227                                                   enum radeon_bo_flag flags,
 228                                                   unsigned priority);
 229
 230         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 231         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 232
 233         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 234                                                     void *pointer,
 235                                                     uint64_t size,
 236                                                     unsigned priority);
 237
 238         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 239                                                    int fd,
 240                                                    unsigned priority,
 241                                                    uint64_t *alloc_size);
 242
 243         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 244                               struct radeon_winsys_bo *bo,
 245                               int *fd);
 246
 247         bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd,
 248                                          enum radeon_bo_domain *domains,
 249                                          enum radeon_bo_flag *flags);
 250
 251         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 252
 253         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 254                                     struct radeon_bo_metadata *md);
 255         void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
 256                                     struct radeon_bo_metadata *md);
 257
 258         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 259                                     uint64_t offset, uint64_t size,
 260                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 261         VkResult (*ctx_create)(struct radeon_winsys *ws,
 262                                enum radeon_ctx_priority priority,
 263                                struct radeon_winsys_ctx **ctx);
 264         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 265
 266         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 267                               enum ring_type ring_type, int ring_index);
 268
 269         struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
 270                                               enum ring_type ring_type);
 271
 272         void (*cs_destroy)(struct radeon_cmdbuf *cs);
 273
 274         void (*cs_reset)(struct radeon_cmdbuf *cs);
 275
 276         bool (*cs_finalize)(struct radeon_cmdbuf *cs);
 277
 278         void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
 279
 280         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 281                          int queue_index,
 282                          struct radeon_cmdbuf **cs_array,
 283                          unsigned cs_count,
 284                          struct radeon_cmdbuf *initial_preamble_cs,
 285                          struct radeon_cmdbuf *continue_preamble_cs,
 286                          struct radv_winsys_sem_info *sem_info,
 287                          const struct radv_winsys_bo_list *bo_list, /* optional */
 288                          bool can_patch,
 289                          struct radeon_winsys_fence *fence);
 290
 291         void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 292                               struct radeon_winsys_bo *bo);
 293
 294         void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 295                                     struct radeon_cmdbuf *child);
 296
 297         void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
 298
 299         int (*surface_init)(struct radeon_winsys *ws,
 300                             const struct ac_surf_info *surf_info,
 301                             struct radeon_surf *surf);
 302
 303         struct radeon_winsys_fence *(*create_fence)();
 304         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 305         void (*reset_fence)(struct radeon_winsys_fence *fence);
 306         void (*signal_fence)(struct radeon_winsys_fence *fence);
 307         bool (*is_fence_waitable)(struct radeon_winsys_fence *fence);
 308         bool (*fence_wait)(struct radeon_winsys *ws,
 309                            struct radeon_winsys_fence *fence,
 310                            bool absolute,
 311                            uint64_t timeout);
 312         bool (*fences_wait)(struct radeon_winsys *ws,
 313                             struct radeon_winsys_fence *const *fences,
 314                             uint32_t fence_count,
 315                             bool wait_all,
 316                             uint64_t timeout);
 317
 318         /* old semaphores - non shareable */
 319         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 320         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 321
 322         /* new shareable sync objects */
 323         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 324         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 325
 326         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 327         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 328         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 329                              bool wait_all, uint64_t timeout);
 330
 331         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 332         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 333
 334         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 335
 336         /* Note that this, unlike the normal import, uses an existing syncobj. */
 337         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 338
 339 };
 340
 341 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 342 {
 343         cs->buf[cs->cdw++] = value;
 344 }
 345
 346 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 347                                      const uint32_t *values, unsigned count)
 348 {
 349         memcpy(cs->buf + cs->cdw, values, count * 4);
 350         cs->cdw += count;
 351 }
 352
 353 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 354 {
 355         return bo->va;
 356 }
 357
 358 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 359                                       struct radeon_cmdbuf *cs,
 360                                       struct radeon_winsys_bo *bo)
 361 {
 362         if (bo->is_local)
 363                 return;
 364
 365         ws->cs_add_buffer(cs, bo);
 366 }
 367
 368 #endif /* RADV_RADEON_WINSYS_H */