src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 struct radeon_info;
  39 struct ac_surf_info;
  40 struct radeon_surf;
  41
  42 #define FREE(x) free(x)
  43
  44 enum radeon_bo_domain { /* bitfield */
  45         RADEON_DOMAIN_GTT  = 2,
  46         RADEON_DOMAIN_VRAM = 4,
  47         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51         RADEON_FLAG_GTT_WC =        (1 << 0),
  52         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54         RADEON_FLAG_VIRTUAL =       (1 << 3),
  55         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  56         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  57         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  58 };
  59
  60 enum radeon_bo_usage { /* bitfield */
  61         RADEON_USAGE_READ = 2,
  62         RADEON_USAGE_WRITE = 4,
  63         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  64 };
  65
  66 enum ring_type {
  67         RING_GFX = 0,
  68         RING_COMPUTE,
  69         RING_DMA,
  70         RING_UVD,
  71         RING_VCE,
  72         RING_LAST,
  73 };
  74
  75 enum radeon_ctx_priority {
  76         RADEON_CTX_PRIORITY_INVALID = -1,
  77         RADEON_CTX_PRIORITY_LOW = 0,
  78         RADEON_CTX_PRIORITY_MEDIUM,
  79         RADEON_CTX_PRIORITY_HIGH,
  80         RADEON_CTX_PRIORITY_REALTIME,
  81 };
  82
  83 struct radeon_winsys_cs {
  84         unsigned cdw;  /* Number of used dwords. */
  85         unsigned max_dw; /* Maximum number of dwords. */
  86         uint32_t *buf; /* The base pointer of the chunk. */
  87 };
  88
  89 #define RADEON_SURF_TYPE_MASK                   0xFF
  90 #define RADEON_SURF_TYPE_SHIFT                  0
  91 #define     RADEON_SURF_TYPE_1D                     0
  92 #define     RADEON_SURF_TYPE_2D                     1
  93 #define     RADEON_SURF_TYPE_3D                     2
  94 #define     RADEON_SURF_TYPE_CUBEMAP                3
  95 #define     RADEON_SURF_TYPE_1D_ARRAY               4
  96 #define     RADEON_SURF_TYPE_2D_ARRAY               5
  97 #define RADEON_SURF_MODE_MASK                   0xFF
  98 #define RADEON_SURF_MODE_SHIFT                  8
  99
 100 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 101 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 102 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 103
 104 enum radeon_bo_layout {
 105         RADEON_LAYOUT_LINEAR = 0,
 106         RADEON_LAYOUT_TILED,
 107         RADEON_LAYOUT_SQUARETILED,
 108
 109         RADEON_LAYOUT_UNKNOWN
 110 };
 111
 112 /* Tiling info for display code, DRI sharing, and other data. */
 113 struct radeon_bo_metadata {
 114         /* Tiling flags describing the texture layout for display code
 115          * and DRI sharing.
 116          */
 117         union {
 118                 struct {
 119                         enum radeon_bo_layout   microtile;
 120                         enum radeon_bo_layout   macrotile;
 121                         unsigned                pipe_config;
 122                         unsigned                bankw;
 123                         unsigned                bankh;
 124                         unsigned                tile_split;
 125                         unsigned                mtilea;
 126                         unsigned                num_banks;
 127                         unsigned                stride;
 128                         bool                    scanout;
 129                 } legacy;
 130
 131                 struct {
 132                         /* surface flags */
 133                         unsigned swizzle_mode:5;
 134                 } gfx9;
 135         } u;
 136
 137         /* Additional metadata associated with the buffer, in bytes.
 138          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 139          * Supported by amdgpu only.
 140          */
 141         uint32_t                size_metadata;
 142         uint32_t                metadata[64];
 143 };
 144
 145 uint32_t syncobj_handle;
 146 struct radeon_winsys_fence;
 147
 148 struct radeon_winsys_bo {
 149         uint64_t va;
 150 };
 151 struct radv_winsys_sem_counts {
 152         uint32_t syncobj_count;
 153         uint32_t sem_count;
 154         uint32_t *syncobj;
 155         struct radeon_winsys_sem **sem;
 156 };
 157
 158 struct radv_winsys_sem_info {
 159         bool cs_emit_signal;
 160         bool cs_emit_wait;
 161         struct radv_winsys_sem_counts wait;
 162         struct radv_winsys_sem_counts signal;
 163 };
 164
 165 struct radeon_winsys {
 166         void (*destroy)(struct radeon_winsys *ws);
 167
 168         void (*query_info)(struct radeon_winsys *ws,
 169                            struct radeon_info *info);
 170
 171         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 172                                unsigned num_registers, uint32_t *out);
 173
 174         const char *(*get_chip_name)(struct radeon_winsys *ws);
 175
 176         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 177                                                   uint64_t size,
 178                                                   unsigned alignment,
 179                                                   enum radeon_bo_domain domain,
 180                                                   enum radeon_bo_flag flags);
 181
 182         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 183         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 184
 185         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 186                                                    int fd,
 187                                                    unsigned *stride, unsigned *offset);
 188
 189         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 190                               struct radeon_winsys_bo *bo,
 191                               int *fd);
 192
 193         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 194
 195         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 196                                     struct radeon_bo_metadata *md);
 197
 198         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 199                                     uint64_t offset, uint64_t size,
 200                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 201         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 202                                                 enum radeon_ctx_priority priority);
 203         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 204
 205         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 206                               enum ring_type ring_type, int ring_index);
 207
 208         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 209                                               enum ring_type ring_type);
 210
 211         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 212
 213         void (*cs_reset)(struct radeon_winsys_cs *cs);
 214
 215         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 216
 217         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 218
 219         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 220                          int queue_index,
 221                          struct radeon_winsys_cs **cs_array,
 222                          unsigned cs_count,
 223                          struct radeon_winsys_cs *initial_preamble_cs,
 224                          struct radeon_winsys_cs *continue_preamble_cs,
 225                          struct radv_winsys_sem_info *sem_info,
 226                          bool can_patch,
 227                          struct radeon_winsys_fence *fence);
 228
 229         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 230                               struct radeon_winsys_bo *bo,
 231                               uint8_t priority);
 232
 233         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 234                                     struct radeon_winsys_cs *child);
 235
 236         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
 237
 238         int (*surface_init)(struct radeon_winsys *ws,
 239                             const struct ac_surf_info *surf_info,
 240                             struct radeon_surf *surf);
 241
 242         int (*surface_best)(struct radeon_winsys *ws,
 243                             struct radeon_surf *surf);
 244
 245         struct radeon_winsys_fence *(*create_fence)();
 246         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 247         bool (*fence_wait)(struct radeon_winsys *ws,
 248                            struct radeon_winsys_fence *fence,
 249                            bool absolute,
 250                            uint64_t timeout);
 251
 252         /* old semaphores - non shareable */
 253         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 254         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 255
 256         /* new shareable sync objects */
 257         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 258         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 259
 260         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 261         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 262
 263 };
 264
 265 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 266 {
 267         cs->buf[cs->cdw++] = value;
 268 }
 269
 270 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 271                                      const uint32_t *values, unsigned count)
 272 {
 273         memcpy(cs->buf + cs->cdw, values, count * 4);
 274         cs->cdw += count;
 275 }
 276
 277 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 278 {
 279         return bo->va;
 280 }
 281
 282 #endif /* RADV_RADEON_WINSYS_H */