src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 struct radeon_info;
  39 struct ac_surf_info;
  40 struct radeon_surf;
  41
  42 #define FREE(x) free(x)
  43
  44 enum radeon_bo_domain { /* bitfield */
  45         RADEON_DOMAIN_GTT  = 2,
  46         RADEON_DOMAIN_VRAM = 4,
  47         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51         RADEON_FLAG_GTT_WC =        (1 << 0),
  52         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54         RADEON_FLAG_VIRTUAL =       (1 << 3),
  55         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  56         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  57         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  58 };
  59
  60 enum radeon_bo_usage { /* bitfield */
  61         RADEON_USAGE_READ = 2,
  62         RADEON_USAGE_WRITE = 4,
  63         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  64 };
  65
  66 enum ring_type {
  67         RING_GFX = 0,
  68         RING_COMPUTE,
  69         RING_DMA,
  70         RING_UVD,
  71         RING_VCE,
  72         RING_LAST,
  73 };
  74
  75 enum radeon_ctx_priority {
  76         RADEON_CTX_PRIORITY_INVALID = -1,
  77         RADEON_CTX_PRIORITY_LOW = 0,
  78         RADEON_CTX_PRIORITY_MEDIUM,
  79         RADEON_CTX_PRIORITY_HIGH,
  80         RADEON_CTX_PRIORITY_REALTIME,
  81 };
  82
  83 enum radeon_value_id {
  84         RADEON_TIMESTAMP,
  85         RADEON_NUM_BYTES_MOVED,
  86         RADEON_NUM_EVICTIONS,
  87         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  88         RADEON_VRAM_USAGE,
  89         RADEON_VRAM_VIS_USAGE,
  90         RADEON_GTT_USAGE,
  91         RADEON_GPU_TEMPERATURE,
  92         RADEON_CURRENT_SCLK,
  93         RADEON_CURRENT_MCLK,
  94 };
  95
  96 struct radeon_winsys_cs {
  97         unsigned cdw;  /* Number of used dwords. */
  98         unsigned max_dw; /* Maximum number of dwords. */
  99         uint32_t *buf; /* The base pointer of the chunk. */
 100 };
 101
 102 #define RADEON_SURF_TYPE_MASK                   0xFF
 103 #define RADEON_SURF_TYPE_SHIFT                  0
 104 #define     RADEON_SURF_TYPE_1D                     0
 105 #define     RADEON_SURF_TYPE_2D                     1
 106 #define     RADEON_SURF_TYPE_3D                     2
 107 #define     RADEON_SURF_TYPE_CUBEMAP                3
 108 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 109 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 110 #define RADEON_SURF_MODE_MASK                   0xFF
 111 #define RADEON_SURF_MODE_SHIFT                  8
 112
 113 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 114 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 115 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 116
 117 enum radeon_bo_layout {
 118         RADEON_LAYOUT_LINEAR = 0,
 119         RADEON_LAYOUT_TILED,
 120         RADEON_LAYOUT_SQUARETILED,
 121
 122         RADEON_LAYOUT_UNKNOWN
 123 };
 124
 125 /* Tiling info for display code, DRI sharing, and other data. */
 126 struct radeon_bo_metadata {
 127         /* Tiling flags describing the texture layout for display code
 128          * and DRI sharing.
 129          */
 130         union {
 131                 struct {
 132                         enum radeon_bo_layout   microtile;
 133                         enum radeon_bo_layout   macrotile;
 134                         unsigned                pipe_config;
 135                         unsigned                bankw;
 136                         unsigned                bankh;
 137                         unsigned                tile_split;
 138                         unsigned                mtilea;
 139                         unsigned                num_banks;
 140                         unsigned                stride;
 141                         bool                    scanout;
 142                 } legacy;
 143
 144                 struct {
 145                         /* surface flags */
 146                         unsigned swizzle_mode:5;
 147                 } gfx9;
 148         } u;
 149
 150         /* Additional metadata associated with the buffer, in bytes.
 151          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 152          * Supported by amdgpu only.
 153          */
 154         uint32_t                size_metadata;
 155         uint32_t                metadata[64];
 156 };
 157
 158 uint32_t syncobj_handle;
 159 struct radeon_winsys_fence;
 160
 161 struct radeon_winsys_bo {
 162         uint64_t va;
 163         bool is_local;
 164 };
 165 struct radv_winsys_sem_counts {
 166         uint32_t syncobj_count;
 167         uint32_t sem_count;
 168         uint32_t *syncobj;
 169         struct radeon_winsys_sem **sem;
 170 };
 171
 172 struct radv_winsys_sem_info {
 173         bool cs_emit_signal;
 174         bool cs_emit_wait;
 175         struct radv_winsys_sem_counts wait;
 176         struct radv_winsys_sem_counts signal;
 177 };
 178
 179 struct radeon_winsys {
 180         void (*destroy)(struct radeon_winsys *ws);
 181
 182         void (*query_info)(struct radeon_winsys *ws,
 183                            struct radeon_info *info);
 184
 185         uint64_t (*query_value)(struct radeon_winsys *ws,
 186                                 enum radeon_value_id value);
 187
 188         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 189                                unsigned num_registers, uint32_t *out);
 190
 191         const char *(*get_chip_name)(struct radeon_winsys *ws);
 192
 193         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 194                                                   uint64_t size,
 195                                                   unsigned alignment,
 196                                                   enum radeon_bo_domain domain,
 197                                                   enum radeon_bo_flag flags);
 198
 199         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 200         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 201
 202         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 203                                                    int fd,
 204                                                    unsigned *stride, unsigned *offset);
 205
 206         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 207                               struct radeon_winsys_bo *bo,
 208                               int *fd);
 209
 210         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 211
 212         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 213                                     struct radeon_bo_metadata *md);
 214
 215         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 216                                     uint64_t offset, uint64_t size,
 217                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 218         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 219                                                 enum radeon_ctx_priority priority);
 220         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 221
 222         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 223                               enum ring_type ring_type, int ring_index);
 224
 225         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 226                                               enum ring_type ring_type);
 227
 228         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 229
 230         void (*cs_reset)(struct radeon_winsys_cs *cs);
 231
 232         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 233
 234         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 235
 236         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 237                          int queue_index,
 238                          struct radeon_winsys_cs **cs_array,
 239                          unsigned cs_count,
 240                          struct radeon_winsys_cs *initial_preamble_cs,
 241                          struct radeon_winsys_cs *continue_preamble_cs,
 242                          struct radv_winsys_sem_info *sem_info,
 243                          bool can_patch,
 244                          struct radeon_winsys_fence *fence);
 245
 246         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 247                               struct radeon_winsys_bo *bo,
 248                               uint8_t priority);
 249
 250         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 251                                     struct radeon_winsys_cs *child);
 252
 253         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
 254
 255         int (*surface_init)(struct radeon_winsys *ws,
 256                             const struct ac_surf_info *surf_info,
 257                             struct radeon_surf *surf);
 258
 259         int (*surface_best)(struct radeon_winsys *ws,
 260                             struct radeon_surf *surf);
 261
 262         struct radeon_winsys_fence *(*create_fence)();
 263         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 264         bool (*fence_wait)(struct radeon_winsys *ws,
 265                            struct radeon_winsys_fence *fence,
 266                            bool absolute,
 267                            uint64_t timeout);
 268
 269         /* old semaphores - non shareable */
 270         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 271         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 272
 273         /* new shareable sync objects */
 274         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 275         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 276
 277         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 278         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 279         bool (*wait_syncobj)(struct radeon_winsys *ws, uint32_t handle, uint64_t timeout);
 280
 281         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 282         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 283
 284         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 285
 286         /* Note that this, unlike the normal import, uses an existing syncobj. */
 287         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 288
 289 };
 290
 291 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 292 {
 293         cs->buf[cs->cdw++] = value;
 294 }
 295
 296 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 297                                      const uint32_t *values, unsigned count)
 298 {
 299         memcpy(cs->buf + cs->cdw, values, count * 4);
 300         cs->cdw += count;
 301 }
 302
 303 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 304 {
 305         return bo->va;
 306 }
 307
 308 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 309                                       struct radeon_winsys_cs *cs,
 310                                       struct radeon_winsys_bo *bo,
 311                                       uint8_t priority)
 312 {
 313         if (bo->is_local)
 314                 return;
 315
 316         ws->cs_add_buffer(cs, bo, priority);
 317 }
 318
 319 #endif /* RADV_RADEON_WINSYS_H */