src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include "main/macros.h"
  37 #include "amd_family.h"
  38
  39 struct radeon_info;
  40 struct ac_surf_info;
  41 struct radeon_surf;
  42
  43 #define FREE(x) free(x)
  44
  45 enum radeon_bo_domain { /* bitfield */
  46         RADEON_DOMAIN_GTT  = 2,
  47         RADEON_DOMAIN_VRAM = 4,
  48         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
  49         RADEON_DOMAIN_GDS = 8,
  50         RADEON_DOMAIN_OA = 16,
  51 };
  52
  53 enum radeon_bo_flag { /* bitfield */
  54         RADEON_FLAG_GTT_WC =        (1 << 0),
  55         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  56         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  57         RADEON_FLAG_VIRTUAL =       (1 << 3),
  58         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  59         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  60         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  61         RADEON_FLAG_READ_ONLY =     (1 << 7),
  62         RADEON_FLAG_32BIT =         (1 << 8),
  63         RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
  64 };
  65
  66 enum radeon_bo_usage { /* bitfield */
  67         RADEON_USAGE_READ = 2,
  68         RADEON_USAGE_WRITE = 4,
  69         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  70 };
  71
  72 enum radeon_ctx_priority {
  73         RADEON_CTX_PRIORITY_INVALID = -1,
  74         RADEON_CTX_PRIORITY_LOW = 0,
  75         RADEON_CTX_PRIORITY_MEDIUM,
  76         RADEON_CTX_PRIORITY_HIGH,
  77         RADEON_CTX_PRIORITY_REALTIME,
  78 };
  79
  80 enum radeon_value_id {
  81         RADEON_ALLOCATED_VRAM,
  82         RADEON_ALLOCATED_VRAM_VIS,
  83         RADEON_ALLOCATED_GTT,
  84         RADEON_TIMESTAMP,
  85         RADEON_NUM_BYTES_MOVED,
  86         RADEON_NUM_EVICTIONS,
  87         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  88         RADEON_VRAM_USAGE,
  89         RADEON_VRAM_VIS_USAGE,
  90         RADEON_GTT_USAGE,
  91         RADEON_GPU_TEMPERATURE,
  92         RADEON_CURRENT_SCLK,
  93         RADEON_CURRENT_MCLK,
  94 };
  95
  96 struct radeon_cmdbuf {
  97         unsigned cdw;  /* Number of used dwords. */
  98         unsigned max_dw; /* Maximum number of dwords. */
  99         uint32_t *buf; /* The base pointer of the chunk. */
 100 };
 101
 102 #define RADEON_SURF_TYPE_MASK                   0xFF
 103 #define RADEON_SURF_TYPE_SHIFT                  0
 104 #define     RADEON_SURF_TYPE_1D                     0
 105 #define     RADEON_SURF_TYPE_2D                     1
 106 #define     RADEON_SURF_TYPE_3D                     2
 107 #define     RADEON_SURF_TYPE_CUBEMAP                3
 108 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 109 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 110 #define RADEON_SURF_MODE_MASK                   0xFF
 111 #define RADEON_SURF_MODE_SHIFT                  8
 112
 113 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 114 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 115 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 116
 117 enum radeon_bo_layout {
 118         RADEON_LAYOUT_LINEAR = 0,
 119         RADEON_LAYOUT_TILED,
 120         RADEON_LAYOUT_SQUARETILED,
 121
 122         RADEON_LAYOUT_UNKNOWN
 123 };
 124
 125 /* Tiling info for display code, DRI sharing, and other data. */
 126 struct radeon_bo_metadata {
 127         /* Tiling flags describing the texture layout for display code
 128          * and DRI sharing.
 129          */
 130         union {
 131                 struct {
 132                         enum radeon_bo_layout   microtile;
 133                         enum radeon_bo_layout   macrotile;
 134                         unsigned                pipe_config;
 135                         unsigned                bankw;
 136                         unsigned                bankh;
 137                         unsigned                tile_split;
 138                         unsigned                mtilea;
 139                         unsigned                num_banks;
 140                         unsigned                stride;
 141                         bool                    scanout;
 142                 } legacy;
 143
 144                 struct {
 145                         /* surface flags */
 146                         unsigned swizzle_mode:5;
 147                         bool scanout;
 148                 } gfx9;
 149         } u;
 150
 151         /* Additional metadata associated with the buffer, in bytes.
 152          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 153          * Supported by amdgpu only.
 154          */
 155         uint32_t                size_metadata;
 156         uint32_t                metadata[64];
 157 };
 158
 159 struct radeon_winsys_fence;
 160
 161 struct radeon_winsys_bo {
 162         uint64_t va;
 163         bool is_local;
 164         bool vram_cpu_access;
 165 };
 166 struct radv_winsys_sem_counts {
 167         uint32_t syncobj_count;
 168         uint32_t sem_count;
 169         uint32_t *syncobj;
 170         struct radeon_winsys_sem **sem;
 171 };
 172
 173 struct radv_winsys_sem_info {
 174         bool cs_emit_signal;
 175         bool cs_emit_wait;
 176         struct radv_winsys_sem_counts wait;
 177         struct radv_winsys_sem_counts signal;
 178 };
 179
 180 struct radv_winsys_bo_list {
 181         struct radeon_winsys_bo **bos;
 182         unsigned count;
 183 };
 184
 185 /* Kernel effectively allows 0-31. This sets some priorities for fixed
 186  * functionality buffers */
 187 enum {
 188         RADV_BO_PRIORITY_APPLICATION_MAX = 28,
 189
 190         /* virtual buffers have 0 priority since the priority is not used. */
 191         RADV_BO_PRIORITY_VIRTUAL = 0,
 192
 193         /* This should be considerably lower than most of the stuff below,
 194          * but how much lower is hard to say since we don't know application
 195          * assignments. Put it pretty high since it is GTT anyway. */
 196         RADV_BO_PRIORITY_QUERY_POOL = 29,
 197
 198         RADV_BO_PRIORITY_DESCRIPTOR = 30,
 199         RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
 200         RADV_BO_PRIORITY_FENCE = 30,
 201         RADV_BO_PRIORITY_SHADER = 31,
 202         RADV_BO_PRIORITY_SCRATCH = 31,
 203         RADV_BO_PRIORITY_CS = 31,
 204 };
 205
 206 struct radeon_winsys {
 207         void (*destroy)(struct radeon_winsys *ws);
 208
 209         void (*query_info)(struct radeon_winsys *ws,
 210                            struct radeon_info *info);
 211
 212         uint64_t (*query_value)(struct radeon_winsys *ws,
 213                                 enum radeon_value_id value);
 214
 215         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 216                                unsigned num_registers, uint32_t *out);
 217
 218         const char *(*get_chip_name)(struct radeon_winsys *ws);
 219
 220         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 221                                                   uint64_t size,
 222                                                   unsigned alignment,
 223                                                   enum radeon_bo_domain domain,
 224                                                   enum radeon_bo_flag flags,
 225                                                   unsigned priority);
 226
 227         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 228         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 229
 230         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 231                                                     void *pointer,
 232                                                     uint64_t size,
 233                                                     unsigned priority);
 234
 235         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 236                                                    int fd,
 237                                                    unsigned priority,
 238                                                    uint64_t *alloc_size);
 239
 240         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 241                               struct radeon_winsys_bo *bo,
 242                               int *fd);
 243
 244         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 245
 246         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 247                                     struct radeon_bo_metadata *md);
 248         void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
 249                                     struct radeon_bo_metadata *md);
 250
 251         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 252                                     uint64_t offset, uint64_t size,
 253                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 254         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 255                                                 enum radeon_ctx_priority priority);
 256         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 257
 258         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 259                               enum ring_type ring_type, int ring_index);
 260
 261         struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
 262                                               enum ring_type ring_type);
 263
 264         void (*cs_destroy)(struct radeon_cmdbuf *cs);
 265
 266         void (*cs_reset)(struct radeon_cmdbuf *cs);
 267
 268         bool (*cs_finalize)(struct radeon_cmdbuf *cs);
 269
 270         void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
 271
 272         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 273                          int queue_index,
 274                          struct radeon_cmdbuf **cs_array,
 275                          unsigned cs_count,
 276                          struct radeon_cmdbuf *initial_preamble_cs,
 277                          struct radeon_cmdbuf *continue_preamble_cs,
 278                          struct radv_winsys_sem_info *sem_info,
 279                          const struct radv_winsys_bo_list *bo_list, /* optional */
 280                          bool can_patch,
 281                          struct radeon_winsys_fence *fence);
 282
 283         void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 284                               struct radeon_winsys_bo *bo);
 285
 286         void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 287                                     struct radeon_cmdbuf *child);
 288
 289         void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
 290
 291         int (*surface_init)(struct radeon_winsys *ws,
 292                             const struct ac_surf_info *surf_info,
 293                             struct radeon_surf *surf);
 294
 295         struct radeon_winsys_fence *(*create_fence)();
 296         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 297         void (*reset_fence)(struct radeon_winsys_fence *fence);
 298         void (*signal_fence)(struct radeon_winsys_fence *fence);
 299         bool (*is_fence_waitable)(struct radeon_winsys_fence *fence);
 300         bool (*fence_wait)(struct radeon_winsys *ws,
 301                            struct radeon_winsys_fence *fence,
 302                            bool absolute,
 303                            uint64_t timeout);
 304         bool (*fences_wait)(struct radeon_winsys *ws,
 305                             struct radeon_winsys_fence *const *fences,
 306                             uint32_t fence_count,
 307                             bool wait_all,
 308                             uint64_t timeout);
 309
 310         /* old semaphores - non shareable */
 311         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 312         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 313
 314         /* new shareable sync objects */
 315         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 316         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 317
 318         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 319         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 320         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 321                              bool wait_all, uint64_t timeout);
 322
 323         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 324         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 325
 326         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 327
 328         /* Note that this, unlike the normal import, uses an existing syncobj. */
 329         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 330
 331 };
 332
 333 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 334 {
 335         cs->buf[cs->cdw++] = value;
 336 }
 337
 338 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 339                                      const uint32_t *values, unsigned count)
 340 {
 341         memcpy(cs->buf + cs->cdw, values, count * 4);
 342         cs->cdw += count;
 343 }
 344
 345 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 346 {
 347         return bo->va;
 348 }
 349
 350 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 351                                       struct radeon_cmdbuf *cs,
 352                                       struct radeon_winsys_bo *bo)
 353 {
 354         if (bo->is_local)
 355                 return;
 356
 357         ws->cs_add_buffer(cs, bo);
 358 }
 359
 360 #endif /* RADV_RADEON_WINSYS_H */