2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
36 #include "main/macros.h"
37 #include "amd_family.h"
43 #define FREE(x) free(x)
45 enum radeon_bo_domain
{ /* bitfield */
46 RADEON_DOMAIN_GTT
= 2,
47 RADEON_DOMAIN_VRAM
= 4,
48 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
51 enum radeon_bo_flag
{ /* bitfield */
52 RADEON_FLAG_GTT_WC
= (1 << 0),
53 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
54 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 RADEON_FLAG_VIRTUAL
= (1 << 3),
56 RADEON_FLAG_VA_UNCACHED
= (1 << 4),
57 RADEON_FLAG_IMPLICIT_SYNC
= (1 << 5),
58 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 6),
59 RADEON_FLAG_READ_ONLY
= (1 << 7),
60 RADEON_FLAG_32BIT
= (1 << 8),
63 enum radeon_bo_usage
{ /* bitfield */
64 RADEON_USAGE_READ
= 2,
65 RADEON_USAGE_WRITE
= 4,
66 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
78 enum radeon_ctx_priority
{
79 RADEON_CTX_PRIORITY_INVALID
= -1,
80 RADEON_CTX_PRIORITY_LOW
= 0,
81 RADEON_CTX_PRIORITY_MEDIUM
,
82 RADEON_CTX_PRIORITY_HIGH
,
83 RADEON_CTX_PRIORITY_REALTIME
,
86 enum radeon_value_id
{
88 RADEON_NUM_BYTES_MOVED
,
90 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
92 RADEON_VRAM_VIS_USAGE
,
94 RADEON_GPU_TEMPERATURE
,
99 struct radeon_cmdbuf
{
100 unsigned cdw
; /* Number of used dwords. */
101 unsigned max_dw
; /* Maximum number of dwords. */
102 uint32_t *buf
; /* The base pointer of the chunk. */
105 #define RADEON_SURF_TYPE_MASK 0xFF
106 #define RADEON_SURF_TYPE_SHIFT 0
107 #define RADEON_SURF_TYPE_1D 0
108 #define RADEON_SURF_TYPE_2D 1
109 #define RADEON_SURF_TYPE_3D 2
110 #define RADEON_SURF_TYPE_CUBEMAP 3
111 #define RADEON_SURF_TYPE_1D_ARRAY 4
112 #define RADEON_SURF_TYPE_2D_ARRAY 5
113 #define RADEON_SURF_MODE_MASK 0xFF
114 #define RADEON_SURF_MODE_SHIFT 8
116 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
117 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
118 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
120 enum radeon_bo_layout
{
121 RADEON_LAYOUT_LINEAR
= 0,
123 RADEON_LAYOUT_SQUARETILED
,
125 RADEON_LAYOUT_UNKNOWN
128 /* Tiling info for display code, DRI sharing, and other data. */
129 struct radeon_bo_metadata
{
130 /* Tiling flags describing the texture layout for display code
135 enum radeon_bo_layout microtile
;
136 enum radeon_bo_layout macrotile
;
137 unsigned pipe_config
;
149 unsigned swizzle_mode
:5;
153 /* Additional metadata associated with the buffer, in bytes.
154 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
155 * Supported by amdgpu only.
157 uint32_t size_metadata
;
158 uint32_t metadata
[64];
161 uint32_t syncobj_handle
;
162 struct radeon_winsys_fence
;
164 struct radeon_winsys_bo
{
168 struct radv_winsys_sem_counts
{
169 uint32_t syncobj_count
;
172 struct radeon_winsys_sem
**sem
;
175 struct radv_winsys_sem_info
{
178 struct radv_winsys_sem_counts wait
;
179 struct radv_winsys_sem_counts signal
;
182 struct radv_winsys_bo_list
{
183 struct radeon_winsys_bo
**bos
;
187 struct radeon_winsys
{
188 void (*destroy
)(struct radeon_winsys
*ws
);
190 void (*query_info
)(struct radeon_winsys
*ws
,
191 struct radeon_info
*info
);
193 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
194 enum radeon_value_id value
);
196 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
197 unsigned num_registers
, uint32_t *out
);
199 const char *(*get_chip_name
)(struct radeon_winsys
*ws
);
201 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
204 enum radeon_bo_domain domain
,
205 enum radeon_bo_flag flags
);
207 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
208 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
210 struct radeon_winsys_bo
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
214 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
216 unsigned *stride
, unsigned *offset
);
218 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
219 struct radeon_winsys_bo
*bo
,
222 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
224 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
225 struct radeon_bo_metadata
*md
);
227 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
228 uint64_t offset
, uint64_t size
,
229 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
230 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
,
231 enum radeon_ctx_priority priority
);
232 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
234 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
235 enum ring_type ring_type
, int ring_index
);
237 struct radeon_cmdbuf
*(*cs_create
)(struct radeon_winsys
*ws
,
238 enum ring_type ring_type
);
240 void (*cs_destroy
)(struct radeon_cmdbuf
*cs
);
242 void (*cs_reset
)(struct radeon_cmdbuf
*cs
);
244 bool (*cs_finalize
)(struct radeon_cmdbuf
*cs
);
246 void (*cs_grow
)(struct radeon_cmdbuf
* cs
, size_t min_size
);
248 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
250 struct radeon_cmdbuf
**cs_array
,
252 struct radeon_cmdbuf
*initial_preamble_cs
,
253 struct radeon_cmdbuf
*continue_preamble_cs
,
254 struct radv_winsys_sem_info
*sem_info
,
255 const struct radv_winsys_bo_list
*bo_list
, /* optional */
257 struct radeon_winsys_fence
*fence
);
259 void (*cs_add_buffer
)(struct radeon_cmdbuf
*cs
,
260 struct radeon_winsys_bo
*bo
);
262 void (*cs_execute_secondary
)(struct radeon_cmdbuf
*parent
,
263 struct radeon_cmdbuf
*child
);
265 void (*cs_dump
)(struct radeon_cmdbuf
*cs
, FILE* file
, const int *trace_ids
, int trace_id_count
);
267 int (*surface_init
)(struct radeon_winsys
*ws
,
268 const struct ac_surf_info
*surf_info
,
269 struct radeon_surf
*surf
);
271 struct radeon_winsys_fence
*(*create_fence
)();
272 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
273 bool (*fence_wait
)(struct radeon_winsys
*ws
,
274 struct radeon_winsys_fence
*fence
,
277 bool (*fences_wait
)(struct radeon_winsys
*ws
,
278 struct radeon_winsys_fence
*const *fences
,
279 uint32_t fence_count
,
283 /* old semaphores - non shareable */
284 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
285 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
287 /* new shareable sync objects */
288 int (*create_syncobj
)(struct radeon_winsys
*ws
, uint32_t *handle
);
289 void (*destroy_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
291 void (*reset_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
292 void (*signal_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
293 bool (*wait_syncobj
)(struct radeon_winsys
*ws
, const uint32_t *handles
, uint32_t handle_count
,
294 bool wait_all
, uint64_t timeout
);
296 int (*export_syncobj
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
297 int (*import_syncobj
)(struct radeon_winsys
*ws
, int fd
, uint32_t *syncobj
);
299 int (*export_syncobj_to_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
301 /* Note that this, unlike the normal import, uses an existing syncobj. */
302 int (*import_syncobj_from_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int fd
);
306 static inline void radeon_emit(struct radeon_cmdbuf
*cs
, uint32_t value
)
308 cs
->buf
[cs
->cdw
++] = value
;
311 static inline void radeon_emit_array(struct radeon_cmdbuf
*cs
,
312 const uint32_t *values
, unsigned count
)
314 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
318 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo
*bo
)
323 static inline void radv_cs_add_buffer(struct radeon_winsys
*ws
,
324 struct radeon_cmdbuf
*cs
,
325 struct radeon_winsys_bo
*bo
)
330 ws
->cs_add_buffer(cs
, bo
);
333 #endif /* RADV_RADEON_WINSYS_H */