src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 #define FREE(x) free(x)
  39
  40 enum radeon_bo_domain { /* bitfield */
  41         RADEON_DOMAIN_GTT  = 2,
  42         RADEON_DOMAIN_VRAM = 4,
  43         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  44 };
  45
  46 enum radeon_bo_flag { /* bitfield */
  47         RADEON_FLAG_GTT_WC =        (1 << 0),
  48         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  49         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  50         RADEON_FLAG_VIRTUAL =       (1 << 3)
  51 };
  52
  53 enum radeon_bo_usage { /* bitfield */
  54         RADEON_USAGE_READ = 2,
  55         RADEON_USAGE_WRITE = 4,
  56         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  57 };
  58
  59 enum ring_type {
  60         RING_GFX = 0,
  61         RING_COMPUTE,
  62         RING_DMA,
  63         RING_UVD,
  64         RING_VCE,
  65         RING_LAST,
  66 };
  67
  68 struct radeon_winsys_cs {
  69         unsigned cdw;  /* Number of used dwords. */
  70         unsigned max_dw; /* Maximum number of dwords. */
  71         uint32_t *buf; /* The base pointer of the chunk. */
  72 };
  73
  74 struct radeon_info {
  75         /* PCI info: domain:bus:dev:func */
  76         uint32_t                    pci_domain;
  77         uint32_t                    pci_bus;
  78         uint32_t                    pci_dev;
  79         uint32_t                    pci_func;
  80
  81         /* Device info. */
  82         uint32_t                    pci_id;
  83         enum radeon_family          family;
  84         const char                  *name;
  85         enum chip_class             chip_class;
  86         uint32_t                    gart_page_size;
  87         uint64_t                    gart_size;
  88         uint64_t                    vram_size;
  89         uint64_t                    visible_vram_size;
  90         bool                        has_dedicated_vram;
  91         bool                     has_virtual_memory;
  92         bool                        gfx_ib_pad_with_type2;
  93         bool                     has_uvd;
  94         uint32_t                    sdma_rings;
  95         uint32_t                    compute_rings;
  96         uint32_t                    vce_fw_version;
  97         uint32_t                    vce_harvest_config;
  98         uint32_t                    clock_crystal_freq; /* in kHz */
  99
 100         /* Kernel info. */
 101         uint32_t                    drm_major; /* version */
 102         uint32_t                    drm_minor;
 103         uint32_t                    drm_patchlevel;
 104         bool                     has_userptr;
 105
 106         /* Shader cores. */
 107         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 108         uint32_t                    max_shader_clock;
 109         uint32_t                    num_good_compute_units;
 110         uint32_t                    max_se; /* shader engines */
 111         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 112
 113         /* Render backends (color + depth blocks). */
 114         uint32_t                    r300_num_gb_pipes;
 115         uint32_t                    r300_num_z_pipes;
 116         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 117         bool                     r600_gb_backend_map_valid;
 118         uint32_t                    r600_num_banks;
 119         uint32_t                    num_render_backends;
 120         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 121         uint32_t                    pipe_interleave_bytes;
 122         uint32_t                    enabled_rb_mask; /* GCN harvest config */
 123
 124         /* Tile modes. */
 125         uint32_t                    si_tile_mode_array[32];
 126         uint32_t                    cik_macrotile_mode_array[16];
 127 };
 128
 129 #define RADEON_SURF_MAX_LEVEL                   32
 130
 131 #define RADEON_SURF_TYPE_MASK                   0xFF
 132 #define RADEON_SURF_TYPE_SHIFT                  0
 133 #define     RADEON_SURF_TYPE_1D                     0
 134 #define     RADEON_SURF_TYPE_2D                     1
 135 #define     RADEON_SURF_TYPE_3D                     2
 136 #define     RADEON_SURF_TYPE_CUBEMAP                3
 137 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 138 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 139 #define RADEON_SURF_MODE_MASK                   0xFF
 140 #define RADEON_SURF_MODE_SHIFT                  8
 141 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 142 #define     RADEON_SURF_MODE_1D                     2
 143 #define     RADEON_SURF_MODE_2D                     3
 144 #define RADEON_SURF_SCANOUT                     (1 << 16)
 145 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 146 #define RADEON_SURF_SBUFFER                     (1 << 18)
 147 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 148 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 149 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 150 #define RADEON_SURF_FMASK                       (1 << 21)
 151 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 152 #define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 153
 154 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 155 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 156 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 157
 158 struct radeon_surf_info {
 159         uint32_t width;
 160         uint32_t height;
 161         uint32_t depth;
 162         uint8_t samples;
 163         uint8_t levels;
 164         uint16_t array_size;
 165 };
 166
 167 struct radeon_surf_level {
 168         uint64_t                    offset;
 169         uint64_t                    slice_size;
 170         uint32_t                    nblk_x;
 171         uint32_t                    nblk_y;
 172         uint32_t                    mode;
 173         uint64_t                    dcc_offset;
 174         uint64_t                    dcc_fast_clear_size;
 175 };
 176
 177
 178 /* surface defintions from the winsys */
 179 struct radeon_surf {
 180         /* These are inputs to the calculator. */
 181         uint32_t                    blk_w;
 182         uint32_t                    blk_h;
 183         uint32_t                    bpe;
 184         uint32_t                    flags;
 185
 186         unsigned                    num_dcc_levels:4;
 187
 188         /* These are return values. Some of them can be set by the caller, but
 189          * they will be treated as hints (e.g. bankw, bankh) and might be
 190          * changed by the calculator.
 191          */
 192         uint64_t                    bo_size;
 193         uint64_t                    bo_alignment;
 194         /* This applies to EG and later. */
 195         uint32_t                    bankw;
 196         uint32_t                    bankh;
 197         uint32_t                    mtilea;
 198         uint32_t                    tile_split;
 199         uint32_t                    stencil_tile_split;
 200         uint64_t                    stencil_offset;
 201         struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 202         struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 203         uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 204         uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 205         uint32_t                    pipe_config;
 206         uint32_t                    num_banks;
 207         uint32_t                    macro_tile_index;
 208         uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 209
 210         /* Whether the depth miptree or stencil miptree as used by the DB are
 211          * adjusted from their TC compatible form to ensure depth/stencil
 212          * compatibility. If either is true, the corresponding plane cannot be
 213          * sampled from.
 214          */
 215         bool                        depth_adjusted;
 216         bool                        stencil_adjusted;
 217
 218         uint64_t                    dcc_size;
 219         uint64_t                    dcc_alignment;
 220
 221         uint64_t                    htile_size;
 222         uint64_t                    htile_slice_size;
 223         uint64_t                    htile_alignment;
 224 };
 225
 226 enum radeon_bo_layout {
 227         RADEON_LAYOUT_LINEAR = 0,
 228         RADEON_LAYOUT_TILED,
 229         RADEON_LAYOUT_SQUARETILED,
 230
 231         RADEON_LAYOUT_UNKNOWN
 232 };
 233
 234 /* Tiling info for display code, DRI sharing, and other data. */
 235 struct radeon_bo_metadata {
 236         /* Tiling flags describing the texture layout for display code
 237          * and DRI sharing.
 238          */
 239         enum radeon_bo_layout   microtile;
 240         enum radeon_bo_layout   macrotile;
 241         unsigned                pipe_config;
 242         unsigned                bankw;
 243         unsigned                bankh;
 244         unsigned                tile_split;
 245         unsigned                mtilea;
 246         unsigned                num_banks;
 247         unsigned                stride;
 248         bool                    scanout;
 249
 250         /* Additional metadata associated with the buffer, in bytes.
 251          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 252          * Supported by amdgpu only.
 253          */
 254         uint32_t                size_metadata;
 255         uint32_t                metadata[64];
 256 };
 257
 258 struct radeon_winsys_bo;
 259 struct radeon_winsys_fence;
 260 struct radeon_winsys_sem;
 261
 262 struct radeon_winsys {
 263         void (*destroy)(struct radeon_winsys *ws);
 264
 265         void (*query_info)(struct radeon_winsys *ws,
 266                            struct radeon_info *info);
 267
 268         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 269                                                   uint64_t size,
 270                                                   unsigned alignment,
 271                                                   enum radeon_bo_domain domain,
 272                                                   enum radeon_bo_flag flags);
 273
 274         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 275         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 276
 277         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 278                                                    int fd,
 279                                                    unsigned *stride, unsigned *offset);
 280
 281         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 282                               struct radeon_winsys_bo *bo,
 283                               int *fd);
 284
 285         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 286
 287         uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
 288
 289         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 290                                     struct radeon_bo_metadata *md);
 291
 292         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 293                                     uint64_t offset, uint64_t size,
 294                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 295         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 296         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 297
 298         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 299                               enum ring_type ring_type, int ring_index);
 300
 301         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 302                                               enum ring_type ring_type);
 303
 304         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 305
 306         void (*cs_reset)(struct radeon_winsys_cs *cs);
 307
 308         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 309
 310         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 311
 312         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 313                          int queue_index,
 314                          struct radeon_winsys_cs **cs_array,
 315                          unsigned cs_count,
 316                          struct radeon_winsys_cs *initial_preamble_cs,
 317                          struct radeon_winsys_cs *continue_preamble_cs,
 318                          struct radeon_winsys_sem **wait_sem,
 319                          unsigned wait_sem_count,
 320                          struct radeon_winsys_sem **signal_sem,
 321                          unsigned signal_sem_count,
 322                          bool can_patch,
 323                          struct radeon_winsys_fence *fence);
 324
 325         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 326                               struct radeon_winsys_bo *bo,
 327                               uint8_t priority);
 328
 329         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 330                                     struct radeon_winsys_cs *child);
 331
 332         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
 333
 334         int (*surface_init)(struct radeon_winsys *ws,
 335                             const struct radeon_surf_info *surf_info,
 336                             struct radeon_surf *surf);
 337
 338         int (*surface_best)(struct radeon_winsys *ws,
 339                             struct radeon_surf *surf);
 340
 341         struct radeon_winsys_fence *(*create_fence)();
 342         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 343         bool (*fence_wait)(struct radeon_winsys *ws,
 344                            struct radeon_winsys_fence *fence,
 345                            bool absolute,
 346                            uint64_t timeout);
 347
 348         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 349         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 350
 351 };
 352
 353 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 354 {
 355         cs->buf[cs->cdw++] = value;
 356 }
 357
 358 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 359                                      const uint32_t *values, unsigned count)
 360 {
 361         memcpy(cs->buf + cs->cdw, values, count * 4);
 362         cs->cdw += count;
 363 }
 364
 365 #endif /* RADV_RADEON_WINSYS_H */