2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
35 #include "main/macros.h"
36 #include "amd_family.h"
41 #define FREE(x) free(x)
43 enum radeon_bo_domain
{ /* bitfield */
44 RADEON_DOMAIN_GTT
= 2,
45 RADEON_DOMAIN_VRAM
= 4,
46 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
49 enum radeon_bo_flag
{ /* bitfield */
50 RADEON_FLAG_GTT_WC
= (1 << 0),
51 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
52 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
53 RADEON_FLAG_VIRTUAL
= (1 << 3)
56 enum radeon_bo_usage
{ /* bitfield */
57 RADEON_USAGE_READ
= 2,
58 RADEON_USAGE_WRITE
= 4,
59 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
71 struct radeon_winsys_cs
{
72 unsigned cdw
; /* Number of used dwords. */
73 unsigned max_dw
; /* Maximum number of dwords. */
74 uint32_t *buf
; /* The base pointer of the chunk. */
78 /* PCI info: domain:bus:dev:func */
86 enum radeon_family family
;
87 enum chip_class chip_class
;
88 uint32_t gart_page_size
;
91 uint64_t visible_vram_size
;
92 bool has_dedicated_vram
;
93 bool has_virtual_memory
;
94 bool gfx_ib_pad_with_type2
;
97 uint32_t compute_rings
;
98 uint32_t vce_fw_version
;
99 uint32_t vce_harvest_config
;
100 uint32_t clock_crystal_freq
; /* in kHz */
103 uint32_t drm_major
; /* version */
105 uint32_t drm_patchlevel
;
109 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
110 uint32_t max_shader_clock
;
111 uint32_t num_good_compute_units
;
112 uint32_t max_se
; /* shader engines */
113 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
115 /* Render backends (color + depth blocks). */
116 uint32_t r300_num_gb_pipes
;
117 uint32_t r300_num_z_pipes
;
118 uint32_t r600_gb_backend_map
; /* R600 harvest config */
119 bool r600_gb_backend_map_valid
;
120 uint32_t r600_num_banks
;
121 uint32_t num_render_backends
;
122 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
123 uint32_t pipe_interleave_bytes
;
124 uint32_t enabled_rb_mask
; /* GCN harvest config */
127 uint32_t si_tile_mode_array
[32];
128 uint32_t cik_macrotile_mode_array
[16];
131 #define RADEON_SURF_TYPE_MASK 0xFF
132 #define RADEON_SURF_TYPE_SHIFT 0
133 #define RADEON_SURF_TYPE_1D 0
134 #define RADEON_SURF_TYPE_2D 1
135 #define RADEON_SURF_TYPE_3D 2
136 #define RADEON_SURF_TYPE_CUBEMAP 3
137 #define RADEON_SURF_TYPE_1D_ARRAY 4
138 #define RADEON_SURF_TYPE_2D_ARRAY 5
139 #define RADEON_SURF_MODE_MASK 0xFF
140 #define RADEON_SURF_MODE_SHIFT 8
142 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
143 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
144 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
146 enum radeon_bo_layout
{
147 RADEON_LAYOUT_LINEAR
= 0,
149 RADEON_LAYOUT_SQUARETILED
,
151 RADEON_LAYOUT_UNKNOWN
154 /* Tiling info for display code, DRI sharing, and other data. */
155 struct radeon_bo_metadata
{
156 /* Tiling flags describing the texture layout for display code
159 enum radeon_bo_layout microtile
;
160 enum radeon_bo_layout macrotile
;
161 unsigned pipe_config
;
170 /* Additional metadata associated with the buffer, in bytes.
171 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
172 * Supported by amdgpu only.
174 uint32_t size_metadata
;
175 uint32_t metadata
[64];
178 struct radeon_winsys_bo
;
179 struct radeon_winsys_fence
;
180 struct radeon_winsys_sem
;
182 struct radeon_winsys
{
183 void (*destroy
)(struct radeon_winsys
*ws
);
185 void (*query_info
)(struct radeon_winsys
*ws
,
186 struct radeon_info
*info
);
188 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
191 enum radeon_bo_domain domain
,
192 enum radeon_bo_flag flags
);
194 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
195 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
197 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
199 unsigned *stride
, unsigned *offset
);
201 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
202 struct radeon_winsys_bo
*bo
,
205 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
207 uint64_t (*buffer_get_va
)(struct radeon_winsys_bo
*bo
);
209 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
210 struct radeon_bo_metadata
*md
);
212 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
213 uint64_t offset
, uint64_t size
,
214 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
215 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
216 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
218 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
219 enum ring_type ring_type
, int ring_index
);
221 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys
*ws
,
222 enum ring_type ring_type
);
224 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
226 void (*cs_reset
)(struct radeon_winsys_cs
*cs
);
228 bool (*cs_finalize
)(struct radeon_winsys_cs
*cs
);
230 void (*cs_grow
)(struct radeon_winsys_cs
* cs
, size_t min_size
);
232 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
234 struct radeon_winsys_cs
**cs_array
,
236 struct radeon_winsys_cs
*initial_preamble_cs
,
237 struct radeon_winsys_cs
*continue_preamble_cs
,
238 struct radeon_winsys_sem
**wait_sem
,
239 unsigned wait_sem_count
,
240 struct radeon_winsys_sem
**signal_sem
,
241 unsigned signal_sem_count
,
243 struct radeon_winsys_fence
*fence
);
245 void (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
246 struct radeon_winsys_bo
*bo
,
249 void (*cs_execute_secondary
)(struct radeon_winsys_cs
*parent
,
250 struct radeon_winsys_cs
*child
);
252 void (*cs_dump
)(struct radeon_winsys_cs
*cs
, FILE* file
, uint32_t trace_id
);
254 int (*surface_init
)(struct radeon_winsys
*ws
,
255 const struct ac_surf_info
*surf_info
,
256 struct radeon_surf
*surf
);
258 int (*surface_best
)(struct radeon_winsys
*ws
,
259 struct radeon_surf
*surf
);
261 struct radeon_winsys_fence
*(*create_fence
)();
262 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
263 bool (*fence_wait
)(struct radeon_winsys
*ws
,
264 struct radeon_winsys_fence
*fence
,
268 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
269 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
273 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
275 cs
->buf
[cs
->cdw
++] = value
;
278 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
279 const uint32_t *values
, unsigned count
)
281 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
285 #endif /* RADV_RADEON_WINSYS_H */