src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include "amd_family.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_math.h"
  40
  41 struct radeon_info;
  42 struct ac_surf_info;
  43 struct radeon_surf;
  44
  45 enum radeon_bo_domain { /* bitfield */
  46         RADEON_DOMAIN_GTT  = 2,
  47         RADEON_DOMAIN_VRAM = 4,
  48         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
  49         RADEON_DOMAIN_GDS = 8,
  50         RADEON_DOMAIN_OA = 16,
  51 };
  52
  53 enum radeon_bo_flag { /* bitfield */
  54         RADEON_FLAG_GTT_WC =        (1 << 0),
  55         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  56         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  57         RADEON_FLAG_VIRTUAL =       (1 << 3),
  58         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  59         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  60         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  61         RADEON_FLAG_READ_ONLY =     (1 << 7),
  62         RADEON_FLAG_32BIT =         (1 << 8),
  63         RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
  64         RADEON_FLAG_ZERO_VRAM = (1 << 10),
  65 };
  66
  67 enum radeon_bo_usage { /* bitfield */
  68         RADEON_USAGE_READ = 2,
  69         RADEON_USAGE_WRITE = 4,
  70         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  71 };
  72
  73 enum radeon_ctx_priority {
  74         RADEON_CTX_PRIORITY_INVALID = -1,
  75         RADEON_CTX_PRIORITY_LOW = 0,
  76         RADEON_CTX_PRIORITY_MEDIUM,
  77         RADEON_CTX_PRIORITY_HIGH,
  78         RADEON_CTX_PRIORITY_REALTIME,
  79 };
  80
  81 enum radeon_value_id {
  82         RADEON_ALLOCATED_VRAM,
  83         RADEON_ALLOCATED_VRAM_VIS,
  84         RADEON_ALLOCATED_GTT,
  85         RADEON_TIMESTAMP,
  86         RADEON_NUM_BYTES_MOVED,
  87         RADEON_NUM_EVICTIONS,
  88         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  89         RADEON_VRAM_USAGE,
  90         RADEON_VRAM_VIS_USAGE,
  91         RADEON_GTT_USAGE,
  92         RADEON_GPU_TEMPERATURE,
  93         RADEON_CURRENT_SCLK,
  94         RADEON_CURRENT_MCLK,
  95 };
  96
  97 struct radeon_cmdbuf {
  98         unsigned cdw;  /* Number of used dwords. */
  99         unsigned max_dw; /* Maximum number of dwords. */
 100         uint32_t *buf; /* The base pointer of the chunk. */
 101 };
 102
 103 #define RADEON_SURF_TYPE_MASK                   0xFF
 104 #define RADEON_SURF_TYPE_SHIFT                  0
 105 #define     RADEON_SURF_TYPE_1D                     0
 106 #define     RADEON_SURF_TYPE_2D                     1
 107 #define     RADEON_SURF_TYPE_3D                     2
 108 #define     RADEON_SURF_TYPE_CUBEMAP                3
 109 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 110 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 111 #define RADEON_SURF_MODE_MASK                   0xFF
 112 #define RADEON_SURF_MODE_SHIFT                  8
 113
 114 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 115 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 116 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 117
 118 enum radeon_bo_layout {
 119         RADEON_LAYOUT_LINEAR = 0,
 120         RADEON_LAYOUT_TILED,
 121         RADEON_LAYOUT_SQUARETILED,
 122
 123         RADEON_LAYOUT_UNKNOWN
 124 };
 125
 126 /* Tiling info for display code, DRI sharing, and other data. */
 127 struct radeon_bo_metadata {
 128         /* Tiling flags describing the texture layout for display code
 129          * and DRI sharing.
 130          */
 131         union {
 132                 struct {
 133                         enum radeon_bo_layout   microtile;
 134                         enum radeon_bo_layout   macrotile;
 135                         unsigned                pipe_config;
 136                         unsigned                bankw;
 137                         unsigned                bankh;
 138                         unsigned                tile_split;
 139                         unsigned                mtilea;
 140                         unsigned                num_banks;
 141                         unsigned                stride;
 142                         bool                    scanout;
 143                 } legacy;
 144
 145                 struct {
 146                         /* surface flags */
 147                         unsigned swizzle_mode:5;
 148                         bool scanout;
 149                 } gfx9;
 150         } u;
 151
 152         /* Additional metadata associated with the buffer, in bytes.
 153          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 154          * Supported by amdgpu only.
 155          */
 156         uint32_t                size_metadata;
 157         uint32_t                metadata[64];
 158 };
 159
 160 struct radeon_winsys_fence;
 161
 162 struct radeon_winsys_bo {
 163         uint64_t va;
 164         bool is_local;
 165         bool vram_no_cpu_access;
 166 };
 167 struct radv_winsys_sem_counts {
 168         uint32_t syncobj_count;
 169         uint32_t sem_count;
 170         uint32_t *syncobj;
 171         struct radeon_winsys_sem **sem;
 172 };
 173
 174 struct radv_winsys_sem_info {
 175         bool cs_emit_signal;
 176         bool cs_emit_wait;
 177         struct radv_winsys_sem_counts wait;
 178         struct radv_winsys_sem_counts signal;
 179 };
 180
 181 struct radv_winsys_bo_list {
 182         struct radeon_winsys_bo **bos;
 183         unsigned count;
 184 };
 185
 186 /* Kernel effectively allows 0-31. This sets some priorities for fixed
 187  * functionality buffers */
 188 enum {
 189         RADV_BO_PRIORITY_APPLICATION_MAX = 28,
 190
 191         /* virtual buffers have 0 priority since the priority is not used. */
 192         RADV_BO_PRIORITY_VIRTUAL = 0,
 193
 194         /* This should be considerably lower than most of the stuff below,
 195          * but how much lower is hard to say since we don't know application
 196          * assignments. Put it pretty high since it is GTT anyway. */
 197         RADV_BO_PRIORITY_QUERY_POOL = 29,
 198
 199         RADV_BO_PRIORITY_DESCRIPTOR = 30,
 200         RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
 201         RADV_BO_PRIORITY_FENCE = 30,
 202         RADV_BO_PRIORITY_SHADER = 31,
 203         RADV_BO_PRIORITY_SCRATCH = 31,
 204         RADV_BO_PRIORITY_CS = 31,
 205 };
 206
 207 struct radeon_winsys {
 208         void (*destroy)(struct radeon_winsys *ws);
 209
 210         void (*query_info)(struct radeon_winsys *ws,
 211                            struct radeon_info *info);
 212
 213         uint64_t (*query_value)(struct radeon_winsys *ws,
 214                                 enum radeon_value_id value);
 215
 216         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 217                                unsigned num_registers, uint32_t *out);
 218
 219         const char *(*get_chip_name)(struct radeon_winsys *ws);
 220
 221         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 222                                                   uint64_t size,
 223                                                   unsigned alignment,
 224                                                   enum radeon_bo_domain domain,
 225                                                   enum radeon_bo_flag flags,
 226                                                   unsigned priority);
 227
 228         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 229         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 230
 231         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 232                                                     void *pointer,
 233                                                     uint64_t size,
 234                                                     unsigned priority);
 235
 236         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 237                                                    int fd,
 238                                                    unsigned priority,
 239                                                    uint64_t *alloc_size);
 240
 241         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 242                               struct radeon_winsys_bo *bo,
 243                               int *fd);
 244
 245         bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd,
 246                                          enum radeon_bo_domain *domains,
 247                                          enum radeon_bo_flag *flags);
 248
 249         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 250
 251         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 252                                     struct radeon_bo_metadata *md);
 253         void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
 254                                     struct radeon_bo_metadata *md);
 255
 256         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 257                                     uint64_t offset, uint64_t size,
 258                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 259         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 260                                                 enum radeon_ctx_priority priority);
 261         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 262
 263         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 264                               enum ring_type ring_type, int ring_index);
 265
 266         struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
 267                                               enum ring_type ring_type);
 268
 269         void (*cs_destroy)(struct radeon_cmdbuf *cs);
 270
 271         void (*cs_reset)(struct radeon_cmdbuf *cs);
 272
 273         bool (*cs_finalize)(struct radeon_cmdbuf *cs);
 274
 275         void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
 276
 277         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 278                          int queue_index,
 279                          struct radeon_cmdbuf **cs_array,
 280                          unsigned cs_count,
 281                          struct radeon_cmdbuf *initial_preamble_cs,
 282                          struct radeon_cmdbuf *continue_preamble_cs,
 283                          struct radv_winsys_sem_info *sem_info,
 284                          const struct radv_winsys_bo_list *bo_list, /* optional */
 285                          bool can_patch,
 286                          struct radeon_winsys_fence *fence);
 287
 288         void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 289                               struct radeon_winsys_bo *bo);
 290
 291         void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 292                                     struct radeon_cmdbuf *child);
 293
 294         void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
 295
 296         int (*surface_init)(struct radeon_winsys *ws,
 297                             const struct ac_surf_info *surf_info,
 298                             struct radeon_surf *surf);
 299
 300         struct radeon_winsys_fence *(*create_fence)();
 301         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 302         void (*reset_fence)(struct radeon_winsys_fence *fence);
 303         void (*signal_fence)(struct radeon_winsys_fence *fence);
 304         bool (*is_fence_waitable)(struct radeon_winsys_fence *fence);
 305         bool (*fence_wait)(struct radeon_winsys *ws,
 306                            struct radeon_winsys_fence *fence,
 307                            bool absolute,
 308                            uint64_t timeout);
 309         bool (*fences_wait)(struct radeon_winsys *ws,
 310                             struct radeon_winsys_fence *const *fences,
 311                             uint32_t fence_count,
 312                             bool wait_all,
 313                             uint64_t timeout);
 314
 315         /* old semaphores - non shareable */
 316         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 317         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 318
 319         /* new shareable sync objects */
 320         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 321         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 322
 323         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 324         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 325         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 326                              bool wait_all, uint64_t timeout);
 327
 328         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 329         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 330
 331         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 332
 333         /* Note that this, unlike the normal import, uses an existing syncobj. */
 334         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 335
 336 };
 337
 338 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 339 {
 340         cs->buf[cs->cdw++] = value;
 341 }
 342
 343 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 344                                      const uint32_t *values, unsigned count)
 345 {
 346         memcpy(cs->buf + cs->cdw, values, count * 4);
 347         cs->cdw += count;
 348 }
 349
 350 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 351 {
 352         return bo->va;
 353 }
 354
 355 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 356                                       struct radeon_cmdbuf *cs,
 357                                       struct radeon_winsys_bo *bo)
 358 {
 359         if (bo->is_local)
 360                 return;
 361
 362         ws->cs_add_buffer(cs, bo);
 363 }
 364
 365 #endif /* RADV_RADEON_WINSYS_H */