src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28 #pragma once
  29
  30 #include <stdint.h>
  31 #include <stdbool.h>
  32 #include <stdlib.h>
  33 #include "main/macros.h"
  34 #include "amd_family.h"
  35
  36 #define FREE(x) free(x)
  37
  38 enum radeon_bo_domain { /* bitfield */
  39         RADEON_DOMAIN_GTT  = 2,
  40         RADEON_DOMAIN_VRAM = 4,
  41         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  42 };
  43
  44 enum radeon_bo_flag { /* bitfield */
  45         RADEON_FLAG_GTT_WC =        (1 << 0),
  46         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  47         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  48 };
  49
  50 enum radeon_bo_usage { /* bitfield */
  51         RADEON_USAGE_READ = 2,
  52         RADEON_USAGE_WRITE = 4,
  53         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  54 };
  55
  56 enum ring_type {
  57         RING_GFX = 0,
  58         RING_COMPUTE,
  59         RING_DMA,
  60         RING_UVD,
  61         RING_VCE,
  62         RING_LAST,
  63 };
  64
  65 struct radeon_winsys_cs {
  66         unsigned cdw;  /* Number of used dwords. */
  67         unsigned max_dw; /* Maximum number of dwords. */
  68         uint32_t *buf; /* The base pointer of the chunk. */
  69 };
  70
  71 struct radeon_info {
  72         /* PCI info: domain:bus:dev:func */
  73         uint32_t                    pci_domain;
  74         uint32_t                    pci_bus;
  75         uint32_t                    pci_dev;
  76         uint32_t                    pci_func;
  77
  78         /* Device info. */
  79         uint32_t                    pci_id;
  80         enum radeon_family          family;
  81         const char                  *name;
  82         enum chip_class             chip_class;
  83         uint32_t                    gart_page_size;
  84         uint64_t                    gart_size;
  85         uint64_t                    vram_size;
  86         bool                        has_dedicated_vram;
  87         bool                     has_virtual_memory;
  88         bool                        gfx_ib_pad_with_type2;
  89         bool                     has_sdma;
  90         bool                     has_uvd;
  91         uint32_t                    vce_fw_version;
  92         uint32_t                    vce_harvest_config;
  93         uint32_t                    clock_crystal_freq;
  94
  95         /* Kernel info. */
  96         uint32_t                    drm_major; /* version */
  97         uint32_t                    drm_minor;
  98         uint32_t                    drm_patchlevel;
  99         bool                     has_userptr;
 100
 101         /* Shader cores. */
 102         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 103         uint32_t                    max_shader_clock;
 104         uint32_t                    num_good_compute_units;
 105         uint32_t                    max_se; /* shader engines */
 106         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 107
 108         /* Render backends (color + depth blocks). */
 109         uint32_t                    r300_num_gb_pipes;
 110         uint32_t                    r300_num_z_pipes;
 111         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 112         bool                     r600_gb_backend_map_valid;
 113         uint32_t                    r600_num_banks;
 114         uint32_t                    num_render_backends;
 115         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 116         uint32_t                    pipe_interleave_bytes;
 117         uint32_t                    enabled_rb_mask; /* GCN harvest config */
 118
 119         /* Tile modes. */
 120         uint32_t                    si_tile_mode_array[32];
 121         uint32_t                    cik_macrotile_mode_array[16];
 122 };
 123
 124 #define RADEON_SURF_MAX_LEVEL                   32
 125
 126 #define RADEON_SURF_TYPE_MASK                   0xFF
 127 #define RADEON_SURF_TYPE_SHIFT                  0
 128 #define     RADEON_SURF_TYPE_1D                     0
 129 #define     RADEON_SURF_TYPE_2D                     1
 130 #define     RADEON_SURF_TYPE_3D                     2
 131 #define     RADEON_SURF_TYPE_CUBEMAP                3
 132 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 133 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 134 #define RADEON_SURF_MODE_MASK                   0xFF
 135 #define RADEON_SURF_MODE_SHIFT                  8
 136 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
 137 #define     RADEON_SURF_MODE_1D                     2
 138 #define     RADEON_SURF_MODE_2D                     3
 139 #define RADEON_SURF_SCANOUT                     (1 << 16)
 140 #define RADEON_SURF_ZBUFFER                     (1 << 17)
 141 #define RADEON_SURF_SBUFFER                     (1 << 18)
 142 #define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
 143 #define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
 144 #define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
 145 #define RADEON_SURF_FMASK                       (1 << 21)
 146 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 147
 148 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 149 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 150 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 151
 152 struct radeon_surf_level {
 153         uint64_t                    offset;
 154         uint64_t                    slice_size;
 155         uint32_t                    npix_x;
 156         uint32_t                    npix_y;
 157         uint32_t                    npix_z;
 158         uint32_t                    nblk_x;
 159         uint32_t                    nblk_y;
 160         uint32_t                    nblk_z;
 161         uint32_t                    pitch_bytes;
 162         uint32_t                    mode;
 163         uint64_t                    dcc_offset;
 164         uint64_t                    dcc_fast_clear_size;
 165         bool                        dcc_enabled;
 166 };
 167
 168
 169 /* surface defintions from the winsys */
 170 struct radeon_surf {
 171         /* These are inputs to the calculator. */
 172         uint32_t                    npix_x;
 173         uint32_t                    npix_y;
 174         uint32_t                    npix_z;
 175         uint32_t                    blk_w;
 176         uint32_t                    blk_h;
 177         uint32_t                    blk_d;
 178         uint32_t                    array_size;
 179         uint32_t                    last_level;
 180         uint32_t                    bpe;
 181         uint32_t                    nsamples;
 182         uint32_t                    flags;
 183
 184         /* These are return values. Some of them can be set by the caller, but
 185          * they will be treated as hints (e.g. bankw, bankh) and might be
 186          * changed by the calculator.
 187          */
 188         uint64_t                    bo_size;
 189         uint64_t                    bo_alignment;
 190         /* This applies to EG and later. */
 191         uint32_t                    bankw;
 192         uint32_t                    bankh;
 193         uint32_t                    mtilea;
 194         uint32_t                    tile_split;
 195         uint32_t                    stencil_tile_split;
 196         uint64_t                    stencil_offset;
 197         struct radeon_surf_level    level[RADEON_SURF_MAX_LEVEL];
 198         struct radeon_surf_level    stencil_level[RADEON_SURF_MAX_LEVEL];
 199         uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
 200         uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
 201         uint32_t                    pipe_config;
 202         uint32_t                    num_banks;
 203         uint32_t                    macro_tile_index;
 204         uint32_t                    micro_tile_mode; /* displayable, thin, depth, rotated */
 205
 206         /* Whether the depth miptree or stencil miptree as used by the DB are
 207          * adjusted from their TC compatible form to ensure depth/stencil
 208          * compatibility. If either is true, the corresponding plane cannot be
 209          * sampled from.
 210          */
 211         bool                        depth_adjusted;
 212         bool                        stencil_adjusted;
 213
 214         uint64_t                    dcc_size;
 215         uint64_t                    dcc_alignment;
 216 };
 217
 218 enum radeon_bo_layout {
 219         RADEON_LAYOUT_LINEAR = 0,
 220         RADEON_LAYOUT_TILED,
 221         RADEON_LAYOUT_SQUARETILED,
 222
 223         RADEON_LAYOUT_UNKNOWN
 224 };
 225
 226 /* Tiling info for display code, DRI sharing, and other data. */
 227 struct radeon_bo_metadata {
 228         /* Tiling flags describing the texture layout for display code
 229          * and DRI sharing.
 230          */
 231         enum radeon_bo_layout   microtile;
 232         enum radeon_bo_layout   macrotile;
 233         unsigned                pipe_config;
 234         unsigned                bankw;
 235         unsigned                bankh;
 236         unsigned                tile_split;
 237         unsigned                mtilea;
 238         unsigned                num_banks;
 239         unsigned                stride;
 240         bool                    scanout;
 241
 242         /* Additional metadata associated with the buffer, in bytes.
 243          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 244          * Supported by amdgpu only.
 245          */
 246         uint32_t                size_metadata;
 247         uint32_t                metadata[64];
 248 };
 249
 250 struct radeon_winsys_bo;
 251 struct radeon_winsys_fence;
 252
 253 struct radeon_winsys {
 254         void (*destroy)(struct radeon_winsys *ws);
 255
 256         void (*query_info)(struct radeon_winsys *ws,
 257                            struct radeon_info *info);
 258
 259         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 260                                                   uint64_t size,
 261                                                   unsigned alignment,
 262                                                   enum radeon_bo_domain domain,
 263                                                   enum radeon_bo_flag flags);
 264
 265         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 266         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 267
 268         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 269                                                    int fd,
 270                                                    unsigned *stride, unsigned *offset);
 271
 272         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 273                               struct radeon_winsys_bo *bo,
 274                               int *fd);
 275
 276         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 277
 278         uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
 279
 280         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 281                                     struct radeon_bo_metadata *md);
 282         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 283         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 284
 285         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx);
 286
 287         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 288                                               enum ring_type ring_type);
 289
 290         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 291
 292         void (*cs_reset)(struct radeon_winsys_cs *cs);
 293
 294         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 295
 296         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 297
 298         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 299                          struct radeon_winsys_cs **cs_array,
 300                          unsigned cs_count,
 301                          bool can_patch,
 302                          struct radeon_winsys_fence *fence);
 303
 304         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 305                               struct radeon_winsys_bo *bo,
 306                               uint8_t priority);
 307
 308         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 309                                     struct radeon_winsys_cs *child);
 310
 311         int (*surface_init)(struct radeon_winsys *ws,
 312                             struct radeon_surf *surf);
 313
 314         int (*surface_best)(struct radeon_winsys *ws,
 315                             struct radeon_surf *surf);
 316
 317         struct radeon_winsys_fence *(*create_fence)();
 318         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 319         bool (*fence_wait)(struct radeon_winsys *ws,
 320                            struct radeon_winsys_fence *fence,
 321                            bool absolute,
 322                            uint64_t timeout);
 323 };
 324
 325 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 326 {
 327         cs->buf[cs->cdw++] = value;
 328 }
 329
 330 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 331                                      const uint32_t *values, unsigned count)
 332 {
 333         memcpy(cs->buf + cs->cdw, values, count * 4);
 334         cs->cdw += count;
 335 }
 336