2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
48 #include "aco_interface.h"
50 #include "util/string_buffer.h"
52 static const struct nir_shader_compiler_options nir_options_llvm
= {
53 .vertex_id_zero_based
= true,
58 .lower_device_index_to_zero
= true,
62 .lower_bitfield_insert_to_bitfield_select
= true,
63 .lower_bitfield_extract
= true,
65 .lower_pack_snorm_2x16
= true,
66 .lower_pack_snorm_4x8
= true,
67 .lower_pack_unorm_2x16
= true,
68 .lower_pack_unorm_4x8
= true,
69 .lower_unpack_snorm_2x16
= true,
70 .lower_unpack_snorm_4x8
= true,
71 .lower_unpack_unorm_2x16
= true,
72 .lower_unpack_unorm_4x8
= true,
73 .lower_extract_byte
= true,
74 .lower_extract_word
= true,
77 .lower_mul_2x32_64
= true,
79 .max_unroll_iterations
= 32,
80 .use_interpolated_input_intrinsics
= true,
81 /* nir_lower_int64() isn't actually called for the LLVM backend, but
82 * this helps the loop unrolling heuristics. */
83 .lower_int64_options
= nir_lower_imul64
|
84 nir_lower_imul_high64
|
85 nir_lower_imul_2x32_64
|
89 .lower_doubles_options
= nir_lower_drcp
|
95 static const struct nir_shader_compiler_options nir_options_aco
= {
96 .vertex_id_zero_based
= true,
100 .lower_flrp64
= true,
101 .lower_device_index_to_zero
= true,
104 .lower_bitfield_insert_to_bitfield_select
= true,
105 .lower_bitfield_extract
= true,
106 .lower_pack_snorm_2x16
= true,
107 .lower_pack_snorm_4x8
= true,
108 .lower_pack_unorm_2x16
= true,
109 .lower_pack_unorm_4x8
= true,
110 .lower_unpack_snorm_2x16
= true,
111 .lower_unpack_snorm_4x8
= true,
112 .lower_unpack_unorm_2x16
= true,
113 .lower_unpack_unorm_4x8
= true,
114 .lower_unpack_half_2x16
= true,
115 .lower_extract_byte
= true,
116 .lower_extract_word
= true,
119 .lower_mul_2x32_64
= true,
120 .lower_rotate
= true,
121 .max_unroll_iterations
= 32,
122 .use_interpolated_input_intrinsics
= true,
123 .lower_int64_options
= nir_lower_imul64
|
124 nir_lower_imul_high64
|
125 nir_lower_imul_2x32_64
|
129 .lower_doubles_options
= nir_lower_drcp
|
136 radv_can_dump_shader(struct radv_device
*device
,
137 struct radv_shader_module
*module
,
138 bool is_gs_copy_shader
)
140 if (!(device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
))
143 return !module
->nir
||
144 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_META_SHADERS
);
146 return is_gs_copy_shader
;
150 radv_can_dump_shader_stats(struct radv_device
*device
,
151 struct radv_shader_module
*module
)
153 /* Only dump non-meta shader stats. */
154 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
155 module
&& !module
->nir
;
158 VkResult
radv_CreateShaderModule(
160 const VkShaderModuleCreateInfo
* pCreateInfo
,
161 const VkAllocationCallbacks
* pAllocator
,
162 VkShaderModule
* pShaderModule
)
164 RADV_FROM_HANDLE(radv_device
, device
, _device
);
165 struct radv_shader_module
*module
;
167 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
168 assert(pCreateInfo
->flags
== 0);
170 module
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
171 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
172 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
174 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
176 vk_object_base_init(&device
->vk
, &module
->base
,
177 VK_OBJECT_TYPE_SHADER_MODULE
);
180 module
->size
= pCreateInfo
->codeSize
;
181 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
183 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
185 *pShaderModule
= radv_shader_module_to_handle(module
);
190 void radv_DestroyShaderModule(
192 VkShaderModule _module
,
193 const VkAllocationCallbacks
* pAllocator
)
195 RADV_FROM_HANDLE(radv_device
, device
, _device
);
196 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
201 vk_object_base_finish(&module
->base
);
202 vk_free2(&device
->vk
.alloc
, pAllocator
, module
);
206 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
210 unsigned lower_flrp
=
211 (shader
->options
->lower_flrp16
? 16 : 0) |
212 (shader
->options
->lower_flrp32
? 32 : 0) |
213 (shader
->options
->lower_flrp64
? 64 : 0);
218 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
219 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
221 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
222 NIR_PASS_V(shader
, nir_lower_pack
);
225 /* Only run this pass in the first call to
226 * radv_optimize_nir. Later calls assume that we've
227 * lowered away any copy_deref instructions and we
228 * don't want to introduce any more.
230 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
233 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
234 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
235 NIR_PASS(progress
, shader
, nir_remove_dead_variables
,
236 nir_var_function_temp
| nir_var_shader_in
| nir_var_shader_out
,
239 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
, NULL
);
240 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
242 NIR_PASS(progress
, shader
, nir_copy_prop
);
243 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
244 NIR_PASS(progress
, shader
, nir_opt_dce
);
245 if (nir_opt_trivial_continues(shader
)) {
247 NIR_PASS(progress
, shader
, nir_copy_prop
);
248 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
249 NIR_PASS(progress
, shader
, nir_opt_dce
);
251 NIR_PASS(progress
, shader
, nir_opt_if
, true);
252 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
253 NIR_PASS(progress
, shader
, nir_opt_cse
);
254 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
255 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
256 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
258 if (lower_flrp
!= 0) {
259 bool lower_flrp_progress
= false;
260 NIR_PASS(lower_flrp_progress
,
264 false /* always_precise */,
265 shader
->options
->lower_ffma
);
266 if (lower_flrp_progress
) {
267 NIR_PASS(progress
, shader
,
268 nir_opt_constant_folding
);
272 /* Nothing should rematerialize any flrps, so we only
273 * need to do this lowering once.
278 NIR_PASS(progress
, shader
, nir_opt_undef
);
279 if (shader
->options
->max_unroll_iterations
) {
280 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
282 } while (progress
&& !optimize_conservatively
);
284 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
285 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
286 NIR_PASS(progress
, shader
, nir_opt_move
, nir_move_load_ubo
);
290 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
292 assert(glsl_type_is_vector_or_scalar(type
));
294 uint32_t comp_size
= glsl_type_is_boolean(type
) ? 4 : glsl_get_bit_size(type
) / 8;
295 unsigned length
= glsl_get_vector_elements(type
);
296 *size
= comp_size
* length
,
301 radv_shader_compile_to_nir(struct radv_device
*device
,
302 struct radv_shader_module
*module
,
303 const char *entrypoint_name
,
304 gl_shader_stage stage
,
305 const VkSpecializationInfo
*spec_info
,
306 const VkPipelineCreateFlags flags
,
307 const struct radv_pipeline_layout
*layout
,
308 unsigned subgroup_size
, unsigned ballot_bit_size
)
311 const nir_shader_compiler_options
*nir_options
=
312 device
->physical_device
->use_llvm
? &nir_options_llvm
:
316 /* Some things such as our meta clear/blit code will give us a NIR
317 * shader directly. In that case, we just ignore the SPIR-V entirely
318 * and just use the NIR shader */
320 nir
->options
= nir_options
;
321 nir_validate_shader(nir
, "in internal shader");
323 assert(exec_list_length(&nir
->functions
) == 1);
325 uint32_t *spirv
= (uint32_t *) module
->data
;
326 assert(module
->size
% 4 == 0);
328 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
329 radv_print_spirv(module
->data
, module
->size
, stderr
);
331 uint32_t num_spec_entries
= 0;
332 struct nir_spirv_specialization
*spec_entries
= NULL
;
333 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
334 num_spec_entries
= spec_info
->mapEntryCount
;
335 spec_entries
= calloc(num_spec_entries
, sizeof(*spec_entries
));
336 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
337 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
338 const void *data
= spec_info
->pData
+ entry
.offset
;
339 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
341 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
342 switch (entry
.size
) {
344 spec_entries
[i
].value
.u64
= *(const uint64_t *)data
;
347 spec_entries
[i
].value
.u32
= *(const uint32_t *)data
;
350 spec_entries
[i
].value
.u16
= *(const uint16_t *)data
;
353 spec_entries
[i
].value
.u8
= *(const uint8_t *)data
;
356 assert(!"Invalid spec constant size");
361 const struct spirv_to_nir_options spirv_options
= {
362 .lower_ubo_ssbo_access_to_offsets
= true,
364 .amd_fragment_mask
= true,
365 .amd_gcn_shader
= true,
366 .amd_image_gather_bias_lod
= true,
367 .amd_image_read_write_lod
= true,
368 .amd_shader_ballot
= true,
369 .amd_shader_explicit_vertex_parameter
= true,
370 .amd_trinary_minmax
= true,
371 .demote_to_helper_invocation
= true,
372 .derivative_group
= true,
373 .descriptor_array_dynamic_indexing
= true,
374 .descriptor_array_non_uniform_indexing
= true,
375 .descriptor_indexing
= true,
376 .device_group
= true,
377 .draw_parameters
= true,
378 .float_controls
= true,
379 .float16
= device
->physical_device
->rad_info
.has_packed_math_16bit
,
380 .float32_atomic_add
= true,
382 .geometry_streams
= true,
383 .image_ms_array
= true,
384 .image_read_without_format
= true,
385 .image_write_without_format
= true,
389 .int64_atomics
= true,
392 .physical_storage_buffer_address
= true,
393 .post_depth_coverage
= true,
394 .runtime_descriptor_array
= true,
395 .shader_clock
= true,
396 .shader_viewport_index_layer
= true,
397 .stencil_export
= true,
398 .storage_8bit
= true,
399 .storage_16bit
= true,
400 .storage_image_ms
= true,
401 .subgroup_arithmetic
= true,
402 .subgroup_ballot
= true,
403 .subgroup_basic
= true,
404 .subgroup_quad
= true,
405 .subgroup_shuffle
= true,
406 .subgroup_vote
= true,
407 .tessellation
= true,
408 .transform_feedback
= true,
409 .variable_pointers
= true,
411 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
412 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
413 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
414 .push_const_addr_format
= nir_address_format_logical
,
415 .shared_addr_format
= nir_address_format_32bit_offset
,
416 .frag_coord_is_sysval
= true,
418 nir
= spirv_to_nir(spirv
, module
->size
/ 4,
419 spec_entries
, num_spec_entries
,
420 stage
, entrypoint_name
,
421 &spirv_options
, nir_options
);
422 assert(nir
->info
.stage
== stage
);
423 nir_validate_shader(nir
, "after spirv_to_nir");
427 /* We have to lower away local constant initializers right before we
428 * inline functions. That way they get properly initialized at the top
429 * of the function and not at the top of its caller.
431 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
432 NIR_PASS_V(nir
, nir_lower_returns
);
433 NIR_PASS_V(nir
, nir_inline_functions
);
434 NIR_PASS_V(nir
, nir_copy_prop
);
435 NIR_PASS_V(nir
, nir_opt_deref
);
437 /* Pick off the single entrypoint that we want */
438 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
439 if (func
->is_entrypoint
)
440 func
->name
= ralloc_strdup(func
, "main");
442 exec_node_remove(&func
->node
);
444 assert(exec_list_length(&nir
->functions
) == 1);
446 /* Make sure we lower constant initializers on output variables so that
447 * nir_remove_dead_variables below sees the corresponding stores
449 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_shader_out
);
451 /* Now that we've deleted all but the main function, we can go ahead and
452 * lower the rest of the constant initializers.
454 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
456 /* Split member structs. We do this before lower_io_to_temporaries so that
457 * it doesn't lower system values to temporaries by accident.
459 NIR_PASS_V(nir
, nir_split_var_copies
);
460 NIR_PASS_V(nir
, nir_split_per_member_structs
);
462 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
463 !device
->physical_device
->use_llvm
)
464 NIR_PASS_V(nir
, nir_lower_io_to_vector
, nir_var_shader_out
);
465 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
466 NIR_PASS_V(nir
, nir_lower_input_attachments
, true);
468 NIR_PASS_V(nir
, nir_remove_dead_variables
,
469 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
| nir_var_mem_shared
,
472 NIR_PASS_V(nir
, nir_propagate_invariant
);
474 NIR_PASS_V(nir
, nir_lower_system_values
);
475 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
476 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
477 if (device
->instance
->debug_flags
& RADV_DEBUG_DISCARD_TO_DEMOTE
)
478 NIR_PASS_V(nir
, nir_lower_discard_to_demote
);
480 nir_lower_doubles_options lower_doubles
=
481 nir
->options
->lower_doubles_options
;
483 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
484 /* GFX6 doesn't support v_floor_f64 and the precision
485 * of v_fract_f64 which is used to implement 64-bit
486 * floor is less than what Vulkan requires.
488 lower_doubles
|= nir_lower_dfloor
;
491 NIR_PASS_V(nir
, nir_lower_doubles
, NULL
, lower_doubles
);
494 /* Vulkan uses the separate-shader linking model */
495 nir
->info
.separate_shader
= true;
497 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
499 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
500 nir_lower_gs_intrinsics(nir
, true);
502 static const nir_lower_tex_options tex_options
= {
504 .lower_tg4_offsets
= true,
507 nir_lower_tex(nir
, &tex_options
);
509 nir_lower_vars_to_ssa(nir
);
511 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
512 nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
513 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
514 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
515 nir_shader_get_entrypoint(nir
), true, true);
516 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
517 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
518 nir_shader_get_entrypoint(nir
), true, false);
521 nir_split_var_copies(nir
);
523 nir_lower_global_vars_to_local(nir
);
524 nir_remove_dead_variables(nir
, nir_var_function_temp
, NULL
);
525 bool gfx7minus
= device
->physical_device
->rad_info
.chip_class
<= GFX7
;
526 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
527 .subgroup_size
= subgroup_size
,
528 .ballot_bit_size
= ballot_bit_size
,
529 .lower_to_scalar
= 1,
530 .lower_subgroup_masks
= 1,
532 .lower_shuffle_to_32bit
= 1,
533 .lower_vote_eq_to_ballot
= 1,
534 .lower_quad_broadcast_dynamic
= 1,
535 .lower_quad_broadcast_dynamic_to_const
= gfx7minus
,
536 .lower_shuffle_to_swizzle_amd
= 1,
539 nir_lower_load_const_to_scalar(nir
);
541 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
542 radv_optimize_nir(nir
, false, true);
544 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
545 * to remove any copies introduced by nir_opt_find_array_copies().
547 nir_lower_var_copies(nir
);
549 /* Lower deref operations for compute shared memory. */
550 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
551 NIR_PASS_V(nir
, nir_lower_vars_to_explicit_types
,
552 nir_var_mem_shared
, shared_var_info
);
553 NIR_PASS_V(nir
, nir_lower_explicit_io
,
554 nir_var_mem_shared
, nir_address_format_32bit_offset
);
557 /* Lower large variables that are always constant with load_constant
558 * intrinsics, which get turned into PC-relative loads from a data
559 * section next to the shader.
561 NIR_PASS_V(nir
, nir_opt_large_constants
,
562 glsl_get_natural_size_align_bytes
, 16);
564 /* Indirect lowering must be called after the radv_optimize_nir() loop
565 * has been called at least once. Otherwise indirect lowering can
566 * bloat the instruction count of the loop and cause it to be
567 * considered too large for unrolling.
569 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
570 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
576 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
578 return glsl_count_attribute_slots(type
, false);
581 static nir_variable
*
582 find_layer_in_var(nir_shader
*nir
)
584 nir_foreach_variable(var
, &nir
->inputs
) {
585 if (var
->data
.location
== VARYING_SLOT_LAYER
) {
591 nir_variable_create(nir
, nir_var_shader_in
, glsl_int_type(), "layer id");
592 var
->data
.location
= VARYING_SLOT_LAYER
;
593 var
->data
.interpolation
= INTERP_MODE_FLAT
;
597 /* We use layered rendering to implement multiview, which means we need to map
598 * view_index to gl_Layer. The attachment lowering also uses needs to know the
599 * layer so that it can sample from the correct layer. The code generates a
600 * load from the layer_id sysval, but since we don't have a way to get at this
601 * information from the fragment shader, we also need to lower this to the
602 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
603 * slot, before lowering io, so that nir_assign_var_locations() will give the
604 * LAYER varying the correct driver_location.
608 lower_view_index(nir_shader
*nir
)
610 bool progress
= false;
611 nir_function_impl
*entry
= nir_shader_get_entrypoint(nir
);
613 nir_builder_init(&b
, entry
);
615 nir_variable
*layer
= NULL
;
616 nir_foreach_block(block
, entry
) {
617 nir_foreach_instr_safe(instr
, block
) {
618 if (instr
->type
!= nir_instr_type_intrinsic
)
621 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
622 if (load
->intrinsic
!= nir_intrinsic_load_view_index
&&
623 load
->intrinsic
!= nir_intrinsic_load_layer_id
)
627 layer
= find_layer_in_var(nir
);
629 b
.cursor
= nir_before_instr(instr
);
630 nir_ssa_def
*def
= nir_load_var(&b
, layer
);
631 nir_ssa_def_rewrite_uses(&load
->dest
.ssa
,
632 nir_src_for_ssa(def
));
634 nir_instr_remove(instr
);
643 radv_lower_fs_io(nir_shader
*nir
)
645 NIR_PASS_V(nir
, lower_view_index
);
646 nir_assign_io_var_locations(&nir
->inputs
, &nir
->num_inputs
,
647 MESA_SHADER_FRAGMENT
);
649 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
, type_size_vec4
, 0);
651 /* This pass needs actual constants */
652 nir_opt_constant_folding(nir
);
654 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_in
);
659 radv_alloc_shader_memory(struct radv_device
*device
,
660 struct radv_shader_variant
*shader
)
662 mtx_lock(&device
->shader_slab_mutex
);
663 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
665 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
666 if (s
->bo_offset
- offset
>= shader
->code_size
) {
667 shader
->bo
= slab
->bo
;
668 shader
->bo_offset
= offset
;
669 list_addtail(&shader
->slab_list
, &s
->slab_list
);
670 mtx_unlock(&device
->shader_slab_mutex
);
671 return slab
->ptr
+ offset
;
673 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
675 if (offset
<= slab
->size
&& slab
->size
- offset
>= shader
->code_size
) {
676 shader
->bo
= slab
->bo
;
677 shader
->bo_offset
= offset
;
678 list_addtail(&shader
->slab_list
, &slab
->shaders
);
679 mtx_unlock(&device
->shader_slab_mutex
);
680 return slab
->ptr
+ offset
;
684 mtx_unlock(&device
->shader_slab_mutex
);
685 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
687 slab
->size
= MAX2(256 * 1024, shader
->code_size
);
688 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
690 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
691 (device
->physical_device
->rad_info
.cpdma_prefetch_writes_memory
?
692 0 : RADEON_FLAG_READ_ONLY
),
693 RADV_BO_PRIORITY_SHADER
);
699 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
701 device
->ws
->buffer_destroy(slab
->bo
);
706 list_inithead(&slab
->shaders
);
708 mtx_lock(&device
->shader_slab_mutex
);
709 list_add(&slab
->slabs
, &device
->shader_slabs
);
711 shader
->bo
= slab
->bo
;
712 shader
->bo_offset
= 0;
713 list_add(&shader
->slab_list
, &slab
->shaders
);
714 mtx_unlock(&device
->shader_slab_mutex
);
719 radv_destroy_shader_slabs(struct radv_device
*device
)
721 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
722 device
->ws
->buffer_destroy(slab
->bo
);
725 mtx_destroy(&device
->shader_slab_mutex
);
728 /* For the UMR disassembler. */
729 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
730 #define DEBUGGER_NUM_MARKERS 5
733 radv_get_shader_binary_size(size_t code_size
)
735 return code_size
+ DEBUGGER_NUM_MARKERS
* 4;
738 static void radv_postprocess_config(const struct radv_physical_device
*pdevice
,
739 const struct ac_shader_config
*config_in
,
740 const struct radv_shader_info
*info
,
741 gl_shader_stage stage
,
742 struct ac_shader_config
*config_out
)
744 bool scratch_enabled
= config_in
->scratch_bytes_per_wave
> 0;
745 unsigned vgpr_comp_cnt
= 0;
746 unsigned num_input_vgprs
= info
->num_input_vgprs
;
748 if (stage
== MESA_SHADER_FRAGMENT
) {
749 num_input_vgprs
= ac_get_fs_input_vgpr_cnt(config_in
, NULL
, NULL
);
752 unsigned num_vgprs
= MAX2(config_in
->num_vgprs
, num_input_vgprs
);
753 /* +3 for scratch wave offset and VCC */
754 unsigned num_sgprs
= MAX2(config_in
->num_sgprs
, info
->num_input_sgprs
+ 3);
755 unsigned num_shared_vgprs
= config_in
->num_shared_vgprs
;
756 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
757 assert((pdevice
->rad_info
.chip_class
>= GFX10
&& num_shared_vgprs
% 8 == 0)
758 || (pdevice
->rad_info
.chip_class
< GFX10
&& num_shared_vgprs
== 0));
759 unsigned num_shared_vgpr_blocks
= num_shared_vgprs
/ 8;
761 *config_out
= *config_in
;
762 config_out
->num_vgprs
= num_vgprs
;
763 config_out
->num_sgprs
= num_sgprs
;
764 config_out
->num_shared_vgprs
= num_shared_vgprs
;
766 config_out
->rsrc2
= S_00B12C_USER_SGPR(info
->num_user_sgprs
) |
767 S_00B12C_SCRATCH_EN(scratch_enabled
);
769 if (!pdevice
->use_ngg_streamout
) {
770 config_out
->rsrc2
|= S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
771 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
772 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
773 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
774 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
777 config_out
->rsrc1
= S_00B848_VGPRS((num_vgprs
- 1) /
778 (info
->wave_size
== 32 ? 8 : 4)) |
779 S_00B848_DX10_CLAMP(1) |
780 S_00B848_FLOAT_MODE(config_out
->float_mode
);
782 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
783 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(info
->num_user_sgprs
>> 5);
785 config_out
->rsrc1
|= S_00B228_SGPRS((num_sgprs
- 1) / 8);
786 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(info
->num_user_sgprs
>> 5);
790 case MESA_SHADER_TESS_EVAL
:
792 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
793 config_out
->rsrc2
|= S_00B22C_OC_LDS_EN(1);
794 } else if (info
->tes
.as_es
) {
795 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
796 vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
798 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
800 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->uses_prim_id
;
801 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
803 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
804 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
806 config_out
->rsrc2
|= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
808 case MESA_SHADER_TESS_CTRL
:
809 if (pdevice
->rad_info
.chip_class
>= GFX9
) {
810 /* We need at least 2 components for LS.
811 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
812 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
814 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
815 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 3 : 1;
817 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
820 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
822 config_out
->rsrc1
|= S_00B428_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
823 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
824 config_out
->rsrc2
|= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
826 case MESA_SHADER_VERTEX
:
828 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
829 } else if (info
->vs
.as_ls
) {
830 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
831 /* We need at least 2 components for LS.
832 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
833 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
835 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
836 } else if (info
->vs
.as_es
) {
837 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
838 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
839 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 1 : 0;
841 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
842 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
843 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
845 if (info
->vs
.needs_instance_id
&& pdevice
->rad_info
.chip_class
>= GFX10
) {
847 } else if (info
->vs
.export_prim_id
) {
849 } else if (info
->vs
.needs_instance_id
) {
855 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
857 config_out
->rsrc2
|= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
859 case MESA_SHADER_FRAGMENT
:
860 config_out
->rsrc1
|= S_00B028_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
861 config_out
->rsrc2
|= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
863 case MESA_SHADER_GEOMETRY
:
864 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
865 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
866 config_out
->rsrc2
|= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
868 case MESA_SHADER_COMPUTE
:
869 config_out
->rsrc1
|= S_00B848_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
870 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
872 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
873 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
874 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
875 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
876 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
877 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
878 S_00B84C_LDS_SIZE(config_in
->lds_size
);
879 config_out
->rsrc3
|= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
883 unreachable("unsupported shader type");
887 if (pdevice
->rad_info
.chip_class
>= GFX10
&& info
->is_ngg
&&
888 (stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_GEOMETRY
)) {
889 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
890 gl_shader_stage es_stage
= stage
;
891 if (stage
== MESA_SHADER_GEOMETRY
)
892 es_stage
= info
->gs
.es_type
;
894 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
895 if (es_stage
== MESA_SHADER_VERTEX
) {
896 es_vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 3 : 0;
897 } else if (es_stage
== MESA_SHADER_TESS_EVAL
) {
898 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->uses_prim_id
;
899 es_vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
901 unreachable("Unexpected ES shader stage");
903 bool tes_triangles
= stage
== MESA_SHADER_TESS_EVAL
&&
904 info
->tes
.primitive_mode
>= 4; /* GL_TRIANGLES */
905 if (info
->uses_invocation_id
|| stage
== MESA_SHADER_VERTEX
) {
906 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
907 } else if (info
->uses_prim_id
) {
908 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
909 } else if (info
->gs
.vertices_in
>= 3 || tes_triangles
) {
910 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
912 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
915 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
) |
916 S_00B228_WGP_MODE(1);
917 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
918 S_00B22C_LDS_SIZE(config_in
->lds_size
) |
919 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
);
920 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
921 stage
== MESA_SHADER_GEOMETRY
) {
922 unsigned es_type
= info
->gs
.es_type
;
923 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
925 if (es_type
== MESA_SHADER_VERTEX
) {
926 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
927 if (info
->vs
.needs_instance_id
) {
928 es_vgpr_comp_cnt
= pdevice
->rad_info
.chip_class
>= GFX10
? 3 : 1;
930 es_vgpr_comp_cnt
= 0;
932 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
933 es_vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
935 unreachable("invalid shader ES type");
938 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
939 * VGPR[0:4] are always loaded.
941 if (info
->uses_invocation_id
) {
942 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
943 } else if (info
->uses_prim_id
) {
944 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
945 } else if (info
->gs
.vertices_in
>= 3) {
946 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
948 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
951 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
952 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
953 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
954 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
955 stage
== MESA_SHADER_TESS_CTRL
) {
956 config_out
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
958 config_out
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
962 struct radv_shader_variant
*
963 radv_shader_variant_create(struct radv_device
*device
,
964 const struct radv_shader_binary
*binary
,
965 bool keep_shader_info
)
967 struct ac_shader_config config
= {0};
968 struct ac_rtld_binary rtld_binary
= {0};
969 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
973 variant
->ref_count
= 1;
975 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
976 struct ac_rtld_symbol lds_symbols
[2];
977 unsigned num_lds_symbols
= 0;
978 const char *elf_data
= (const char *)((struct radv_shader_binary_rtld
*)binary
)->data
;
979 size_t elf_size
= ((struct radv_shader_binary_rtld
*)binary
)->elf_size
;
981 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
982 (binary
->stage
== MESA_SHADER_GEOMETRY
|| binary
->info
.is_ngg
) &&
983 !binary
->is_gs_copy_shader
) {
984 /* We add this symbol even on LLVM <= 8 to ensure that
985 * shader->config.lds_size is set correctly below.
987 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
988 sym
->name
= "esgs_ring";
989 sym
->size
= binary
->info
.ngg_info
.esgs_ring_size
;
990 sym
->align
= 64 * 1024;
993 if (binary
->info
.is_ngg
&&
994 binary
->stage
== MESA_SHADER_GEOMETRY
) {
995 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
996 sym
->name
= "ngg_emit";
997 sym
->size
= binary
->info
.ngg_info
.ngg_emit_size
* 4;
1001 struct ac_rtld_open_info open_info
= {
1002 .info
= &device
->physical_device
->rad_info
,
1003 .shader_type
= binary
->stage
,
1004 .wave_size
= binary
->info
.wave_size
,
1006 .elf_ptrs
= &elf_data
,
1007 .elf_sizes
= &elf_size
,
1008 .num_shared_lds_symbols
= num_lds_symbols
,
1009 .shared_lds_symbols
= lds_symbols
,
1012 if (!ac_rtld_open(&rtld_binary
, open_info
)) {
1017 if (!ac_rtld_read_config(&device
->physical_device
->rad_info
,
1018 &rtld_binary
, &config
)) {
1019 ac_rtld_close(&rtld_binary
);
1024 if (rtld_binary
.lds_size
> 0) {
1025 unsigned alloc_granularity
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1026 config
.lds_size
= align(rtld_binary
.lds_size
, alloc_granularity
) / alloc_granularity
;
1029 variant
->code_size
= rtld_binary
.rx_size
;
1030 variant
->exec_size
= rtld_binary
.exec_size
;
1032 assert(binary
->type
== RADV_BINARY_TYPE_LEGACY
);
1033 config
= ((struct radv_shader_binary_legacy
*)binary
)->config
;
1034 variant
->code_size
= radv_get_shader_binary_size(((struct radv_shader_binary_legacy
*)binary
)->code_size
);
1035 variant
->exec_size
= ((struct radv_shader_binary_legacy
*)binary
)->exec_size
;
1038 variant
->info
= binary
->info
;
1039 radv_postprocess_config(device
->physical_device
, &config
, &binary
->info
,
1040 binary
->stage
, &variant
->config
);
1042 void *dest_ptr
= radv_alloc_shader_memory(device
, variant
);
1044 if (binary
->type
== RADV_BINARY_TYPE_RTLD
)
1045 ac_rtld_close(&rtld_binary
);
1050 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
1051 struct radv_shader_binary_rtld
* bin
= (struct radv_shader_binary_rtld
*)binary
;
1052 struct ac_rtld_upload_info info
= {
1053 .binary
= &rtld_binary
,
1054 .rx_va
= radv_buffer_get_va(variant
->bo
) + variant
->bo_offset
,
1058 if (!ac_rtld_upload(&info
)) {
1059 radv_shader_variant_destroy(device
, variant
);
1060 ac_rtld_close(&rtld_binary
);
1064 if (keep_shader_info
||
1065 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
)) {
1066 const char *disasm_data
;
1068 if (!ac_rtld_get_section_by_name(&rtld_binary
, ".AMDGPU.disasm", &disasm_data
, &disasm_size
)) {
1069 radv_shader_variant_destroy(device
, variant
);
1070 ac_rtld_close(&rtld_binary
);
1074 variant
->ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->elf_size
)) : NULL
;
1075 variant
->disasm_string
= malloc(disasm_size
+ 1);
1076 memcpy(variant
->disasm_string
, disasm_data
, disasm_size
);
1077 variant
->disasm_string
[disasm_size
] = 0;
1080 ac_rtld_close(&rtld_binary
);
1082 struct radv_shader_binary_legacy
* bin
= (struct radv_shader_binary_legacy
*)binary
;
1083 memcpy(dest_ptr
, bin
->data
+ bin
->stats_size
, bin
->code_size
);
1085 /* Add end-of-code markers for the UMR disassembler. */
1086 uint32_t *ptr32
= (uint32_t *)dest_ptr
+ bin
->code_size
/ 4;
1087 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
1088 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
1090 variant
->ir_string
= bin
->ir_size
? strdup((const char*)(bin
->data
+ bin
->stats_size
+ bin
->code_size
)) : NULL
;
1091 variant
->disasm_string
= bin
->disasm_size
? strdup((const char*)(bin
->data
+ bin
->stats_size
+ bin
->code_size
+ bin
->ir_size
)) : NULL
;
1093 if (bin
->stats_size
) {
1094 variant
->statistics
= calloc(bin
->stats_size
, 1);
1095 memcpy(variant
->statistics
, bin
->data
, bin
->stats_size
);
1102 radv_dump_nir_shaders(struct nir_shader
* const *shaders
,
1108 FILE *f
= open_memstream(&data
, &size
);
1110 for (int i
= 0; i
< shader_count
; ++i
)
1111 nir_print_shader(shaders
[i
], f
);
1115 ret
= malloc(size
+ 1);
1117 memcpy(ret
, data
, size
);
1124 static struct radv_shader_variant
*
1125 shader_variant_compile(struct radv_device
*device
,
1126 struct radv_shader_module
*module
,
1127 struct nir_shader
* const *shaders
,
1129 gl_shader_stage stage
,
1130 struct radv_shader_info
*info
,
1131 struct radv_nir_compiler_options
*options
,
1132 bool gs_copy_shader
,
1133 bool keep_shader_info
,
1134 bool keep_statistic_info
,
1135 struct radv_shader_binary
**binary_out
)
1137 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
1138 struct radv_shader_binary
*binary
= NULL
;
1140 options
->family
= chip_family
;
1141 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
1142 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
1143 options
->dump_preoptir
= options
->dump_shader
&&
1144 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
1145 options
->record_ir
= keep_shader_info
;
1146 options
->record_stats
= keep_statistic_info
;
1147 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
1148 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
1149 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
1150 options
->has_ls_vgpr_init_bug
= device
->physical_device
->rad_info
.has_ls_vgpr_init_bug
;
1151 options
->use_ngg_streamout
= device
->physical_device
->use_ngg_streamout
;
1152 options
->enable_mrt_output_nan_fixup
= device
->instance
->enable_mrt_output_nan_fixup
;
1154 struct radv_shader_args args
= {};
1155 args
.options
= options
;
1156 args
.shader_info
= info
;
1157 args
.is_gs_copy_shader
= gs_copy_shader
;
1158 radv_declare_shader_args(&args
,
1159 gs_copy_shader
? MESA_SHADER_VERTEX
1160 : shaders
[shader_count
- 1]->info
.stage
,
1162 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
1163 : MESA_SHADER_VERTEX
);
1165 if (device
->physical_device
->use_llvm
||
1166 options
->dump_shader
|| options
->record_ir
)
1167 ac_init_llvm_once();
1169 if (device
->physical_device
->use_llvm
) {
1170 llvm_compile_shader(device
, shader_count
, shaders
, &binary
, &args
);
1172 aco_compile_shader(shader_count
, shaders
, &binary
, &args
);
1175 binary
->info
= *info
;
1177 struct radv_shader_variant
*variant
= radv_shader_variant_create(device
, binary
,
1184 if (options
->dump_shader
) {
1185 fprintf(stderr
, "%s", radv_get_shader_name(info
, shaders
[0]->info
.stage
));
1186 for (int i
= 1; i
< shader_count
; ++i
)
1187 fprintf(stderr
, " + %s", radv_get_shader_name(info
, shaders
[i
]->info
.stage
));
1189 fprintf(stderr
, "\ndisasm:\n%s\n", variant
->disasm_string
);
1193 if (keep_shader_info
) {
1194 variant
->nir_string
= radv_dump_nir_shaders(shaders
, shader_count
);
1195 if (!gs_copy_shader
&& !module
->nir
) {
1196 variant
->spirv
= malloc(module
->size
);
1197 if (!variant
->spirv
) {
1203 memcpy(variant
->spirv
, module
->data
, module
->size
);
1204 variant
->spirv_size
= module
->size
;
1209 *binary_out
= binary
;
1216 struct radv_shader_variant
*
1217 radv_shader_variant_compile(struct radv_device
*device
,
1218 struct radv_shader_module
*module
,
1219 struct nir_shader
*const *shaders
,
1221 struct radv_pipeline_layout
*layout
,
1222 const struct radv_shader_variant_key
*key
,
1223 struct radv_shader_info
*info
,
1224 bool keep_shader_info
, bool keep_statistic_info
,
1225 struct radv_shader_binary
**binary_out
)
1227 struct radv_nir_compiler_options options
= {0};
1229 options
.layout
= layout
;
1233 options
.explicit_scratch_args
= !device
->physical_device
->use_llvm
;
1234 options
.robust_buffer_access
= device
->robust_buffer_access
;
1236 return shader_variant_compile(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
, info
,
1237 &options
, false, keep_shader_info
, keep_statistic_info
, binary_out
);
1240 struct radv_shader_variant
*
1241 radv_create_gs_copy_shader(struct radv_device
*device
,
1242 struct nir_shader
*shader
,
1243 struct radv_shader_info
*info
,
1244 struct radv_shader_binary
**binary_out
,
1245 bool keep_shader_info
, bool keep_statistic_info
,
1248 struct radv_nir_compiler_options options
= {0};
1250 options
.explicit_scratch_args
= !device
->physical_device
->use_llvm
;
1251 options
.key
.has_multiview_view_index
= multiview
;
1253 return shader_variant_compile(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
1254 info
, &options
, true, keep_shader_info
, keep_statistic_info
, binary_out
);
1258 radv_shader_variant_destroy(struct radv_device
*device
,
1259 struct radv_shader_variant
*variant
)
1261 if (!p_atomic_dec_zero(&variant
->ref_count
))
1264 mtx_lock(&device
->shader_slab_mutex
);
1265 list_del(&variant
->slab_list
);
1266 mtx_unlock(&device
->shader_slab_mutex
);
1268 free(variant
->spirv
);
1269 free(variant
->nir_string
);
1270 free(variant
->disasm_string
);
1271 free(variant
->ir_string
);
1272 free(variant
->statistics
);
1277 radv_get_shader_name(struct radv_shader_info
*info
,
1278 gl_shader_stage stage
)
1281 case MESA_SHADER_VERTEX
:
1283 return "Vertex Shader as LS";
1284 else if (info
->vs
.as_es
)
1285 return "Vertex Shader as ES";
1286 else if (info
->is_ngg
)
1287 return "Vertex Shader as ESGS";
1289 return "Vertex Shader as VS";
1290 case MESA_SHADER_TESS_CTRL
:
1291 return "Tessellation Control Shader";
1292 case MESA_SHADER_TESS_EVAL
:
1293 if (info
->tes
.as_es
)
1294 return "Tessellation Evaluation Shader as ES";
1295 else if (info
->is_ngg
)
1296 return "Tessellation Evaluation Shader as ESGS";
1298 return "Tessellation Evaluation Shader as VS";
1299 case MESA_SHADER_GEOMETRY
:
1300 return "Geometry Shader";
1301 case MESA_SHADER_FRAGMENT
:
1302 return "Pixel Shader";
1303 case MESA_SHADER_COMPUTE
:
1304 return "Compute Shader";
1306 return "Unknown shader";
1311 radv_get_max_workgroup_size(enum chip_class chip_class
,
1312 gl_shader_stage stage
,
1313 const unsigned *sizes
)
1316 case MESA_SHADER_TESS_CTRL
:
1317 return chip_class
>= GFX7
? 128 : 64;
1318 case MESA_SHADER_GEOMETRY
:
1319 return chip_class
>= GFX9
? 128 : 64;
1320 case MESA_SHADER_COMPUTE
:
1326 unsigned max_workgroup_size
= sizes
[0] * sizes
[1] * sizes
[2];
1327 return max_workgroup_size
;
1331 radv_get_max_waves(struct radv_device
*device
,
1332 struct radv_shader_variant
*variant
,
1333 gl_shader_stage stage
)
1335 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
1336 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
1337 uint8_t wave_size
= variant
->info
.wave_size
;
1338 struct ac_shader_config
*conf
= &variant
->config
;
1339 unsigned max_simd_waves
;
1340 unsigned lds_per_wave
= 0;
1342 max_simd_waves
= device
->physical_device
->rad_info
.max_wave64_per_simd
;
1344 if (stage
== MESA_SHADER_FRAGMENT
) {
1345 lds_per_wave
= conf
->lds_size
* lds_increment
+
1346 align(variant
->info
.ps
.num_interp
* 48,
1348 } else if (stage
== MESA_SHADER_COMPUTE
) {
1349 unsigned max_workgroup_size
=
1350 radv_get_max_workgroup_size(chip_class
, stage
, variant
->info
.cs
.block_size
);
1351 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
1352 DIV_ROUND_UP(max_workgroup_size
, wave_size
);
1355 if (conf
->num_sgprs
) {
1356 unsigned sgprs
= align(conf
->num_sgprs
, chip_class
>= GFX8
? 16 : 8);
1358 MIN2(max_simd_waves
,
1359 device
->physical_device
->rad_info
.num_physical_sgprs_per_simd
/
1363 if (conf
->num_vgprs
) {
1364 unsigned vgprs
= align(conf
->num_vgprs
, wave_size
== 32 ? 8 : 4);
1366 MIN2(max_simd_waves
,
1367 device
->physical_device
->rad_info
.num_physical_wave64_vgprs_per_simd
/ vgprs
);
1370 unsigned max_lds_per_simd
= device
->physical_device
->rad_info
.lds_size_per_workgroup
/ device
->physical_device
->rad_info
.num_simd_per_compute_unit
;
1372 max_simd_waves
= MIN2(max_simd_waves
, max_lds_per_simd
/ lds_per_wave
);
1374 return max_simd_waves
;
1378 generate_shader_stats(struct radv_device
*device
,
1379 struct radv_shader_variant
*variant
,
1380 gl_shader_stage stage
,
1381 struct _mesa_string_buffer
*buf
)
1383 struct ac_shader_config
*conf
= &variant
->config
;
1384 unsigned max_simd_waves
= radv_get_max_waves(device
, variant
, stage
);
1386 if (stage
== MESA_SHADER_FRAGMENT
) {
1387 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
1388 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1389 "SPI_PS_INPUT_ENA = 0x%04x\n",
1390 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
1393 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
1396 "Spilled SGPRs: %d\n"
1397 "Spilled VGPRs: %d\n"
1398 "PrivMem VGPRS: %d\n"
1399 "Code Size: %d bytes\n"
1401 "Scratch: %d bytes per wave\n"
1403 conf
->num_sgprs
, conf
->num_vgprs
,
1404 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
1405 variant
->info
.private_mem_vgprs
, variant
->exec_size
,
1406 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
1409 if (variant
->statistics
) {
1410 _mesa_string_buffer_printf(buf
, "*** COMPILER STATS ***\n");
1411 for (unsigned i
= 0; i
< variant
->statistics
->count
; i
++) {
1412 struct radv_compiler_statistic_info
*info
= &variant
->statistics
->infos
[i
];
1413 uint32_t value
= variant
->statistics
->values
[i
];
1414 _mesa_string_buffer_printf(buf
, "%s: %lu\n", info
->name
, value
);
1418 _mesa_string_buffer_printf(buf
, "********************\n\n\n");
1422 radv_shader_dump_stats(struct radv_device
*device
,
1423 struct radv_shader_variant
*variant
,
1424 gl_shader_stage stage
,
1427 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
1429 generate_shader_stats(device
, variant
, stage
, buf
);
1431 fprintf(file
, "\n%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1432 fprintf(file
, "%s", buf
->buf
);
1434 _mesa_string_buffer_destroy(buf
);
1438 radv_GetShaderInfoAMD(VkDevice _device
,
1439 VkPipeline _pipeline
,
1440 VkShaderStageFlagBits shaderStage
,
1441 VkShaderInfoTypeAMD infoType
,
1445 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1446 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
1447 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
1448 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
1449 struct _mesa_string_buffer
*buf
;
1450 VkResult result
= VK_SUCCESS
;
1452 /* Spec doesn't indicate what to do if the stage is invalid, so just
1453 * return no info for this. */
1455 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1458 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
1460 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
1462 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1463 struct ac_shader_config
*conf
= &variant
->config
;
1465 VkShaderStatisticsInfoAMD statistics
= {};
1466 statistics
.shaderStageMask
= shaderStage
;
1467 statistics
.numPhysicalVgprs
= device
->physical_device
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1468 statistics
.numPhysicalSgprs
= device
->physical_device
->rad_info
.num_physical_sgprs_per_simd
;
1469 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
1471 if (stage
== MESA_SHADER_COMPUTE
) {
1472 unsigned *local_size
= variant
->info
.cs
.block_size
;
1473 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
1475 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
1476 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
1478 statistics
.computeWorkGroupSize
[0] = local_size
[0];
1479 statistics
.computeWorkGroupSize
[1] = local_size
[1];
1480 statistics
.computeWorkGroupSize
[2] = local_size
[2];
1482 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
1485 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
1486 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
1487 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
1488 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
1489 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
1491 size_t size
= *pInfoSize
;
1492 *pInfoSize
= sizeof(statistics
);
1494 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
1496 if (size
< *pInfoSize
)
1497 result
= VK_INCOMPLETE
;
1501 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
1502 buf
= _mesa_string_buffer_create(NULL
, 1024);
1504 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1505 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->ir_string
);
1506 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
1507 generate_shader_stats(device
, variant
, stage
, buf
);
1509 /* Need to include the null terminator. */
1510 size_t length
= buf
->length
+ 1;
1513 *pInfoSize
= length
;
1515 size_t size
= *pInfoSize
;
1516 *pInfoSize
= length
;
1518 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
1521 result
= VK_INCOMPLETE
;
1524 _mesa_string_buffer_destroy(buf
);
1527 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1528 result
= VK_ERROR_FEATURE_NOT_PRESENT
;