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nir/lower_input_attachments: Refactor to use an options struct
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 if (shader->options->max_unroll_iterations) {
282 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
283 }
284 } while (progress && !optimize_conservatively);
285
286 NIR_PASS(progress, shader, nir_opt_conditional_discard);
287 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 struct radv_spirv_debug_data {
303 struct radv_device *device;
304 const struct radv_shader_module *module;
305 };
306
307 static void radv_spirv_nir_debug(void *private_data,
308 enum nir_spirv_debug_level level,
309 size_t spirv_offset,
310 const char *message)
311 {
312 struct radv_spirv_debug_data *debug_data = private_data;
313 struct radv_instance *instance = debug_data->device->instance;
314
315 static const VkDebugReportFlagsEXT vk_flags[] = {
316 [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
317 [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
318 [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
319 };
320 char buffer[256];
321
322 snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s",
323 (unsigned long)spirv_offset, message);
324
325 vk_debug_report(&instance->debug_report_callbacks,
326 vk_flags[level],
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
328 (uint64_t)(uintptr_t)debug_data->module,
329 0, 0, "radv", buffer);
330 }
331
332 nir_shader *
333 radv_shader_compile_to_nir(struct radv_device *device,
334 struct radv_shader_module *module,
335 const char *entrypoint_name,
336 gl_shader_stage stage,
337 const VkSpecializationInfo *spec_info,
338 const VkPipelineCreateFlags flags,
339 const struct radv_pipeline_layout *layout,
340 unsigned subgroup_size, unsigned ballot_bit_size)
341 {
342 nir_shader *nir;
343 const nir_shader_compiler_options *nir_options =
344 radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco;
345
346 if (module->nir) {
347 /* Some things such as our meta clear/blit code will give us a NIR
348 * shader directly. In that case, we just ignore the SPIR-V entirely
349 * and just use the NIR shader */
350 nir = module->nir;
351 nir->options = nir_options;
352 nir_validate_shader(nir, "in internal shader");
353
354 assert(exec_list_length(&nir->functions) == 1);
355 } else {
356 uint32_t *spirv = (uint32_t *) module->data;
357 assert(module->size % 4 == 0);
358
359 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
360 radv_print_spirv(module->data, module->size, stderr);
361
362 uint32_t num_spec_entries = 0;
363 struct nir_spirv_specialization *spec_entries = NULL;
364 if (spec_info && spec_info->mapEntryCount > 0) {
365 num_spec_entries = spec_info->mapEntryCount;
366 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
367 for (uint32_t i = 0; i < num_spec_entries; i++) {
368 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
369 const void *data = spec_info->pData + entry.offset;
370 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
371
372 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
373 switch (entry.size) {
374 case 8:
375 spec_entries[i].value.u64 = *(const uint64_t *)data;
376 break;
377 case 4:
378 spec_entries[i].value.u32 = *(const uint32_t *)data;
379 break;
380 case 2:
381 spec_entries[i].value.u16 = *(const uint16_t *)data;
382 break;
383 case 1:
384 spec_entries[i].value.u8 = *(const uint8_t *)data;
385 break;
386 default:
387 assert(!"Invalid spec constant size");
388 break;
389 }
390 }
391 }
392
393 struct radv_spirv_debug_data spirv_debug_data = {
394 .device = device,
395 .module = module,
396 };
397 const struct spirv_to_nir_options spirv_options = {
398 .lower_ubo_ssbo_access_to_offsets = true,
399 .caps = {
400 .amd_fragment_mask = true,
401 .amd_gcn_shader = true,
402 .amd_image_gather_bias_lod = true,
403 .amd_image_read_write_lod = true,
404 .amd_shader_ballot = true,
405 .amd_shader_explicit_vertex_parameter = true,
406 .amd_trinary_minmax = true,
407 .demote_to_helper_invocation = true,
408 .derivative_group = true,
409 .descriptor_array_dynamic_indexing = true,
410 .descriptor_array_non_uniform_indexing = true,
411 .descriptor_indexing = true,
412 .device_group = true,
413 .draw_parameters = true,
414 .float_controls = true,
415 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
416 .float32_atomic_add = true,
417 .float64 = true,
418 .geometry_streams = true,
419 .image_ms_array = true,
420 .image_read_without_format = true,
421 .image_write_without_format = true,
422 .int8 = true,
423 .int16 = true,
424 .int64 = true,
425 .int64_atomics = true,
426 .min_lod = true,
427 .multiview = true,
428 .physical_storage_buffer_address = true,
429 .post_depth_coverage = true,
430 .runtime_descriptor_array = true,
431 .shader_clock = true,
432 .shader_viewport_index_layer = true,
433 .stencil_export = true,
434 .storage_8bit = true,
435 .storage_16bit = true,
436 .storage_image_ms = true,
437 .subgroup_arithmetic = true,
438 .subgroup_ballot = true,
439 .subgroup_basic = true,
440 .subgroup_quad = true,
441 .subgroup_shuffle = true,
442 .subgroup_vote = true,
443 .tessellation = true,
444 .transform_feedback = true,
445 .variable_pointers = true,
446 .vk_memory_model = true,
447 .vk_memory_model_device_scope = true,
448 },
449 .ubo_addr_format = nir_address_format_32bit_index_offset,
450 .ssbo_addr_format = nir_address_format_32bit_index_offset,
451 .phys_ssbo_addr_format = nir_address_format_64bit_global,
452 .push_const_addr_format = nir_address_format_logical,
453 .shared_addr_format = nir_address_format_32bit_offset,
454 .frag_coord_is_sysval = true,
455 .debug = {
456 .func = radv_spirv_nir_debug,
457 .private_data = &spirv_debug_data,
458 },
459 };
460 nir = spirv_to_nir(spirv, module->size / 4,
461 spec_entries, num_spec_entries,
462 stage, entrypoint_name,
463 &spirv_options, nir_options);
464 assert(nir->info.stage == stage);
465 nir_validate_shader(nir, "after spirv_to_nir");
466
467 free(spec_entries);
468
469 /* We have to lower away local constant initializers right before we
470 * inline functions. That way they get properly initialized at the top
471 * of the function and not at the top of its caller.
472 */
473 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
474 NIR_PASS_V(nir, nir_lower_returns);
475 NIR_PASS_V(nir, nir_inline_functions);
476 NIR_PASS_V(nir, nir_copy_prop);
477 NIR_PASS_V(nir, nir_opt_deref);
478
479 /* Pick off the single entrypoint that we want */
480 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
481 if (func->is_entrypoint)
482 func->name = ralloc_strdup(func, "main");
483 else
484 exec_node_remove(&func->node);
485 }
486 assert(exec_list_length(&nir->functions) == 1);
487
488 /* Make sure we lower constant initializers on output variables so that
489 * nir_remove_dead_variables below sees the corresponding stores
490 */
491 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
492
493 /* Now that we've deleted all but the main function, we can go ahead and
494 * lower the rest of the constant initializers.
495 */
496 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
497
498 /* Split member structs. We do this before lower_io_to_temporaries so that
499 * it doesn't lower system values to temporaries by accident.
500 */
501 NIR_PASS_V(nir, nir_split_var_copies);
502 NIR_PASS_V(nir, nir_split_per_member_structs);
503
504 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
505 !radv_use_llvm_for_stage(device, nir->info.stage))
506 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
507 if (nir->info.stage == MESA_SHADER_FRAGMENT)
508 NIR_PASS_V(nir, nir_lower_input_attachments,
509 &(nir_input_attachment_options) {
510 .use_fragcoord_sysval = true,
511 });
512
513 NIR_PASS_V(nir, nir_remove_dead_variables,
514 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
515 NULL);
516
517 NIR_PASS_V(nir, nir_propagate_invariant);
518
519 NIR_PASS_V(nir, nir_lower_system_values);
520 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
521
522 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
523 NIR_PASS_V(nir, nir_lower_discard_to_demote);
524
525 nir_lower_doubles_options lower_doubles =
526 nir->options->lower_doubles_options;
527
528 if (device->physical_device->rad_info.chip_class == GFX6) {
529 /* GFX6 doesn't support v_floor_f64 and the precision
530 * of v_fract_f64 which is used to implement 64-bit
531 * floor is less than what Vulkan requires.
532 */
533 lower_doubles |= nir_lower_dfloor;
534 }
535
536 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
537 }
538
539 /* Vulkan uses the separate-shader linking model */
540 nir->info.separate_shader = true;
541
542 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
543
544 if (nir->info.stage == MESA_SHADER_GEOMETRY)
545 nir_lower_gs_intrinsics(nir, true);
546
547 static const nir_lower_tex_options tex_options = {
548 .lower_txp = ~0,
549 .lower_tg4_offsets = true,
550 };
551
552 nir_lower_tex(nir, &tex_options);
553
554 nir_lower_vars_to_ssa(nir);
555
556 if (nir->info.stage == MESA_SHADER_VERTEX ||
557 nir->info.stage == MESA_SHADER_GEOMETRY ||
558 nir->info.stage == MESA_SHADER_FRAGMENT) {
559 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
560 nir_shader_get_entrypoint(nir), true, true);
561 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
562 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
563 nir_shader_get_entrypoint(nir), true, false);
564 }
565
566 nir_split_var_copies(nir);
567
568 nir_lower_global_vars_to_local(nir);
569 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
570 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
571 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
572 .subgroup_size = subgroup_size,
573 .ballot_bit_size = ballot_bit_size,
574 .lower_to_scalar = 1,
575 .lower_subgroup_masks = 1,
576 .lower_shuffle = 1,
577 .lower_shuffle_to_32bit = 1,
578 .lower_vote_eq_to_ballot = 1,
579 .lower_quad_broadcast_dynamic = 1,
580 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
581 .lower_shuffle_to_swizzle_amd = 1,
582 });
583
584 nir_lower_load_const_to_scalar(nir);
585
586 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
587 radv_optimize_nir(nir, false, true);
588
589 /* call radv_nir_lower_ycbcr_textures() late as there might still be
590 * tex with undef texture/sampler before first optimization */
591 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
592
593 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
594 * to remove any copies introduced by nir_opt_find_array_copies().
595 */
596 nir_lower_var_copies(nir);
597
598 /* Lower deref operations for compute shared memory. */
599 if (nir->info.stage == MESA_SHADER_COMPUTE) {
600 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
601 nir_var_mem_shared, shared_var_info);
602 NIR_PASS_V(nir, nir_lower_explicit_io,
603 nir_var_mem_shared, nir_address_format_32bit_offset);
604 }
605
606 /* Lower large variables that are always constant with load_constant
607 * intrinsics, which get turned into PC-relative loads from a data
608 * section next to the shader.
609 */
610 NIR_PASS_V(nir, nir_opt_large_constants,
611 glsl_get_natural_size_align_bytes, 16);
612
613 /* Indirect lowering must be called after the radv_optimize_nir() loop
614 * has been called at least once. Otherwise indirect lowering can
615 * bloat the instruction count of the loop and cause it to be
616 * considered too large for unrolling.
617 */
618 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
619 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
620
621 return nir;
622 }
623
624 static int
625 type_size_vec4(const struct glsl_type *type, bool bindless)
626 {
627 return glsl_count_attribute_slots(type, false);
628 }
629
630 static nir_variable *
631 find_layer_in_var(nir_shader *nir)
632 {
633 nir_variable *var =
634 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
635 if (var != NULL)
636 return var;
637
638 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
639 var->data.location = VARYING_SLOT_LAYER;
640 var->data.interpolation = INTERP_MODE_FLAT;
641 return var;
642 }
643
644 /* We use layered rendering to implement multiview, which means we need to map
645 * view_index to gl_Layer. The attachment lowering also uses needs to know the
646 * layer so that it can sample from the correct layer. The code generates a
647 * load from the layer_id sysval, but since we don't have a way to get at this
648 * information from the fragment shader, we also need to lower this to the
649 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
650 * slot, before lowering io, so that nir_assign_var_locations() will give the
651 * LAYER varying the correct driver_location.
652 */
653
654 static bool
655 lower_view_index(nir_shader *nir)
656 {
657 bool progress = false;
658 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
659 nir_builder b;
660 nir_builder_init(&b, entry);
661
662 nir_variable *layer = NULL;
663 nir_foreach_block(block, entry) {
664 nir_foreach_instr_safe(instr, block) {
665 if (instr->type != nir_instr_type_intrinsic)
666 continue;
667
668 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
669 if (load->intrinsic != nir_intrinsic_load_view_index &&
670 load->intrinsic != nir_intrinsic_load_layer_id)
671 continue;
672
673 if (!layer)
674 layer = find_layer_in_var(nir);
675
676 b.cursor = nir_before_instr(instr);
677 nir_ssa_def *def = nir_load_var(&b, layer);
678 nir_ssa_def_rewrite_uses(&load->dest.ssa,
679 nir_src_for_ssa(def));
680
681 nir_instr_remove(instr);
682 progress = true;
683 }
684 }
685
686 return progress;
687 }
688
689 void
690 radv_lower_fs_io(nir_shader *nir)
691 {
692 NIR_PASS_V(nir, lower_view_index);
693 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
694 MESA_SHADER_FRAGMENT);
695
696 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
697
698 /* This pass needs actual constants */
699 nir_opt_constant_folding(nir);
700
701 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
702 }
703
704
705 static void *
706 radv_alloc_shader_memory(struct radv_device *device,
707 struct radv_shader_variant *shader)
708 {
709 mtx_lock(&device->shader_slab_mutex);
710 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
711 uint64_t offset = 0;
712 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
713 if (s->bo_offset - offset >= shader->code_size) {
714 shader->bo = slab->bo;
715 shader->bo_offset = offset;
716 list_addtail(&shader->slab_list, &s->slab_list);
717 mtx_unlock(&device->shader_slab_mutex);
718 return slab->ptr + offset;
719 }
720 offset = align_u64(s->bo_offset + s->code_size, 256);
721 }
722 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
723 shader->bo = slab->bo;
724 shader->bo_offset = offset;
725 list_addtail(&shader->slab_list, &slab->shaders);
726 mtx_unlock(&device->shader_slab_mutex);
727 return slab->ptr + offset;
728 }
729 }
730
731 mtx_unlock(&device->shader_slab_mutex);
732 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
733
734 slab->size = MAX2(256 * 1024, shader->code_size);
735 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
736 RADEON_DOMAIN_VRAM,
737 RADEON_FLAG_NO_INTERPROCESS_SHARING |
738 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
739 0 : RADEON_FLAG_READ_ONLY),
740 RADV_BO_PRIORITY_SHADER);
741 if (!slab->bo) {
742 free(slab);
743 return NULL;
744 }
745
746 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
747 if (!slab->ptr) {
748 device->ws->buffer_destroy(slab->bo);
749 free(slab);
750 return NULL;
751 }
752
753 list_inithead(&slab->shaders);
754
755 mtx_lock(&device->shader_slab_mutex);
756 list_add(&slab->slabs, &device->shader_slabs);
757
758 shader->bo = slab->bo;
759 shader->bo_offset = 0;
760 list_add(&shader->slab_list, &slab->shaders);
761 mtx_unlock(&device->shader_slab_mutex);
762 return slab->ptr;
763 }
764
765 void
766 radv_destroy_shader_slabs(struct radv_device *device)
767 {
768 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
769 device->ws->buffer_destroy(slab->bo);
770 free(slab);
771 }
772 mtx_destroy(&device->shader_slab_mutex);
773 }
774
775 /* For the UMR disassembler. */
776 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
777 #define DEBUGGER_NUM_MARKERS 5
778
779 static unsigned
780 radv_get_shader_binary_size(size_t code_size)
781 {
782 return code_size + DEBUGGER_NUM_MARKERS * 4;
783 }
784
785 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
786 const struct ac_shader_config *config_in,
787 const struct radv_shader_info *info,
788 gl_shader_stage stage,
789 struct ac_shader_config *config_out)
790 {
791 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
792 unsigned vgpr_comp_cnt = 0;
793 unsigned num_input_vgprs = info->num_input_vgprs;
794
795 if (stage == MESA_SHADER_FRAGMENT) {
796 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
797 }
798
799 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
800 /* +3 for scratch wave offset and VCC */
801 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
802 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
803 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
804 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
805 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
806 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
807
808 *config_out = *config_in;
809 config_out->num_vgprs = num_vgprs;
810 config_out->num_sgprs = num_sgprs;
811 config_out->num_shared_vgprs = num_shared_vgprs;
812
813 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
814 S_00B12C_SCRATCH_EN(scratch_enabled);
815
816 if (!pdevice->use_ngg_streamout) {
817 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
818 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
819 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
820 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
821 S_00B12C_SO_EN(!!info->so.num_outputs);
822 }
823
824 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
825 (info->wave_size == 32 ? 8 : 4)) |
826 S_00B848_DX10_CLAMP(1) |
827 S_00B848_FLOAT_MODE(config_out->float_mode);
828
829 if (pdevice->rad_info.chip_class >= GFX10) {
830 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
831 } else {
832 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
833 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
834 }
835
836 switch (stage) {
837 case MESA_SHADER_TESS_EVAL:
838 if (info->is_ngg) {
839 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
840 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
841 } else if (info->tes.as_es) {
842 assert(pdevice->rad_info.chip_class <= GFX8);
843 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
844
845 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
846 } else {
847 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
848 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
849
850 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
851 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
852 }
853 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
854 break;
855 case MESA_SHADER_TESS_CTRL:
856 if (pdevice->rad_info.chip_class >= GFX9) {
857 /* We need at least 2 components for LS.
858 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
859 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
860 */
861 if (pdevice->rad_info.chip_class >= GFX10) {
862 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
863 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
864 } else {
865 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
866 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
867 }
868 } else {
869 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
870 }
871 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
872 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
873 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
874 break;
875 case MESA_SHADER_VERTEX:
876 if (info->is_ngg) {
877 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
878 } else if (info->vs.as_ls) {
879 assert(pdevice->rad_info.chip_class <= GFX8);
880 /* We need at least 2 components for LS.
881 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
882 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
883 */
884 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
885 } else if (info->vs.as_es) {
886 assert(pdevice->rad_info.chip_class <= GFX8);
887 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
888 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
889 } else {
890 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
891 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
892 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
893 */
894 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
895 vgpr_comp_cnt = 3;
896 } else if (info->vs.export_prim_id) {
897 vgpr_comp_cnt = 2;
898 } else if (info->vs.needs_instance_id) {
899 vgpr_comp_cnt = 1;
900 } else {
901 vgpr_comp_cnt = 0;
902 }
903
904 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
905 }
906 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
907 break;
908 case MESA_SHADER_FRAGMENT:
909 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
910 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
911 break;
912 case MESA_SHADER_GEOMETRY:
913 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
914 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
915 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
916 break;
917 case MESA_SHADER_COMPUTE:
918 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
919 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
920 config_out->rsrc2 |=
921 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
922 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
923 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
924 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
925 info->cs.uses_thread_id[1] ? 1 : 0) |
926 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
927 S_00B84C_LDS_SIZE(config_in->lds_size);
928 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
929
930 break;
931 default:
932 unreachable("unsupported shader type");
933 break;
934 }
935
936 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
937 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
938 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
939 gl_shader_stage es_stage = stage;
940 if (stage == MESA_SHADER_GEOMETRY)
941 es_stage = info->gs.es_type;
942
943 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
944 if (es_stage == MESA_SHADER_VERTEX) {
945 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
946 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
947 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
948 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
949 } else
950 unreachable("Unexpected ES shader stage");
951
952 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
953 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
954 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
955 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
956 } else if (info->uses_prim_id) {
957 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
958 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
959 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
960 } else {
961 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
962 }
963
964 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
965 S_00B228_WGP_MODE(1);
966 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
967 S_00B22C_LDS_SIZE(config_in->lds_size) |
968 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
969 } else if (pdevice->rad_info.chip_class >= GFX9 &&
970 stage == MESA_SHADER_GEOMETRY) {
971 unsigned es_type = info->gs.es_type;
972 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
973
974 if (es_type == MESA_SHADER_VERTEX) {
975 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
976 if (info->vs.needs_instance_id) {
977 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
978 } else {
979 es_vgpr_comp_cnt = 0;
980 }
981 } else if (es_type == MESA_SHADER_TESS_EVAL) {
982 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
983 } else {
984 unreachable("invalid shader ES type");
985 }
986
987 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
988 * VGPR[0:4] are always loaded.
989 */
990 if (info->uses_invocation_id) {
991 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
992 } else if (info->uses_prim_id) {
993 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
994 } else if (info->gs.vertices_in >= 3) {
995 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
996 } else {
997 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
998 }
999
1000 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
1001 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1002 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
1003 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1004 stage == MESA_SHADER_TESS_CTRL) {
1005 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
1006 } else {
1007 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
1008 }
1009 }
1010
1011 struct radv_shader_variant *
1012 radv_shader_variant_create(struct radv_device *device,
1013 const struct radv_shader_binary *binary,
1014 bool keep_shader_info)
1015 {
1016 struct ac_shader_config config = {0};
1017 struct ac_rtld_binary rtld_binary = {0};
1018 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
1019 if (!variant)
1020 return NULL;
1021
1022 variant->ref_count = 1;
1023
1024 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1025 struct ac_rtld_symbol lds_symbols[2];
1026 unsigned num_lds_symbols = 0;
1027 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
1028 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
1029
1030 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1031 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
1032 !binary->is_gs_copy_shader) {
1033 /* We add this symbol even on LLVM <= 8 to ensure that
1034 * shader->config.lds_size is set correctly below.
1035 */
1036 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1037 sym->name = "esgs_ring";
1038 sym->size = binary->info.ngg_info.esgs_ring_size;
1039 sym->align = 64 * 1024;
1040 }
1041
1042 if (binary->info.is_ngg &&
1043 binary->stage == MESA_SHADER_GEOMETRY) {
1044 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1045 sym->name = "ngg_emit";
1046 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1047 sym->align = 4;
1048 }
1049
1050 struct ac_rtld_open_info open_info = {
1051 .info = &device->physical_device->rad_info,
1052 .shader_type = binary->stage,
1053 .wave_size = binary->info.wave_size,
1054 .num_parts = 1,
1055 .elf_ptrs = &elf_data,
1056 .elf_sizes = &elf_size,
1057 .num_shared_lds_symbols = num_lds_symbols,
1058 .shared_lds_symbols = lds_symbols,
1059 };
1060
1061 if (!ac_rtld_open(&rtld_binary, open_info)) {
1062 free(variant);
1063 return NULL;
1064 }
1065
1066 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1067 &rtld_binary, &config)) {
1068 ac_rtld_close(&rtld_binary);
1069 free(variant);
1070 return NULL;
1071 }
1072
1073 if (rtld_binary.lds_size > 0) {
1074 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1075 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1076 }
1077
1078 variant->code_size = rtld_binary.rx_size;
1079 variant->exec_size = rtld_binary.exec_size;
1080 } else {
1081 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1082 config = ((struct radv_shader_binary_legacy *)binary)->config;
1083 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1084 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1085 }
1086
1087 variant->info = binary->info;
1088 radv_postprocess_config(device->physical_device, &config, &binary->info,
1089 binary->stage, &variant->config);
1090
1091 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1092 if (!dest_ptr) {
1093 if (binary->type == RADV_BINARY_TYPE_RTLD)
1094 ac_rtld_close(&rtld_binary);
1095 free(variant);
1096 return NULL;
1097 }
1098
1099 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1100 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1101 struct ac_rtld_upload_info info = {
1102 .binary = &rtld_binary,
1103 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1104 .rx_ptr = dest_ptr,
1105 };
1106
1107 if (!ac_rtld_upload(&info)) {
1108 radv_shader_variant_destroy(device, variant);
1109 ac_rtld_close(&rtld_binary);
1110 return NULL;
1111 }
1112
1113 if (keep_shader_info ||
1114 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1115 const char *disasm_data;
1116 size_t disasm_size;
1117 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1118 radv_shader_variant_destroy(device, variant);
1119 ac_rtld_close(&rtld_binary);
1120 return NULL;
1121 }
1122
1123 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1124 variant->disasm_string = malloc(disasm_size + 1);
1125 memcpy(variant->disasm_string, disasm_data, disasm_size);
1126 variant->disasm_string[disasm_size] = 0;
1127 }
1128
1129 ac_rtld_close(&rtld_binary);
1130 } else {
1131 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1132 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1133
1134 /* Add end-of-code markers for the UMR disassembler. */
1135 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1136 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1137 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1138
1139 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1140 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1141
1142 if (bin->stats_size) {
1143 variant->statistics = calloc(bin->stats_size, 1);
1144 memcpy(variant->statistics, bin->data, bin->stats_size);
1145 }
1146 }
1147 return variant;
1148 }
1149
1150 static char *
1151 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1152 int shader_count)
1153 {
1154 char *data = NULL;
1155 char *ret = NULL;
1156 size_t size = 0;
1157 FILE *f = open_memstream(&data, &size);
1158 if (f) {
1159 for (int i = 0; i < shader_count; ++i)
1160 nir_print_shader(shaders[i], f);
1161 fclose(f);
1162 }
1163
1164 ret = malloc(size + 1);
1165 if (ret) {
1166 memcpy(ret, data, size);
1167 ret[size] = 0;
1168 }
1169 free(data);
1170 return ret;
1171 }
1172
1173 static struct radv_shader_variant *
1174 shader_variant_compile(struct radv_device *device,
1175 struct radv_shader_module *module,
1176 struct nir_shader * const *shaders,
1177 int shader_count,
1178 gl_shader_stage stage,
1179 struct radv_shader_info *info,
1180 struct radv_nir_compiler_options *options,
1181 bool gs_copy_shader,
1182 bool keep_shader_info,
1183 bool keep_statistic_info,
1184 struct radv_shader_binary **binary_out)
1185 {
1186 enum radeon_family chip_family = device->physical_device->rad_info.family;
1187 struct radv_shader_binary *binary = NULL;
1188
1189 options->family = chip_family;
1190 options->chip_class = device->physical_device->rad_info.chip_class;
1191 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1192 options->dump_preoptir = options->dump_shader &&
1193 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1194 options->record_ir = keep_shader_info;
1195 options->record_stats = keep_statistic_info;
1196 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1197 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1198 options->address32_hi = device->physical_device->rad_info.address32_hi;
1199 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1200 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1201 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1202
1203 struct radv_shader_args args = {};
1204 args.options = options;
1205 args.shader_info = info;
1206 args.is_gs_copy_shader = gs_copy_shader;
1207 radv_declare_shader_args(&args,
1208 gs_copy_shader ? MESA_SHADER_VERTEX
1209 : shaders[shader_count - 1]->info.stage,
1210 shader_count >= 2,
1211 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1212 : MESA_SHADER_VERTEX);
1213
1214 if (radv_use_llvm_for_stage(device, stage) ||
1215 options->dump_shader || options->record_ir)
1216 ac_init_llvm_once();
1217
1218 if (radv_use_llvm_for_stage(device, stage)) {
1219 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1220 } else {
1221 aco_compile_shader(shader_count, shaders, &binary, &args);
1222 }
1223
1224 binary->info = *info;
1225
1226 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1227 keep_shader_info);
1228 if (!variant) {
1229 free(binary);
1230 return NULL;
1231 }
1232
1233 if (options->dump_shader) {
1234 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1235 for (int i = 1; i < shader_count; ++i)
1236 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1237
1238 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1239 }
1240
1241
1242 if (keep_shader_info) {
1243 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1244 if (!gs_copy_shader && !module->nir) {
1245 variant->spirv = malloc(module->size);
1246 if (!variant->spirv) {
1247 free(variant);
1248 free(binary);
1249 return NULL;
1250 }
1251
1252 memcpy(variant->spirv, module->data, module->size);
1253 variant->spirv_size = module->size;
1254 }
1255 }
1256
1257 if (binary_out)
1258 *binary_out = binary;
1259 else
1260 free(binary);
1261
1262 return variant;
1263 }
1264
1265 struct radv_shader_variant *
1266 radv_shader_variant_compile(struct radv_device *device,
1267 struct radv_shader_module *module,
1268 struct nir_shader *const *shaders,
1269 int shader_count,
1270 struct radv_pipeline_layout *layout,
1271 const struct radv_shader_variant_key *key,
1272 struct radv_shader_info *info,
1273 bool keep_shader_info, bool keep_statistic_info,
1274 struct radv_shader_binary **binary_out)
1275 {
1276 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
1277 struct radv_nir_compiler_options options = {0};
1278
1279 options.layout = layout;
1280 if (key)
1281 options.key = *key;
1282
1283 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1284 options.robust_buffer_access = device->robust_buffer_access;
1285
1286 return shader_variant_compile(device, module, shaders, shader_count, stage, info,
1287 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1288 }
1289
1290 struct radv_shader_variant *
1291 radv_create_gs_copy_shader(struct radv_device *device,
1292 struct nir_shader *shader,
1293 struct radv_shader_info *info,
1294 struct radv_shader_binary **binary_out,
1295 bool keep_shader_info, bool keep_statistic_info,
1296 bool multiview)
1297 {
1298 struct radv_nir_compiler_options options = {0};
1299 gl_shader_stage stage = MESA_SHADER_VERTEX;
1300
1301 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1302 options.key.has_multiview_view_index = multiview;
1303
1304 return shader_variant_compile(device, NULL, &shader, 1, stage,
1305 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1306 }
1307
1308 void
1309 radv_shader_variant_destroy(struct radv_device *device,
1310 struct radv_shader_variant *variant)
1311 {
1312 if (!p_atomic_dec_zero(&variant->ref_count))
1313 return;
1314
1315 mtx_lock(&device->shader_slab_mutex);
1316 list_del(&variant->slab_list);
1317 mtx_unlock(&device->shader_slab_mutex);
1318
1319 free(variant->spirv);
1320 free(variant->nir_string);
1321 free(variant->disasm_string);
1322 free(variant->ir_string);
1323 free(variant->statistics);
1324 free(variant);
1325 }
1326
1327 const char *
1328 radv_get_shader_name(struct radv_shader_info *info,
1329 gl_shader_stage stage)
1330 {
1331 switch (stage) {
1332 case MESA_SHADER_VERTEX:
1333 if (info->vs.as_ls)
1334 return "Vertex Shader as LS";
1335 else if (info->vs.as_es)
1336 return "Vertex Shader as ES";
1337 else if (info->is_ngg)
1338 return "Vertex Shader as ESGS";
1339 else
1340 return "Vertex Shader as VS";
1341 case MESA_SHADER_TESS_CTRL:
1342 return "Tessellation Control Shader";
1343 case MESA_SHADER_TESS_EVAL:
1344 if (info->tes.as_es)
1345 return "Tessellation Evaluation Shader as ES";
1346 else if (info->is_ngg)
1347 return "Tessellation Evaluation Shader as ESGS";
1348 else
1349 return "Tessellation Evaluation Shader as VS";
1350 case MESA_SHADER_GEOMETRY:
1351 return "Geometry Shader";
1352 case MESA_SHADER_FRAGMENT:
1353 return "Pixel Shader";
1354 case MESA_SHADER_COMPUTE:
1355 return "Compute Shader";
1356 default:
1357 return "Unknown shader";
1358 };
1359 }
1360
1361 unsigned
1362 radv_get_max_workgroup_size(enum chip_class chip_class,
1363 gl_shader_stage stage,
1364 const unsigned *sizes)
1365 {
1366 switch (stage) {
1367 case MESA_SHADER_TESS_CTRL:
1368 return chip_class >= GFX7 ? 128 : 64;
1369 case MESA_SHADER_GEOMETRY:
1370 return chip_class >= GFX9 ? 128 : 64;
1371 case MESA_SHADER_COMPUTE:
1372 break;
1373 default:
1374 return 0;
1375 }
1376
1377 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1378 return max_workgroup_size;
1379 }
1380
1381 unsigned
1382 radv_get_max_waves(struct radv_device *device,
1383 struct radv_shader_variant *variant,
1384 gl_shader_stage stage)
1385 {
1386 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1387 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1388 uint8_t wave_size = variant->info.wave_size;
1389 struct ac_shader_config *conf = &variant->config;
1390 unsigned max_simd_waves;
1391 unsigned lds_per_wave = 0;
1392
1393 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1394
1395 if (stage == MESA_SHADER_FRAGMENT) {
1396 lds_per_wave = conf->lds_size * lds_increment +
1397 align(variant->info.ps.num_interp * 48,
1398 lds_increment);
1399 } else if (stage == MESA_SHADER_COMPUTE) {
1400 unsigned max_workgroup_size =
1401 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1402 lds_per_wave = (conf->lds_size * lds_increment) /
1403 DIV_ROUND_UP(max_workgroup_size, wave_size);
1404 }
1405
1406 if (conf->num_sgprs) {
1407 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1408 max_simd_waves =
1409 MIN2(max_simd_waves,
1410 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1411 sgprs);
1412 }
1413
1414 if (conf->num_vgprs) {
1415 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1416 max_simd_waves =
1417 MIN2(max_simd_waves,
1418 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1419 }
1420
1421 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1422 if (lds_per_wave)
1423 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1424
1425 return max_simd_waves;
1426 }
1427
1428 static void
1429 generate_shader_stats(struct radv_device *device,
1430 struct radv_shader_variant *variant,
1431 gl_shader_stage stage,
1432 struct _mesa_string_buffer *buf)
1433 {
1434 struct ac_shader_config *conf = &variant->config;
1435 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1436
1437 if (stage == MESA_SHADER_FRAGMENT) {
1438 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1439 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1440 "SPI_PS_INPUT_ENA = 0x%04x\n",
1441 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1442 }
1443
1444 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1445 "SGPRS: %d\n"
1446 "VGPRS: %d\n"
1447 "Spilled SGPRs: %d\n"
1448 "Spilled VGPRs: %d\n"
1449 "PrivMem VGPRS: %d\n"
1450 "Code Size: %d bytes\n"
1451 "LDS: %d blocks\n"
1452 "Scratch: %d bytes per wave\n"
1453 "Max Waves: %d\n",
1454 conf->num_sgprs, conf->num_vgprs,
1455 conf->spilled_sgprs, conf->spilled_vgprs,
1456 variant->info.private_mem_vgprs, variant->exec_size,
1457 conf->lds_size, conf->scratch_bytes_per_wave,
1458 max_simd_waves);
1459
1460 if (variant->statistics) {
1461 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1462 for (unsigned i = 0; i < variant->statistics->count; i++) {
1463 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1464 uint32_t value = variant->statistics->values[i];
1465 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1466 }
1467 }
1468
1469 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1470 }
1471
1472 void
1473 radv_shader_dump_stats(struct radv_device *device,
1474 struct radv_shader_variant *variant,
1475 gl_shader_stage stage,
1476 FILE *file)
1477 {
1478 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1479
1480 generate_shader_stats(device, variant, stage, buf);
1481
1482 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1483 fprintf(file, "%s", buf->buf);
1484
1485 _mesa_string_buffer_destroy(buf);
1486 }
1487
1488 VkResult
1489 radv_GetShaderInfoAMD(VkDevice _device,
1490 VkPipeline _pipeline,
1491 VkShaderStageFlagBits shaderStage,
1492 VkShaderInfoTypeAMD infoType,
1493 size_t* pInfoSize,
1494 void* pInfo)
1495 {
1496 RADV_FROM_HANDLE(radv_device, device, _device);
1497 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1498 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1499 struct radv_shader_variant *variant = pipeline->shaders[stage];
1500 struct _mesa_string_buffer *buf;
1501 VkResult result = VK_SUCCESS;
1502
1503 /* Spec doesn't indicate what to do if the stage is invalid, so just
1504 * return no info for this. */
1505 if (!variant)
1506 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1507
1508 switch (infoType) {
1509 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1510 if (!pInfo) {
1511 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1512 } else {
1513 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1514 struct ac_shader_config *conf = &variant->config;
1515
1516 VkShaderStatisticsInfoAMD statistics = {};
1517 statistics.shaderStageMask = shaderStage;
1518 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1519 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1520 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1521
1522 if (stage == MESA_SHADER_COMPUTE) {
1523 unsigned *local_size = variant->info.cs.block_size;
1524 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1525
1526 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1527 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1528
1529 statistics.computeWorkGroupSize[0] = local_size[0];
1530 statistics.computeWorkGroupSize[1] = local_size[1];
1531 statistics.computeWorkGroupSize[2] = local_size[2];
1532 } else {
1533 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1534 }
1535
1536 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1537 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1538 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1539 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1540 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1541
1542 size_t size = *pInfoSize;
1543 *pInfoSize = sizeof(statistics);
1544
1545 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1546
1547 if (size < *pInfoSize)
1548 result = VK_INCOMPLETE;
1549 }
1550
1551 break;
1552 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1553 buf = _mesa_string_buffer_create(NULL, 1024);
1554
1555 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1556 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1557 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1558 generate_shader_stats(device, variant, stage, buf);
1559
1560 /* Need to include the null terminator. */
1561 size_t length = buf->length + 1;
1562
1563 if (!pInfo) {
1564 *pInfoSize = length;
1565 } else {
1566 size_t size = *pInfoSize;
1567 *pInfoSize = length;
1568
1569 memcpy(pInfo, buf->buf, MIN2(size, length));
1570
1571 if (size < length)
1572 result = VK_INCOMPLETE;
1573 }
1574
1575 _mesa_string_buffer_destroy(buf);
1576 break;
1577 default:
1578 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1579 result = VK_ERROR_FEATURE_NOT_PRESENT;
1580 break;
1581 }
1582
1583 return result;
1584 }