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radv/aco: enable VK_KHR_memory_model
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 if (shader->options->max_unroll_iterations) {
282 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
283 }
284 } while (progress && !optimize_conservatively);
285
286 NIR_PASS(progress, shader, nir_opt_conditional_discard);
287 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 nir_shader *
303 radv_shader_compile_to_nir(struct radv_device *device,
304 struct radv_shader_module *module,
305 const char *entrypoint_name,
306 gl_shader_stage stage,
307 const VkSpecializationInfo *spec_info,
308 const VkPipelineCreateFlags flags,
309 const struct radv_pipeline_layout *layout,
310 unsigned subgroup_size, unsigned ballot_bit_size)
311 {
312 nir_shader *nir;
313 const nir_shader_compiler_options *nir_options =
314 device->physical_device->use_llvm ? &nir_options_llvm :
315 &nir_options_aco;
316
317 if (module->nir) {
318 /* Some things such as our meta clear/blit code will give us a NIR
319 * shader directly. In that case, we just ignore the SPIR-V entirely
320 * and just use the NIR shader */
321 nir = module->nir;
322 nir->options = nir_options;
323 nir_validate_shader(nir, "in internal shader");
324
325 assert(exec_list_length(&nir->functions) == 1);
326 } else {
327 uint32_t *spirv = (uint32_t *) module->data;
328 assert(module->size % 4 == 0);
329
330 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
331 radv_print_spirv(module->data, module->size, stderr);
332
333 uint32_t num_spec_entries = 0;
334 struct nir_spirv_specialization *spec_entries = NULL;
335 if (spec_info && spec_info->mapEntryCount > 0) {
336 num_spec_entries = spec_info->mapEntryCount;
337 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
338 for (uint32_t i = 0; i < num_spec_entries; i++) {
339 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
340 const void *data = spec_info->pData + entry.offset;
341 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
342
343 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
344 switch (entry.size) {
345 case 8:
346 spec_entries[i].value.u64 = *(const uint64_t *)data;
347 break;
348 case 4:
349 spec_entries[i].value.u32 = *(const uint32_t *)data;
350 break;
351 case 2:
352 spec_entries[i].value.u16 = *(const uint16_t *)data;
353 break;
354 case 1:
355 spec_entries[i].value.u8 = *(const uint8_t *)data;
356 break;
357 default:
358 assert(!"Invalid spec constant size");
359 break;
360 }
361 }
362 }
363 const struct spirv_to_nir_options spirv_options = {
364 .lower_ubo_ssbo_access_to_offsets = true,
365 .caps = {
366 .amd_fragment_mask = true,
367 .amd_gcn_shader = true,
368 .amd_image_gather_bias_lod = true,
369 .amd_image_read_write_lod = true,
370 .amd_shader_ballot = true,
371 .amd_shader_explicit_vertex_parameter = true,
372 .amd_trinary_minmax = true,
373 .demote_to_helper_invocation = true,
374 .derivative_group = true,
375 .descriptor_array_dynamic_indexing = true,
376 .descriptor_array_non_uniform_indexing = true,
377 .descriptor_indexing = true,
378 .device_group = true,
379 .draw_parameters = true,
380 .float_controls = true,
381 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
382 .float32_atomic_add = true,
383 .float64 = true,
384 .geometry_streams = true,
385 .image_ms_array = true,
386 .image_read_without_format = true,
387 .image_write_without_format = true,
388 .int8 = true,
389 .int16 = true,
390 .int64 = true,
391 .int64_atomics = true,
392 .min_lod = true,
393 .multiview = true,
394 .physical_storage_buffer_address = true,
395 .post_depth_coverage = true,
396 .runtime_descriptor_array = true,
397 .shader_clock = true,
398 .shader_viewport_index_layer = true,
399 .stencil_export = true,
400 .storage_8bit = true,
401 .storage_16bit = true,
402 .storage_image_ms = true,
403 .subgroup_arithmetic = true,
404 .subgroup_ballot = true,
405 .subgroup_basic = true,
406 .subgroup_quad = true,
407 .subgroup_shuffle = true,
408 .subgroup_vote = true,
409 .tessellation = true,
410 .transform_feedback = true,
411 .variable_pointers = true,
412 .vk_memory_model = !device->physical_device->use_llvm,
413 .vk_memory_model_device_scope = !device->physical_device->use_llvm,
414 },
415 .ubo_addr_format = nir_address_format_32bit_index_offset,
416 .ssbo_addr_format = nir_address_format_32bit_index_offset,
417 .phys_ssbo_addr_format = nir_address_format_64bit_global,
418 .push_const_addr_format = nir_address_format_logical,
419 .shared_addr_format = nir_address_format_32bit_offset,
420 .frag_coord_is_sysval = true,
421 };
422 nir = spirv_to_nir(spirv, module->size / 4,
423 spec_entries, num_spec_entries,
424 stage, entrypoint_name,
425 &spirv_options, nir_options);
426 assert(nir->info.stage == stage);
427 nir_validate_shader(nir, "after spirv_to_nir");
428
429 free(spec_entries);
430
431 /* We have to lower away local constant initializers right before we
432 * inline functions. That way they get properly initialized at the top
433 * of the function and not at the top of its caller.
434 */
435 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
436 NIR_PASS_V(nir, nir_lower_returns);
437 NIR_PASS_V(nir, nir_inline_functions);
438 NIR_PASS_V(nir, nir_copy_prop);
439 NIR_PASS_V(nir, nir_opt_deref);
440
441 /* Pick off the single entrypoint that we want */
442 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
443 if (func->is_entrypoint)
444 func->name = ralloc_strdup(func, "main");
445 else
446 exec_node_remove(&func->node);
447 }
448 assert(exec_list_length(&nir->functions) == 1);
449
450 /* Make sure we lower constant initializers on output variables so that
451 * nir_remove_dead_variables below sees the corresponding stores
452 */
453 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
454
455 /* Now that we've deleted all but the main function, we can go ahead and
456 * lower the rest of the constant initializers.
457 */
458 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
459
460 /* Split member structs. We do this before lower_io_to_temporaries so that
461 * it doesn't lower system values to temporaries by accident.
462 */
463 NIR_PASS_V(nir, nir_split_var_copies);
464 NIR_PASS_V(nir, nir_split_per_member_structs);
465
466 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
467 !device->physical_device->use_llvm)
468 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
469 if (nir->info.stage == MESA_SHADER_FRAGMENT)
470 NIR_PASS_V(nir, nir_lower_input_attachments, true);
471
472 NIR_PASS_V(nir, nir_remove_dead_variables,
473 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
474 NULL);
475
476 NIR_PASS_V(nir, nir_propagate_invariant);
477
478 NIR_PASS_V(nir, nir_lower_system_values);
479 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
480
481 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
482 NIR_PASS_V(nir, nir_lower_discard_to_demote);
483
484 nir_lower_doubles_options lower_doubles =
485 nir->options->lower_doubles_options;
486
487 if (device->physical_device->rad_info.chip_class == GFX6) {
488 /* GFX6 doesn't support v_floor_f64 and the precision
489 * of v_fract_f64 which is used to implement 64-bit
490 * floor is less than what Vulkan requires.
491 */
492 lower_doubles |= nir_lower_dfloor;
493 }
494
495 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
496 }
497
498 /* Vulkan uses the separate-shader linking model */
499 nir->info.separate_shader = true;
500
501 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
502
503 if (nir->info.stage == MESA_SHADER_GEOMETRY)
504 nir_lower_gs_intrinsics(nir, true);
505
506 static const nir_lower_tex_options tex_options = {
507 .lower_txp = ~0,
508 .lower_tg4_offsets = true,
509 };
510
511 nir_lower_tex(nir, &tex_options);
512
513 nir_lower_vars_to_ssa(nir);
514
515 if (nir->info.stage == MESA_SHADER_VERTEX ||
516 nir->info.stage == MESA_SHADER_GEOMETRY ||
517 nir->info.stage == MESA_SHADER_FRAGMENT) {
518 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
519 nir_shader_get_entrypoint(nir), true, true);
520 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
521 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
522 nir_shader_get_entrypoint(nir), true, false);
523 }
524
525 nir_split_var_copies(nir);
526
527 nir_lower_global_vars_to_local(nir);
528 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
529 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
530 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
531 .subgroup_size = subgroup_size,
532 .ballot_bit_size = ballot_bit_size,
533 .lower_to_scalar = 1,
534 .lower_subgroup_masks = 1,
535 .lower_shuffle = 1,
536 .lower_shuffle_to_32bit = 1,
537 .lower_vote_eq_to_ballot = 1,
538 .lower_quad_broadcast_dynamic = 1,
539 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
540 .lower_shuffle_to_swizzle_amd = 1,
541 });
542
543 nir_lower_load_const_to_scalar(nir);
544
545 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
546 radv_optimize_nir(nir, false, true);
547
548 /* call radv_nir_lower_ycbcr_textures() late as there might still be
549 * tex with undef texture/sampler before first optimization */
550 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
551
552 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
553 * to remove any copies introduced by nir_opt_find_array_copies().
554 */
555 nir_lower_var_copies(nir);
556
557 /* Lower deref operations for compute shared memory. */
558 if (nir->info.stage == MESA_SHADER_COMPUTE) {
559 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
560 nir_var_mem_shared, shared_var_info);
561 NIR_PASS_V(nir, nir_lower_explicit_io,
562 nir_var_mem_shared, nir_address_format_32bit_offset);
563 }
564
565 /* Lower large variables that are always constant with load_constant
566 * intrinsics, which get turned into PC-relative loads from a data
567 * section next to the shader.
568 */
569 NIR_PASS_V(nir, nir_opt_large_constants,
570 glsl_get_natural_size_align_bytes, 16);
571
572 /* Indirect lowering must be called after the radv_optimize_nir() loop
573 * has been called at least once. Otherwise indirect lowering can
574 * bloat the instruction count of the loop and cause it to be
575 * considered too large for unrolling.
576 */
577 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
578 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
579
580 return nir;
581 }
582
583 static int
584 type_size_vec4(const struct glsl_type *type, bool bindless)
585 {
586 return glsl_count_attribute_slots(type, false);
587 }
588
589 static nir_variable *
590 find_layer_in_var(nir_shader *nir)
591 {
592 nir_variable *var =
593 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
594 if (var != NULL)
595 return var;
596
597 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
598 var->data.location = VARYING_SLOT_LAYER;
599 var->data.interpolation = INTERP_MODE_FLAT;
600 return var;
601 }
602
603 /* We use layered rendering to implement multiview, which means we need to map
604 * view_index to gl_Layer. The attachment lowering also uses needs to know the
605 * layer so that it can sample from the correct layer. The code generates a
606 * load from the layer_id sysval, but since we don't have a way to get at this
607 * information from the fragment shader, we also need to lower this to the
608 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
609 * slot, before lowering io, so that nir_assign_var_locations() will give the
610 * LAYER varying the correct driver_location.
611 */
612
613 static bool
614 lower_view_index(nir_shader *nir)
615 {
616 bool progress = false;
617 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
618 nir_builder b;
619 nir_builder_init(&b, entry);
620
621 nir_variable *layer = NULL;
622 nir_foreach_block(block, entry) {
623 nir_foreach_instr_safe(instr, block) {
624 if (instr->type != nir_instr_type_intrinsic)
625 continue;
626
627 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
628 if (load->intrinsic != nir_intrinsic_load_view_index &&
629 load->intrinsic != nir_intrinsic_load_layer_id)
630 continue;
631
632 if (!layer)
633 layer = find_layer_in_var(nir);
634
635 b.cursor = nir_before_instr(instr);
636 nir_ssa_def *def = nir_load_var(&b, layer);
637 nir_ssa_def_rewrite_uses(&load->dest.ssa,
638 nir_src_for_ssa(def));
639
640 nir_instr_remove(instr);
641 progress = true;
642 }
643 }
644
645 return progress;
646 }
647
648 void
649 radv_lower_fs_io(nir_shader *nir)
650 {
651 NIR_PASS_V(nir, lower_view_index);
652 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
653 MESA_SHADER_FRAGMENT);
654
655 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
656
657 /* This pass needs actual constants */
658 nir_opt_constant_folding(nir);
659
660 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
661 }
662
663
664 static void *
665 radv_alloc_shader_memory(struct radv_device *device,
666 struct radv_shader_variant *shader)
667 {
668 mtx_lock(&device->shader_slab_mutex);
669 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
670 uint64_t offset = 0;
671 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
672 if (s->bo_offset - offset >= shader->code_size) {
673 shader->bo = slab->bo;
674 shader->bo_offset = offset;
675 list_addtail(&shader->slab_list, &s->slab_list);
676 mtx_unlock(&device->shader_slab_mutex);
677 return slab->ptr + offset;
678 }
679 offset = align_u64(s->bo_offset + s->code_size, 256);
680 }
681 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
682 shader->bo = slab->bo;
683 shader->bo_offset = offset;
684 list_addtail(&shader->slab_list, &slab->shaders);
685 mtx_unlock(&device->shader_slab_mutex);
686 return slab->ptr + offset;
687 }
688 }
689
690 mtx_unlock(&device->shader_slab_mutex);
691 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
692
693 slab->size = MAX2(256 * 1024, shader->code_size);
694 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
695 RADEON_DOMAIN_VRAM,
696 RADEON_FLAG_NO_INTERPROCESS_SHARING |
697 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
698 0 : RADEON_FLAG_READ_ONLY),
699 RADV_BO_PRIORITY_SHADER);
700 if (!slab->bo) {
701 free(slab);
702 return NULL;
703 }
704
705 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
706 if (!slab->ptr) {
707 device->ws->buffer_destroy(slab->bo);
708 free(slab);
709 return NULL;
710 }
711
712 list_inithead(&slab->shaders);
713
714 mtx_lock(&device->shader_slab_mutex);
715 list_add(&slab->slabs, &device->shader_slabs);
716
717 shader->bo = slab->bo;
718 shader->bo_offset = 0;
719 list_add(&shader->slab_list, &slab->shaders);
720 mtx_unlock(&device->shader_slab_mutex);
721 return slab->ptr;
722 }
723
724 void
725 radv_destroy_shader_slabs(struct radv_device *device)
726 {
727 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
728 device->ws->buffer_destroy(slab->bo);
729 free(slab);
730 }
731 mtx_destroy(&device->shader_slab_mutex);
732 }
733
734 /* For the UMR disassembler. */
735 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
736 #define DEBUGGER_NUM_MARKERS 5
737
738 static unsigned
739 radv_get_shader_binary_size(size_t code_size)
740 {
741 return code_size + DEBUGGER_NUM_MARKERS * 4;
742 }
743
744 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
745 const struct ac_shader_config *config_in,
746 const struct radv_shader_info *info,
747 gl_shader_stage stage,
748 struct ac_shader_config *config_out)
749 {
750 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
751 unsigned vgpr_comp_cnt = 0;
752 unsigned num_input_vgprs = info->num_input_vgprs;
753
754 if (stage == MESA_SHADER_FRAGMENT) {
755 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
756 }
757
758 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
759 /* +3 for scratch wave offset and VCC */
760 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
761 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
762 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
763 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
764 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
765 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
766
767 *config_out = *config_in;
768 config_out->num_vgprs = num_vgprs;
769 config_out->num_sgprs = num_sgprs;
770 config_out->num_shared_vgprs = num_shared_vgprs;
771
772 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
773 S_00B12C_SCRATCH_EN(scratch_enabled);
774
775 if (!pdevice->use_ngg_streamout) {
776 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
777 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
778 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
779 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
780 S_00B12C_SO_EN(!!info->so.num_outputs);
781 }
782
783 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
784 (info->wave_size == 32 ? 8 : 4)) |
785 S_00B848_DX10_CLAMP(1) |
786 S_00B848_FLOAT_MODE(config_out->float_mode);
787
788 if (pdevice->rad_info.chip_class >= GFX10) {
789 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
790 } else {
791 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
792 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
793 }
794
795 switch (stage) {
796 case MESA_SHADER_TESS_EVAL:
797 if (info->is_ngg) {
798 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
799 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
800 } else if (info->tes.as_es) {
801 assert(pdevice->rad_info.chip_class <= GFX8);
802 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
803
804 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
805 } else {
806 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
807 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
808
809 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
810 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
811 }
812 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
813 break;
814 case MESA_SHADER_TESS_CTRL:
815 if (pdevice->rad_info.chip_class >= GFX9) {
816 /* We need at least 2 components for LS.
817 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
818 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
819 */
820 if (pdevice->rad_info.chip_class >= GFX10) {
821 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
822 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
823 } else {
824 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
825 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
826 }
827 } else {
828 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
829 }
830 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
831 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
832 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
833 break;
834 case MESA_SHADER_VERTEX:
835 if (info->is_ngg) {
836 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
837 } else if (info->vs.as_ls) {
838 assert(pdevice->rad_info.chip_class <= GFX8);
839 /* We need at least 2 components for LS.
840 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
841 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
842 */
843 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
844 } else if (info->vs.as_es) {
845 assert(pdevice->rad_info.chip_class <= GFX8);
846 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
847 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
848 } else {
849 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
850 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
851 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
852 */
853 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
854 vgpr_comp_cnt = 3;
855 } else if (info->vs.export_prim_id) {
856 vgpr_comp_cnt = 2;
857 } else if (info->vs.needs_instance_id) {
858 vgpr_comp_cnt = 1;
859 } else {
860 vgpr_comp_cnt = 0;
861 }
862
863 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
864 }
865 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
866 break;
867 case MESA_SHADER_FRAGMENT:
868 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
869 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
870 break;
871 case MESA_SHADER_GEOMETRY:
872 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
873 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
874 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
875 break;
876 case MESA_SHADER_COMPUTE:
877 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
878 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
879 config_out->rsrc2 |=
880 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
881 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
882 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
883 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
884 info->cs.uses_thread_id[1] ? 1 : 0) |
885 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
886 S_00B84C_LDS_SIZE(config_in->lds_size);
887 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
888
889 break;
890 default:
891 unreachable("unsupported shader type");
892 break;
893 }
894
895 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
896 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
897 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
898 gl_shader_stage es_stage = stage;
899 if (stage == MESA_SHADER_GEOMETRY)
900 es_stage = info->gs.es_type;
901
902 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
903 if (es_stage == MESA_SHADER_VERTEX) {
904 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
905 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
906 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
907 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
908 } else
909 unreachable("Unexpected ES shader stage");
910
911 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
912 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
913 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
914 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
915 } else if (info->uses_prim_id) {
916 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
917 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
918 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
919 } else {
920 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
921 }
922
923 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
924 S_00B228_WGP_MODE(1);
925 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
926 S_00B22C_LDS_SIZE(config_in->lds_size) |
927 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
928 } else if (pdevice->rad_info.chip_class >= GFX9 &&
929 stage == MESA_SHADER_GEOMETRY) {
930 unsigned es_type = info->gs.es_type;
931 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
932
933 if (es_type == MESA_SHADER_VERTEX) {
934 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
935 if (info->vs.needs_instance_id) {
936 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
937 } else {
938 es_vgpr_comp_cnt = 0;
939 }
940 } else if (es_type == MESA_SHADER_TESS_EVAL) {
941 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
942 } else {
943 unreachable("invalid shader ES type");
944 }
945
946 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
947 * VGPR[0:4] are always loaded.
948 */
949 if (info->uses_invocation_id) {
950 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
951 } else if (info->uses_prim_id) {
952 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
953 } else if (info->gs.vertices_in >= 3) {
954 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
955 } else {
956 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
957 }
958
959 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
960 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
961 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
962 } else if (pdevice->rad_info.chip_class >= GFX9 &&
963 stage == MESA_SHADER_TESS_CTRL) {
964 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
965 } else {
966 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
967 }
968 }
969
970 struct radv_shader_variant *
971 radv_shader_variant_create(struct radv_device *device,
972 const struct radv_shader_binary *binary,
973 bool keep_shader_info)
974 {
975 struct ac_shader_config config = {0};
976 struct ac_rtld_binary rtld_binary = {0};
977 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
978 if (!variant)
979 return NULL;
980
981 variant->ref_count = 1;
982
983 if (binary->type == RADV_BINARY_TYPE_RTLD) {
984 struct ac_rtld_symbol lds_symbols[2];
985 unsigned num_lds_symbols = 0;
986 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
987 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
988
989 if (device->physical_device->rad_info.chip_class >= GFX9 &&
990 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
991 !binary->is_gs_copy_shader) {
992 /* We add this symbol even on LLVM <= 8 to ensure that
993 * shader->config.lds_size is set correctly below.
994 */
995 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
996 sym->name = "esgs_ring";
997 sym->size = binary->info.ngg_info.esgs_ring_size;
998 sym->align = 64 * 1024;
999 }
1000
1001 if (binary->info.is_ngg &&
1002 binary->stage == MESA_SHADER_GEOMETRY) {
1003 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1004 sym->name = "ngg_emit";
1005 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1006 sym->align = 4;
1007 }
1008
1009 struct ac_rtld_open_info open_info = {
1010 .info = &device->physical_device->rad_info,
1011 .shader_type = binary->stage,
1012 .wave_size = binary->info.wave_size,
1013 .num_parts = 1,
1014 .elf_ptrs = &elf_data,
1015 .elf_sizes = &elf_size,
1016 .num_shared_lds_symbols = num_lds_symbols,
1017 .shared_lds_symbols = lds_symbols,
1018 };
1019
1020 if (!ac_rtld_open(&rtld_binary, open_info)) {
1021 free(variant);
1022 return NULL;
1023 }
1024
1025 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1026 &rtld_binary, &config)) {
1027 ac_rtld_close(&rtld_binary);
1028 free(variant);
1029 return NULL;
1030 }
1031
1032 if (rtld_binary.lds_size > 0) {
1033 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1034 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1035 }
1036
1037 variant->code_size = rtld_binary.rx_size;
1038 variant->exec_size = rtld_binary.exec_size;
1039 } else {
1040 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1041 config = ((struct radv_shader_binary_legacy *)binary)->config;
1042 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1043 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1044 }
1045
1046 variant->info = binary->info;
1047 radv_postprocess_config(device->physical_device, &config, &binary->info,
1048 binary->stage, &variant->config);
1049
1050 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1051 if (!dest_ptr) {
1052 if (binary->type == RADV_BINARY_TYPE_RTLD)
1053 ac_rtld_close(&rtld_binary);
1054 free(variant);
1055 return NULL;
1056 }
1057
1058 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1059 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1060 struct ac_rtld_upload_info info = {
1061 .binary = &rtld_binary,
1062 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1063 .rx_ptr = dest_ptr,
1064 };
1065
1066 if (!ac_rtld_upload(&info)) {
1067 radv_shader_variant_destroy(device, variant);
1068 ac_rtld_close(&rtld_binary);
1069 return NULL;
1070 }
1071
1072 if (keep_shader_info ||
1073 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1074 const char *disasm_data;
1075 size_t disasm_size;
1076 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1077 radv_shader_variant_destroy(device, variant);
1078 ac_rtld_close(&rtld_binary);
1079 return NULL;
1080 }
1081
1082 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1083 variant->disasm_string = malloc(disasm_size + 1);
1084 memcpy(variant->disasm_string, disasm_data, disasm_size);
1085 variant->disasm_string[disasm_size] = 0;
1086 }
1087
1088 ac_rtld_close(&rtld_binary);
1089 } else {
1090 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1091 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1092
1093 /* Add end-of-code markers for the UMR disassembler. */
1094 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1095 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1096 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1097
1098 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1099 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1100
1101 if (bin->stats_size) {
1102 variant->statistics = calloc(bin->stats_size, 1);
1103 memcpy(variant->statistics, bin->data, bin->stats_size);
1104 }
1105 }
1106 return variant;
1107 }
1108
1109 static char *
1110 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1111 int shader_count)
1112 {
1113 char *data = NULL;
1114 char *ret = NULL;
1115 size_t size = 0;
1116 FILE *f = open_memstream(&data, &size);
1117 if (f) {
1118 for (int i = 0; i < shader_count; ++i)
1119 nir_print_shader(shaders[i], f);
1120 fclose(f);
1121 }
1122
1123 ret = malloc(size + 1);
1124 if (ret) {
1125 memcpy(ret, data, size);
1126 ret[size] = 0;
1127 }
1128 free(data);
1129 return ret;
1130 }
1131
1132 static struct radv_shader_variant *
1133 shader_variant_compile(struct radv_device *device,
1134 struct radv_shader_module *module,
1135 struct nir_shader * const *shaders,
1136 int shader_count,
1137 gl_shader_stage stage,
1138 struct radv_shader_info *info,
1139 struct radv_nir_compiler_options *options,
1140 bool gs_copy_shader,
1141 bool keep_shader_info,
1142 bool keep_statistic_info,
1143 struct radv_shader_binary **binary_out)
1144 {
1145 enum radeon_family chip_family = device->physical_device->rad_info.family;
1146 struct radv_shader_binary *binary = NULL;
1147
1148 options->family = chip_family;
1149 options->chip_class = device->physical_device->rad_info.chip_class;
1150 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1151 options->dump_preoptir = options->dump_shader &&
1152 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1153 options->record_ir = keep_shader_info;
1154 options->record_stats = keep_statistic_info;
1155 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1156 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1157 options->address32_hi = device->physical_device->rad_info.address32_hi;
1158 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1159 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1160 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1161
1162 struct radv_shader_args args = {};
1163 args.options = options;
1164 args.shader_info = info;
1165 args.is_gs_copy_shader = gs_copy_shader;
1166 radv_declare_shader_args(&args,
1167 gs_copy_shader ? MESA_SHADER_VERTEX
1168 : shaders[shader_count - 1]->info.stage,
1169 shader_count >= 2,
1170 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1171 : MESA_SHADER_VERTEX);
1172
1173 if (device->physical_device->use_llvm ||
1174 options->dump_shader || options->record_ir)
1175 ac_init_llvm_once();
1176
1177 if (device->physical_device->use_llvm) {
1178 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1179 } else {
1180 aco_compile_shader(shader_count, shaders, &binary, &args);
1181 }
1182
1183 binary->info = *info;
1184
1185 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1186 keep_shader_info);
1187 if (!variant) {
1188 free(binary);
1189 return NULL;
1190 }
1191
1192 if (options->dump_shader) {
1193 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1194 for (int i = 1; i < shader_count; ++i)
1195 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1196
1197 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1198 }
1199
1200
1201 if (keep_shader_info) {
1202 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1203 if (!gs_copy_shader && !module->nir) {
1204 variant->spirv = malloc(module->size);
1205 if (!variant->spirv) {
1206 free(variant);
1207 free(binary);
1208 return NULL;
1209 }
1210
1211 memcpy(variant->spirv, module->data, module->size);
1212 variant->spirv_size = module->size;
1213 }
1214 }
1215
1216 if (binary_out)
1217 *binary_out = binary;
1218 else
1219 free(binary);
1220
1221 return variant;
1222 }
1223
1224 struct radv_shader_variant *
1225 radv_shader_variant_compile(struct radv_device *device,
1226 struct radv_shader_module *module,
1227 struct nir_shader *const *shaders,
1228 int shader_count,
1229 struct radv_pipeline_layout *layout,
1230 const struct radv_shader_variant_key *key,
1231 struct radv_shader_info *info,
1232 bool keep_shader_info, bool keep_statistic_info,
1233 struct radv_shader_binary **binary_out)
1234 {
1235 struct radv_nir_compiler_options options = {0};
1236
1237 options.layout = layout;
1238 if (key)
1239 options.key = *key;
1240
1241 options.explicit_scratch_args = !device->physical_device->use_llvm;
1242 options.robust_buffer_access = device->robust_buffer_access;
1243
1244 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1245 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1246 }
1247
1248 struct radv_shader_variant *
1249 radv_create_gs_copy_shader(struct radv_device *device,
1250 struct nir_shader *shader,
1251 struct radv_shader_info *info,
1252 struct radv_shader_binary **binary_out,
1253 bool keep_shader_info, bool keep_statistic_info,
1254 bool multiview)
1255 {
1256 struct radv_nir_compiler_options options = {0};
1257
1258 options.explicit_scratch_args = !device->physical_device->use_llvm;
1259 options.key.has_multiview_view_index = multiview;
1260
1261 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1262 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1263 }
1264
1265 void
1266 radv_shader_variant_destroy(struct radv_device *device,
1267 struct radv_shader_variant *variant)
1268 {
1269 if (!p_atomic_dec_zero(&variant->ref_count))
1270 return;
1271
1272 mtx_lock(&device->shader_slab_mutex);
1273 list_del(&variant->slab_list);
1274 mtx_unlock(&device->shader_slab_mutex);
1275
1276 free(variant->spirv);
1277 free(variant->nir_string);
1278 free(variant->disasm_string);
1279 free(variant->ir_string);
1280 free(variant->statistics);
1281 free(variant);
1282 }
1283
1284 const char *
1285 radv_get_shader_name(struct radv_shader_info *info,
1286 gl_shader_stage stage)
1287 {
1288 switch (stage) {
1289 case MESA_SHADER_VERTEX:
1290 if (info->vs.as_ls)
1291 return "Vertex Shader as LS";
1292 else if (info->vs.as_es)
1293 return "Vertex Shader as ES";
1294 else if (info->is_ngg)
1295 return "Vertex Shader as ESGS";
1296 else
1297 return "Vertex Shader as VS";
1298 case MESA_SHADER_TESS_CTRL:
1299 return "Tessellation Control Shader";
1300 case MESA_SHADER_TESS_EVAL:
1301 if (info->tes.as_es)
1302 return "Tessellation Evaluation Shader as ES";
1303 else if (info->is_ngg)
1304 return "Tessellation Evaluation Shader as ESGS";
1305 else
1306 return "Tessellation Evaluation Shader as VS";
1307 case MESA_SHADER_GEOMETRY:
1308 return "Geometry Shader";
1309 case MESA_SHADER_FRAGMENT:
1310 return "Pixel Shader";
1311 case MESA_SHADER_COMPUTE:
1312 return "Compute Shader";
1313 default:
1314 return "Unknown shader";
1315 };
1316 }
1317
1318 unsigned
1319 radv_get_max_workgroup_size(enum chip_class chip_class,
1320 gl_shader_stage stage,
1321 const unsigned *sizes)
1322 {
1323 switch (stage) {
1324 case MESA_SHADER_TESS_CTRL:
1325 return chip_class >= GFX7 ? 128 : 64;
1326 case MESA_SHADER_GEOMETRY:
1327 return chip_class >= GFX9 ? 128 : 64;
1328 case MESA_SHADER_COMPUTE:
1329 break;
1330 default:
1331 return 0;
1332 }
1333
1334 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1335 return max_workgroup_size;
1336 }
1337
1338 unsigned
1339 radv_get_max_waves(struct radv_device *device,
1340 struct radv_shader_variant *variant,
1341 gl_shader_stage stage)
1342 {
1343 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1344 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1345 uint8_t wave_size = variant->info.wave_size;
1346 struct ac_shader_config *conf = &variant->config;
1347 unsigned max_simd_waves;
1348 unsigned lds_per_wave = 0;
1349
1350 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1351
1352 if (stage == MESA_SHADER_FRAGMENT) {
1353 lds_per_wave = conf->lds_size * lds_increment +
1354 align(variant->info.ps.num_interp * 48,
1355 lds_increment);
1356 } else if (stage == MESA_SHADER_COMPUTE) {
1357 unsigned max_workgroup_size =
1358 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1359 lds_per_wave = (conf->lds_size * lds_increment) /
1360 DIV_ROUND_UP(max_workgroup_size, wave_size);
1361 }
1362
1363 if (conf->num_sgprs) {
1364 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1365 max_simd_waves =
1366 MIN2(max_simd_waves,
1367 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1368 sgprs);
1369 }
1370
1371 if (conf->num_vgprs) {
1372 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1373 max_simd_waves =
1374 MIN2(max_simd_waves,
1375 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1376 }
1377
1378 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1379 if (lds_per_wave)
1380 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1381
1382 return max_simd_waves;
1383 }
1384
1385 static void
1386 generate_shader_stats(struct radv_device *device,
1387 struct radv_shader_variant *variant,
1388 gl_shader_stage stage,
1389 struct _mesa_string_buffer *buf)
1390 {
1391 struct ac_shader_config *conf = &variant->config;
1392 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1393
1394 if (stage == MESA_SHADER_FRAGMENT) {
1395 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1396 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1397 "SPI_PS_INPUT_ENA = 0x%04x\n",
1398 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1399 }
1400
1401 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1402 "SGPRS: %d\n"
1403 "VGPRS: %d\n"
1404 "Spilled SGPRs: %d\n"
1405 "Spilled VGPRs: %d\n"
1406 "PrivMem VGPRS: %d\n"
1407 "Code Size: %d bytes\n"
1408 "LDS: %d blocks\n"
1409 "Scratch: %d bytes per wave\n"
1410 "Max Waves: %d\n",
1411 conf->num_sgprs, conf->num_vgprs,
1412 conf->spilled_sgprs, conf->spilled_vgprs,
1413 variant->info.private_mem_vgprs, variant->exec_size,
1414 conf->lds_size, conf->scratch_bytes_per_wave,
1415 max_simd_waves);
1416
1417 if (variant->statistics) {
1418 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1419 for (unsigned i = 0; i < variant->statistics->count; i++) {
1420 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1421 uint32_t value = variant->statistics->values[i];
1422 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1423 }
1424 }
1425
1426 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1427 }
1428
1429 void
1430 radv_shader_dump_stats(struct radv_device *device,
1431 struct radv_shader_variant *variant,
1432 gl_shader_stage stage,
1433 FILE *file)
1434 {
1435 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1436
1437 generate_shader_stats(device, variant, stage, buf);
1438
1439 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1440 fprintf(file, "%s", buf->buf);
1441
1442 _mesa_string_buffer_destroy(buf);
1443 }
1444
1445 VkResult
1446 radv_GetShaderInfoAMD(VkDevice _device,
1447 VkPipeline _pipeline,
1448 VkShaderStageFlagBits shaderStage,
1449 VkShaderInfoTypeAMD infoType,
1450 size_t* pInfoSize,
1451 void* pInfo)
1452 {
1453 RADV_FROM_HANDLE(radv_device, device, _device);
1454 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1455 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1456 struct radv_shader_variant *variant = pipeline->shaders[stage];
1457 struct _mesa_string_buffer *buf;
1458 VkResult result = VK_SUCCESS;
1459
1460 /* Spec doesn't indicate what to do if the stage is invalid, so just
1461 * return no info for this. */
1462 if (!variant)
1463 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1464
1465 switch (infoType) {
1466 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1467 if (!pInfo) {
1468 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1469 } else {
1470 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1471 struct ac_shader_config *conf = &variant->config;
1472
1473 VkShaderStatisticsInfoAMD statistics = {};
1474 statistics.shaderStageMask = shaderStage;
1475 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1476 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1477 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1478
1479 if (stage == MESA_SHADER_COMPUTE) {
1480 unsigned *local_size = variant->info.cs.block_size;
1481 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1482
1483 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1484 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1485
1486 statistics.computeWorkGroupSize[0] = local_size[0];
1487 statistics.computeWorkGroupSize[1] = local_size[1];
1488 statistics.computeWorkGroupSize[2] = local_size[2];
1489 } else {
1490 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1491 }
1492
1493 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1494 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1495 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1496 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1497 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1498
1499 size_t size = *pInfoSize;
1500 *pInfoSize = sizeof(statistics);
1501
1502 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1503
1504 if (size < *pInfoSize)
1505 result = VK_INCOMPLETE;
1506 }
1507
1508 break;
1509 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1510 buf = _mesa_string_buffer_create(NULL, 1024);
1511
1512 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1513 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1514 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1515 generate_shader_stats(device, variant, stage, buf);
1516
1517 /* Need to include the null terminator. */
1518 size_t length = buf->length + 1;
1519
1520 if (!pInfo) {
1521 *pInfoSize = length;
1522 } else {
1523 size_t size = *pInfoSize;
1524 *pInfoSize = length;
1525
1526 memcpy(pInfo, buf->buf, MIN2(size, length));
1527
1528 if (size < length)
1529 result = VK_INCOMPLETE;
1530 }
1531
1532 _mesa_string_buffer_destroy(buf);
1533 break;
1534 default:
1535 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1536 result = VK_ERROR_FEATURE_NOT_PRESENT;
1537 break;
1538 }
1539
1540 return result;
1541 }