vallium: disable VK_KHR_shader_float16_int8.
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
282 if (shader->options->max_unroll_iterations) {
283 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
284 }
285 } while (progress && !optimize_conservatively);
286
287 NIR_PASS(progress, shader, nir_opt_conditional_discard);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 struct radv_shader_debug_data {
303 struct radv_device *device;
304 const struct radv_shader_module *module;
305 };
306
307 static void radv_spirv_nir_debug(void *private_data,
308 enum nir_spirv_debug_level level,
309 size_t spirv_offset,
310 const char *message)
311 {
312 struct radv_shader_debug_data *debug_data = private_data;
313 struct radv_instance *instance = debug_data->device->instance;
314
315 static const VkDebugReportFlagsEXT vk_flags[] = {
316 [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
317 [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
318 [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
319 };
320 char buffer[256];
321
322 snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s",
323 (unsigned long)spirv_offset, message);
324
325 vk_debug_report(&instance->debug_report_callbacks,
326 vk_flags[level],
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
328 (uint64_t)(uintptr_t)debug_data->module,
329 0, 0, "radv", buffer);
330 }
331
332 static void radv_compiler_debug(void *private_data,
333 enum radv_compiler_debug_level level,
334 const char *message)
335 {
336 struct radv_shader_debug_data *debug_data = private_data;
337 struct radv_instance *instance = debug_data->device->instance;
338
339 static const VkDebugReportFlagsEXT vk_flags[] = {
340 [RADV_COMPILER_DEBUG_LEVEL_PERFWARN] = VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT,
341 [RADV_COMPILER_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
342 };
343
344 /* VK_DEBUG_REPORT_DEBUG_BIT_EXT specifies diagnostic information
345 * from the implementation and layers.
346 */
347 vk_debug_report(&instance->debug_report_callbacks,
348 vk_flags[level] | VK_DEBUG_REPORT_DEBUG_BIT_EXT,
349 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
350 (uint64_t)(uintptr_t)debug_data->module,
351 0, 0, "radv", message);
352 }
353
354 nir_shader *
355 radv_shader_compile_to_nir(struct radv_device *device,
356 struct radv_shader_module *module,
357 const char *entrypoint_name,
358 gl_shader_stage stage,
359 const VkSpecializationInfo *spec_info,
360 const VkPipelineCreateFlags flags,
361 const struct radv_pipeline_layout *layout,
362 unsigned subgroup_size, unsigned ballot_bit_size)
363 {
364 nir_shader *nir;
365 const nir_shader_compiler_options *nir_options =
366 radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco;
367
368 if (module->nir) {
369 /* Some things such as our meta clear/blit code will give us a NIR
370 * shader directly. In that case, we just ignore the SPIR-V entirely
371 * and just use the NIR shader */
372 nir = module->nir;
373 nir->options = nir_options;
374 nir_validate_shader(nir, "in internal shader");
375
376 assert(exec_list_length(&nir->functions) == 1);
377 } else {
378 uint32_t *spirv = (uint32_t *) module->data;
379 assert(module->size % 4 == 0);
380
381 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
382 radv_print_spirv(module->data, module->size, stderr);
383
384 uint32_t num_spec_entries = 0;
385 struct nir_spirv_specialization *spec_entries = NULL;
386 if (spec_info && spec_info->mapEntryCount > 0) {
387 num_spec_entries = spec_info->mapEntryCount;
388 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
389 for (uint32_t i = 0; i < num_spec_entries; i++) {
390 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
391 const void *data = spec_info->pData + entry.offset;
392 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
393
394 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
395 switch (entry.size) {
396 case 8:
397 spec_entries[i].value.u64 = *(const uint64_t *)data;
398 break;
399 case 4:
400 spec_entries[i].value.u32 = *(const uint32_t *)data;
401 break;
402 case 2:
403 spec_entries[i].value.u16 = *(const uint16_t *)data;
404 break;
405 case 1:
406 spec_entries[i].value.u8 = *(const uint8_t *)data;
407 break;
408 default:
409 assert(!"Invalid spec constant size");
410 break;
411 }
412 }
413 }
414
415 struct radv_shader_debug_data spirv_debug_data = {
416 .device = device,
417 .module = module,
418 };
419 const struct spirv_to_nir_options spirv_options = {
420 .lower_ubo_ssbo_access_to_offsets = true,
421 .caps = {
422 .amd_fragment_mask = true,
423 .amd_gcn_shader = true,
424 .amd_image_gather_bias_lod = true,
425 .amd_image_read_write_lod = true,
426 .amd_shader_ballot = true,
427 .amd_shader_explicit_vertex_parameter = true,
428 .amd_trinary_minmax = true,
429 .demote_to_helper_invocation = true,
430 .derivative_group = true,
431 .descriptor_array_dynamic_indexing = true,
432 .descriptor_array_non_uniform_indexing = true,
433 .descriptor_indexing = true,
434 .device_group = true,
435 .draw_parameters = true,
436 .float_controls = true,
437 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
438 .float32_atomic_add = true,
439 .float64 = true,
440 .geometry_streams = true,
441 .image_ms_array = true,
442 .image_read_without_format = true,
443 .image_write_without_format = true,
444 .int8 = true,
445 .int16 = true,
446 .int64 = true,
447 .int64_atomics = true,
448 .min_lod = true,
449 .multiview = true,
450 .physical_storage_buffer_address = true,
451 .post_depth_coverage = true,
452 .runtime_descriptor_array = true,
453 .shader_clock = true,
454 .shader_viewport_index_layer = true,
455 .stencil_export = true,
456 .storage_8bit = true,
457 .storage_16bit = true,
458 .storage_image_ms = true,
459 .subgroup_arithmetic = true,
460 .subgroup_ballot = true,
461 .subgroup_basic = true,
462 .subgroup_quad = true,
463 .subgroup_shuffle = true,
464 .subgroup_vote = true,
465 .tessellation = true,
466 .transform_feedback = true,
467 .variable_pointers = true,
468 .vk_memory_model = true,
469 .vk_memory_model_device_scope = true,
470 },
471 .ubo_addr_format = nir_address_format_32bit_index_offset,
472 .ssbo_addr_format = nir_address_format_32bit_index_offset,
473 .phys_ssbo_addr_format = nir_address_format_64bit_global,
474 .push_const_addr_format = nir_address_format_logical,
475 .shared_addr_format = nir_address_format_32bit_offset,
476 .frag_coord_is_sysval = true,
477 .debug = {
478 .func = radv_spirv_nir_debug,
479 .private_data = &spirv_debug_data,
480 },
481 };
482 nir = spirv_to_nir(spirv, module->size / 4,
483 spec_entries, num_spec_entries,
484 stage, entrypoint_name,
485 &spirv_options, nir_options);
486 assert(nir->info.stage == stage);
487 nir_validate_shader(nir, "after spirv_to_nir");
488
489 free(spec_entries);
490
491 /* We have to lower away local constant initializers right before we
492 * inline functions. That way they get properly initialized at the top
493 * of the function and not at the top of its caller.
494 */
495 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
496 NIR_PASS_V(nir, nir_lower_returns);
497 NIR_PASS_V(nir, nir_inline_functions);
498 NIR_PASS_V(nir, nir_copy_prop);
499 NIR_PASS_V(nir, nir_opt_deref);
500
501 /* Pick off the single entrypoint that we want */
502 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
503 if (func->is_entrypoint)
504 func->name = ralloc_strdup(func, "main");
505 else
506 exec_node_remove(&func->node);
507 }
508 assert(exec_list_length(&nir->functions) == 1);
509
510 /* Make sure we lower constant initializers on output variables so that
511 * nir_remove_dead_variables below sees the corresponding stores
512 */
513 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
514
515 /* Now that we've deleted all but the main function, we can go ahead and
516 * lower the rest of the constant initializers.
517 */
518 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
519
520 /* Split member structs. We do this before lower_io_to_temporaries so that
521 * it doesn't lower system values to temporaries by accident.
522 */
523 NIR_PASS_V(nir, nir_split_var_copies);
524 NIR_PASS_V(nir, nir_split_per_member_structs);
525
526 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
527 !radv_use_llvm_for_stage(device, nir->info.stage))
528 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
529 if (nir->info.stage == MESA_SHADER_FRAGMENT)
530 NIR_PASS_V(nir, nir_lower_input_attachments,
531 &(nir_input_attachment_options) {
532 .use_fragcoord_sysval = true,
533 .use_layer_id_sysval = false,
534 });
535
536 NIR_PASS_V(nir, nir_remove_dead_variables,
537 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
538 NULL);
539
540 NIR_PASS_V(nir, nir_propagate_invariant);
541
542 NIR_PASS_V(nir, nir_lower_system_values);
543 NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
544
545 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
546
547 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
548 NIR_PASS_V(nir, nir_lower_discard_to_demote);
549
550 nir_lower_doubles_options lower_doubles =
551 nir->options->lower_doubles_options;
552
553 if (device->physical_device->rad_info.chip_class == GFX6) {
554 /* GFX6 doesn't support v_floor_f64 and the precision
555 * of v_fract_f64 which is used to implement 64-bit
556 * floor is less than what Vulkan requires.
557 */
558 lower_doubles |= nir_lower_dfloor;
559 }
560
561 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
562 }
563
564 /* Vulkan uses the separate-shader linking model */
565 nir->info.separate_shader = true;
566
567 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
568
569 if (nir->info.stage == MESA_SHADER_GEOMETRY)
570 nir_lower_gs_intrinsics(nir, true);
571
572 static const nir_lower_tex_options tex_options = {
573 .lower_txp = ~0,
574 .lower_tg4_offsets = true,
575 };
576
577 nir_lower_tex(nir, &tex_options);
578
579 nir_lower_vars_to_ssa(nir);
580
581 if (nir->info.stage == MESA_SHADER_VERTEX ||
582 nir->info.stage == MESA_SHADER_GEOMETRY ||
583 nir->info.stage == MESA_SHADER_FRAGMENT) {
584 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
585 nir_shader_get_entrypoint(nir), true, true);
586 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
587 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
588 nir_shader_get_entrypoint(nir), true, false);
589 }
590
591 nir_split_var_copies(nir);
592
593 nir_lower_global_vars_to_local(nir);
594 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
595 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
596 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
597 .subgroup_size = subgroup_size,
598 .ballot_bit_size = ballot_bit_size,
599 .lower_to_scalar = 1,
600 .lower_subgroup_masks = 1,
601 .lower_shuffle = 1,
602 .lower_shuffle_to_32bit = 1,
603 .lower_vote_eq_to_ballot = 1,
604 .lower_quad_broadcast_dynamic = 1,
605 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
606 .lower_shuffle_to_swizzle_amd = 1,
607 });
608
609 nir_lower_load_const_to_scalar(nir);
610
611 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
612 radv_optimize_nir(nir, false, true);
613
614 /* call radv_nir_lower_ycbcr_textures() late as there might still be
615 * tex with undef texture/sampler before first optimization */
616 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
617
618 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
619 * to remove any copies introduced by nir_opt_find_array_copies().
620 */
621 nir_lower_var_copies(nir);
622
623 /* Lower deref operations for compute shared memory. */
624 if (nir->info.stage == MESA_SHADER_COMPUTE) {
625 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
626 nir_var_mem_shared, shared_var_info);
627 NIR_PASS_V(nir, nir_lower_explicit_io,
628 nir_var_mem_shared, nir_address_format_32bit_offset);
629 }
630
631 /* Lower large variables that are always constant with load_constant
632 * intrinsics, which get turned into PC-relative loads from a data
633 * section next to the shader.
634 */
635 NIR_PASS_V(nir, nir_opt_large_constants,
636 glsl_get_natural_size_align_bytes, 16);
637
638 /* Indirect lowering must be called after the radv_optimize_nir() loop
639 * has been called at least once. Otherwise indirect lowering can
640 * bloat the instruction count of the loop and cause it to be
641 * considered too large for unrolling.
642 */
643 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
644 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
645
646 return nir;
647 }
648
649 static int
650 type_size_vec4(const struct glsl_type *type, bool bindless)
651 {
652 return glsl_count_attribute_slots(type, false);
653 }
654
655 static nir_variable *
656 find_layer_in_var(nir_shader *nir)
657 {
658 nir_variable *var =
659 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
660 if (var != NULL)
661 return var;
662
663 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
664 var->data.location = VARYING_SLOT_LAYER;
665 var->data.interpolation = INTERP_MODE_FLAT;
666 return var;
667 }
668
669 /* We use layered rendering to implement multiview, which means we need to map
670 * view_index to gl_Layer. The code generates a load from the layer_id sysval,
671 * but since we don't have a way to get at this information from the fragment
672 * shader, we also need to lower this to the gl_Layer varying. This pass
673 * lowers both to a varying load from the LAYER slot, before lowering io, so
674 * that nir_assign_var_locations() will give the LAYER varying the correct
675 * driver_location.
676 */
677
678 static bool
679 lower_view_index(nir_shader *nir)
680 {
681 bool progress = false;
682 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
683 nir_builder b;
684 nir_builder_init(&b, entry);
685
686 nir_variable *layer = NULL;
687 nir_foreach_block(block, entry) {
688 nir_foreach_instr_safe(instr, block) {
689 if (instr->type != nir_instr_type_intrinsic)
690 continue;
691
692 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
693 if (load->intrinsic != nir_intrinsic_load_view_index)
694 continue;
695
696 if (!layer)
697 layer = find_layer_in_var(nir);
698
699 b.cursor = nir_before_instr(instr);
700 nir_ssa_def *def = nir_load_var(&b, layer);
701 nir_ssa_def_rewrite_uses(&load->dest.ssa,
702 nir_src_for_ssa(def));
703
704 nir_instr_remove(instr);
705 progress = true;
706 }
707 }
708
709 return progress;
710 }
711
712 void
713 radv_lower_fs_io(nir_shader *nir)
714 {
715 NIR_PASS_V(nir, lower_view_index);
716 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
717 MESA_SHADER_FRAGMENT);
718
719 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
720
721 /* This pass needs actual constants */
722 nir_opt_constant_folding(nir);
723
724 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
725 }
726
727
728 static void *
729 radv_alloc_shader_memory(struct radv_device *device,
730 struct radv_shader_variant *shader)
731 {
732 mtx_lock(&device->shader_slab_mutex);
733 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
734 uint64_t offset = 0;
735 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
736 if (s->bo_offset - offset >= shader->code_size) {
737 shader->bo = slab->bo;
738 shader->bo_offset = offset;
739 list_addtail(&shader->slab_list, &s->slab_list);
740 mtx_unlock(&device->shader_slab_mutex);
741 return slab->ptr + offset;
742 }
743 offset = align_u64(s->bo_offset + s->code_size, 256);
744 }
745 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
746 shader->bo = slab->bo;
747 shader->bo_offset = offset;
748 list_addtail(&shader->slab_list, &slab->shaders);
749 mtx_unlock(&device->shader_slab_mutex);
750 return slab->ptr + offset;
751 }
752 }
753
754 mtx_unlock(&device->shader_slab_mutex);
755 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
756
757 slab->size = MAX2(256 * 1024, shader->code_size);
758 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
759 RADEON_DOMAIN_VRAM,
760 RADEON_FLAG_NO_INTERPROCESS_SHARING |
761 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
762 0 : RADEON_FLAG_READ_ONLY),
763 RADV_BO_PRIORITY_SHADER);
764 if (!slab->bo) {
765 free(slab);
766 return NULL;
767 }
768
769 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
770 if (!slab->ptr) {
771 device->ws->buffer_destroy(slab->bo);
772 free(slab);
773 return NULL;
774 }
775
776 list_inithead(&slab->shaders);
777
778 mtx_lock(&device->shader_slab_mutex);
779 list_add(&slab->slabs, &device->shader_slabs);
780
781 shader->bo = slab->bo;
782 shader->bo_offset = 0;
783 list_add(&shader->slab_list, &slab->shaders);
784 mtx_unlock(&device->shader_slab_mutex);
785 return slab->ptr;
786 }
787
788 void
789 radv_destroy_shader_slabs(struct radv_device *device)
790 {
791 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
792 device->ws->buffer_destroy(slab->bo);
793 free(slab);
794 }
795 mtx_destroy(&device->shader_slab_mutex);
796 }
797
798 /* For the UMR disassembler. */
799 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
800 #define DEBUGGER_NUM_MARKERS 5
801
802 static unsigned
803 radv_get_shader_binary_size(size_t code_size)
804 {
805 return code_size + DEBUGGER_NUM_MARKERS * 4;
806 }
807
808 static void radv_postprocess_config(const struct radv_device *device,
809 const struct ac_shader_config *config_in,
810 const struct radv_shader_info *info,
811 gl_shader_stage stage,
812 struct ac_shader_config *config_out)
813 {
814 const struct radv_physical_device *pdevice = device->physical_device;
815 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
816 bool trap_enabled = !!device->trap_handler_shader;
817 unsigned vgpr_comp_cnt = 0;
818 unsigned num_input_vgprs = info->num_input_vgprs;
819
820 if (stage == MESA_SHADER_FRAGMENT) {
821 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
822 }
823
824 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
825 /* +3 for scratch wave offset and VCC */
826 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
827 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
828 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
829 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
830 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
831 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
832 unsigned excp_en = 0;
833
834 *config_out = *config_in;
835 config_out->num_vgprs = num_vgprs;
836 config_out->num_sgprs = num_sgprs;
837 config_out->num_shared_vgprs = num_shared_vgprs;
838
839 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
840 S_00B12C_SCRATCH_EN(scratch_enabled) |
841 S_00B12C_TRAP_PRESENT(trap_enabled);
842
843 if (trap_enabled) {
844 /* Configure the shader exceptions like memory violation, etc.
845 * TODO: Enable (and validate) more exceptions.
846 */
847 excp_en = 1 << 8; /* mem_viol */
848 }
849
850 if (!pdevice->use_ngg_streamout) {
851 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
852 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
853 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
854 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
855 S_00B12C_SO_EN(!!info->so.num_outputs);
856 }
857
858 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
859 (info->wave_size == 32 ? 8 : 4)) |
860 S_00B848_DX10_CLAMP(1) |
861 S_00B848_FLOAT_MODE(config_out->float_mode);
862
863 if (pdevice->rad_info.chip_class >= GFX10) {
864 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
865 } else {
866 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
867 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
868 }
869
870 switch (stage) {
871 case MESA_SHADER_TESS_EVAL:
872 if (info->is_ngg) {
873 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
874 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1) |
875 S_00B22C_EXCP_EN(excp_en);
876 } else if (info->tes.as_es) {
877 assert(pdevice->rad_info.chip_class <= GFX8);
878 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
879
880 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) |
881 S_00B12C_EXCP_EN(excp_en);
882 } else {
883 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
884 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
885
886 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
887 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) |
888 S_00B12C_EXCP_EN(excp_en);
889 }
890 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
891 break;
892 case MESA_SHADER_TESS_CTRL:
893 if (pdevice->rad_info.chip_class >= GFX9) {
894 /* We need at least 2 components for LS.
895 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
896 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
897 */
898 if (pdevice->rad_info.chip_class >= GFX10) {
899 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
900 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) |
901 S_00B42C_EXCP_EN_GFX10(excp_en);
902 } else {
903 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
904 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) |
905 S_00B42C_EXCP_EN_GFX9(excp_en);
906 }
907 } else {
908 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) |
909 S_00B12C_EXCP_EN(excp_en);
910 }
911 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
912 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
913 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
914 break;
915 case MESA_SHADER_VERTEX:
916 if (info->is_ngg) {
917 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
918 } else if (info->vs.as_ls) {
919 assert(pdevice->rad_info.chip_class <= GFX8);
920 /* We need at least 2 components for LS.
921 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
922 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
923 */
924 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
925 } else if (info->vs.as_es) {
926 assert(pdevice->rad_info.chip_class <= GFX8);
927 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
928 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
929 } else {
930 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
931 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
932 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
933 */
934 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
935 vgpr_comp_cnt = 3;
936 } else if (info->vs.export_prim_id) {
937 vgpr_comp_cnt = 2;
938 } else if (info->vs.needs_instance_id) {
939 vgpr_comp_cnt = 1;
940 } else {
941 vgpr_comp_cnt = 0;
942 }
943
944 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
945 }
946 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
947 S_00B12C_EXCP_EN(excp_en);
948 break;
949 case MESA_SHADER_FRAGMENT:
950 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
951 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
952 S_00B02C_TRAP_PRESENT(1) |
953 S_00B02C_EXCP_EN(excp_en);
954 break;
955 case MESA_SHADER_GEOMETRY:
956 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
957 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
958 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
959 S_00B22C_EXCP_EN(excp_en);
960 break;
961 case MESA_SHADER_COMPUTE:
962 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
963 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
964 config_out->rsrc2 |=
965 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
966 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
967 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
968 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
969 info->cs.uses_thread_id[1] ? 1 : 0) |
970 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
971 S_00B84C_LDS_SIZE(config_in->lds_size) |
972 S_00B84C_EXCP_EN(excp_en);
973 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
974
975 break;
976 default:
977 unreachable("unsupported shader type");
978 break;
979 }
980
981 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
982 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
983 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
984 gl_shader_stage es_stage = stage;
985 if (stage == MESA_SHADER_GEOMETRY)
986 es_stage = info->gs.es_type;
987
988 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
989 if (es_stage == MESA_SHADER_VERTEX) {
990 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
991 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
992 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
993 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
994 } else
995 unreachable("Unexpected ES shader stage");
996
997 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
998 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
999 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
1000 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1001 } else if (info->uses_prim_id) {
1002 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1003 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
1004 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1005 } else {
1006 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1007 }
1008
1009 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
1010 S_00B228_WGP_MODE(1);
1011 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1012 S_00B22C_LDS_SIZE(config_in->lds_size) |
1013 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
1014 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1015 stage == MESA_SHADER_GEOMETRY) {
1016 unsigned es_type = info->gs.es_type;
1017 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
1018
1019 if (es_type == MESA_SHADER_VERTEX) {
1020 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
1021 if (info->vs.needs_instance_id) {
1022 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
1023 } else {
1024 es_vgpr_comp_cnt = 0;
1025 }
1026 } else if (es_type == MESA_SHADER_TESS_EVAL) {
1027 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
1028 } else {
1029 unreachable("invalid shader ES type");
1030 }
1031
1032 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1033 * VGPR[0:4] are always loaded.
1034 */
1035 if (info->uses_invocation_id) {
1036 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1037 } else if (info->uses_prim_id) {
1038 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1039 } else if (info->gs.vertices_in >= 3) {
1040 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1041 } else {
1042 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1043 }
1044
1045 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
1046 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1047 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
1048 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1049 stage == MESA_SHADER_TESS_CTRL) {
1050 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
1051 } else {
1052 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
1053 }
1054 }
1055
1056 struct radv_shader_variant *
1057 radv_shader_variant_create(struct radv_device *device,
1058 const struct radv_shader_binary *binary,
1059 bool keep_shader_info)
1060 {
1061 struct ac_shader_config config = {0};
1062 struct ac_rtld_binary rtld_binary = {0};
1063 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
1064 if (!variant)
1065 return NULL;
1066
1067 variant->ref_count = 1;
1068
1069 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1070 struct ac_rtld_symbol lds_symbols[2];
1071 unsigned num_lds_symbols = 0;
1072 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
1073 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
1074
1075 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1076 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
1077 !binary->is_gs_copy_shader) {
1078 /* We add this symbol even on LLVM <= 8 to ensure that
1079 * shader->config.lds_size is set correctly below.
1080 */
1081 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1082 sym->name = "esgs_ring";
1083 sym->size = binary->info.ngg_info.esgs_ring_size;
1084 sym->align = 64 * 1024;
1085 }
1086
1087 if (binary->info.is_ngg &&
1088 binary->stage == MESA_SHADER_GEOMETRY) {
1089 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1090 sym->name = "ngg_emit";
1091 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1092 sym->align = 4;
1093 }
1094
1095 struct ac_rtld_open_info open_info = {
1096 .info = &device->physical_device->rad_info,
1097 .shader_type = binary->stage,
1098 .wave_size = binary->info.wave_size,
1099 .num_parts = 1,
1100 .elf_ptrs = &elf_data,
1101 .elf_sizes = &elf_size,
1102 .num_shared_lds_symbols = num_lds_symbols,
1103 .shared_lds_symbols = lds_symbols,
1104 };
1105
1106 if (!ac_rtld_open(&rtld_binary, open_info)) {
1107 free(variant);
1108 return NULL;
1109 }
1110
1111 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1112 &rtld_binary, &config)) {
1113 ac_rtld_close(&rtld_binary);
1114 free(variant);
1115 return NULL;
1116 }
1117
1118 if (rtld_binary.lds_size > 0) {
1119 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1120 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1121 }
1122
1123 variant->code_size = rtld_binary.rx_size;
1124 variant->exec_size = rtld_binary.exec_size;
1125 } else {
1126 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1127 config = ((struct radv_shader_binary_legacy *)binary)->config;
1128 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1129 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1130 }
1131
1132 variant->info = binary->info;
1133 radv_postprocess_config(device, &config, &binary->info,
1134 binary->stage, &variant->config);
1135
1136 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1137 if (!dest_ptr) {
1138 if (binary->type == RADV_BINARY_TYPE_RTLD)
1139 ac_rtld_close(&rtld_binary);
1140 free(variant);
1141 return NULL;
1142 }
1143
1144 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1145 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1146 struct ac_rtld_upload_info info = {
1147 .binary = &rtld_binary,
1148 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1149 .rx_ptr = dest_ptr,
1150 };
1151
1152 if (!ac_rtld_upload(&info)) {
1153 radv_shader_variant_destroy(device, variant);
1154 ac_rtld_close(&rtld_binary);
1155 return NULL;
1156 }
1157
1158 if (keep_shader_info ||
1159 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1160 const char *disasm_data;
1161 size_t disasm_size;
1162 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1163 radv_shader_variant_destroy(device, variant);
1164 ac_rtld_close(&rtld_binary);
1165 return NULL;
1166 }
1167
1168 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1169 variant->disasm_string = malloc(disasm_size + 1);
1170 memcpy(variant->disasm_string, disasm_data, disasm_size);
1171 variant->disasm_string[disasm_size] = 0;
1172 }
1173
1174 ac_rtld_close(&rtld_binary);
1175 } else {
1176 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1177 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1178
1179 /* Add end-of-code markers for the UMR disassembler. */
1180 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1181 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1182 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1183
1184 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1185 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1186
1187 if (bin->stats_size) {
1188 variant->statistics = calloc(bin->stats_size, 1);
1189 memcpy(variant->statistics, bin->data, bin->stats_size);
1190 }
1191 }
1192 return variant;
1193 }
1194
1195 static char *
1196 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1197 int shader_count)
1198 {
1199 char *data = NULL;
1200 char *ret = NULL;
1201 size_t size = 0;
1202 FILE *f = open_memstream(&data, &size);
1203 if (f) {
1204 for (int i = 0; i < shader_count; ++i)
1205 nir_print_shader(shaders[i], f);
1206 fclose(f);
1207 }
1208
1209 ret = malloc(size + 1);
1210 if (ret) {
1211 memcpy(ret, data, size);
1212 ret[size] = 0;
1213 }
1214 free(data);
1215 return ret;
1216 }
1217
1218 static struct radv_shader_variant *
1219 shader_variant_compile(struct radv_device *device,
1220 struct radv_shader_module *module,
1221 struct nir_shader * const *shaders,
1222 int shader_count,
1223 gl_shader_stage stage,
1224 struct radv_shader_info *info,
1225 struct radv_nir_compiler_options *options,
1226 bool gs_copy_shader,
1227 bool trap_handler_shader,
1228 bool keep_shader_info,
1229 bool keep_statistic_info,
1230 struct radv_shader_binary **binary_out)
1231 {
1232 enum radeon_family chip_family = device->physical_device->rad_info.family;
1233 struct radv_shader_binary *binary = NULL;
1234
1235 struct radv_shader_debug_data debug_data = {
1236 .device = device,
1237 .module = module,
1238 };
1239
1240 options->family = chip_family;
1241 options->chip_class = device->physical_device->rad_info.chip_class;
1242 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1243 options->dump_preoptir = options->dump_shader &&
1244 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1245 options->record_ir = keep_shader_info;
1246 options->record_stats = keep_statistic_info;
1247 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1248 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1249 options->address32_hi = device->physical_device->rad_info.address32_hi;
1250 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1251 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1252 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1253 options->debug.func = radv_compiler_debug;
1254 options->debug.private_data = &debug_data;
1255
1256 struct radv_shader_args args = {};
1257 args.options = options;
1258 args.shader_info = info;
1259 args.is_gs_copy_shader = gs_copy_shader;
1260 args.is_trap_handler_shader = trap_handler_shader;
1261
1262 radv_declare_shader_args(&args,
1263 gs_copy_shader ? MESA_SHADER_VERTEX
1264 : shaders[shader_count - 1]->info.stage,
1265 shader_count >= 2,
1266 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1267 : MESA_SHADER_VERTEX);
1268
1269 if (radv_use_llvm_for_stage(device, stage) ||
1270 options->dump_shader || options->record_ir)
1271 ac_init_llvm_once();
1272
1273 if (radv_use_llvm_for_stage(device, stage)) {
1274 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1275 } else {
1276 aco_compile_shader(shader_count, shaders, &binary, &args);
1277 }
1278
1279 binary->info = *info;
1280
1281 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1282 keep_shader_info);
1283 if (!variant) {
1284 free(binary);
1285 return NULL;
1286 }
1287
1288 if (options->dump_shader) {
1289 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1290 for (int i = 1; i < shader_count; ++i)
1291 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1292
1293 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1294 }
1295
1296
1297 if (keep_shader_info) {
1298 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1299 if (!gs_copy_shader && !trap_handler_shader && !module->nir) {
1300 variant->spirv = malloc(module->size);
1301 if (!variant->spirv) {
1302 free(variant);
1303 free(binary);
1304 return NULL;
1305 }
1306
1307 memcpy(variant->spirv, module->data, module->size);
1308 variant->spirv_size = module->size;
1309 }
1310 }
1311
1312 if (binary_out)
1313 *binary_out = binary;
1314 else
1315 free(binary);
1316
1317 return variant;
1318 }
1319
1320 struct radv_shader_variant *
1321 radv_shader_variant_compile(struct radv_device *device,
1322 struct radv_shader_module *module,
1323 struct nir_shader *const *shaders,
1324 int shader_count,
1325 struct radv_pipeline_layout *layout,
1326 const struct radv_shader_variant_key *key,
1327 struct radv_shader_info *info,
1328 bool keep_shader_info, bool keep_statistic_info,
1329 struct radv_shader_binary **binary_out)
1330 {
1331 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
1332 struct radv_nir_compiler_options options = {0};
1333
1334 options.layout = layout;
1335 if (key)
1336 options.key = *key;
1337
1338 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1339 options.robust_buffer_access = device->robust_buffer_access;
1340
1341 return shader_variant_compile(device, module, shaders, shader_count, stage, info,
1342 &options, false, false,
1343 keep_shader_info, keep_statistic_info, binary_out);
1344 }
1345
1346 struct radv_shader_variant *
1347 radv_create_gs_copy_shader(struct radv_device *device,
1348 struct nir_shader *shader,
1349 struct radv_shader_info *info,
1350 struct radv_shader_binary **binary_out,
1351 bool keep_shader_info, bool keep_statistic_info,
1352 bool multiview)
1353 {
1354 struct radv_nir_compiler_options options = {0};
1355 gl_shader_stage stage = MESA_SHADER_VERTEX;
1356
1357 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1358 options.key.has_multiview_view_index = multiview;
1359
1360 return shader_variant_compile(device, NULL, &shader, 1, stage,
1361 info, &options, true, false,
1362 keep_shader_info, keep_statistic_info, binary_out);
1363 }
1364
1365 struct radv_shader_variant *
1366 radv_create_trap_handler_shader(struct radv_device *device)
1367 {
1368 struct radv_nir_compiler_options options = {0};
1369 struct radv_shader_variant *shader = NULL;
1370 struct radv_shader_binary *binary = NULL;
1371 struct radv_shader_info info = {0};
1372
1373 nir_builder b;
1374 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1375 b.shader->info.name = ralloc_strdup(b.shader, "meta_trap_handler");
1376
1377 options.explicit_scratch_args = true;
1378 info.wave_size = 64;
1379
1380 shader = shader_variant_compile(device, NULL, &b.shader, 1,
1381 MESA_SHADER_COMPUTE, &info, &options,
1382 false, true, true, false, &binary);
1383
1384 ralloc_free(b.shader);
1385 free(binary);
1386
1387 return shader;
1388 }
1389
1390 void
1391 radv_shader_variant_destroy(struct radv_device *device,
1392 struct radv_shader_variant *variant)
1393 {
1394 if (!p_atomic_dec_zero(&variant->ref_count))
1395 return;
1396
1397 mtx_lock(&device->shader_slab_mutex);
1398 list_del(&variant->slab_list);
1399 mtx_unlock(&device->shader_slab_mutex);
1400
1401 free(variant->spirv);
1402 free(variant->nir_string);
1403 free(variant->disasm_string);
1404 free(variant->ir_string);
1405 free(variant->statistics);
1406 free(variant);
1407 }
1408
1409 const char *
1410 radv_get_shader_name(struct radv_shader_info *info,
1411 gl_shader_stage stage)
1412 {
1413 switch (stage) {
1414 case MESA_SHADER_VERTEX:
1415 if (info->vs.as_ls)
1416 return "Vertex Shader as LS";
1417 else if (info->vs.as_es)
1418 return "Vertex Shader as ES";
1419 else if (info->is_ngg)
1420 return "Vertex Shader as ESGS";
1421 else
1422 return "Vertex Shader as VS";
1423 case MESA_SHADER_TESS_CTRL:
1424 return "Tessellation Control Shader";
1425 case MESA_SHADER_TESS_EVAL:
1426 if (info->tes.as_es)
1427 return "Tessellation Evaluation Shader as ES";
1428 else if (info->is_ngg)
1429 return "Tessellation Evaluation Shader as ESGS";
1430 else
1431 return "Tessellation Evaluation Shader as VS";
1432 case MESA_SHADER_GEOMETRY:
1433 return "Geometry Shader";
1434 case MESA_SHADER_FRAGMENT:
1435 return "Pixel Shader";
1436 case MESA_SHADER_COMPUTE:
1437 return "Compute Shader";
1438 default:
1439 return "Unknown shader";
1440 };
1441 }
1442
1443 unsigned
1444 radv_get_max_workgroup_size(enum chip_class chip_class,
1445 gl_shader_stage stage,
1446 const unsigned *sizes)
1447 {
1448 switch (stage) {
1449 case MESA_SHADER_TESS_CTRL:
1450 return chip_class >= GFX7 ? 128 : 64;
1451 case MESA_SHADER_GEOMETRY:
1452 return chip_class >= GFX9 ? 128 : 64;
1453 case MESA_SHADER_COMPUTE:
1454 break;
1455 default:
1456 return 0;
1457 }
1458
1459 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1460 return max_workgroup_size;
1461 }
1462
1463 unsigned
1464 radv_get_max_waves(struct radv_device *device,
1465 struct radv_shader_variant *variant,
1466 gl_shader_stage stage)
1467 {
1468 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1469 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1470 uint8_t wave_size = variant->info.wave_size;
1471 struct ac_shader_config *conf = &variant->config;
1472 unsigned max_simd_waves;
1473 unsigned lds_per_wave = 0;
1474
1475 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1476
1477 if (stage == MESA_SHADER_FRAGMENT) {
1478 lds_per_wave = conf->lds_size * lds_increment +
1479 align(variant->info.ps.num_interp * 48,
1480 lds_increment);
1481 } else if (stage == MESA_SHADER_COMPUTE) {
1482 unsigned max_workgroup_size =
1483 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1484 lds_per_wave = (conf->lds_size * lds_increment) /
1485 DIV_ROUND_UP(max_workgroup_size, wave_size);
1486 }
1487
1488 if (conf->num_sgprs) {
1489 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1490 max_simd_waves =
1491 MIN2(max_simd_waves,
1492 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1493 sgprs);
1494 }
1495
1496 if (conf->num_vgprs) {
1497 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1498 max_simd_waves =
1499 MIN2(max_simd_waves,
1500 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1501 }
1502
1503 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1504 if (lds_per_wave)
1505 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1506
1507 return max_simd_waves;
1508 }
1509
1510 static void
1511 generate_shader_stats(struct radv_device *device,
1512 struct radv_shader_variant *variant,
1513 gl_shader_stage stage,
1514 struct _mesa_string_buffer *buf)
1515 {
1516 struct ac_shader_config *conf = &variant->config;
1517 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1518
1519 if (stage == MESA_SHADER_FRAGMENT) {
1520 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1521 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1522 "SPI_PS_INPUT_ENA = 0x%04x\n",
1523 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1524 }
1525
1526 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1527 "SGPRS: %d\n"
1528 "VGPRS: %d\n"
1529 "Spilled SGPRs: %d\n"
1530 "Spilled VGPRs: %d\n"
1531 "PrivMem VGPRS: %d\n"
1532 "Code Size: %d bytes\n"
1533 "LDS: %d blocks\n"
1534 "Scratch: %d bytes per wave\n"
1535 "Max Waves: %d\n",
1536 conf->num_sgprs, conf->num_vgprs,
1537 conf->spilled_sgprs, conf->spilled_vgprs,
1538 variant->info.private_mem_vgprs, variant->exec_size,
1539 conf->lds_size, conf->scratch_bytes_per_wave,
1540 max_simd_waves);
1541
1542 if (variant->statistics) {
1543 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1544 for (unsigned i = 0; i < variant->statistics->count; i++) {
1545 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1546 uint32_t value = variant->statistics->values[i];
1547 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1548 }
1549 }
1550
1551 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1552 }
1553
1554 void
1555 radv_shader_dump_stats(struct radv_device *device,
1556 struct radv_shader_variant *variant,
1557 gl_shader_stage stage,
1558 FILE *file)
1559 {
1560 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1561
1562 generate_shader_stats(device, variant, stage, buf);
1563
1564 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1565 fprintf(file, "%s", buf->buf);
1566
1567 _mesa_string_buffer_destroy(buf);
1568 }
1569
1570 VkResult
1571 radv_GetShaderInfoAMD(VkDevice _device,
1572 VkPipeline _pipeline,
1573 VkShaderStageFlagBits shaderStage,
1574 VkShaderInfoTypeAMD infoType,
1575 size_t* pInfoSize,
1576 void* pInfo)
1577 {
1578 RADV_FROM_HANDLE(radv_device, device, _device);
1579 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1580 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1581 struct radv_shader_variant *variant = pipeline->shaders[stage];
1582 struct _mesa_string_buffer *buf;
1583 VkResult result = VK_SUCCESS;
1584
1585 /* Spec doesn't indicate what to do if the stage is invalid, so just
1586 * return no info for this. */
1587 if (!variant)
1588 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1589
1590 switch (infoType) {
1591 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1592 if (!pInfo) {
1593 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1594 } else {
1595 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1596 struct ac_shader_config *conf = &variant->config;
1597
1598 VkShaderStatisticsInfoAMD statistics = {};
1599 statistics.shaderStageMask = shaderStage;
1600 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1601 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1602 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1603
1604 if (stage == MESA_SHADER_COMPUTE) {
1605 unsigned *local_size = variant->info.cs.block_size;
1606 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1607
1608 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1609 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1610
1611 statistics.computeWorkGroupSize[0] = local_size[0];
1612 statistics.computeWorkGroupSize[1] = local_size[1];
1613 statistics.computeWorkGroupSize[2] = local_size[2];
1614 } else {
1615 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1616 }
1617
1618 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1619 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1620 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1621 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1622 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1623
1624 size_t size = *pInfoSize;
1625 *pInfoSize = sizeof(statistics);
1626
1627 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1628
1629 if (size < *pInfoSize)
1630 result = VK_INCOMPLETE;
1631 }
1632
1633 break;
1634 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1635 buf = _mesa_string_buffer_create(NULL, 1024);
1636
1637 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1638 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1639 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1640 generate_shader_stats(device, variant, stage, buf);
1641
1642 /* Need to include the null terminator. */
1643 size_t length = buf->length + 1;
1644
1645 if (!pInfo) {
1646 *pInfoSize = length;
1647 } else {
1648 size_t size = *pInfoSize;
1649 *pInfoSize = length;
1650
1651 memcpy(pInfo, buf->buf, MIN2(size, length));
1652
1653 if (size < length)
1654 result = VK_INCOMPLETE;
1655 }
1656
1657 _mesa_string_buffer_destroy(buf);
1658 break;
1659 default:
1660 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1661 result = VK_ERROR_FEATURE_NOT_PRESENT;
1662 break;
1663 }
1664
1665 return result;
1666 }