projects / mesa.git / blob
? search:


81680e548b56c9e38ee64bb1d84c244bef5a0dee
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 if (shader->options->max_unroll_iterations) {
282 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
283 }
284 } while (progress && !optimize_conservatively);
285
286 NIR_PASS(progress, shader, nir_opt_conditional_discard);
287 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 nir_shader *
303 radv_shader_compile_to_nir(struct radv_device *device,
304 struct radv_shader_module *module,
305 const char *entrypoint_name,
306 gl_shader_stage stage,
307 const VkSpecializationInfo *spec_info,
308 const VkPipelineCreateFlags flags,
309 const struct radv_pipeline_layout *layout,
310 unsigned subgroup_size, unsigned ballot_bit_size)
311 {
312 nir_shader *nir;
313 const nir_shader_compiler_options *nir_options =
314 radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco;
315
316 if (module->nir) {
317 /* Some things such as our meta clear/blit code will give us a NIR
318 * shader directly. In that case, we just ignore the SPIR-V entirely
319 * and just use the NIR shader */
320 nir = module->nir;
321 nir->options = nir_options;
322 nir_validate_shader(nir, "in internal shader");
323
324 assert(exec_list_length(&nir->functions) == 1);
325 } else {
326 uint32_t *spirv = (uint32_t *) module->data;
327 assert(module->size % 4 == 0);
328
329 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
330 radv_print_spirv(module->data, module->size, stderr);
331
332 uint32_t num_spec_entries = 0;
333 struct nir_spirv_specialization *spec_entries = NULL;
334 if (spec_info && spec_info->mapEntryCount > 0) {
335 num_spec_entries = spec_info->mapEntryCount;
336 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
337 for (uint32_t i = 0; i < num_spec_entries; i++) {
338 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
339 const void *data = spec_info->pData + entry.offset;
340 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
341
342 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
343 switch (entry.size) {
344 case 8:
345 spec_entries[i].value.u64 = *(const uint64_t *)data;
346 break;
347 case 4:
348 spec_entries[i].value.u32 = *(const uint32_t *)data;
349 break;
350 case 2:
351 spec_entries[i].value.u16 = *(const uint16_t *)data;
352 break;
353 case 1:
354 spec_entries[i].value.u8 = *(const uint8_t *)data;
355 break;
356 default:
357 assert(!"Invalid spec constant size");
358 break;
359 }
360 }
361 }
362 const struct spirv_to_nir_options spirv_options = {
363 .lower_ubo_ssbo_access_to_offsets = true,
364 .caps = {
365 .amd_fragment_mask = true,
366 .amd_gcn_shader = true,
367 .amd_image_gather_bias_lod = true,
368 .amd_image_read_write_lod = true,
369 .amd_shader_ballot = true,
370 .amd_shader_explicit_vertex_parameter = true,
371 .amd_trinary_minmax = true,
372 .demote_to_helper_invocation = true,
373 .derivative_group = true,
374 .descriptor_array_dynamic_indexing = true,
375 .descriptor_array_non_uniform_indexing = true,
376 .descriptor_indexing = true,
377 .device_group = true,
378 .draw_parameters = true,
379 .float_controls = true,
380 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
381 .float32_atomic_add = true,
382 .float64 = true,
383 .geometry_streams = true,
384 .image_ms_array = true,
385 .image_read_without_format = true,
386 .image_write_without_format = true,
387 .int8 = true,
388 .int16 = true,
389 .int64 = true,
390 .int64_atomics = true,
391 .min_lod = true,
392 .multiview = true,
393 .physical_storage_buffer_address = true,
394 .post_depth_coverage = true,
395 .runtime_descriptor_array = true,
396 .shader_clock = true,
397 .shader_viewport_index_layer = true,
398 .stencil_export = true,
399 .storage_8bit = true,
400 .storage_16bit = true,
401 .storage_image_ms = true,
402 .subgroup_arithmetic = true,
403 .subgroup_ballot = true,
404 .subgroup_basic = true,
405 .subgroup_quad = true,
406 .subgroup_shuffle = true,
407 .subgroup_vote = true,
408 .tessellation = true,
409 .transform_feedback = true,
410 .variable_pointers = true,
411 .vk_memory_model = true,
412 .vk_memory_model_device_scope = true,
413 },
414 .ubo_addr_format = nir_address_format_32bit_index_offset,
415 .ssbo_addr_format = nir_address_format_32bit_index_offset,
416 .phys_ssbo_addr_format = nir_address_format_64bit_global,
417 .push_const_addr_format = nir_address_format_logical,
418 .shared_addr_format = nir_address_format_32bit_offset,
419 .frag_coord_is_sysval = true,
420 };
421 nir = spirv_to_nir(spirv, module->size / 4,
422 spec_entries, num_spec_entries,
423 stage, entrypoint_name,
424 &spirv_options, nir_options);
425 assert(nir->info.stage == stage);
426 nir_validate_shader(nir, "after spirv_to_nir");
427
428 free(spec_entries);
429
430 /* We have to lower away local constant initializers right before we
431 * inline functions. That way they get properly initialized at the top
432 * of the function and not at the top of its caller.
433 */
434 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
435 NIR_PASS_V(nir, nir_lower_returns);
436 NIR_PASS_V(nir, nir_inline_functions);
437 NIR_PASS_V(nir, nir_copy_prop);
438 NIR_PASS_V(nir, nir_opt_deref);
439
440 /* Pick off the single entrypoint that we want */
441 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
442 if (func->is_entrypoint)
443 func->name = ralloc_strdup(func, "main");
444 else
445 exec_node_remove(&func->node);
446 }
447 assert(exec_list_length(&nir->functions) == 1);
448
449 /* Make sure we lower constant initializers on output variables so that
450 * nir_remove_dead_variables below sees the corresponding stores
451 */
452 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
453
454 /* Now that we've deleted all but the main function, we can go ahead and
455 * lower the rest of the constant initializers.
456 */
457 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
458
459 /* Split member structs. We do this before lower_io_to_temporaries so that
460 * it doesn't lower system values to temporaries by accident.
461 */
462 NIR_PASS_V(nir, nir_split_var_copies);
463 NIR_PASS_V(nir, nir_split_per_member_structs);
464
465 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
466 !radv_use_llvm_for_stage(device, nir->info.stage))
467 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
468 if (nir->info.stage == MESA_SHADER_FRAGMENT)
469 NIR_PASS_V(nir, nir_lower_input_attachments, true);
470
471 NIR_PASS_V(nir, nir_remove_dead_variables,
472 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
473 NULL);
474
475 NIR_PASS_V(nir, nir_propagate_invariant);
476
477 NIR_PASS_V(nir, nir_lower_system_values);
478 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
479
480 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
481 NIR_PASS_V(nir, nir_lower_discard_to_demote);
482
483 nir_lower_doubles_options lower_doubles =
484 nir->options->lower_doubles_options;
485
486 if (device->physical_device->rad_info.chip_class == GFX6) {
487 /* GFX6 doesn't support v_floor_f64 and the precision
488 * of v_fract_f64 which is used to implement 64-bit
489 * floor is less than what Vulkan requires.
490 */
491 lower_doubles |= nir_lower_dfloor;
492 }
493
494 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
495 }
496
497 /* Vulkan uses the separate-shader linking model */
498 nir->info.separate_shader = true;
499
500 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
501
502 if (nir->info.stage == MESA_SHADER_GEOMETRY)
503 nir_lower_gs_intrinsics(nir, true);
504
505 static const nir_lower_tex_options tex_options = {
506 .lower_txp = ~0,
507 .lower_tg4_offsets = true,
508 };
509
510 nir_lower_tex(nir, &tex_options);
511
512 nir_lower_vars_to_ssa(nir);
513
514 if (nir->info.stage == MESA_SHADER_VERTEX ||
515 nir->info.stage == MESA_SHADER_GEOMETRY ||
516 nir->info.stage == MESA_SHADER_FRAGMENT) {
517 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
518 nir_shader_get_entrypoint(nir), true, true);
519 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
520 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
521 nir_shader_get_entrypoint(nir), true, false);
522 }
523
524 nir_split_var_copies(nir);
525
526 nir_lower_global_vars_to_local(nir);
527 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
528 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
529 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
530 .subgroup_size = subgroup_size,
531 .ballot_bit_size = ballot_bit_size,
532 .lower_to_scalar = 1,
533 .lower_subgroup_masks = 1,
534 .lower_shuffle = 1,
535 .lower_shuffle_to_32bit = 1,
536 .lower_vote_eq_to_ballot = 1,
537 .lower_quad_broadcast_dynamic = 1,
538 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
539 .lower_shuffle_to_swizzle_amd = 1,
540 });
541
542 nir_lower_load_const_to_scalar(nir);
543
544 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
545 radv_optimize_nir(nir, false, true);
546
547 /* call radv_nir_lower_ycbcr_textures() late as there might still be
548 * tex with undef texture/sampler before first optimization */
549 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
550
551 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
552 * to remove any copies introduced by nir_opt_find_array_copies().
553 */
554 nir_lower_var_copies(nir);
555
556 /* Lower deref operations for compute shared memory. */
557 if (nir->info.stage == MESA_SHADER_COMPUTE) {
558 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
559 nir_var_mem_shared, shared_var_info);
560 NIR_PASS_V(nir, nir_lower_explicit_io,
561 nir_var_mem_shared, nir_address_format_32bit_offset);
562 }
563
564 /* Lower large variables that are always constant with load_constant
565 * intrinsics, which get turned into PC-relative loads from a data
566 * section next to the shader.
567 */
568 NIR_PASS_V(nir, nir_opt_large_constants,
569 glsl_get_natural_size_align_bytes, 16);
570
571 /* Indirect lowering must be called after the radv_optimize_nir() loop
572 * has been called at least once. Otherwise indirect lowering can
573 * bloat the instruction count of the loop and cause it to be
574 * considered too large for unrolling.
575 */
576 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
577 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
578
579 return nir;
580 }
581
582 static int
583 type_size_vec4(const struct glsl_type *type, bool bindless)
584 {
585 return glsl_count_attribute_slots(type, false);
586 }
587
588 static nir_variable *
589 find_layer_in_var(nir_shader *nir)
590 {
591 nir_variable *var =
592 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
593 if (var != NULL)
594 return var;
595
596 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
597 var->data.location = VARYING_SLOT_LAYER;
598 var->data.interpolation = INTERP_MODE_FLAT;
599 return var;
600 }
601
602 /* We use layered rendering to implement multiview, which means we need to map
603 * view_index to gl_Layer. The attachment lowering also uses needs to know the
604 * layer so that it can sample from the correct layer. The code generates a
605 * load from the layer_id sysval, but since we don't have a way to get at this
606 * information from the fragment shader, we also need to lower this to the
607 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
608 * slot, before lowering io, so that nir_assign_var_locations() will give the
609 * LAYER varying the correct driver_location.
610 */
611
612 static bool
613 lower_view_index(nir_shader *nir)
614 {
615 bool progress = false;
616 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
617 nir_builder b;
618 nir_builder_init(&b, entry);
619
620 nir_variable *layer = NULL;
621 nir_foreach_block(block, entry) {
622 nir_foreach_instr_safe(instr, block) {
623 if (instr->type != nir_instr_type_intrinsic)
624 continue;
625
626 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
627 if (load->intrinsic != nir_intrinsic_load_view_index &&
628 load->intrinsic != nir_intrinsic_load_layer_id)
629 continue;
630
631 if (!layer)
632 layer = find_layer_in_var(nir);
633
634 b.cursor = nir_before_instr(instr);
635 nir_ssa_def *def = nir_load_var(&b, layer);
636 nir_ssa_def_rewrite_uses(&load->dest.ssa,
637 nir_src_for_ssa(def));
638
639 nir_instr_remove(instr);
640 progress = true;
641 }
642 }
643
644 return progress;
645 }
646
647 void
648 radv_lower_fs_io(nir_shader *nir)
649 {
650 NIR_PASS_V(nir, lower_view_index);
651 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
652 MESA_SHADER_FRAGMENT);
653
654 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
655
656 /* This pass needs actual constants */
657 nir_opt_constant_folding(nir);
658
659 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
660 }
661
662
663 static void *
664 radv_alloc_shader_memory(struct radv_device *device,
665 struct radv_shader_variant *shader)
666 {
667 mtx_lock(&device->shader_slab_mutex);
668 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
669 uint64_t offset = 0;
670 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
671 if (s->bo_offset - offset >= shader->code_size) {
672 shader->bo = slab->bo;
673 shader->bo_offset = offset;
674 list_addtail(&shader->slab_list, &s->slab_list);
675 mtx_unlock(&device->shader_slab_mutex);
676 return slab->ptr + offset;
677 }
678 offset = align_u64(s->bo_offset + s->code_size, 256);
679 }
680 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
681 shader->bo = slab->bo;
682 shader->bo_offset = offset;
683 list_addtail(&shader->slab_list, &slab->shaders);
684 mtx_unlock(&device->shader_slab_mutex);
685 return slab->ptr + offset;
686 }
687 }
688
689 mtx_unlock(&device->shader_slab_mutex);
690 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
691
692 slab->size = MAX2(256 * 1024, shader->code_size);
693 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
694 RADEON_DOMAIN_VRAM,
695 RADEON_FLAG_NO_INTERPROCESS_SHARING |
696 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
697 0 : RADEON_FLAG_READ_ONLY),
698 RADV_BO_PRIORITY_SHADER);
699 if (!slab->bo) {
700 free(slab);
701 return NULL;
702 }
703
704 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
705 if (!slab->ptr) {
706 device->ws->buffer_destroy(slab->bo);
707 free(slab);
708 return NULL;
709 }
710
711 list_inithead(&slab->shaders);
712
713 mtx_lock(&device->shader_slab_mutex);
714 list_add(&slab->slabs, &device->shader_slabs);
715
716 shader->bo = slab->bo;
717 shader->bo_offset = 0;
718 list_add(&shader->slab_list, &slab->shaders);
719 mtx_unlock(&device->shader_slab_mutex);
720 return slab->ptr;
721 }
722
723 void
724 radv_destroy_shader_slabs(struct radv_device *device)
725 {
726 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
727 device->ws->buffer_destroy(slab->bo);
728 free(slab);
729 }
730 mtx_destroy(&device->shader_slab_mutex);
731 }
732
733 /* For the UMR disassembler. */
734 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
735 #define DEBUGGER_NUM_MARKERS 5
736
737 static unsigned
738 radv_get_shader_binary_size(size_t code_size)
739 {
740 return code_size + DEBUGGER_NUM_MARKERS * 4;
741 }
742
743 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
744 const struct ac_shader_config *config_in,
745 const struct radv_shader_info *info,
746 gl_shader_stage stage,
747 struct ac_shader_config *config_out)
748 {
749 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
750 unsigned vgpr_comp_cnt = 0;
751 unsigned num_input_vgprs = info->num_input_vgprs;
752
753 if (stage == MESA_SHADER_FRAGMENT) {
754 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
755 }
756
757 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
758 /* +3 for scratch wave offset and VCC */
759 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
760 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
761 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
762 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
763 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
764 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
765
766 *config_out = *config_in;
767 config_out->num_vgprs = num_vgprs;
768 config_out->num_sgprs = num_sgprs;
769 config_out->num_shared_vgprs = num_shared_vgprs;
770
771 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
772 S_00B12C_SCRATCH_EN(scratch_enabled);
773
774 if (!pdevice->use_ngg_streamout) {
775 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
776 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
777 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
778 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
779 S_00B12C_SO_EN(!!info->so.num_outputs);
780 }
781
782 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
783 (info->wave_size == 32 ? 8 : 4)) |
784 S_00B848_DX10_CLAMP(1) |
785 S_00B848_FLOAT_MODE(config_out->float_mode);
786
787 if (pdevice->rad_info.chip_class >= GFX10) {
788 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
789 } else {
790 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
791 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
792 }
793
794 switch (stage) {
795 case MESA_SHADER_TESS_EVAL:
796 if (info->is_ngg) {
797 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
798 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
799 } else if (info->tes.as_es) {
800 assert(pdevice->rad_info.chip_class <= GFX8);
801 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
802
803 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
804 } else {
805 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
806 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
807
808 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
809 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
810 }
811 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
812 break;
813 case MESA_SHADER_TESS_CTRL:
814 if (pdevice->rad_info.chip_class >= GFX9) {
815 /* We need at least 2 components for LS.
816 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
817 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
818 */
819 if (pdevice->rad_info.chip_class >= GFX10) {
820 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
821 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
822 } else {
823 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
824 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
825 }
826 } else {
827 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
828 }
829 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
830 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
831 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
832 break;
833 case MESA_SHADER_VERTEX:
834 if (info->is_ngg) {
835 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
836 } else if (info->vs.as_ls) {
837 assert(pdevice->rad_info.chip_class <= GFX8);
838 /* We need at least 2 components for LS.
839 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
840 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
841 */
842 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
843 } else if (info->vs.as_es) {
844 assert(pdevice->rad_info.chip_class <= GFX8);
845 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
846 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
847 } else {
848 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
849 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
850 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
851 */
852 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
853 vgpr_comp_cnt = 3;
854 } else if (info->vs.export_prim_id) {
855 vgpr_comp_cnt = 2;
856 } else if (info->vs.needs_instance_id) {
857 vgpr_comp_cnt = 1;
858 } else {
859 vgpr_comp_cnt = 0;
860 }
861
862 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
863 }
864 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
865 break;
866 case MESA_SHADER_FRAGMENT:
867 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
868 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
869 break;
870 case MESA_SHADER_GEOMETRY:
871 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
872 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
873 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
874 break;
875 case MESA_SHADER_COMPUTE:
876 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
877 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
878 config_out->rsrc2 |=
879 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
880 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
881 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
882 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
883 info->cs.uses_thread_id[1] ? 1 : 0) |
884 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
885 S_00B84C_LDS_SIZE(config_in->lds_size);
886 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
887
888 break;
889 default:
890 unreachable("unsupported shader type");
891 break;
892 }
893
894 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
895 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
896 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
897 gl_shader_stage es_stage = stage;
898 if (stage == MESA_SHADER_GEOMETRY)
899 es_stage = info->gs.es_type;
900
901 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
902 if (es_stage == MESA_SHADER_VERTEX) {
903 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
904 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
905 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
906 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
907 } else
908 unreachable("Unexpected ES shader stage");
909
910 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
911 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
912 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
913 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
914 } else if (info->uses_prim_id) {
915 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
916 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
917 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
918 } else {
919 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
920 }
921
922 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
923 S_00B228_WGP_MODE(1);
924 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
925 S_00B22C_LDS_SIZE(config_in->lds_size) |
926 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
927 } else if (pdevice->rad_info.chip_class >= GFX9 &&
928 stage == MESA_SHADER_GEOMETRY) {
929 unsigned es_type = info->gs.es_type;
930 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
931
932 if (es_type == MESA_SHADER_VERTEX) {
933 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
934 if (info->vs.needs_instance_id) {
935 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
936 } else {
937 es_vgpr_comp_cnt = 0;
938 }
939 } else if (es_type == MESA_SHADER_TESS_EVAL) {
940 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
941 } else {
942 unreachable("invalid shader ES type");
943 }
944
945 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
946 * VGPR[0:4] are always loaded.
947 */
948 if (info->uses_invocation_id) {
949 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
950 } else if (info->uses_prim_id) {
951 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
952 } else if (info->gs.vertices_in >= 3) {
953 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
954 } else {
955 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
956 }
957
958 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
959 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
960 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
961 } else if (pdevice->rad_info.chip_class >= GFX9 &&
962 stage == MESA_SHADER_TESS_CTRL) {
963 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
964 } else {
965 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
966 }
967 }
968
969 struct radv_shader_variant *
970 radv_shader_variant_create(struct radv_device *device,
971 const struct radv_shader_binary *binary,
972 bool keep_shader_info)
973 {
974 struct ac_shader_config config = {0};
975 struct ac_rtld_binary rtld_binary = {0};
976 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
977 if (!variant)
978 return NULL;
979
980 variant->ref_count = 1;
981
982 if (binary->type == RADV_BINARY_TYPE_RTLD) {
983 struct ac_rtld_symbol lds_symbols[2];
984 unsigned num_lds_symbols = 0;
985 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
986 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
987
988 if (device->physical_device->rad_info.chip_class >= GFX9 &&
989 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
990 !binary->is_gs_copy_shader) {
991 /* We add this symbol even on LLVM <= 8 to ensure that
992 * shader->config.lds_size is set correctly below.
993 */
994 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
995 sym->name = "esgs_ring";
996 sym->size = binary->info.ngg_info.esgs_ring_size;
997 sym->align = 64 * 1024;
998 }
999
1000 if (binary->info.is_ngg &&
1001 binary->stage == MESA_SHADER_GEOMETRY) {
1002 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1003 sym->name = "ngg_emit";
1004 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1005 sym->align = 4;
1006 }
1007
1008 struct ac_rtld_open_info open_info = {
1009 .info = &device->physical_device->rad_info,
1010 .shader_type = binary->stage,
1011 .wave_size = binary->info.wave_size,
1012 .num_parts = 1,
1013 .elf_ptrs = &elf_data,
1014 .elf_sizes = &elf_size,
1015 .num_shared_lds_symbols = num_lds_symbols,
1016 .shared_lds_symbols = lds_symbols,
1017 };
1018
1019 if (!ac_rtld_open(&rtld_binary, open_info)) {
1020 free(variant);
1021 return NULL;
1022 }
1023
1024 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1025 &rtld_binary, &config)) {
1026 ac_rtld_close(&rtld_binary);
1027 free(variant);
1028 return NULL;
1029 }
1030
1031 if (rtld_binary.lds_size > 0) {
1032 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1033 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1034 }
1035
1036 variant->code_size = rtld_binary.rx_size;
1037 variant->exec_size = rtld_binary.exec_size;
1038 } else {
1039 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1040 config = ((struct radv_shader_binary_legacy *)binary)->config;
1041 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1042 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1043 }
1044
1045 variant->info = binary->info;
1046 radv_postprocess_config(device->physical_device, &config, &binary->info,
1047 binary->stage, &variant->config);
1048
1049 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1050 if (!dest_ptr) {
1051 if (binary->type == RADV_BINARY_TYPE_RTLD)
1052 ac_rtld_close(&rtld_binary);
1053 free(variant);
1054 return NULL;
1055 }
1056
1057 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1058 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1059 struct ac_rtld_upload_info info = {
1060 .binary = &rtld_binary,
1061 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1062 .rx_ptr = dest_ptr,
1063 };
1064
1065 if (!ac_rtld_upload(&info)) {
1066 radv_shader_variant_destroy(device, variant);
1067 ac_rtld_close(&rtld_binary);
1068 return NULL;
1069 }
1070
1071 if (keep_shader_info ||
1072 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1073 const char *disasm_data;
1074 size_t disasm_size;
1075 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1076 radv_shader_variant_destroy(device, variant);
1077 ac_rtld_close(&rtld_binary);
1078 return NULL;
1079 }
1080
1081 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1082 variant->disasm_string = malloc(disasm_size + 1);
1083 memcpy(variant->disasm_string, disasm_data, disasm_size);
1084 variant->disasm_string[disasm_size] = 0;
1085 }
1086
1087 ac_rtld_close(&rtld_binary);
1088 } else {
1089 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1090 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1091
1092 /* Add end-of-code markers for the UMR disassembler. */
1093 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1094 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1095 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1096
1097 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1098 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1099
1100 if (bin->stats_size) {
1101 variant->statistics = calloc(bin->stats_size, 1);
1102 memcpy(variant->statistics, bin->data, bin->stats_size);
1103 }
1104 }
1105 return variant;
1106 }
1107
1108 static char *
1109 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1110 int shader_count)
1111 {
1112 char *data = NULL;
1113 char *ret = NULL;
1114 size_t size = 0;
1115 FILE *f = open_memstream(&data, &size);
1116 if (f) {
1117 for (int i = 0; i < shader_count; ++i)
1118 nir_print_shader(shaders[i], f);
1119 fclose(f);
1120 }
1121
1122 ret = malloc(size + 1);
1123 if (ret) {
1124 memcpy(ret, data, size);
1125 ret[size] = 0;
1126 }
1127 free(data);
1128 return ret;
1129 }
1130
1131 static struct radv_shader_variant *
1132 shader_variant_compile(struct radv_device *device,
1133 struct radv_shader_module *module,
1134 struct nir_shader * const *shaders,
1135 int shader_count,
1136 gl_shader_stage stage,
1137 struct radv_shader_info *info,
1138 struct radv_nir_compiler_options *options,
1139 bool gs_copy_shader,
1140 bool keep_shader_info,
1141 bool keep_statistic_info,
1142 struct radv_shader_binary **binary_out)
1143 {
1144 enum radeon_family chip_family = device->physical_device->rad_info.family;
1145 struct radv_shader_binary *binary = NULL;
1146
1147 options->family = chip_family;
1148 options->chip_class = device->physical_device->rad_info.chip_class;
1149 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1150 options->dump_preoptir = options->dump_shader &&
1151 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1152 options->record_ir = keep_shader_info;
1153 options->record_stats = keep_statistic_info;
1154 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1155 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1156 options->address32_hi = device->physical_device->rad_info.address32_hi;
1157 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1158 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1159 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1160
1161 struct radv_shader_args args = {};
1162 args.options = options;
1163 args.shader_info = info;
1164 args.is_gs_copy_shader = gs_copy_shader;
1165 radv_declare_shader_args(&args,
1166 gs_copy_shader ? MESA_SHADER_VERTEX
1167 : shaders[shader_count - 1]->info.stage,
1168 shader_count >= 2,
1169 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1170 : MESA_SHADER_VERTEX);
1171
1172 if (radv_use_llvm_for_stage(device, stage) ||
1173 options->dump_shader || options->record_ir)
1174 ac_init_llvm_once();
1175
1176 if (radv_use_llvm_for_stage(device, stage)) {
1177 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1178 } else {
1179 aco_compile_shader(shader_count, shaders, &binary, &args);
1180 }
1181
1182 binary->info = *info;
1183
1184 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1185 keep_shader_info);
1186 if (!variant) {
1187 free(binary);
1188 return NULL;
1189 }
1190
1191 if (options->dump_shader) {
1192 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1193 for (int i = 1; i < shader_count; ++i)
1194 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1195
1196 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1197 }
1198
1199
1200 if (keep_shader_info) {
1201 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1202 if (!gs_copy_shader && !module->nir) {
1203 variant->spirv = malloc(module->size);
1204 if (!variant->spirv) {
1205 free(variant);
1206 free(binary);
1207 return NULL;
1208 }
1209
1210 memcpy(variant->spirv, module->data, module->size);
1211 variant->spirv_size = module->size;
1212 }
1213 }
1214
1215 if (binary_out)
1216 *binary_out = binary;
1217 else
1218 free(binary);
1219
1220 return variant;
1221 }
1222
1223 struct radv_shader_variant *
1224 radv_shader_variant_compile(struct radv_device *device,
1225 struct radv_shader_module *module,
1226 struct nir_shader *const *shaders,
1227 int shader_count,
1228 struct radv_pipeline_layout *layout,
1229 const struct radv_shader_variant_key *key,
1230 struct radv_shader_info *info,
1231 bool keep_shader_info, bool keep_statistic_info,
1232 struct radv_shader_binary **binary_out)
1233 {
1234 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
1235 struct radv_nir_compiler_options options = {0};
1236
1237 options.layout = layout;
1238 if (key)
1239 options.key = *key;
1240
1241 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1242 options.robust_buffer_access = device->robust_buffer_access;
1243
1244 return shader_variant_compile(device, module, shaders, shader_count, stage, info,
1245 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1246 }
1247
1248 struct radv_shader_variant *
1249 radv_create_gs_copy_shader(struct radv_device *device,
1250 struct nir_shader *shader,
1251 struct radv_shader_info *info,
1252 struct radv_shader_binary **binary_out,
1253 bool keep_shader_info, bool keep_statistic_info,
1254 bool multiview)
1255 {
1256 struct radv_nir_compiler_options options = {0};
1257 gl_shader_stage stage = MESA_SHADER_VERTEX;
1258
1259 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1260 options.key.has_multiview_view_index = multiview;
1261
1262 return shader_variant_compile(device, NULL, &shader, 1, stage,
1263 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1264 }
1265
1266 void
1267 radv_shader_variant_destroy(struct radv_device *device,
1268 struct radv_shader_variant *variant)
1269 {
1270 if (!p_atomic_dec_zero(&variant->ref_count))
1271 return;
1272
1273 mtx_lock(&device->shader_slab_mutex);
1274 list_del(&variant->slab_list);
1275 mtx_unlock(&device->shader_slab_mutex);
1276
1277 free(variant->spirv);
1278 free(variant->nir_string);
1279 free(variant->disasm_string);
1280 free(variant->ir_string);
1281 free(variant->statistics);
1282 free(variant);
1283 }
1284
1285 const char *
1286 radv_get_shader_name(struct radv_shader_info *info,
1287 gl_shader_stage stage)
1288 {
1289 switch (stage) {
1290 case MESA_SHADER_VERTEX:
1291 if (info->vs.as_ls)
1292 return "Vertex Shader as LS";
1293 else if (info->vs.as_es)
1294 return "Vertex Shader as ES";
1295 else if (info->is_ngg)
1296 return "Vertex Shader as ESGS";
1297 else
1298 return "Vertex Shader as VS";
1299 case MESA_SHADER_TESS_CTRL:
1300 return "Tessellation Control Shader";
1301 case MESA_SHADER_TESS_EVAL:
1302 if (info->tes.as_es)
1303 return "Tessellation Evaluation Shader as ES";
1304 else if (info->is_ngg)
1305 return "Tessellation Evaluation Shader as ESGS";
1306 else
1307 return "Tessellation Evaluation Shader as VS";
1308 case MESA_SHADER_GEOMETRY:
1309 return "Geometry Shader";
1310 case MESA_SHADER_FRAGMENT:
1311 return "Pixel Shader";
1312 case MESA_SHADER_COMPUTE:
1313 return "Compute Shader";
1314 default:
1315 return "Unknown shader";
1316 };
1317 }
1318
1319 unsigned
1320 radv_get_max_workgroup_size(enum chip_class chip_class,
1321 gl_shader_stage stage,
1322 const unsigned *sizes)
1323 {
1324 switch (stage) {
1325 case MESA_SHADER_TESS_CTRL:
1326 return chip_class >= GFX7 ? 128 : 64;
1327 case MESA_SHADER_GEOMETRY:
1328 return chip_class >= GFX9 ? 128 : 64;
1329 case MESA_SHADER_COMPUTE:
1330 break;
1331 default:
1332 return 0;
1333 }
1334
1335 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1336 return max_workgroup_size;
1337 }
1338
1339 unsigned
1340 radv_get_max_waves(struct radv_device *device,
1341 struct radv_shader_variant *variant,
1342 gl_shader_stage stage)
1343 {
1344 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1345 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1346 uint8_t wave_size = variant->info.wave_size;
1347 struct ac_shader_config *conf = &variant->config;
1348 unsigned max_simd_waves;
1349 unsigned lds_per_wave = 0;
1350
1351 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1352
1353 if (stage == MESA_SHADER_FRAGMENT) {
1354 lds_per_wave = conf->lds_size * lds_increment +
1355 align(variant->info.ps.num_interp * 48,
1356 lds_increment);
1357 } else if (stage == MESA_SHADER_COMPUTE) {
1358 unsigned max_workgroup_size =
1359 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1360 lds_per_wave = (conf->lds_size * lds_increment) /
1361 DIV_ROUND_UP(max_workgroup_size, wave_size);
1362 }
1363
1364 if (conf->num_sgprs) {
1365 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1366 max_simd_waves =
1367 MIN2(max_simd_waves,
1368 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1369 sgprs);
1370 }
1371
1372 if (conf->num_vgprs) {
1373 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1374 max_simd_waves =
1375 MIN2(max_simd_waves,
1376 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1377 }
1378
1379 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1380 if (lds_per_wave)
1381 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1382
1383 return max_simd_waves;
1384 }
1385
1386 static void
1387 generate_shader_stats(struct radv_device *device,
1388 struct radv_shader_variant *variant,
1389 gl_shader_stage stage,
1390 struct _mesa_string_buffer *buf)
1391 {
1392 struct ac_shader_config *conf = &variant->config;
1393 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1394
1395 if (stage == MESA_SHADER_FRAGMENT) {
1396 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1397 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1398 "SPI_PS_INPUT_ENA = 0x%04x\n",
1399 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1400 }
1401
1402 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1403 "SGPRS: %d\n"
1404 "VGPRS: %d\n"
1405 "Spilled SGPRs: %d\n"
1406 "Spilled VGPRs: %d\n"
1407 "PrivMem VGPRS: %d\n"
1408 "Code Size: %d bytes\n"
1409 "LDS: %d blocks\n"
1410 "Scratch: %d bytes per wave\n"
1411 "Max Waves: %d\n",
1412 conf->num_sgprs, conf->num_vgprs,
1413 conf->spilled_sgprs, conf->spilled_vgprs,
1414 variant->info.private_mem_vgprs, variant->exec_size,
1415 conf->lds_size, conf->scratch_bytes_per_wave,
1416 max_simd_waves);
1417
1418 if (variant->statistics) {
1419 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1420 for (unsigned i = 0; i < variant->statistics->count; i++) {
1421 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1422 uint32_t value = variant->statistics->values[i];
1423 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1424 }
1425 }
1426
1427 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1428 }
1429
1430 void
1431 radv_shader_dump_stats(struct radv_device *device,
1432 struct radv_shader_variant *variant,
1433 gl_shader_stage stage,
1434 FILE *file)
1435 {
1436 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1437
1438 generate_shader_stats(device, variant, stage, buf);
1439
1440 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1441 fprintf(file, "%s", buf->buf);
1442
1443 _mesa_string_buffer_destroy(buf);
1444 }
1445
1446 VkResult
1447 radv_GetShaderInfoAMD(VkDevice _device,
1448 VkPipeline _pipeline,
1449 VkShaderStageFlagBits shaderStage,
1450 VkShaderInfoTypeAMD infoType,
1451 size_t* pInfoSize,
1452 void* pInfo)
1453 {
1454 RADV_FROM_HANDLE(radv_device, device, _device);
1455 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1456 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1457 struct radv_shader_variant *variant = pipeline->shaders[stage];
1458 struct _mesa_string_buffer *buf;
1459 VkResult result = VK_SUCCESS;
1460
1461 /* Spec doesn't indicate what to do if the stage is invalid, so just
1462 * return no info for this. */
1463 if (!variant)
1464 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1465
1466 switch (infoType) {
1467 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1468 if (!pInfo) {
1469 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1470 } else {
1471 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1472 struct ac_shader_config *conf = &variant->config;
1473
1474 VkShaderStatisticsInfoAMD statistics = {};
1475 statistics.shaderStageMask = shaderStage;
1476 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1477 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1478 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1479
1480 if (stage == MESA_SHADER_COMPUTE) {
1481 unsigned *local_size = variant->info.cs.block_size;
1482 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1483
1484 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1485 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1486
1487 statistics.computeWorkGroupSize[0] = local_size[0];
1488 statistics.computeWorkGroupSize[1] = local_size[1];
1489 statistics.computeWorkGroupSize[2] = local_size[2];
1490 } else {
1491 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1492 }
1493
1494 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1495 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1496 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1497 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1498 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1499
1500 size_t size = *pInfoSize;
1501 *pInfoSize = sizeof(statistics);
1502
1503 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1504
1505 if (size < *pInfoSize)
1506 result = VK_INCOMPLETE;
1507 }
1508
1509 break;
1510 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1511 buf = _mesa_string_buffer_create(NULL, 1024);
1512
1513 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1514 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1515 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1516 generate_shader_stats(device, variant, stage, buf);
1517
1518 /* Need to include the null terminator. */
1519 size_t length = buf->length + 1;
1520
1521 if (!pInfo) {
1522 *pInfoSize = length;
1523 } else {
1524 size_t size = *pInfoSize;
1525 *pInfoSize = length;
1526
1527 memcpy(pInfo, buf->buf, MIN2(size, length));
1528
1529 if (size < length)
1530 result = VK_INCOMPLETE;
1531 }
1532
1533 _mesa_string_buffer_destroy(buf);
1534 break;
1535 default:
1536 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1537 result = VK_ERROR_FEATURE_NOT_PRESENT;
1538 break;
1539 }
1540
1541 return result;
1542 }