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radv: set LDS TCS size at shaders creation for GFX9+
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 /* nir_lower_int64() isn't actually called for the LLVM backend, but
82 * this helps the loop unrolling heuristics. */
83 .lower_int64_options = nir_lower_imul64 |
84 nir_lower_imul_high64 |
85 nir_lower_imul_2x32_64 |
86 nir_lower_divmod64 |
87 nir_lower_minmax64 |
88 nir_lower_iabs64,
89 .lower_doubles_options = nir_lower_drcp |
90 nir_lower_dsqrt |
91 nir_lower_drsq |
92 nir_lower_ddiv,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_minmax64 |
128 nir_lower_iabs64,
129 .lower_doubles_options = nir_lower_drcp |
130 nir_lower_dsqrt |
131 nir_lower_drsq |
132 nir_lower_ddiv,
133 };
134
135 bool
136 radv_can_dump_shader(struct radv_device *device,
137 struct radv_shader_module *module,
138 bool is_gs_copy_shader)
139 {
140 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
141 return false;
142 if (module)
143 return !module->nir ||
144 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
145
146 return is_gs_copy_shader;
147 }
148
149 bool
150 radv_can_dump_shader_stats(struct radv_device *device,
151 struct radv_shader_module *module)
152 {
153 /* Only dump non-meta shader stats. */
154 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
155 module && !module->nir;
156 }
157
158 VkResult radv_CreateShaderModule(
159 VkDevice _device,
160 const VkShaderModuleCreateInfo* pCreateInfo,
161 const VkAllocationCallbacks* pAllocator,
162 VkShaderModule* pShaderModule)
163 {
164 RADV_FROM_HANDLE(radv_device, device, _device);
165 struct radv_shader_module *module;
166
167 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
168 assert(pCreateInfo->flags == 0);
169
170 module = vk_alloc2(&device->vk.alloc, pAllocator,
171 sizeof(*module) + pCreateInfo->codeSize, 8,
172 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
173 if (module == NULL)
174 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
175
176 vk_object_base_init(&device->vk, &module->base,
177 VK_OBJECT_TYPE_SHADER_MODULE);
178
179 module->nir = NULL;
180 module->size = pCreateInfo->codeSize;
181 memcpy(module->data, pCreateInfo->pCode, module->size);
182
183 _mesa_sha1_compute(module->data, module->size, module->sha1);
184
185 *pShaderModule = radv_shader_module_to_handle(module);
186
187 return VK_SUCCESS;
188 }
189
190 void radv_DestroyShaderModule(
191 VkDevice _device,
192 VkShaderModule _module,
193 const VkAllocationCallbacks* pAllocator)
194 {
195 RADV_FROM_HANDLE(radv_device, device, _device);
196 RADV_FROM_HANDLE(radv_shader_module, module, _module);
197
198 if (!module)
199 return;
200
201 vk_object_base_finish(&module->base);
202 vk_free2(&device->vk.alloc, pAllocator, module);
203 }
204
205 void
206 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
207 bool allow_copies)
208 {
209 bool progress;
210 unsigned lower_flrp =
211 (shader->options->lower_flrp16 ? 16 : 0) |
212 (shader->options->lower_flrp32 ? 32 : 0) |
213 (shader->options->lower_flrp64 ? 64 : 0);
214
215 do {
216 progress = false;
217
218 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
219 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
220
221 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
222 NIR_PASS_V(shader, nir_lower_pack);
223
224 if (allow_copies) {
225 /* Only run this pass in the first call to
226 * radv_optimize_nir. Later calls assume that we've
227 * lowered away any copy_deref instructions and we
228 * don't want to introduce any more.
229 */
230 NIR_PASS(progress, shader, nir_opt_find_array_copies);
231 }
232
233 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
234 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
235 NIR_PASS(progress, shader, nir_remove_dead_variables,
236 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
237 NULL);
238
239 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
240 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
241
242 NIR_PASS(progress, shader, nir_copy_prop);
243 NIR_PASS(progress, shader, nir_opt_remove_phis);
244 NIR_PASS(progress, shader, nir_opt_dce);
245 if (nir_opt_trivial_continues(shader)) {
246 progress = true;
247 NIR_PASS(progress, shader, nir_copy_prop);
248 NIR_PASS(progress, shader, nir_opt_remove_phis);
249 NIR_PASS(progress, shader, nir_opt_dce);
250 }
251 NIR_PASS(progress, shader, nir_opt_if, true);
252 NIR_PASS(progress, shader, nir_opt_dead_cf);
253 NIR_PASS(progress, shader, nir_opt_cse);
254 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
255 NIR_PASS(progress, shader, nir_opt_constant_folding);
256 NIR_PASS(progress, shader, nir_opt_algebraic);
257
258 if (lower_flrp != 0) {
259 bool lower_flrp_progress = false;
260 NIR_PASS(lower_flrp_progress,
261 shader,
262 nir_lower_flrp,
263 lower_flrp,
264 false /* always_precise */,
265 shader->options->lower_ffma);
266 if (lower_flrp_progress) {
267 NIR_PASS(progress, shader,
268 nir_opt_constant_folding);
269 progress = true;
270 }
271
272 /* Nothing should rematerialize any flrps, so we only
273 * need to do this lowering once.
274 */
275 lower_flrp = 0;
276 }
277
278 NIR_PASS(progress, shader, nir_opt_undef);
279 if (shader->options->max_unroll_iterations) {
280 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
281 }
282 } while (progress && !optimize_conservatively);
283
284 NIR_PASS(progress, shader, nir_opt_conditional_discard);
285 NIR_PASS(progress, shader, nir_opt_shrink_load);
286 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
287 }
288
289 static void
290 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
291 {
292 assert(glsl_type_is_vector_or_scalar(type));
293
294 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
295 unsigned length = glsl_get_vector_elements(type);
296 *size = comp_size * length,
297 *align = comp_size;
298 }
299
300 nir_shader *
301 radv_shader_compile_to_nir(struct radv_device *device,
302 struct radv_shader_module *module,
303 const char *entrypoint_name,
304 gl_shader_stage stage,
305 const VkSpecializationInfo *spec_info,
306 const VkPipelineCreateFlags flags,
307 const struct radv_pipeline_layout *layout,
308 unsigned subgroup_size, unsigned ballot_bit_size)
309 {
310 nir_shader *nir;
311 const nir_shader_compiler_options *nir_options =
312 device->physical_device->use_llvm ? &nir_options_llvm :
313 &nir_options_aco;
314
315 if (module->nir) {
316 /* Some things such as our meta clear/blit code will give us a NIR
317 * shader directly. In that case, we just ignore the SPIR-V entirely
318 * and just use the NIR shader */
319 nir = module->nir;
320 nir->options = nir_options;
321 nir_validate_shader(nir, "in internal shader");
322
323 assert(exec_list_length(&nir->functions) == 1);
324 } else {
325 uint32_t *spirv = (uint32_t *) module->data;
326 assert(module->size % 4 == 0);
327
328 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
329 radv_print_spirv(module->data, module->size, stderr);
330
331 uint32_t num_spec_entries = 0;
332 struct nir_spirv_specialization *spec_entries = NULL;
333 if (spec_info && spec_info->mapEntryCount > 0) {
334 num_spec_entries = spec_info->mapEntryCount;
335 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
336 for (uint32_t i = 0; i < num_spec_entries; i++) {
337 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
338 const void *data = spec_info->pData + entry.offset;
339 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
340
341 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
342 switch (entry.size) {
343 case 8:
344 spec_entries[i].value.u64 = *(const uint64_t *)data;
345 break;
346 case 4:
347 spec_entries[i].value.u32 = *(const uint32_t *)data;
348 break;
349 case 2:
350 spec_entries[i].value.u16 = *(const uint16_t *)data;
351 break;
352 case 1:
353 spec_entries[i].value.u8 = *(const uint8_t *)data;
354 break;
355 default:
356 assert(!"Invalid spec constant size");
357 break;
358 }
359 }
360 }
361 const struct spirv_to_nir_options spirv_options = {
362 .lower_ubo_ssbo_access_to_offsets = true,
363 .caps = {
364 .amd_fragment_mask = true,
365 .amd_gcn_shader = true,
366 .amd_image_gather_bias_lod = true,
367 .amd_image_read_write_lod = true,
368 .amd_shader_ballot = true,
369 .amd_shader_explicit_vertex_parameter = true,
370 .amd_trinary_minmax = true,
371 .demote_to_helper_invocation = true,
372 .derivative_group = true,
373 .descriptor_array_dynamic_indexing = true,
374 .descriptor_array_non_uniform_indexing = true,
375 .descriptor_indexing = true,
376 .device_group = true,
377 .draw_parameters = true,
378 .float_controls = true,
379 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
380 .float32_atomic_add = true,
381 .float64 = true,
382 .geometry_streams = true,
383 .image_ms_array = true,
384 .image_read_without_format = true,
385 .image_write_without_format = true,
386 .int8 = true,
387 .int16 = true,
388 .int64 = true,
389 .int64_atomics = true,
390 .min_lod = true,
391 .multiview = true,
392 .physical_storage_buffer_address = true,
393 .post_depth_coverage = true,
394 .runtime_descriptor_array = true,
395 .shader_clock = true,
396 .shader_viewport_index_layer = true,
397 .stencil_export = true,
398 .storage_8bit = true,
399 .storage_16bit = true,
400 .storage_image_ms = true,
401 .subgroup_arithmetic = true,
402 .subgroup_ballot = true,
403 .subgroup_basic = true,
404 .subgroup_quad = true,
405 .subgroup_shuffle = true,
406 .subgroup_vote = true,
407 .tessellation = true,
408 .transform_feedback = true,
409 .variable_pointers = true,
410 },
411 .ubo_addr_format = nir_address_format_32bit_index_offset,
412 .ssbo_addr_format = nir_address_format_32bit_index_offset,
413 .phys_ssbo_addr_format = nir_address_format_64bit_global,
414 .push_const_addr_format = nir_address_format_logical,
415 .shared_addr_format = nir_address_format_32bit_offset,
416 .frag_coord_is_sysval = true,
417 };
418 nir = spirv_to_nir(spirv, module->size / 4,
419 spec_entries, num_spec_entries,
420 stage, entrypoint_name,
421 &spirv_options, nir_options);
422 assert(nir->info.stage == stage);
423 nir_validate_shader(nir, "after spirv_to_nir");
424
425 free(spec_entries);
426
427 /* We have to lower away local constant initializers right before we
428 * inline functions. That way they get properly initialized at the top
429 * of the function and not at the top of its caller.
430 */
431 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
432 NIR_PASS_V(nir, nir_lower_returns);
433 NIR_PASS_V(nir, nir_inline_functions);
434 NIR_PASS_V(nir, nir_copy_prop);
435 NIR_PASS_V(nir, nir_opt_deref);
436
437 /* Pick off the single entrypoint that we want */
438 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
439 if (func->is_entrypoint)
440 func->name = ralloc_strdup(func, "main");
441 else
442 exec_node_remove(&func->node);
443 }
444 assert(exec_list_length(&nir->functions) == 1);
445
446 /* Make sure we lower constant initializers on output variables so that
447 * nir_remove_dead_variables below sees the corresponding stores
448 */
449 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
450
451 /* Now that we've deleted all but the main function, we can go ahead and
452 * lower the rest of the constant initializers.
453 */
454 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
455
456 /* Split member structs. We do this before lower_io_to_temporaries so that
457 * it doesn't lower system values to temporaries by accident.
458 */
459 NIR_PASS_V(nir, nir_split_var_copies);
460 NIR_PASS_V(nir, nir_split_per_member_structs);
461
462 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
463 !device->physical_device->use_llvm)
464 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
465 if (nir->info.stage == MESA_SHADER_FRAGMENT)
466 NIR_PASS_V(nir, nir_lower_input_attachments, true);
467
468 NIR_PASS_V(nir, nir_remove_dead_variables,
469 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
470 NULL);
471
472 NIR_PASS_V(nir, nir_propagate_invariant);
473
474 NIR_PASS_V(nir, nir_lower_system_values);
475 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
476 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
477 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
478 NIR_PASS_V(nir, nir_lower_discard_to_demote);
479
480 nir_lower_doubles_options lower_doubles =
481 nir->options->lower_doubles_options;
482
483 if (device->physical_device->rad_info.chip_class == GFX6) {
484 /* GFX6 doesn't support v_floor_f64 and the precision
485 * of v_fract_f64 which is used to implement 64-bit
486 * floor is less than what Vulkan requires.
487 */
488 lower_doubles |= nir_lower_dfloor;
489 }
490
491 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
492 }
493
494 /* Vulkan uses the separate-shader linking model */
495 nir->info.separate_shader = true;
496
497 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
498
499 if (nir->info.stage == MESA_SHADER_GEOMETRY)
500 nir_lower_gs_intrinsics(nir, true);
501
502 static const nir_lower_tex_options tex_options = {
503 .lower_txp = ~0,
504 .lower_tg4_offsets = true,
505 };
506
507 nir_lower_tex(nir, &tex_options);
508
509 nir_lower_vars_to_ssa(nir);
510
511 if (nir->info.stage == MESA_SHADER_VERTEX ||
512 nir->info.stage == MESA_SHADER_GEOMETRY ||
513 nir->info.stage == MESA_SHADER_FRAGMENT) {
514 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
515 nir_shader_get_entrypoint(nir), true, true);
516 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
517 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
518 nir_shader_get_entrypoint(nir), true, false);
519 }
520
521 nir_split_var_copies(nir);
522
523 nir_lower_global_vars_to_local(nir);
524 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
525 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
526 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
527 .subgroup_size = subgroup_size,
528 .ballot_bit_size = ballot_bit_size,
529 .lower_to_scalar = 1,
530 .lower_subgroup_masks = 1,
531 .lower_shuffle = 1,
532 .lower_shuffle_to_32bit = 1,
533 .lower_vote_eq_to_ballot = 1,
534 .lower_quad_broadcast_dynamic = 1,
535 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
536 .lower_shuffle_to_swizzle_amd = 1,
537 });
538
539 nir_lower_load_const_to_scalar(nir);
540
541 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
542 radv_optimize_nir(nir, false, true);
543
544 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
545 * to remove any copies introduced by nir_opt_find_array_copies().
546 */
547 nir_lower_var_copies(nir);
548
549 /* Lower deref operations for compute shared memory. */
550 if (nir->info.stage == MESA_SHADER_COMPUTE) {
551 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
552 nir_var_mem_shared, shared_var_info);
553 NIR_PASS_V(nir, nir_lower_explicit_io,
554 nir_var_mem_shared, nir_address_format_32bit_offset);
555 }
556
557 /* Lower large variables that are always constant with load_constant
558 * intrinsics, which get turned into PC-relative loads from a data
559 * section next to the shader.
560 */
561 NIR_PASS_V(nir, nir_opt_large_constants,
562 glsl_get_natural_size_align_bytes, 16);
563
564 /* Indirect lowering must be called after the radv_optimize_nir() loop
565 * has been called at least once. Otherwise indirect lowering can
566 * bloat the instruction count of the loop and cause it to be
567 * considered too large for unrolling.
568 */
569 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
570 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
571
572 return nir;
573 }
574
575 static int
576 type_size_vec4(const struct glsl_type *type, bool bindless)
577 {
578 return glsl_count_attribute_slots(type, false);
579 }
580
581 static nir_variable *
582 find_layer_in_var(nir_shader *nir)
583 {
584 nir_foreach_variable(var, &nir->inputs) {
585 if (var->data.location == VARYING_SLOT_LAYER) {
586 return var;
587 }
588 }
589
590 nir_variable *var =
591 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
592 var->data.location = VARYING_SLOT_LAYER;
593 var->data.interpolation = INTERP_MODE_FLAT;
594 return var;
595 }
596
597 /* We use layered rendering to implement multiview, which means we need to map
598 * view_index to gl_Layer. The attachment lowering also uses needs to know the
599 * layer so that it can sample from the correct layer. The code generates a
600 * load from the layer_id sysval, but since we don't have a way to get at this
601 * information from the fragment shader, we also need to lower this to the
602 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
603 * slot, before lowering io, so that nir_assign_var_locations() will give the
604 * LAYER varying the correct driver_location.
605 */
606
607 static bool
608 lower_view_index(nir_shader *nir)
609 {
610 bool progress = false;
611 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
612 nir_builder b;
613 nir_builder_init(&b, entry);
614
615 nir_variable *layer = NULL;
616 nir_foreach_block(block, entry) {
617 nir_foreach_instr_safe(instr, block) {
618 if (instr->type != nir_instr_type_intrinsic)
619 continue;
620
621 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
622 if (load->intrinsic != nir_intrinsic_load_view_index &&
623 load->intrinsic != nir_intrinsic_load_layer_id)
624 continue;
625
626 if (!layer)
627 layer = find_layer_in_var(nir);
628
629 b.cursor = nir_before_instr(instr);
630 nir_ssa_def *def = nir_load_var(&b, layer);
631 nir_ssa_def_rewrite_uses(&load->dest.ssa,
632 nir_src_for_ssa(def));
633
634 nir_instr_remove(instr);
635 progress = true;
636 }
637 }
638
639 return progress;
640 }
641
642 void
643 radv_lower_fs_io(nir_shader *nir)
644 {
645 NIR_PASS_V(nir, lower_view_index);
646 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
647 MESA_SHADER_FRAGMENT);
648
649 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
650
651 /* This pass needs actual constants */
652 nir_opt_constant_folding(nir);
653
654 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
655 }
656
657
658 static void *
659 radv_alloc_shader_memory(struct radv_device *device,
660 struct radv_shader_variant *shader)
661 {
662 mtx_lock(&device->shader_slab_mutex);
663 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
664 uint64_t offset = 0;
665 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
666 if (s->bo_offset - offset >= shader->code_size) {
667 shader->bo = slab->bo;
668 shader->bo_offset = offset;
669 list_addtail(&shader->slab_list, &s->slab_list);
670 mtx_unlock(&device->shader_slab_mutex);
671 return slab->ptr + offset;
672 }
673 offset = align_u64(s->bo_offset + s->code_size, 256);
674 }
675 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
676 shader->bo = slab->bo;
677 shader->bo_offset = offset;
678 list_addtail(&shader->slab_list, &slab->shaders);
679 mtx_unlock(&device->shader_slab_mutex);
680 return slab->ptr + offset;
681 }
682 }
683
684 mtx_unlock(&device->shader_slab_mutex);
685 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
686
687 slab->size = MAX2(256 * 1024, shader->code_size);
688 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
689 RADEON_DOMAIN_VRAM,
690 RADEON_FLAG_NO_INTERPROCESS_SHARING |
691 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
692 0 : RADEON_FLAG_READ_ONLY),
693 RADV_BO_PRIORITY_SHADER);
694 if (!slab->bo) {
695 free(slab);
696 return NULL;
697 }
698
699 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
700 if (!slab->ptr) {
701 device->ws->buffer_destroy(slab->bo);
702 free(slab);
703 return NULL;
704 }
705
706 list_inithead(&slab->shaders);
707
708 mtx_lock(&device->shader_slab_mutex);
709 list_add(&slab->slabs, &device->shader_slabs);
710
711 shader->bo = slab->bo;
712 shader->bo_offset = 0;
713 list_add(&shader->slab_list, &slab->shaders);
714 mtx_unlock(&device->shader_slab_mutex);
715 return slab->ptr;
716 }
717
718 void
719 radv_destroy_shader_slabs(struct radv_device *device)
720 {
721 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
722 device->ws->buffer_destroy(slab->bo);
723 free(slab);
724 }
725 mtx_destroy(&device->shader_slab_mutex);
726 }
727
728 /* For the UMR disassembler. */
729 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
730 #define DEBUGGER_NUM_MARKERS 5
731
732 static unsigned
733 radv_get_shader_binary_size(size_t code_size)
734 {
735 return code_size + DEBUGGER_NUM_MARKERS * 4;
736 }
737
738 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
739 const struct ac_shader_config *config_in,
740 const struct radv_shader_info *info,
741 gl_shader_stage stage,
742 struct ac_shader_config *config_out)
743 {
744 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
745 unsigned vgpr_comp_cnt = 0;
746 unsigned num_input_vgprs = info->num_input_vgprs;
747
748 if (stage == MESA_SHADER_FRAGMENT) {
749 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
750 }
751
752 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
753 /* +3 for scratch wave offset and VCC */
754 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
755 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
756 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
757 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
758 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
759 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
760
761 *config_out = *config_in;
762 config_out->num_vgprs = num_vgprs;
763 config_out->num_sgprs = num_sgprs;
764 config_out->num_shared_vgprs = num_shared_vgprs;
765
766 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
767 S_00B12C_SCRATCH_EN(scratch_enabled);
768
769 if (!pdevice->use_ngg_streamout) {
770 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
771 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
772 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
773 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
774 S_00B12C_SO_EN(!!info->so.num_outputs);
775 }
776
777 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
778 (info->wave_size == 32 ? 8 : 4)) |
779 S_00B848_DX10_CLAMP(1) |
780 S_00B848_FLOAT_MODE(config_out->float_mode);
781
782 if (pdevice->rad_info.chip_class >= GFX10) {
783 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
784 } else {
785 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
786 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
787 }
788
789 switch (stage) {
790 case MESA_SHADER_TESS_EVAL:
791 if (info->is_ngg) {
792 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
793 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
794 } else if (info->tes.as_es) {
795 assert(pdevice->rad_info.chip_class <= GFX8);
796 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
797
798 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
799 } else {
800 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
801 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
802
803 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
804 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
805 }
806 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
807 break;
808 case MESA_SHADER_TESS_CTRL:
809 if (pdevice->rad_info.chip_class >= GFX9) {
810 /* We need at least 2 components for LS.
811 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
812 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
813 */
814 if (pdevice->rad_info.chip_class >= GFX10) {
815 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
816 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
817 } else {
818 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
819 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
820 }
821 } else {
822 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
823 }
824 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
825 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
826 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
827 break;
828 case MESA_SHADER_VERTEX:
829 if (info->is_ngg) {
830 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
831 } else if (info->vs.as_ls) {
832 assert(pdevice->rad_info.chip_class <= GFX8);
833 /* We need at least 2 components for LS.
834 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
835 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
836 */
837 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
838 } else if (info->vs.as_es) {
839 assert(pdevice->rad_info.chip_class <= GFX8);
840 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
841 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
842 } else {
843 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
844 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
845 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
846 */
847 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
848 vgpr_comp_cnt = 3;
849 } else if (info->vs.export_prim_id) {
850 vgpr_comp_cnt = 2;
851 } else if (info->vs.needs_instance_id) {
852 vgpr_comp_cnt = 1;
853 } else {
854 vgpr_comp_cnt = 0;
855 }
856
857 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
858 }
859 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
860 break;
861 case MESA_SHADER_FRAGMENT:
862 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
863 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
864 break;
865 case MESA_SHADER_GEOMETRY:
866 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
867 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
868 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
869 break;
870 case MESA_SHADER_COMPUTE:
871 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
872 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
873 config_out->rsrc2 |=
874 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
875 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
876 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
877 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
878 info->cs.uses_thread_id[1] ? 1 : 0) |
879 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
880 S_00B84C_LDS_SIZE(config_in->lds_size);
881 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
882
883 break;
884 default:
885 unreachable("unsupported shader type");
886 break;
887 }
888
889 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
890 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
891 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
892 gl_shader_stage es_stage = stage;
893 if (stage == MESA_SHADER_GEOMETRY)
894 es_stage = info->gs.es_type;
895
896 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
897 if (es_stage == MESA_SHADER_VERTEX) {
898 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
899 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
900 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
901 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
902 } else
903 unreachable("Unexpected ES shader stage");
904
905 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
906 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
907 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
908 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
909 } else if (info->uses_prim_id) {
910 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
911 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
912 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
913 } else {
914 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
915 }
916
917 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
918 S_00B228_WGP_MODE(1);
919 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
920 S_00B22C_LDS_SIZE(config_in->lds_size) |
921 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
922 } else if (pdevice->rad_info.chip_class >= GFX9 &&
923 stage == MESA_SHADER_GEOMETRY) {
924 unsigned es_type = info->gs.es_type;
925 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
926
927 if (es_type == MESA_SHADER_VERTEX) {
928 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
929 if (info->vs.needs_instance_id) {
930 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
931 } else {
932 es_vgpr_comp_cnt = 0;
933 }
934 } else if (es_type == MESA_SHADER_TESS_EVAL) {
935 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
936 } else {
937 unreachable("invalid shader ES type");
938 }
939
940 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
941 * VGPR[0:4] are always loaded.
942 */
943 if (info->uses_invocation_id) {
944 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
945 } else if (info->uses_prim_id) {
946 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
947 } else if (info->gs.vertices_in >= 3) {
948 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
949 } else {
950 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
951 }
952
953 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
954 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
955 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
956 } else if (pdevice->rad_info.chip_class >= GFX9 &&
957 stage == MESA_SHADER_TESS_CTRL) {
958 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
959 } else {
960 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
961 }
962 }
963
964 struct radv_shader_variant *
965 radv_shader_variant_create(struct radv_device *device,
966 const struct radv_shader_binary *binary,
967 bool keep_shader_info)
968 {
969 struct ac_shader_config config = {0};
970 struct ac_rtld_binary rtld_binary = {0};
971 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
972 if (!variant)
973 return NULL;
974
975 variant->ref_count = 1;
976
977 if (binary->type == RADV_BINARY_TYPE_RTLD) {
978 struct ac_rtld_symbol lds_symbols[2];
979 unsigned num_lds_symbols = 0;
980 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
981 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
982
983 if (device->physical_device->rad_info.chip_class >= GFX9 &&
984 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
985 !binary->is_gs_copy_shader) {
986 /* We add this symbol even on LLVM <= 8 to ensure that
987 * shader->config.lds_size is set correctly below.
988 */
989 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
990 sym->name = "esgs_ring";
991 sym->size = binary->info.ngg_info.esgs_ring_size;
992 sym->align = 64 * 1024;
993 }
994
995 if (binary->info.is_ngg &&
996 binary->stage == MESA_SHADER_GEOMETRY) {
997 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
998 sym->name = "ngg_emit";
999 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1000 sym->align = 4;
1001 }
1002
1003 struct ac_rtld_open_info open_info = {
1004 .info = &device->physical_device->rad_info,
1005 .shader_type = binary->stage,
1006 .wave_size = binary->info.wave_size,
1007 .num_parts = 1,
1008 .elf_ptrs = &elf_data,
1009 .elf_sizes = &elf_size,
1010 .num_shared_lds_symbols = num_lds_symbols,
1011 .shared_lds_symbols = lds_symbols,
1012 };
1013
1014 if (!ac_rtld_open(&rtld_binary, open_info)) {
1015 free(variant);
1016 return NULL;
1017 }
1018
1019 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1020 &rtld_binary, &config)) {
1021 ac_rtld_close(&rtld_binary);
1022 free(variant);
1023 return NULL;
1024 }
1025
1026 if (rtld_binary.lds_size > 0) {
1027 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1028 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1029 }
1030
1031 variant->code_size = rtld_binary.rx_size;
1032 variant->exec_size = rtld_binary.exec_size;
1033 } else {
1034 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1035 config = ((struct radv_shader_binary_legacy *)binary)->config;
1036 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1037 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1038 }
1039
1040 variant->info = binary->info;
1041 radv_postprocess_config(device->physical_device, &config, &binary->info,
1042 binary->stage, &variant->config);
1043
1044 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1045 if (!dest_ptr) {
1046 if (binary->type == RADV_BINARY_TYPE_RTLD)
1047 ac_rtld_close(&rtld_binary);
1048 free(variant);
1049 return NULL;
1050 }
1051
1052 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1053 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1054 struct ac_rtld_upload_info info = {
1055 .binary = &rtld_binary,
1056 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1057 .rx_ptr = dest_ptr,
1058 };
1059
1060 if (!ac_rtld_upload(&info)) {
1061 radv_shader_variant_destroy(device, variant);
1062 ac_rtld_close(&rtld_binary);
1063 return NULL;
1064 }
1065
1066 if (keep_shader_info ||
1067 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1068 const char *disasm_data;
1069 size_t disasm_size;
1070 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1071 radv_shader_variant_destroy(device, variant);
1072 ac_rtld_close(&rtld_binary);
1073 return NULL;
1074 }
1075
1076 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1077 variant->disasm_string = malloc(disasm_size + 1);
1078 memcpy(variant->disasm_string, disasm_data, disasm_size);
1079 variant->disasm_string[disasm_size] = 0;
1080 }
1081
1082 ac_rtld_close(&rtld_binary);
1083 } else {
1084 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1085 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1086
1087 /* Add end-of-code markers for the UMR disassembler. */
1088 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1089 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1090 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1091
1092 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1093 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1094
1095 if (bin->stats_size) {
1096 variant->statistics = calloc(bin->stats_size, 1);
1097 memcpy(variant->statistics, bin->data, bin->stats_size);
1098 }
1099 }
1100 return variant;
1101 }
1102
1103 static char *
1104 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1105 int shader_count)
1106 {
1107 char *data = NULL;
1108 char *ret = NULL;
1109 size_t size = 0;
1110 FILE *f = open_memstream(&data, &size);
1111 if (f) {
1112 for (int i = 0; i < shader_count; ++i)
1113 nir_print_shader(shaders[i], f);
1114 fclose(f);
1115 }
1116
1117 ret = malloc(size + 1);
1118 if (ret) {
1119 memcpy(ret, data, size);
1120 ret[size] = 0;
1121 }
1122 free(data);
1123 return ret;
1124 }
1125
1126 static struct radv_shader_variant *
1127 shader_variant_compile(struct radv_device *device,
1128 struct radv_shader_module *module,
1129 struct nir_shader * const *shaders,
1130 int shader_count,
1131 gl_shader_stage stage,
1132 struct radv_shader_info *info,
1133 struct radv_nir_compiler_options *options,
1134 bool gs_copy_shader,
1135 bool keep_shader_info,
1136 bool keep_statistic_info,
1137 struct radv_shader_binary **binary_out)
1138 {
1139 enum radeon_family chip_family = device->physical_device->rad_info.family;
1140 struct radv_shader_binary *binary = NULL;
1141
1142 options->family = chip_family;
1143 options->chip_class = device->physical_device->rad_info.chip_class;
1144 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1145 options->dump_preoptir = options->dump_shader &&
1146 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1147 options->record_ir = keep_shader_info;
1148 options->record_stats = keep_statistic_info;
1149 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1150 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1151 options->address32_hi = device->physical_device->rad_info.address32_hi;
1152 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1153 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1154 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1155
1156 struct radv_shader_args args = {};
1157 args.options = options;
1158 args.shader_info = info;
1159 args.is_gs_copy_shader = gs_copy_shader;
1160 radv_declare_shader_args(&args,
1161 gs_copy_shader ? MESA_SHADER_VERTEX
1162 : shaders[shader_count - 1]->info.stage,
1163 shader_count >= 2,
1164 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1165 : MESA_SHADER_VERTEX);
1166
1167 if (device->physical_device->use_llvm ||
1168 options->dump_shader || options->record_ir)
1169 ac_init_llvm_once();
1170
1171 if (device->physical_device->use_llvm) {
1172 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1173 } else {
1174 aco_compile_shader(shader_count, shaders, &binary, &args);
1175 }
1176
1177 binary->info = *info;
1178
1179 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1180 keep_shader_info);
1181 if (!variant) {
1182 free(binary);
1183 return NULL;
1184 }
1185
1186 if (options->dump_shader) {
1187 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1188 for (int i = 1; i < shader_count; ++i)
1189 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1190
1191 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1192 }
1193
1194
1195 if (keep_shader_info) {
1196 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1197 if (!gs_copy_shader && !module->nir) {
1198 variant->spirv = malloc(module->size);
1199 if (!variant->spirv) {
1200 free(variant);
1201 free(binary);
1202 return NULL;
1203 }
1204
1205 memcpy(variant->spirv, module->data, module->size);
1206 variant->spirv_size = module->size;
1207 }
1208 }
1209
1210 if (binary_out)
1211 *binary_out = binary;
1212 else
1213 free(binary);
1214
1215 return variant;
1216 }
1217
1218 struct radv_shader_variant *
1219 radv_shader_variant_compile(struct radv_device *device,
1220 struct radv_shader_module *module,
1221 struct nir_shader *const *shaders,
1222 int shader_count,
1223 struct radv_pipeline_layout *layout,
1224 const struct radv_shader_variant_key *key,
1225 struct radv_shader_info *info,
1226 bool keep_shader_info, bool keep_statistic_info,
1227 struct radv_shader_binary **binary_out)
1228 {
1229 struct radv_nir_compiler_options options = {0};
1230
1231 options.layout = layout;
1232 if (key)
1233 options.key = *key;
1234
1235 options.explicit_scratch_args = !device->physical_device->use_llvm;
1236 options.robust_buffer_access = device->robust_buffer_access;
1237
1238 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1239 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1240 }
1241
1242 struct radv_shader_variant *
1243 radv_create_gs_copy_shader(struct radv_device *device,
1244 struct nir_shader *shader,
1245 struct radv_shader_info *info,
1246 struct radv_shader_binary **binary_out,
1247 bool keep_shader_info, bool keep_statistic_info,
1248 bool multiview)
1249 {
1250 struct radv_nir_compiler_options options = {0};
1251
1252 options.explicit_scratch_args = !device->physical_device->use_llvm;
1253 options.key.has_multiview_view_index = multiview;
1254
1255 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1256 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1257 }
1258
1259 void
1260 radv_shader_variant_destroy(struct radv_device *device,
1261 struct radv_shader_variant *variant)
1262 {
1263 if (!p_atomic_dec_zero(&variant->ref_count))
1264 return;
1265
1266 mtx_lock(&device->shader_slab_mutex);
1267 list_del(&variant->slab_list);
1268 mtx_unlock(&device->shader_slab_mutex);
1269
1270 free(variant->spirv);
1271 free(variant->nir_string);
1272 free(variant->disasm_string);
1273 free(variant->ir_string);
1274 free(variant->statistics);
1275 free(variant);
1276 }
1277
1278 const char *
1279 radv_get_shader_name(struct radv_shader_info *info,
1280 gl_shader_stage stage)
1281 {
1282 switch (stage) {
1283 case MESA_SHADER_VERTEX:
1284 if (info->vs.as_ls)
1285 return "Vertex Shader as LS";
1286 else if (info->vs.as_es)
1287 return "Vertex Shader as ES";
1288 else if (info->is_ngg)
1289 return "Vertex Shader as ESGS";
1290 else
1291 return "Vertex Shader as VS";
1292 case MESA_SHADER_TESS_CTRL:
1293 return "Tessellation Control Shader";
1294 case MESA_SHADER_TESS_EVAL:
1295 if (info->tes.as_es)
1296 return "Tessellation Evaluation Shader as ES";
1297 else if (info->is_ngg)
1298 return "Tessellation Evaluation Shader as ESGS";
1299 else
1300 return "Tessellation Evaluation Shader as VS";
1301 case MESA_SHADER_GEOMETRY:
1302 return "Geometry Shader";
1303 case MESA_SHADER_FRAGMENT:
1304 return "Pixel Shader";
1305 case MESA_SHADER_COMPUTE:
1306 return "Compute Shader";
1307 default:
1308 return "Unknown shader";
1309 };
1310 }
1311
1312 unsigned
1313 radv_get_max_workgroup_size(enum chip_class chip_class,
1314 gl_shader_stage stage,
1315 const unsigned *sizes)
1316 {
1317 switch (stage) {
1318 case MESA_SHADER_TESS_CTRL:
1319 return chip_class >= GFX7 ? 128 : 64;
1320 case MESA_SHADER_GEOMETRY:
1321 return chip_class >= GFX9 ? 128 : 64;
1322 case MESA_SHADER_COMPUTE:
1323 break;
1324 default:
1325 return 0;
1326 }
1327
1328 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1329 return max_workgroup_size;
1330 }
1331
1332 unsigned
1333 radv_get_max_waves(struct radv_device *device,
1334 struct radv_shader_variant *variant,
1335 gl_shader_stage stage)
1336 {
1337 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1338 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1339 uint8_t wave_size = variant->info.wave_size;
1340 struct ac_shader_config *conf = &variant->config;
1341 unsigned max_simd_waves;
1342 unsigned lds_per_wave = 0;
1343
1344 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1345
1346 if (stage == MESA_SHADER_FRAGMENT) {
1347 lds_per_wave = conf->lds_size * lds_increment +
1348 align(variant->info.ps.num_interp * 48,
1349 lds_increment);
1350 } else if (stage == MESA_SHADER_COMPUTE) {
1351 unsigned max_workgroup_size =
1352 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1353 lds_per_wave = (conf->lds_size * lds_increment) /
1354 DIV_ROUND_UP(max_workgroup_size, wave_size);
1355 }
1356
1357 if (conf->num_sgprs) {
1358 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1359 max_simd_waves =
1360 MIN2(max_simd_waves,
1361 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1362 sgprs);
1363 }
1364
1365 if (conf->num_vgprs) {
1366 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1367 max_simd_waves =
1368 MIN2(max_simd_waves,
1369 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1370 }
1371
1372 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1373 if (lds_per_wave)
1374 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1375
1376 return max_simd_waves;
1377 }
1378
1379 static void
1380 generate_shader_stats(struct radv_device *device,
1381 struct radv_shader_variant *variant,
1382 gl_shader_stage stage,
1383 struct _mesa_string_buffer *buf)
1384 {
1385 struct ac_shader_config *conf = &variant->config;
1386 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1387
1388 if (stage == MESA_SHADER_FRAGMENT) {
1389 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1390 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1391 "SPI_PS_INPUT_ENA = 0x%04x\n",
1392 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1393 }
1394
1395 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1396 "SGPRS: %d\n"
1397 "VGPRS: %d\n"
1398 "Spilled SGPRs: %d\n"
1399 "Spilled VGPRs: %d\n"
1400 "PrivMem VGPRS: %d\n"
1401 "Code Size: %d bytes\n"
1402 "LDS: %d blocks\n"
1403 "Scratch: %d bytes per wave\n"
1404 "Max Waves: %d\n",
1405 conf->num_sgprs, conf->num_vgprs,
1406 conf->spilled_sgprs, conf->spilled_vgprs,
1407 variant->info.private_mem_vgprs, variant->exec_size,
1408 conf->lds_size, conf->scratch_bytes_per_wave,
1409 max_simd_waves);
1410
1411 if (variant->statistics) {
1412 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1413 for (unsigned i = 0; i < variant->statistics->count; i++) {
1414 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1415 uint32_t value = variant->statistics->values[i];
1416 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1417 }
1418 }
1419
1420 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1421 }
1422
1423 void
1424 radv_shader_dump_stats(struct radv_device *device,
1425 struct radv_shader_variant *variant,
1426 gl_shader_stage stage,
1427 FILE *file)
1428 {
1429 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1430
1431 generate_shader_stats(device, variant, stage, buf);
1432
1433 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1434 fprintf(file, "%s", buf->buf);
1435
1436 _mesa_string_buffer_destroy(buf);
1437 }
1438
1439 VkResult
1440 radv_GetShaderInfoAMD(VkDevice _device,
1441 VkPipeline _pipeline,
1442 VkShaderStageFlagBits shaderStage,
1443 VkShaderInfoTypeAMD infoType,
1444 size_t* pInfoSize,
1445 void* pInfo)
1446 {
1447 RADV_FROM_HANDLE(radv_device, device, _device);
1448 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1449 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1450 struct radv_shader_variant *variant = pipeline->shaders[stage];
1451 struct _mesa_string_buffer *buf;
1452 VkResult result = VK_SUCCESS;
1453
1454 /* Spec doesn't indicate what to do if the stage is invalid, so just
1455 * return no info for this. */
1456 if (!variant)
1457 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1458
1459 switch (infoType) {
1460 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1461 if (!pInfo) {
1462 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1463 } else {
1464 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1465 struct ac_shader_config *conf = &variant->config;
1466
1467 VkShaderStatisticsInfoAMD statistics = {};
1468 statistics.shaderStageMask = shaderStage;
1469 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1470 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1471 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1472
1473 if (stage == MESA_SHADER_COMPUTE) {
1474 unsigned *local_size = variant->info.cs.block_size;
1475 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1476
1477 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1478 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1479
1480 statistics.computeWorkGroupSize[0] = local_size[0];
1481 statistics.computeWorkGroupSize[1] = local_size[1];
1482 statistics.computeWorkGroupSize[2] = local_size[2];
1483 } else {
1484 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1485 }
1486
1487 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1488 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1489 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1490 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1491 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1492
1493 size_t size = *pInfoSize;
1494 *pInfoSize = sizeof(statistics);
1495
1496 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1497
1498 if (size < *pInfoSize)
1499 result = VK_INCOMPLETE;
1500 }
1501
1502 break;
1503 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1504 buf = _mesa_string_buffer_create(NULL, 1024);
1505
1506 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1507 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1508 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1509 generate_shader_stats(device, variant, stage, buf);
1510
1511 /* Need to include the null terminator. */
1512 size_t length = buf->length + 1;
1513
1514 if (!pInfo) {
1515 *pInfoSize = length;
1516 } else {
1517 size_t size = *pInfoSize;
1518 *pInfoSize = length;
1519
1520 memcpy(pInfo, buf->buf, MIN2(size, length));
1521
1522 if (size < length)
1523 result = VK_INCOMPLETE;
1524 }
1525
1526 _mesa_string_buffer_destroy(buf);
1527 break;
1528 default:
1529 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1530 result = VK_ERROR_FEATURE_NOT_PRESENT;
1531 break;
1532 }
1533
1534 return result;
1535 }