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c3a2b538ab7a430147376fac9fee7b081ddae5f9
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 if (shader->options->max_unroll_iterations) {
282 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
283 }
284 } while (progress && !optimize_conservatively);
285
286 NIR_PASS(progress, shader, nir_opt_conditional_discard);
287 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 struct radv_spirv_debug_data {
303 struct radv_device *device;
304 const struct radv_shader_module *module;
305 };
306
307 static void radv_spirv_nir_debug(void *private_data,
308 enum nir_spirv_debug_level level,
309 size_t spirv_offset,
310 const char *message)
311 {
312 struct radv_spirv_debug_data *debug_data = private_data;
313 struct radv_instance *instance = debug_data->device->instance;
314
315 static const VkDebugReportFlagsEXT vk_flags[] = {
316 [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
317 [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
318 [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
319 };
320 char buffer[256];
321
322 snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s",
323 (unsigned long)spirv_offset, message);
324
325 vk_debug_report(&instance->debug_report_callbacks,
326 vk_flags[level],
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
328 (uint64_t)(uintptr_t)debug_data->module,
329 0, 0, "radv", buffer);
330 }
331
332 nir_shader *
333 radv_shader_compile_to_nir(struct radv_device *device,
334 struct radv_shader_module *module,
335 const char *entrypoint_name,
336 gl_shader_stage stage,
337 const VkSpecializationInfo *spec_info,
338 const VkPipelineCreateFlags flags,
339 const struct radv_pipeline_layout *layout,
340 unsigned subgroup_size, unsigned ballot_bit_size)
341 {
342 nir_shader *nir;
343 const nir_shader_compiler_options *nir_options =
344 radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco;
345
346 if (module->nir) {
347 /* Some things such as our meta clear/blit code will give us a NIR
348 * shader directly. In that case, we just ignore the SPIR-V entirely
349 * and just use the NIR shader */
350 nir = module->nir;
351 nir->options = nir_options;
352 nir_validate_shader(nir, "in internal shader");
353
354 assert(exec_list_length(&nir->functions) == 1);
355 } else {
356 uint32_t *spirv = (uint32_t *) module->data;
357 assert(module->size % 4 == 0);
358
359 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
360 radv_print_spirv(module->data, module->size, stderr);
361
362 uint32_t num_spec_entries = 0;
363 struct nir_spirv_specialization *spec_entries = NULL;
364 if (spec_info && spec_info->mapEntryCount > 0) {
365 num_spec_entries = spec_info->mapEntryCount;
366 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
367 for (uint32_t i = 0; i < num_spec_entries; i++) {
368 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
369 const void *data = spec_info->pData + entry.offset;
370 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
371
372 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
373 switch (entry.size) {
374 case 8:
375 spec_entries[i].value.u64 = *(const uint64_t *)data;
376 break;
377 case 4:
378 spec_entries[i].value.u32 = *(const uint32_t *)data;
379 break;
380 case 2:
381 spec_entries[i].value.u16 = *(const uint16_t *)data;
382 break;
383 case 1:
384 spec_entries[i].value.u8 = *(const uint8_t *)data;
385 break;
386 default:
387 assert(!"Invalid spec constant size");
388 break;
389 }
390 }
391 }
392
393 struct radv_spirv_debug_data spirv_debug_data = {
394 .device = device,
395 .module = module,
396 };
397 const struct spirv_to_nir_options spirv_options = {
398 .lower_ubo_ssbo_access_to_offsets = true,
399 .caps = {
400 .amd_fragment_mask = true,
401 .amd_gcn_shader = true,
402 .amd_image_gather_bias_lod = true,
403 .amd_image_read_write_lod = true,
404 .amd_shader_ballot = true,
405 .amd_shader_explicit_vertex_parameter = true,
406 .amd_trinary_minmax = true,
407 .demote_to_helper_invocation = true,
408 .derivative_group = true,
409 .descriptor_array_dynamic_indexing = true,
410 .descriptor_array_non_uniform_indexing = true,
411 .descriptor_indexing = true,
412 .device_group = true,
413 .draw_parameters = true,
414 .float_controls = true,
415 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
416 .float32_atomic_add = true,
417 .float64 = true,
418 .geometry_streams = true,
419 .image_ms_array = true,
420 .image_read_without_format = true,
421 .image_write_without_format = true,
422 .int8 = true,
423 .int16 = true,
424 .int64 = true,
425 .int64_atomics = true,
426 .min_lod = true,
427 .multiview = true,
428 .physical_storage_buffer_address = true,
429 .post_depth_coverage = true,
430 .runtime_descriptor_array = true,
431 .shader_clock = true,
432 .shader_viewport_index_layer = true,
433 .stencil_export = true,
434 .storage_8bit = true,
435 .storage_16bit = true,
436 .storage_image_ms = true,
437 .subgroup_arithmetic = true,
438 .subgroup_ballot = true,
439 .subgroup_basic = true,
440 .subgroup_quad = true,
441 .subgroup_shuffle = true,
442 .subgroup_vote = true,
443 .tessellation = true,
444 .transform_feedback = true,
445 .variable_pointers = true,
446 .vk_memory_model = true,
447 .vk_memory_model_device_scope = true,
448 },
449 .ubo_addr_format = nir_address_format_32bit_index_offset,
450 .ssbo_addr_format = nir_address_format_32bit_index_offset,
451 .phys_ssbo_addr_format = nir_address_format_64bit_global,
452 .push_const_addr_format = nir_address_format_logical,
453 .shared_addr_format = nir_address_format_32bit_offset,
454 .frag_coord_is_sysval = true,
455 .debug = {
456 .func = radv_spirv_nir_debug,
457 .private_data = &spirv_debug_data,
458 },
459 };
460 nir = spirv_to_nir(spirv, module->size / 4,
461 spec_entries, num_spec_entries,
462 stage, entrypoint_name,
463 &spirv_options, nir_options);
464 assert(nir->info.stage == stage);
465 nir_validate_shader(nir, "after spirv_to_nir");
466
467 free(spec_entries);
468
469 /* We have to lower away local constant initializers right before we
470 * inline functions. That way they get properly initialized at the top
471 * of the function and not at the top of its caller.
472 */
473 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
474 NIR_PASS_V(nir, nir_lower_returns);
475 NIR_PASS_V(nir, nir_inline_functions);
476 NIR_PASS_V(nir, nir_copy_prop);
477 NIR_PASS_V(nir, nir_opt_deref);
478
479 /* Pick off the single entrypoint that we want */
480 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
481 if (func->is_entrypoint)
482 func->name = ralloc_strdup(func, "main");
483 else
484 exec_node_remove(&func->node);
485 }
486 assert(exec_list_length(&nir->functions) == 1);
487
488 /* Make sure we lower constant initializers on output variables so that
489 * nir_remove_dead_variables below sees the corresponding stores
490 */
491 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
492
493 /* Now that we've deleted all but the main function, we can go ahead and
494 * lower the rest of the constant initializers.
495 */
496 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
497
498 /* Split member structs. We do this before lower_io_to_temporaries so that
499 * it doesn't lower system values to temporaries by accident.
500 */
501 NIR_PASS_V(nir, nir_split_var_copies);
502 NIR_PASS_V(nir, nir_split_per_member_structs);
503
504 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
505 !radv_use_llvm_for_stage(device, nir->info.stage))
506 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
507 if (nir->info.stage == MESA_SHADER_FRAGMENT)
508 NIR_PASS_V(nir, nir_lower_input_attachments,
509 &(nir_input_attachment_options) {
510 .use_fragcoord_sysval = true,
511 .use_layer_id_sysval = false,
512 });
513
514 NIR_PASS_V(nir, nir_remove_dead_variables,
515 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
516 NULL);
517
518 NIR_PASS_V(nir, nir_propagate_invariant);
519
520 NIR_PASS_V(nir, nir_lower_system_values);
521 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
522
523 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
524 NIR_PASS_V(nir, nir_lower_discard_to_demote);
525
526 nir_lower_doubles_options lower_doubles =
527 nir->options->lower_doubles_options;
528
529 if (device->physical_device->rad_info.chip_class == GFX6) {
530 /* GFX6 doesn't support v_floor_f64 and the precision
531 * of v_fract_f64 which is used to implement 64-bit
532 * floor is less than what Vulkan requires.
533 */
534 lower_doubles |= nir_lower_dfloor;
535 }
536
537 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
538 }
539
540 /* Vulkan uses the separate-shader linking model */
541 nir->info.separate_shader = true;
542
543 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
544
545 if (nir->info.stage == MESA_SHADER_GEOMETRY)
546 nir_lower_gs_intrinsics(nir, true);
547
548 static const nir_lower_tex_options tex_options = {
549 .lower_txp = ~0,
550 .lower_tg4_offsets = true,
551 };
552
553 nir_lower_tex(nir, &tex_options);
554
555 nir_lower_vars_to_ssa(nir);
556
557 if (nir->info.stage == MESA_SHADER_VERTEX ||
558 nir->info.stage == MESA_SHADER_GEOMETRY ||
559 nir->info.stage == MESA_SHADER_FRAGMENT) {
560 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
561 nir_shader_get_entrypoint(nir), true, true);
562 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
563 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
564 nir_shader_get_entrypoint(nir), true, false);
565 }
566
567 nir_split_var_copies(nir);
568
569 nir_lower_global_vars_to_local(nir);
570 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
571 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
572 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
573 .subgroup_size = subgroup_size,
574 .ballot_bit_size = ballot_bit_size,
575 .lower_to_scalar = 1,
576 .lower_subgroup_masks = 1,
577 .lower_shuffle = 1,
578 .lower_shuffle_to_32bit = 1,
579 .lower_vote_eq_to_ballot = 1,
580 .lower_quad_broadcast_dynamic = 1,
581 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
582 .lower_shuffle_to_swizzle_amd = 1,
583 });
584
585 nir_lower_load_const_to_scalar(nir);
586
587 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
588 radv_optimize_nir(nir, false, true);
589
590 /* call radv_nir_lower_ycbcr_textures() late as there might still be
591 * tex with undef texture/sampler before first optimization */
592 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
593
594 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
595 * to remove any copies introduced by nir_opt_find_array_copies().
596 */
597 nir_lower_var_copies(nir);
598
599 /* Lower deref operations for compute shared memory. */
600 if (nir->info.stage == MESA_SHADER_COMPUTE) {
601 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
602 nir_var_mem_shared, shared_var_info);
603 NIR_PASS_V(nir, nir_lower_explicit_io,
604 nir_var_mem_shared, nir_address_format_32bit_offset);
605 }
606
607 /* Lower large variables that are always constant with load_constant
608 * intrinsics, which get turned into PC-relative loads from a data
609 * section next to the shader.
610 */
611 NIR_PASS_V(nir, nir_opt_large_constants,
612 glsl_get_natural_size_align_bytes, 16);
613
614 /* Indirect lowering must be called after the radv_optimize_nir() loop
615 * has been called at least once. Otherwise indirect lowering can
616 * bloat the instruction count of the loop and cause it to be
617 * considered too large for unrolling.
618 */
619 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
620 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
621
622 return nir;
623 }
624
625 static int
626 type_size_vec4(const struct glsl_type *type, bool bindless)
627 {
628 return glsl_count_attribute_slots(type, false);
629 }
630
631 static nir_variable *
632 find_layer_in_var(nir_shader *nir)
633 {
634 nir_variable *var =
635 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
636 if (var != NULL)
637 return var;
638
639 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
640 var->data.location = VARYING_SLOT_LAYER;
641 var->data.interpolation = INTERP_MODE_FLAT;
642 return var;
643 }
644
645 /* We use layered rendering to implement multiview, which means we need to map
646 * view_index to gl_Layer. The code generates a load from the layer_id sysval,
647 * but since we don't have a way to get at this information from the fragment
648 * shader, we also need to lower this to the gl_Layer varying. This pass
649 * lowers both to a varying load from the LAYER slot, before lowering io, so
650 * that nir_assign_var_locations() will give the LAYER varying the correct
651 * driver_location.
652 */
653
654 static bool
655 lower_view_index(nir_shader *nir)
656 {
657 bool progress = false;
658 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
659 nir_builder b;
660 nir_builder_init(&b, entry);
661
662 nir_variable *layer = NULL;
663 nir_foreach_block(block, entry) {
664 nir_foreach_instr_safe(instr, block) {
665 if (instr->type != nir_instr_type_intrinsic)
666 continue;
667
668 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
669 if (load->intrinsic != nir_intrinsic_load_view_index)
670 continue;
671
672 if (!layer)
673 layer = find_layer_in_var(nir);
674
675 b.cursor = nir_before_instr(instr);
676 nir_ssa_def *def = nir_load_var(&b, layer);
677 nir_ssa_def_rewrite_uses(&load->dest.ssa,
678 nir_src_for_ssa(def));
679
680 nir_instr_remove(instr);
681 progress = true;
682 }
683 }
684
685 return progress;
686 }
687
688 void
689 radv_lower_fs_io(nir_shader *nir)
690 {
691 NIR_PASS_V(nir, lower_view_index);
692 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
693 MESA_SHADER_FRAGMENT);
694
695 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
696
697 /* This pass needs actual constants */
698 nir_opt_constant_folding(nir);
699
700 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
701 }
702
703
704 static void *
705 radv_alloc_shader_memory(struct radv_device *device,
706 struct radv_shader_variant *shader)
707 {
708 mtx_lock(&device->shader_slab_mutex);
709 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
710 uint64_t offset = 0;
711 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
712 if (s->bo_offset - offset >= shader->code_size) {
713 shader->bo = slab->bo;
714 shader->bo_offset = offset;
715 list_addtail(&shader->slab_list, &s->slab_list);
716 mtx_unlock(&device->shader_slab_mutex);
717 return slab->ptr + offset;
718 }
719 offset = align_u64(s->bo_offset + s->code_size, 256);
720 }
721 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
722 shader->bo = slab->bo;
723 shader->bo_offset = offset;
724 list_addtail(&shader->slab_list, &slab->shaders);
725 mtx_unlock(&device->shader_slab_mutex);
726 return slab->ptr + offset;
727 }
728 }
729
730 mtx_unlock(&device->shader_slab_mutex);
731 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
732
733 slab->size = MAX2(256 * 1024, shader->code_size);
734 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
735 RADEON_DOMAIN_VRAM,
736 RADEON_FLAG_NO_INTERPROCESS_SHARING |
737 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
738 0 : RADEON_FLAG_READ_ONLY),
739 RADV_BO_PRIORITY_SHADER);
740 if (!slab->bo) {
741 free(slab);
742 return NULL;
743 }
744
745 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
746 if (!slab->ptr) {
747 device->ws->buffer_destroy(slab->bo);
748 free(slab);
749 return NULL;
750 }
751
752 list_inithead(&slab->shaders);
753
754 mtx_lock(&device->shader_slab_mutex);
755 list_add(&slab->slabs, &device->shader_slabs);
756
757 shader->bo = slab->bo;
758 shader->bo_offset = 0;
759 list_add(&shader->slab_list, &slab->shaders);
760 mtx_unlock(&device->shader_slab_mutex);
761 return slab->ptr;
762 }
763
764 void
765 radv_destroy_shader_slabs(struct radv_device *device)
766 {
767 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
768 device->ws->buffer_destroy(slab->bo);
769 free(slab);
770 }
771 mtx_destroy(&device->shader_slab_mutex);
772 }
773
774 /* For the UMR disassembler. */
775 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
776 #define DEBUGGER_NUM_MARKERS 5
777
778 static unsigned
779 radv_get_shader_binary_size(size_t code_size)
780 {
781 return code_size + DEBUGGER_NUM_MARKERS * 4;
782 }
783
784 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
785 const struct ac_shader_config *config_in,
786 const struct radv_shader_info *info,
787 gl_shader_stage stage,
788 struct ac_shader_config *config_out)
789 {
790 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
791 unsigned vgpr_comp_cnt = 0;
792 unsigned num_input_vgprs = info->num_input_vgprs;
793
794 if (stage == MESA_SHADER_FRAGMENT) {
795 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
796 }
797
798 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
799 /* +3 for scratch wave offset and VCC */
800 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
801 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
802 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
803 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
804 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
805 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
806
807 *config_out = *config_in;
808 config_out->num_vgprs = num_vgprs;
809 config_out->num_sgprs = num_sgprs;
810 config_out->num_shared_vgprs = num_shared_vgprs;
811
812 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
813 S_00B12C_SCRATCH_EN(scratch_enabled);
814
815 if (!pdevice->use_ngg_streamout) {
816 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
817 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
818 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
819 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
820 S_00B12C_SO_EN(!!info->so.num_outputs);
821 }
822
823 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
824 (info->wave_size == 32 ? 8 : 4)) |
825 S_00B848_DX10_CLAMP(1) |
826 S_00B848_FLOAT_MODE(config_out->float_mode);
827
828 if (pdevice->rad_info.chip_class >= GFX10) {
829 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
830 } else {
831 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
832 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
833 }
834
835 switch (stage) {
836 case MESA_SHADER_TESS_EVAL:
837 if (info->is_ngg) {
838 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
839 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
840 } else if (info->tes.as_es) {
841 assert(pdevice->rad_info.chip_class <= GFX8);
842 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
843
844 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
845 } else {
846 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
847 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
848
849 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
850 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
851 }
852 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
853 break;
854 case MESA_SHADER_TESS_CTRL:
855 if (pdevice->rad_info.chip_class >= GFX9) {
856 /* We need at least 2 components for LS.
857 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
858 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
859 */
860 if (pdevice->rad_info.chip_class >= GFX10) {
861 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
862 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
863 } else {
864 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
865 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
866 }
867 } else {
868 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
869 }
870 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
871 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
872 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
873 break;
874 case MESA_SHADER_VERTEX:
875 if (info->is_ngg) {
876 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
877 } else if (info->vs.as_ls) {
878 assert(pdevice->rad_info.chip_class <= GFX8);
879 /* We need at least 2 components for LS.
880 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
881 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
882 */
883 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
884 } else if (info->vs.as_es) {
885 assert(pdevice->rad_info.chip_class <= GFX8);
886 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
887 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
888 } else {
889 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
890 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
891 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
892 */
893 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
894 vgpr_comp_cnt = 3;
895 } else if (info->vs.export_prim_id) {
896 vgpr_comp_cnt = 2;
897 } else if (info->vs.needs_instance_id) {
898 vgpr_comp_cnt = 1;
899 } else {
900 vgpr_comp_cnt = 0;
901 }
902
903 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
904 }
905 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
906 break;
907 case MESA_SHADER_FRAGMENT:
908 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
909 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
910 break;
911 case MESA_SHADER_GEOMETRY:
912 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
913 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
914 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
915 break;
916 case MESA_SHADER_COMPUTE:
917 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
918 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
919 config_out->rsrc2 |=
920 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
921 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
922 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
923 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
924 info->cs.uses_thread_id[1] ? 1 : 0) |
925 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
926 S_00B84C_LDS_SIZE(config_in->lds_size);
927 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
928
929 break;
930 default:
931 unreachable("unsupported shader type");
932 break;
933 }
934
935 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
936 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
937 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
938 gl_shader_stage es_stage = stage;
939 if (stage == MESA_SHADER_GEOMETRY)
940 es_stage = info->gs.es_type;
941
942 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
943 if (es_stage == MESA_SHADER_VERTEX) {
944 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
945 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
946 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
947 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
948 } else
949 unreachable("Unexpected ES shader stage");
950
951 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
952 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
953 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
954 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
955 } else if (info->uses_prim_id) {
956 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
957 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
958 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
959 } else {
960 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
961 }
962
963 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
964 S_00B228_WGP_MODE(1);
965 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
966 S_00B22C_LDS_SIZE(config_in->lds_size) |
967 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
968 } else if (pdevice->rad_info.chip_class >= GFX9 &&
969 stage == MESA_SHADER_GEOMETRY) {
970 unsigned es_type = info->gs.es_type;
971 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
972
973 if (es_type == MESA_SHADER_VERTEX) {
974 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
975 if (info->vs.needs_instance_id) {
976 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
977 } else {
978 es_vgpr_comp_cnt = 0;
979 }
980 } else if (es_type == MESA_SHADER_TESS_EVAL) {
981 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
982 } else {
983 unreachable("invalid shader ES type");
984 }
985
986 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
987 * VGPR[0:4] are always loaded.
988 */
989 if (info->uses_invocation_id) {
990 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
991 } else if (info->uses_prim_id) {
992 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
993 } else if (info->gs.vertices_in >= 3) {
994 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
995 } else {
996 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
997 }
998
999 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
1000 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1001 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
1002 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1003 stage == MESA_SHADER_TESS_CTRL) {
1004 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
1005 } else {
1006 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
1007 }
1008 }
1009
1010 struct radv_shader_variant *
1011 radv_shader_variant_create(struct radv_device *device,
1012 const struct radv_shader_binary *binary,
1013 bool keep_shader_info)
1014 {
1015 struct ac_shader_config config = {0};
1016 struct ac_rtld_binary rtld_binary = {0};
1017 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
1018 if (!variant)
1019 return NULL;
1020
1021 variant->ref_count = 1;
1022
1023 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1024 struct ac_rtld_symbol lds_symbols[2];
1025 unsigned num_lds_symbols = 0;
1026 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
1027 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
1028
1029 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1030 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
1031 !binary->is_gs_copy_shader) {
1032 /* We add this symbol even on LLVM <= 8 to ensure that
1033 * shader->config.lds_size is set correctly below.
1034 */
1035 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1036 sym->name = "esgs_ring";
1037 sym->size = binary->info.ngg_info.esgs_ring_size;
1038 sym->align = 64 * 1024;
1039 }
1040
1041 if (binary->info.is_ngg &&
1042 binary->stage == MESA_SHADER_GEOMETRY) {
1043 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1044 sym->name = "ngg_emit";
1045 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1046 sym->align = 4;
1047 }
1048
1049 struct ac_rtld_open_info open_info = {
1050 .info = &device->physical_device->rad_info,
1051 .shader_type = binary->stage,
1052 .wave_size = binary->info.wave_size,
1053 .num_parts = 1,
1054 .elf_ptrs = &elf_data,
1055 .elf_sizes = &elf_size,
1056 .num_shared_lds_symbols = num_lds_symbols,
1057 .shared_lds_symbols = lds_symbols,
1058 };
1059
1060 if (!ac_rtld_open(&rtld_binary, open_info)) {
1061 free(variant);
1062 return NULL;
1063 }
1064
1065 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1066 &rtld_binary, &config)) {
1067 ac_rtld_close(&rtld_binary);
1068 free(variant);
1069 return NULL;
1070 }
1071
1072 if (rtld_binary.lds_size > 0) {
1073 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1074 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1075 }
1076
1077 variant->code_size = rtld_binary.rx_size;
1078 variant->exec_size = rtld_binary.exec_size;
1079 } else {
1080 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1081 config = ((struct radv_shader_binary_legacy *)binary)->config;
1082 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1083 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1084 }
1085
1086 variant->info = binary->info;
1087 radv_postprocess_config(device->physical_device, &config, &binary->info,
1088 binary->stage, &variant->config);
1089
1090 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1091 if (!dest_ptr) {
1092 if (binary->type == RADV_BINARY_TYPE_RTLD)
1093 ac_rtld_close(&rtld_binary);
1094 free(variant);
1095 return NULL;
1096 }
1097
1098 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1099 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1100 struct ac_rtld_upload_info info = {
1101 .binary = &rtld_binary,
1102 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1103 .rx_ptr = dest_ptr,
1104 };
1105
1106 if (!ac_rtld_upload(&info)) {
1107 radv_shader_variant_destroy(device, variant);
1108 ac_rtld_close(&rtld_binary);
1109 return NULL;
1110 }
1111
1112 if (keep_shader_info ||
1113 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1114 const char *disasm_data;
1115 size_t disasm_size;
1116 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1117 radv_shader_variant_destroy(device, variant);
1118 ac_rtld_close(&rtld_binary);
1119 return NULL;
1120 }
1121
1122 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1123 variant->disasm_string = malloc(disasm_size + 1);
1124 memcpy(variant->disasm_string, disasm_data, disasm_size);
1125 variant->disasm_string[disasm_size] = 0;
1126 }
1127
1128 ac_rtld_close(&rtld_binary);
1129 } else {
1130 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1131 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1132
1133 /* Add end-of-code markers for the UMR disassembler. */
1134 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1135 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1136 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1137
1138 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1139 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1140
1141 if (bin->stats_size) {
1142 variant->statistics = calloc(bin->stats_size, 1);
1143 memcpy(variant->statistics, bin->data, bin->stats_size);
1144 }
1145 }
1146 return variant;
1147 }
1148
1149 static char *
1150 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1151 int shader_count)
1152 {
1153 char *data = NULL;
1154 char *ret = NULL;
1155 size_t size = 0;
1156 FILE *f = open_memstream(&data, &size);
1157 if (f) {
1158 for (int i = 0; i < shader_count; ++i)
1159 nir_print_shader(shaders[i], f);
1160 fclose(f);
1161 }
1162
1163 ret = malloc(size + 1);
1164 if (ret) {
1165 memcpy(ret, data, size);
1166 ret[size] = 0;
1167 }
1168 free(data);
1169 return ret;
1170 }
1171
1172 static struct radv_shader_variant *
1173 shader_variant_compile(struct radv_device *device,
1174 struct radv_shader_module *module,
1175 struct nir_shader * const *shaders,
1176 int shader_count,
1177 gl_shader_stage stage,
1178 struct radv_shader_info *info,
1179 struct radv_nir_compiler_options *options,
1180 bool gs_copy_shader,
1181 bool keep_shader_info,
1182 bool keep_statistic_info,
1183 struct radv_shader_binary **binary_out)
1184 {
1185 enum radeon_family chip_family = device->physical_device->rad_info.family;
1186 struct radv_shader_binary *binary = NULL;
1187
1188 options->family = chip_family;
1189 options->chip_class = device->physical_device->rad_info.chip_class;
1190 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1191 options->dump_preoptir = options->dump_shader &&
1192 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1193 options->record_ir = keep_shader_info;
1194 options->record_stats = keep_statistic_info;
1195 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1196 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1197 options->address32_hi = device->physical_device->rad_info.address32_hi;
1198 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1199 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1200 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1201
1202 struct radv_shader_args args = {};
1203 args.options = options;
1204 args.shader_info = info;
1205 args.is_gs_copy_shader = gs_copy_shader;
1206 radv_declare_shader_args(&args,
1207 gs_copy_shader ? MESA_SHADER_VERTEX
1208 : shaders[shader_count - 1]->info.stage,
1209 shader_count >= 2,
1210 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1211 : MESA_SHADER_VERTEX);
1212
1213 if (radv_use_llvm_for_stage(device, stage) ||
1214 options->dump_shader || options->record_ir)
1215 ac_init_llvm_once();
1216
1217 if (radv_use_llvm_for_stage(device, stage)) {
1218 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1219 } else {
1220 aco_compile_shader(shader_count, shaders, &binary, &args);
1221 }
1222
1223 binary->info = *info;
1224
1225 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1226 keep_shader_info);
1227 if (!variant) {
1228 free(binary);
1229 return NULL;
1230 }
1231
1232 if (options->dump_shader) {
1233 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1234 for (int i = 1; i < shader_count; ++i)
1235 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1236
1237 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1238 }
1239
1240
1241 if (keep_shader_info) {
1242 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1243 if (!gs_copy_shader && !module->nir) {
1244 variant->spirv = malloc(module->size);
1245 if (!variant->spirv) {
1246 free(variant);
1247 free(binary);
1248 return NULL;
1249 }
1250
1251 memcpy(variant->spirv, module->data, module->size);
1252 variant->spirv_size = module->size;
1253 }
1254 }
1255
1256 if (binary_out)
1257 *binary_out = binary;
1258 else
1259 free(binary);
1260
1261 return variant;
1262 }
1263
1264 struct radv_shader_variant *
1265 radv_shader_variant_compile(struct radv_device *device,
1266 struct radv_shader_module *module,
1267 struct nir_shader *const *shaders,
1268 int shader_count,
1269 struct radv_pipeline_layout *layout,
1270 const struct radv_shader_variant_key *key,
1271 struct radv_shader_info *info,
1272 bool keep_shader_info, bool keep_statistic_info,
1273 struct radv_shader_binary **binary_out)
1274 {
1275 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
1276 struct radv_nir_compiler_options options = {0};
1277
1278 options.layout = layout;
1279 if (key)
1280 options.key = *key;
1281
1282 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1283 options.robust_buffer_access = device->robust_buffer_access;
1284
1285 return shader_variant_compile(device, module, shaders, shader_count, stage, info,
1286 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1287 }
1288
1289 struct radv_shader_variant *
1290 radv_create_gs_copy_shader(struct radv_device *device,
1291 struct nir_shader *shader,
1292 struct radv_shader_info *info,
1293 struct radv_shader_binary **binary_out,
1294 bool keep_shader_info, bool keep_statistic_info,
1295 bool multiview)
1296 {
1297 struct radv_nir_compiler_options options = {0};
1298 gl_shader_stage stage = MESA_SHADER_VERTEX;
1299
1300 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1301 options.key.has_multiview_view_index = multiview;
1302
1303 return shader_variant_compile(device, NULL, &shader, 1, stage,
1304 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1305 }
1306
1307 void
1308 radv_shader_variant_destroy(struct radv_device *device,
1309 struct radv_shader_variant *variant)
1310 {
1311 if (!p_atomic_dec_zero(&variant->ref_count))
1312 return;
1313
1314 mtx_lock(&device->shader_slab_mutex);
1315 list_del(&variant->slab_list);
1316 mtx_unlock(&device->shader_slab_mutex);
1317
1318 free(variant->spirv);
1319 free(variant->nir_string);
1320 free(variant->disasm_string);
1321 free(variant->ir_string);
1322 free(variant->statistics);
1323 free(variant);
1324 }
1325
1326 const char *
1327 radv_get_shader_name(struct radv_shader_info *info,
1328 gl_shader_stage stage)
1329 {
1330 switch (stage) {
1331 case MESA_SHADER_VERTEX:
1332 if (info->vs.as_ls)
1333 return "Vertex Shader as LS";
1334 else if (info->vs.as_es)
1335 return "Vertex Shader as ES";
1336 else if (info->is_ngg)
1337 return "Vertex Shader as ESGS";
1338 else
1339 return "Vertex Shader as VS";
1340 case MESA_SHADER_TESS_CTRL:
1341 return "Tessellation Control Shader";
1342 case MESA_SHADER_TESS_EVAL:
1343 if (info->tes.as_es)
1344 return "Tessellation Evaluation Shader as ES";
1345 else if (info->is_ngg)
1346 return "Tessellation Evaluation Shader as ESGS";
1347 else
1348 return "Tessellation Evaluation Shader as VS";
1349 case MESA_SHADER_GEOMETRY:
1350 return "Geometry Shader";
1351 case MESA_SHADER_FRAGMENT:
1352 return "Pixel Shader";
1353 case MESA_SHADER_COMPUTE:
1354 return "Compute Shader";
1355 default:
1356 return "Unknown shader";
1357 };
1358 }
1359
1360 unsigned
1361 radv_get_max_workgroup_size(enum chip_class chip_class,
1362 gl_shader_stage stage,
1363 const unsigned *sizes)
1364 {
1365 switch (stage) {
1366 case MESA_SHADER_TESS_CTRL:
1367 return chip_class >= GFX7 ? 128 : 64;
1368 case MESA_SHADER_GEOMETRY:
1369 return chip_class >= GFX9 ? 128 : 64;
1370 case MESA_SHADER_COMPUTE:
1371 break;
1372 default:
1373 return 0;
1374 }
1375
1376 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1377 return max_workgroup_size;
1378 }
1379
1380 unsigned
1381 radv_get_max_waves(struct radv_device *device,
1382 struct radv_shader_variant *variant,
1383 gl_shader_stage stage)
1384 {
1385 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1386 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1387 uint8_t wave_size = variant->info.wave_size;
1388 struct ac_shader_config *conf = &variant->config;
1389 unsigned max_simd_waves;
1390 unsigned lds_per_wave = 0;
1391
1392 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1393
1394 if (stage == MESA_SHADER_FRAGMENT) {
1395 lds_per_wave = conf->lds_size * lds_increment +
1396 align(variant->info.ps.num_interp * 48,
1397 lds_increment);
1398 } else if (stage == MESA_SHADER_COMPUTE) {
1399 unsigned max_workgroup_size =
1400 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1401 lds_per_wave = (conf->lds_size * lds_increment) /
1402 DIV_ROUND_UP(max_workgroup_size, wave_size);
1403 }
1404
1405 if (conf->num_sgprs) {
1406 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1407 max_simd_waves =
1408 MIN2(max_simd_waves,
1409 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1410 sgprs);
1411 }
1412
1413 if (conf->num_vgprs) {
1414 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1415 max_simd_waves =
1416 MIN2(max_simd_waves,
1417 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1418 }
1419
1420 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1421 if (lds_per_wave)
1422 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1423
1424 return max_simd_waves;
1425 }
1426
1427 static void
1428 generate_shader_stats(struct radv_device *device,
1429 struct radv_shader_variant *variant,
1430 gl_shader_stage stage,
1431 struct _mesa_string_buffer *buf)
1432 {
1433 struct ac_shader_config *conf = &variant->config;
1434 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1435
1436 if (stage == MESA_SHADER_FRAGMENT) {
1437 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1438 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1439 "SPI_PS_INPUT_ENA = 0x%04x\n",
1440 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1441 }
1442
1443 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1444 "SGPRS: %d\n"
1445 "VGPRS: %d\n"
1446 "Spilled SGPRs: %d\n"
1447 "Spilled VGPRs: %d\n"
1448 "PrivMem VGPRS: %d\n"
1449 "Code Size: %d bytes\n"
1450 "LDS: %d blocks\n"
1451 "Scratch: %d bytes per wave\n"
1452 "Max Waves: %d\n",
1453 conf->num_sgprs, conf->num_vgprs,
1454 conf->spilled_sgprs, conf->spilled_vgprs,
1455 variant->info.private_mem_vgprs, variant->exec_size,
1456 conf->lds_size, conf->scratch_bytes_per_wave,
1457 max_simd_waves);
1458
1459 if (variant->statistics) {
1460 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1461 for (unsigned i = 0; i < variant->statistics->count; i++) {
1462 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1463 uint32_t value = variant->statistics->values[i];
1464 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1465 }
1466 }
1467
1468 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1469 }
1470
1471 void
1472 radv_shader_dump_stats(struct radv_device *device,
1473 struct radv_shader_variant *variant,
1474 gl_shader_stage stage,
1475 FILE *file)
1476 {
1477 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1478
1479 generate_shader_stats(device, variant, stage, buf);
1480
1481 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1482 fprintf(file, "%s", buf->buf);
1483
1484 _mesa_string_buffer_destroy(buf);
1485 }
1486
1487 VkResult
1488 radv_GetShaderInfoAMD(VkDevice _device,
1489 VkPipeline _pipeline,
1490 VkShaderStageFlagBits shaderStage,
1491 VkShaderInfoTypeAMD infoType,
1492 size_t* pInfoSize,
1493 void* pInfo)
1494 {
1495 RADV_FROM_HANDLE(radv_device, device, _device);
1496 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1497 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1498 struct radv_shader_variant *variant = pipeline->shaders[stage];
1499 struct _mesa_string_buffer *buf;
1500 VkResult result = VK_SUCCESS;
1501
1502 /* Spec doesn't indicate what to do if the stage is invalid, so just
1503 * return no info for this. */
1504 if (!variant)
1505 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1506
1507 switch (infoType) {
1508 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1509 if (!pInfo) {
1510 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1511 } else {
1512 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1513 struct ac_shader_config *conf = &variant->config;
1514
1515 VkShaderStatisticsInfoAMD statistics = {};
1516 statistics.shaderStageMask = shaderStage;
1517 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1518 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1519 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1520
1521 if (stage == MESA_SHADER_COMPUTE) {
1522 unsigned *local_size = variant->info.cs.block_size;
1523 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1524
1525 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1526 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1527
1528 statistics.computeWorkGroupSize[0] = local_size[0];
1529 statistics.computeWorkGroupSize[1] = local_size[1];
1530 statistics.computeWorkGroupSize[2] = local_size[2];
1531 } else {
1532 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1533 }
1534
1535 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1536 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1537 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1538 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1539 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1540
1541 size_t size = *pInfoSize;
1542 *pInfoSize = sizeof(statistics);
1543
1544 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1545
1546 if (size < *pInfoSize)
1547 result = VK_INCOMPLETE;
1548 }
1549
1550 break;
1551 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1552 buf = _mesa_string_buffer_create(NULL, 1024);
1553
1554 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1555 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1556 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1557 generate_shader_stats(device, variant, stage, buf);
1558
1559 /* Need to include the null terminator. */
1560 size_t length = buf->length + 1;
1561
1562 if (!pInfo) {
1563 *pInfoSize = length;
1564 } else {
1565 size_t size = *pInfoSize;
1566 *pInfoSize = length;
1567
1568 memcpy(pInfo, buf->buf, MIN2(size, length));
1569
1570 if (size < length)
1571 result = VK_INCOMPLETE;
1572 }
1573
1574 _mesa_string_buffer_destroy(buf);
1575 break;
1576 default:
1577 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1578 result = VK_ERROR_FEATURE_NOT_PRESENT;
1579 break;
1580 }
1581
1582 return result;
1583 }