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c76975c22526d09edf175127dbb209d171054899
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 static const struct nir_shader_compiler_options nir_options_llvm = {
51 .vertex_id_zero_based = true,
52 .lower_scmp = true,
53 .lower_flrp16 = true,
54 .lower_flrp32 = true,
55 .lower_flrp64 = true,
56 .lower_device_index_to_zero = true,
57 .lower_fsat = true,
58 .lower_fdiv = true,
59 .lower_fmod = true,
60 .lower_bitfield_insert_to_bitfield_select = true,
61 .lower_bitfield_extract = true,
62 .lower_sub = true,
63 .lower_pack_snorm_2x16 = true,
64 .lower_pack_snorm_4x8 = true,
65 .lower_pack_unorm_2x16 = true,
66 .lower_pack_unorm_4x8 = true,
67 .lower_unpack_snorm_2x16 = true,
68 .lower_unpack_snorm_4x8 = true,
69 .lower_unpack_unorm_2x16 = true,
70 .lower_unpack_unorm_4x8 = true,
71 .lower_extract_byte = true,
72 .lower_extract_word = true,
73 .lower_ffma = true,
74 .lower_fpow = true,
75 .lower_mul_2x32_64 = true,
76 .lower_rotate = true,
77 .use_scoped_barrier = true,
78 .max_unroll_iterations = 32,
79 .use_interpolated_input_intrinsics = true,
80 /* nir_lower_int64() isn't actually called for the LLVM backend, but
81 * this helps the loop unrolling heuristics. */
82 .lower_int64_options = nir_lower_imul64 |
83 nir_lower_imul_high64 |
84 nir_lower_imul_2x32_64 |
85 nir_lower_divmod64 |
86 nir_lower_minmax64 |
87 nir_lower_iabs64,
88 .lower_doubles_options = nir_lower_drcp |
89 nir_lower_dsqrt |
90 nir_lower_drsq |
91 nir_lower_ddiv,
92 };
93
94 static const struct nir_shader_compiler_options nir_options_aco = {
95 .vertex_id_zero_based = true,
96 .lower_scmp = true,
97 .lower_flrp16 = true,
98 .lower_flrp32 = true,
99 .lower_flrp64 = true,
100 .lower_device_index_to_zero = true,
101 .lower_fdiv = true,
102 .lower_fmod = true,
103 .lower_bitfield_insert_to_bitfield_select = true,
104 .lower_bitfield_extract = true,
105 .lower_pack_snorm_2x16 = true,
106 .lower_pack_snorm_4x8 = true,
107 .lower_pack_unorm_2x16 = true,
108 .lower_pack_unorm_4x8 = true,
109 .lower_unpack_snorm_2x16 = true,
110 .lower_unpack_snorm_4x8 = true,
111 .lower_unpack_unorm_2x16 = true,
112 .lower_unpack_unorm_4x8 = true,
113 .lower_unpack_half_2x16 = true,
114 .lower_extract_byte = true,
115 .lower_extract_word = true,
116 .lower_ffma = true,
117 .lower_fpow = true,
118 .lower_mul_2x32_64 = true,
119 .lower_rotate = true,
120 .use_scoped_barrier = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_minmax64 |
128 nir_lower_iabs64,
129 .lower_doubles_options = nir_lower_drcp |
130 nir_lower_dsqrt |
131 nir_lower_drsq |
132 nir_lower_ddiv,
133 };
134
135 bool
136 radv_can_dump_shader(struct radv_device *device,
137 struct radv_shader_module *module,
138 bool is_gs_copy_shader)
139 {
140 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
141 return false;
142 if (module)
143 return !module->nir ||
144 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
145
146 return is_gs_copy_shader;
147 }
148
149 bool
150 radv_can_dump_shader_stats(struct radv_device *device,
151 struct radv_shader_module *module)
152 {
153 /* Only dump non-meta shader stats. */
154 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
155 module && !module->nir;
156 }
157
158 VkResult radv_CreateShaderModule(
159 VkDevice _device,
160 const VkShaderModuleCreateInfo* pCreateInfo,
161 const VkAllocationCallbacks* pAllocator,
162 VkShaderModule* pShaderModule)
163 {
164 RADV_FROM_HANDLE(radv_device, device, _device);
165 struct radv_shader_module *module;
166
167 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
168 assert(pCreateInfo->flags == 0);
169
170 module = vk_alloc2(&device->vk.alloc, pAllocator,
171 sizeof(*module) + pCreateInfo->codeSize, 8,
172 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
173 if (module == NULL)
174 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
175
176 vk_object_base_init(&device->vk, &module->base,
177 VK_OBJECT_TYPE_SHADER_MODULE);
178
179 module->nir = NULL;
180 module->size = pCreateInfo->codeSize;
181 memcpy(module->data, pCreateInfo->pCode, module->size);
182
183 _mesa_sha1_compute(module->data, module->size, module->sha1);
184
185 *pShaderModule = radv_shader_module_to_handle(module);
186
187 return VK_SUCCESS;
188 }
189
190 void radv_DestroyShaderModule(
191 VkDevice _device,
192 VkShaderModule _module,
193 const VkAllocationCallbacks* pAllocator)
194 {
195 RADV_FROM_HANDLE(radv_device, device, _device);
196 RADV_FROM_HANDLE(radv_shader_module, module, _module);
197
198 if (!module)
199 return;
200
201 vk_object_base_finish(&module->base);
202 vk_free2(&device->vk.alloc, pAllocator, module);
203 }
204
205 void
206 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
207 bool allow_copies)
208 {
209 bool progress;
210 unsigned lower_flrp =
211 (shader->options->lower_flrp16 ? 16 : 0) |
212 (shader->options->lower_flrp32 ? 32 : 0) |
213 (shader->options->lower_flrp64 ? 64 : 0);
214
215 do {
216 progress = false;
217
218 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
219 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
220
221 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
222 NIR_PASS_V(shader, nir_lower_pack);
223
224 if (allow_copies) {
225 /* Only run this pass in the first call to
226 * radv_optimize_nir. Later calls assume that we've
227 * lowered away any copy_deref instructions and we
228 * don't want to introduce any more.
229 */
230 NIR_PASS(progress, shader, nir_opt_find_array_copies);
231 }
232
233 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
234 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
235 NIR_PASS(progress, shader, nir_remove_dead_variables,
236 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
237 NULL);
238
239 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
240 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
241
242 NIR_PASS(progress, shader, nir_copy_prop);
243 NIR_PASS(progress, shader, nir_opt_remove_phis);
244 NIR_PASS(progress, shader, nir_opt_dce);
245 if (nir_opt_trivial_continues(shader)) {
246 progress = true;
247 NIR_PASS(progress, shader, nir_copy_prop);
248 NIR_PASS(progress, shader, nir_opt_remove_phis);
249 NIR_PASS(progress, shader, nir_opt_dce);
250 }
251 NIR_PASS(progress, shader, nir_opt_if, true);
252 NIR_PASS(progress, shader, nir_opt_dead_cf);
253 NIR_PASS(progress, shader, nir_opt_cse);
254 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
255 NIR_PASS(progress, shader, nir_opt_constant_folding);
256 NIR_PASS(progress, shader, nir_opt_algebraic);
257
258 if (lower_flrp != 0) {
259 bool lower_flrp_progress = false;
260 NIR_PASS(lower_flrp_progress,
261 shader,
262 nir_lower_flrp,
263 lower_flrp,
264 false /* always_precise */,
265 shader->options->lower_ffma);
266 if (lower_flrp_progress) {
267 NIR_PASS(progress, shader,
268 nir_opt_constant_folding);
269 progress = true;
270 }
271
272 /* Nothing should rematerialize any flrps, so we only
273 * need to do this lowering once.
274 */
275 lower_flrp = 0;
276 }
277
278 NIR_PASS(progress, shader, nir_opt_undef);
279 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
280 if (shader->options->max_unroll_iterations) {
281 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
282 }
283 } while (progress && !optimize_conservatively);
284
285 NIR_PASS(progress, shader, nir_opt_conditional_discard);
286 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
287 }
288
289 static void
290 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
291 {
292 assert(glsl_type_is_vector_or_scalar(type));
293
294 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
295 unsigned length = glsl_get_vector_elements(type);
296 *size = comp_size * length,
297 *align = comp_size;
298 }
299
300 struct radv_shader_debug_data {
301 struct radv_device *device;
302 const struct radv_shader_module *module;
303 };
304
305 static void radv_spirv_nir_debug(void *private_data,
306 enum nir_spirv_debug_level level,
307 size_t spirv_offset,
308 const char *message)
309 {
310 struct radv_shader_debug_data *debug_data = private_data;
311 struct radv_instance *instance = debug_data->device->instance;
312
313 static const VkDebugReportFlagsEXT vk_flags[] = {
314 [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
315 [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
316 [NIR_SPIRV_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
317 };
318 char buffer[256];
319
320 snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s",
321 (unsigned long)spirv_offset, message);
322
323 vk_debug_report(&instance->debug_report_callbacks,
324 vk_flags[level],
325 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
326 (uint64_t)(uintptr_t)debug_data->module,
327 0, 0, "radv", buffer);
328 }
329
330 static void radv_compiler_debug(void *private_data,
331 enum radv_compiler_debug_level level,
332 const char *message)
333 {
334 struct radv_shader_debug_data *debug_data = private_data;
335 struct radv_instance *instance = debug_data->device->instance;
336
337 static const VkDebugReportFlagsEXT vk_flags[] = {
338 [RADV_COMPILER_DEBUG_LEVEL_PERFWARN] = VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT,
339 [RADV_COMPILER_DEBUG_LEVEL_ERROR] = VK_DEBUG_REPORT_ERROR_BIT_EXT,
340 };
341
342 /* VK_DEBUG_REPORT_DEBUG_BIT_EXT specifies diagnostic information
343 * from the implementation and layers.
344 */
345 vk_debug_report(&instance->debug_report_callbacks,
346 vk_flags[level] | VK_DEBUG_REPORT_DEBUG_BIT_EXT,
347 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
348 (uint64_t)(uintptr_t)debug_data->module,
349 0, 0, "radv", message);
350 }
351
352 nir_shader *
353 radv_shader_compile_to_nir(struct radv_device *device,
354 struct radv_shader_module *module,
355 const char *entrypoint_name,
356 gl_shader_stage stage,
357 const VkSpecializationInfo *spec_info,
358 const VkPipelineCreateFlags flags,
359 const struct radv_pipeline_layout *layout,
360 unsigned subgroup_size, unsigned ballot_bit_size)
361 {
362 nir_shader *nir;
363 const nir_shader_compiler_options *nir_options =
364 radv_use_llvm_for_stage(device, stage) ? &nir_options_llvm : &nir_options_aco;
365
366 if (module->nir) {
367 /* Some things such as our meta clear/blit code will give us a NIR
368 * shader directly. In that case, we just ignore the SPIR-V entirely
369 * and just use the NIR shader */
370 nir = module->nir;
371 nir->options = nir_options;
372 nir_validate_shader(nir, "in internal shader");
373
374 assert(exec_list_length(&nir->functions) == 1);
375 } else {
376 uint32_t *spirv = (uint32_t *) module->data;
377 assert(module->size % 4 == 0);
378
379 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
380 radv_print_spirv(module->data, module->size, stderr);
381
382 uint32_t num_spec_entries = 0;
383 struct nir_spirv_specialization *spec_entries = NULL;
384 if (spec_info && spec_info->mapEntryCount > 0) {
385 num_spec_entries = spec_info->mapEntryCount;
386 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
387 for (uint32_t i = 0; i < num_spec_entries; i++) {
388 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
389 const void *data = spec_info->pData + entry.offset;
390 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
391
392 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
393 switch (entry.size) {
394 case 8:
395 spec_entries[i].value.u64 = *(const uint64_t *)data;
396 break;
397 case 4:
398 spec_entries[i].value.u32 = *(const uint32_t *)data;
399 break;
400 case 2:
401 spec_entries[i].value.u16 = *(const uint16_t *)data;
402 break;
403 case 1:
404 spec_entries[i].value.u8 = *(const uint8_t *)data;
405 break;
406 default:
407 assert(!"Invalid spec constant size");
408 break;
409 }
410 }
411 }
412
413 struct radv_shader_debug_data spirv_debug_data = {
414 .device = device,
415 .module = module,
416 };
417 const struct spirv_to_nir_options spirv_options = {
418 .lower_ubo_ssbo_access_to_offsets = true,
419 .caps = {
420 .amd_fragment_mask = true,
421 .amd_gcn_shader = true,
422 .amd_image_gather_bias_lod = true,
423 .amd_image_read_write_lod = true,
424 .amd_shader_ballot = true,
425 .amd_shader_explicit_vertex_parameter = true,
426 .amd_trinary_minmax = true,
427 .demote_to_helper_invocation = true,
428 .derivative_group = true,
429 .descriptor_array_dynamic_indexing = true,
430 .descriptor_array_non_uniform_indexing = true,
431 .descriptor_indexing = true,
432 .device_group = true,
433 .draw_parameters = true,
434 .float_controls = true,
435 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
436 .float32_atomic_add = true,
437 .float64 = true,
438 .geometry_streams = true,
439 .image_ms_array = true,
440 .image_read_without_format = true,
441 .image_write_without_format = true,
442 .int8 = true,
443 .int16 = true,
444 .int64 = true,
445 .int64_atomics = true,
446 .min_lod = true,
447 .multiview = true,
448 .physical_storage_buffer_address = true,
449 .post_depth_coverage = true,
450 .runtime_descriptor_array = true,
451 .shader_clock = true,
452 .shader_viewport_index_layer = true,
453 .stencil_export = true,
454 .storage_8bit = true,
455 .storage_16bit = true,
456 .storage_image_ms = true,
457 .subgroup_arithmetic = true,
458 .subgroup_ballot = true,
459 .subgroup_basic = true,
460 .subgroup_quad = true,
461 .subgroup_shuffle = true,
462 .subgroup_vote = true,
463 .tessellation = true,
464 .transform_feedback = true,
465 .variable_pointers = true,
466 .vk_memory_model = true,
467 .vk_memory_model_device_scope = true,
468 },
469 .ubo_addr_format = nir_address_format_32bit_index_offset,
470 .ssbo_addr_format = nir_address_format_32bit_index_offset,
471 .phys_ssbo_addr_format = nir_address_format_64bit_global,
472 .push_const_addr_format = nir_address_format_logical,
473 .shared_addr_format = nir_address_format_32bit_offset,
474 .frag_coord_is_sysval = true,
475 .debug = {
476 .func = radv_spirv_nir_debug,
477 .private_data = &spirv_debug_data,
478 },
479 };
480 nir = spirv_to_nir(spirv, module->size / 4,
481 spec_entries, num_spec_entries,
482 stage, entrypoint_name,
483 &spirv_options, nir_options);
484 assert(nir->info.stage == stage);
485 nir_validate_shader(nir, "after spirv_to_nir");
486
487 free(spec_entries);
488
489 /* We have to lower away local constant initializers right before we
490 * inline functions. That way they get properly initialized at the top
491 * of the function and not at the top of its caller.
492 */
493 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
494 NIR_PASS_V(nir, nir_lower_returns);
495 NIR_PASS_V(nir, nir_inline_functions);
496 NIR_PASS_V(nir, nir_copy_prop);
497 NIR_PASS_V(nir, nir_opt_deref);
498
499 /* Pick off the single entrypoint that we want */
500 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
501 if (func->is_entrypoint)
502 func->name = ralloc_strdup(func, "main");
503 else
504 exec_node_remove(&func->node);
505 }
506 assert(exec_list_length(&nir->functions) == 1);
507
508 /* Make sure we lower constant initializers on output variables so that
509 * nir_remove_dead_variables below sees the corresponding stores
510 */
511 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
512
513 /* Now that we've deleted all but the main function, we can go ahead and
514 * lower the rest of the constant initializers.
515 */
516 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
517
518 /* Split member structs. We do this before lower_io_to_temporaries so that
519 * it doesn't lower system values to temporaries by accident.
520 */
521 NIR_PASS_V(nir, nir_split_var_copies);
522 NIR_PASS_V(nir, nir_split_per_member_structs);
523
524 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
525 !radv_use_llvm_for_stage(device, nir->info.stage))
526 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
527 if (nir->info.stage == MESA_SHADER_FRAGMENT)
528 NIR_PASS_V(nir, nir_lower_input_attachments,
529 &(nir_input_attachment_options) {
530 .use_fragcoord_sysval = true,
531 .use_layer_id_sysval = false,
532 });
533
534 NIR_PASS_V(nir, nir_remove_dead_variables,
535 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
536 NULL);
537
538 NIR_PASS_V(nir, nir_propagate_invariant);
539
540 NIR_PASS_V(nir, nir_lower_system_values);
541 NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
542
543 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
544
545 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
546 NIR_PASS_V(nir, nir_lower_discard_to_demote);
547
548 nir_lower_doubles_options lower_doubles =
549 nir->options->lower_doubles_options;
550
551 if (device->physical_device->rad_info.chip_class == GFX6) {
552 /* GFX6 doesn't support v_floor_f64 and the precision
553 * of v_fract_f64 which is used to implement 64-bit
554 * floor is less than what Vulkan requires.
555 */
556 lower_doubles |= nir_lower_dfloor;
557 }
558
559 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
560 }
561
562 /* Vulkan uses the separate-shader linking model */
563 nir->info.separate_shader = true;
564
565 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
566
567 if (nir->info.stage == MESA_SHADER_GEOMETRY)
568 nir_lower_gs_intrinsics(nir, true);
569
570 static const nir_lower_tex_options tex_options = {
571 .lower_txp = ~0,
572 .lower_tg4_offsets = true,
573 };
574
575 nir_lower_tex(nir, &tex_options);
576
577 nir_lower_vars_to_ssa(nir);
578
579 if (nir->info.stage == MESA_SHADER_VERTEX ||
580 nir->info.stage == MESA_SHADER_GEOMETRY ||
581 nir->info.stage == MESA_SHADER_FRAGMENT) {
582 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
583 nir_shader_get_entrypoint(nir), true, true);
584 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
585 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
586 nir_shader_get_entrypoint(nir), true, false);
587 }
588
589 nir_split_var_copies(nir);
590
591 nir_lower_global_vars_to_local(nir);
592 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
593 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
594 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
595 .subgroup_size = subgroup_size,
596 .ballot_bit_size = ballot_bit_size,
597 .lower_to_scalar = 1,
598 .lower_subgroup_masks = 1,
599 .lower_shuffle = 1,
600 .lower_shuffle_to_32bit = 1,
601 .lower_vote_eq_to_ballot = 1,
602 .lower_quad_broadcast_dynamic = 1,
603 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
604 .lower_shuffle_to_swizzle_amd = 1,
605 });
606
607 nir_lower_load_const_to_scalar(nir);
608
609 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
610 radv_optimize_nir(nir, false, true);
611
612 /* call radv_nir_lower_ycbcr_textures() late as there might still be
613 * tex with undef texture/sampler before first optimization */
614 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
615
616 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
617 * to remove any copies introduced by nir_opt_find_array_copies().
618 */
619 nir_lower_var_copies(nir);
620
621 /* Lower deref operations for compute shared memory. */
622 if (nir->info.stage == MESA_SHADER_COMPUTE) {
623 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
624 nir_var_mem_shared, shared_var_info);
625 NIR_PASS_V(nir, nir_lower_explicit_io,
626 nir_var_mem_shared, nir_address_format_32bit_offset);
627 }
628
629 /* Lower large variables that are always constant with load_constant
630 * intrinsics, which get turned into PC-relative loads from a data
631 * section next to the shader.
632 */
633 NIR_PASS_V(nir, nir_opt_large_constants,
634 glsl_get_natural_size_align_bytes, 16);
635
636 /* Indirect lowering must be called after the radv_optimize_nir() loop
637 * has been called at least once. Otherwise indirect lowering can
638 * bloat the instruction count of the loop and cause it to be
639 * considered too large for unrolling.
640 */
641 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
642 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
643
644 return nir;
645 }
646
647 static int
648 type_size_vec4(const struct glsl_type *type, bool bindless)
649 {
650 return glsl_count_attribute_slots(type, false);
651 }
652
653 static nir_variable *
654 find_layer_in_var(nir_shader *nir)
655 {
656 nir_variable *var =
657 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
658 if (var != NULL)
659 return var;
660
661 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
662 var->data.location = VARYING_SLOT_LAYER;
663 var->data.interpolation = INTERP_MODE_FLAT;
664 return var;
665 }
666
667 /* We use layered rendering to implement multiview, which means we need to map
668 * view_index to gl_Layer. The code generates a load from the layer_id sysval,
669 * but since we don't have a way to get at this information from the fragment
670 * shader, we also need to lower this to the gl_Layer varying. This pass
671 * lowers both to a varying load from the LAYER slot, before lowering io, so
672 * that nir_assign_var_locations() will give the LAYER varying the correct
673 * driver_location.
674 */
675
676 static bool
677 lower_view_index(nir_shader *nir)
678 {
679 bool progress = false;
680 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
681 nir_builder b;
682 nir_builder_init(&b, entry);
683
684 nir_variable *layer = NULL;
685 nir_foreach_block(block, entry) {
686 nir_foreach_instr_safe(instr, block) {
687 if (instr->type != nir_instr_type_intrinsic)
688 continue;
689
690 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
691 if (load->intrinsic != nir_intrinsic_load_view_index)
692 continue;
693
694 if (!layer)
695 layer = find_layer_in_var(nir);
696
697 b.cursor = nir_before_instr(instr);
698 nir_ssa_def *def = nir_load_var(&b, layer);
699 nir_ssa_def_rewrite_uses(&load->dest.ssa,
700 nir_src_for_ssa(def));
701
702 nir_instr_remove(instr);
703 progress = true;
704 }
705 }
706
707 return progress;
708 }
709
710 void
711 radv_lower_fs_io(nir_shader *nir)
712 {
713 NIR_PASS_V(nir, lower_view_index);
714 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
715 MESA_SHADER_FRAGMENT);
716
717 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
718
719 /* This pass needs actual constants */
720 nir_opt_constant_folding(nir);
721
722 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
723 }
724
725
726 static void *
727 radv_alloc_shader_memory(struct radv_device *device,
728 struct radv_shader_variant *shader)
729 {
730 mtx_lock(&device->shader_slab_mutex);
731 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
732 uint64_t offset = 0;
733 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
734 if (s->bo_offset - offset >= shader->code_size) {
735 shader->bo = slab->bo;
736 shader->bo_offset = offset;
737 list_addtail(&shader->slab_list, &s->slab_list);
738 mtx_unlock(&device->shader_slab_mutex);
739 return slab->ptr + offset;
740 }
741 offset = align_u64(s->bo_offset + s->code_size, 256);
742 }
743 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
744 shader->bo = slab->bo;
745 shader->bo_offset = offset;
746 list_addtail(&shader->slab_list, &slab->shaders);
747 mtx_unlock(&device->shader_slab_mutex);
748 return slab->ptr + offset;
749 }
750 }
751
752 mtx_unlock(&device->shader_slab_mutex);
753 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
754
755 slab->size = MAX2(256 * 1024, shader->code_size);
756 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
757 RADEON_DOMAIN_VRAM,
758 RADEON_FLAG_NO_INTERPROCESS_SHARING |
759 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
760 0 : RADEON_FLAG_READ_ONLY),
761 RADV_BO_PRIORITY_SHADER);
762 if (!slab->bo) {
763 free(slab);
764 return NULL;
765 }
766
767 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
768 if (!slab->ptr) {
769 device->ws->buffer_destroy(slab->bo);
770 free(slab);
771 return NULL;
772 }
773
774 list_inithead(&slab->shaders);
775
776 mtx_lock(&device->shader_slab_mutex);
777 list_add(&slab->slabs, &device->shader_slabs);
778
779 shader->bo = slab->bo;
780 shader->bo_offset = 0;
781 list_add(&shader->slab_list, &slab->shaders);
782 mtx_unlock(&device->shader_slab_mutex);
783 return slab->ptr;
784 }
785
786 void
787 radv_destroy_shader_slabs(struct radv_device *device)
788 {
789 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
790 device->ws->buffer_destroy(slab->bo);
791 free(slab);
792 }
793 mtx_destroy(&device->shader_slab_mutex);
794 }
795
796 /* For the UMR disassembler. */
797 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
798 #define DEBUGGER_NUM_MARKERS 5
799
800 static unsigned
801 radv_get_shader_binary_size(size_t code_size)
802 {
803 return code_size + DEBUGGER_NUM_MARKERS * 4;
804 }
805
806 static void radv_postprocess_config(const struct radv_device *device,
807 const struct ac_shader_config *config_in,
808 const struct radv_shader_info *info,
809 gl_shader_stage stage,
810 struct ac_shader_config *config_out)
811 {
812 const struct radv_physical_device *pdevice = device->physical_device;
813 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
814 bool trap_enabled = !!device->trap_handler_shader;
815 unsigned vgpr_comp_cnt = 0;
816 unsigned num_input_vgprs = info->num_input_vgprs;
817
818 if (stage == MESA_SHADER_FRAGMENT) {
819 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
820 }
821
822 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
823 /* +3 for scratch wave offset and VCC */
824 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
825 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
826 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
827 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
828 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
829 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
830 unsigned excp_en = 0;
831
832 *config_out = *config_in;
833 config_out->num_vgprs = num_vgprs;
834 config_out->num_sgprs = num_sgprs;
835 config_out->num_shared_vgprs = num_shared_vgprs;
836
837 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
838 S_00B12C_SCRATCH_EN(scratch_enabled) |
839 S_00B12C_TRAP_PRESENT(trap_enabled);
840
841 if (trap_enabled) {
842 /* Configure the shader exceptions like memory violation, etc.
843 * TODO: Enable (and validate) more exceptions.
844 */
845 excp_en = 1 << 8; /* mem_viol */
846 }
847
848 if (!pdevice->use_ngg_streamout) {
849 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
850 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
851 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
852 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
853 S_00B12C_SO_EN(!!info->so.num_outputs);
854 }
855
856 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
857 (info->wave_size == 32 ? 8 : 4)) |
858 S_00B848_DX10_CLAMP(1) |
859 S_00B848_FLOAT_MODE(config_out->float_mode);
860
861 if (pdevice->rad_info.chip_class >= GFX10) {
862 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
863 } else {
864 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
865 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
866 }
867
868 switch (stage) {
869 case MESA_SHADER_TESS_EVAL:
870 if (info->is_ngg) {
871 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
872 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1) |
873 S_00B22C_EXCP_EN(excp_en);
874 } else if (info->tes.as_es) {
875 assert(pdevice->rad_info.chip_class <= GFX8);
876 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
877
878 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) |
879 S_00B12C_EXCP_EN(excp_en);
880 } else {
881 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
882 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
883
884 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
885 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) |
886 S_00B12C_EXCP_EN(excp_en);
887 }
888 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
889 break;
890 case MESA_SHADER_TESS_CTRL:
891 if (pdevice->rad_info.chip_class >= GFX9) {
892 /* We need at least 2 components for LS.
893 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
894 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
895 */
896 if (pdevice->rad_info.chip_class >= GFX10) {
897 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
898 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks) |
899 S_00B42C_EXCP_EN_GFX6(excp_en);
900 } else {
901 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
902 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks) |
903 S_00B42C_EXCP_EN_GFX9(excp_en);
904 }
905 } else {
906 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) |
907 S_00B12C_EXCP_EN(excp_en);
908 }
909 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
910 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
911 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
912 break;
913 case MESA_SHADER_VERTEX:
914 if (info->is_ngg) {
915 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
916 } else if (info->vs.as_ls) {
917 assert(pdevice->rad_info.chip_class <= GFX8);
918 /* We need at least 2 components for LS.
919 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
920 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
921 */
922 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
923 } else if (info->vs.as_es) {
924 assert(pdevice->rad_info.chip_class <= GFX8);
925 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
926 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
927 } else {
928 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
929 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
930 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
931 */
932 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
933 vgpr_comp_cnt = 3;
934 } else if (info->vs.export_prim_id) {
935 vgpr_comp_cnt = 2;
936 } else if (info->vs.needs_instance_id) {
937 vgpr_comp_cnt = 1;
938 } else {
939 vgpr_comp_cnt = 0;
940 }
941
942 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
943 }
944 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
945 S_00B12C_EXCP_EN(excp_en);
946 break;
947 case MESA_SHADER_FRAGMENT:
948 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
949 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
950 S_00B02C_TRAP_PRESENT(1) |
951 S_00B02C_EXCP_EN(excp_en);
952 break;
953 case MESA_SHADER_GEOMETRY:
954 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
955 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
956 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks) |
957 S_00B22C_EXCP_EN(excp_en);
958 break;
959 case MESA_SHADER_COMPUTE:
960 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
961 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
962 config_out->rsrc2 |=
963 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
964 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
965 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
966 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
967 info->cs.uses_thread_id[1] ? 1 : 0) |
968 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
969 S_00B84C_LDS_SIZE(config_in->lds_size) |
970 S_00B84C_EXCP_EN(excp_en);
971 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
972
973 break;
974 default:
975 unreachable("unsupported shader type");
976 break;
977 }
978
979 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
980 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
981 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
982 gl_shader_stage es_stage = stage;
983 if (stage == MESA_SHADER_GEOMETRY)
984 es_stage = info->gs.es_type;
985
986 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
987 if (es_stage == MESA_SHADER_VERTEX) {
988 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
989 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
990 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
991 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
992 } else
993 unreachable("Unexpected ES shader stage");
994
995 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
996 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
997 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
998 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
999 } else if (info->uses_prim_id) {
1000 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1001 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
1002 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1003 } else {
1004 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1005 }
1006
1007 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
1008 S_00B228_WGP_MODE(1);
1009 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1010 S_00B22C_LDS_SIZE(config_in->lds_size) |
1011 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
1012 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1013 stage == MESA_SHADER_GEOMETRY) {
1014 unsigned es_type = info->gs.es_type;
1015 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
1016
1017 if (es_type == MESA_SHADER_VERTEX) {
1018 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
1019 if (info->vs.needs_instance_id) {
1020 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
1021 } else {
1022 es_vgpr_comp_cnt = 0;
1023 }
1024 } else if (es_type == MESA_SHADER_TESS_EVAL) {
1025 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
1026 } else {
1027 unreachable("invalid shader ES type");
1028 }
1029
1030 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1031 * VGPR[0:4] are always loaded.
1032 */
1033 if (info->uses_invocation_id) {
1034 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1035 } else if (info->uses_prim_id) {
1036 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1037 } else if (info->gs.vertices_in >= 3) {
1038 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1039 } else {
1040 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1041 }
1042
1043 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
1044 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1045 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
1046 } else if (pdevice->rad_info.chip_class >= GFX9 &&
1047 stage == MESA_SHADER_TESS_CTRL) {
1048 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
1049 } else {
1050 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
1051 }
1052 }
1053
1054 struct radv_shader_variant *
1055 radv_shader_variant_create(struct radv_device *device,
1056 const struct radv_shader_binary *binary,
1057 bool keep_shader_info)
1058 {
1059 struct ac_shader_config config = {0};
1060 struct ac_rtld_binary rtld_binary = {0};
1061 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
1062 if (!variant)
1063 return NULL;
1064
1065 variant->ref_count = 1;
1066
1067 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1068 struct ac_rtld_symbol lds_symbols[2];
1069 unsigned num_lds_symbols = 0;
1070 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
1071 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
1072
1073 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1074 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
1075 !binary->is_gs_copy_shader) {
1076 /* We add this symbol even on LLVM <= 8 to ensure that
1077 * shader->config.lds_size is set correctly below.
1078 */
1079 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1080 sym->name = "esgs_ring";
1081 sym->size = binary->info.ngg_info.esgs_ring_size;
1082 sym->align = 64 * 1024;
1083 }
1084
1085 if (binary->info.is_ngg &&
1086 binary->stage == MESA_SHADER_GEOMETRY) {
1087 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1088 sym->name = "ngg_emit";
1089 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1090 sym->align = 4;
1091 }
1092
1093 struct ac_rtld_open_info open_info = {
1094 .info = &device->physical_device->rad_info,
1095 .shader_type = binary->stage,
1096 .wave_size = binary->info.wave_size,
1097 .num_parts = 1,
1098 .elf_ptrs = &elf_data,
1099 .elf_sizes = &elf_size,
1100 .num_shared_lds_symbols = num_lds_symbols,
1101 .shared_lds_symbols = lds_symbols,
1102 };
1103
1104 if (!ac_rtld_open(&rtld_binary, open_info)) {
1105 free(variant);
1106 return NULL;
1107 }
1108
1109 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1110 &rtld_binary, &config)) {
1111 ac_rtld_close(&rtld_binary);
1112 free(variant);
1113 return NULL;
1114 }
1115
1116 if (rtld_binary.lds_size > 0) {
1117 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1118 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1119 }
1120
1121 variant->code_size = rtld_binary.rx_size;
1122 variant->exec_size = rtld_binary.exec_size;
1123 } else {
1124 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1125 config = ((struct radv_shader_binary_legacy *)binary)->config;
1126 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1127 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1128 }
1129
1130 variant->info = binary->info;
1131 radv_postprocess_config(device, &config, &binary->info,
1132 binary->stage, &variant->config);
1133
1134 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1135 if (!dest_ptr) {
1136 if (binary->type == RADV_BINARY_TYPE_RTLD)
1137 ac_rtld_close(&rtld_binary);
1138 free(variant);
1139 return NULL;
1140 }
1141
1142 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1143 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1144 struct ac_rtld_upload_info info = {
1145 .binary = &rtld_binary,
1146 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1147 .rx_ptr = dest_ptr,
1148 };
1149
1150 if (!ac_rtld_upload(&info)) {
1151 radv_shader_variant_destroy(device, variant);
1152 ac_rtld_close(&rtld_binary);
1153 return NULL;
1154 }
1155
1156 if (keep_shader_info ||
1157 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1158 const char *disasm_data;
1159 size_t disasm_size;
1160 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1161 radv_shader_variant_destroy(device, variant);
1162 ac_rtld_close(&rtld_binary);
1163 return NULL;
1164 }
1165
1166 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1167 variant->disasm_string = malloc(disasm_size + 1);
1168 memcpy(variant->disasm_string, disasm_data, disasm_size);
1169 variant->disasm_string[disasm_size] = 0;
1170 }
1171
1172 ac_rtld_close(&rtld_binary);
1173 } else {
1174 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1175 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1176
1177 /* Add end-of-code markers for the UMR disassembler. */
1178 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1179 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1180 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1181
1182 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1183 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1184
1185 if (bin->stats_size) {
1186 variant->statistics = calloc(bin->stats_size, 1);
1187 memcpy(variant->statistics, bin->data, bin->stats_size);
1188 }
1189 }
1190 return variant;
1191 }
1192
1193 static char *
1194 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1195 int shader_count)
1196 {
1197 char *data = NULL;
1198 char *ret = NULL;
1199 size_t size = 0;
1200 FILE *f = open_memstream(&data, &size);
1201 if (f) {
1202 for (int i = 0; i < shader_count; ++i)
1203 nir_print_shader(shaders[i], f);
1204 fclose(f);
1205 }
1206
1207 ret = malloc(size + 1);
1208 if (ret) {
1209 memcpy(ret, data, size);
1210 ret[size] = 0;
1211 }
1212 free(data);
1213 return ret;
1214 }
1215
1216 static struct radv_shader_variant *
1217 shader_variant_compile(struct radv_device *device,
1218 struct radv_shader_module *module,
1219 struct nir_shader * const *shaders,
1220 int shader_count,
1221 gl_shader_stage stage,
1222 struct radv_shader_info *info,
1223 struct radv_nir_compiler_options *options,
1224 bool gs_copy_shader,
1225 bool trap_handler_shader,
1226 bool keep_shader_info,
1227 bool keep_statistic_info,
1228 struct radv_shader_binary **binary_out)
1229 {
1230 enum radeon_family chip_family = device->physical_device->rad_info.family;
1231 struct radv_shader_binary *binary = NULL;
1232
1233 struct radv_shader_debug_data debug_data = {
1234 .device = device,
1235 .module = module,
1236 };
1237
1238 options->family = chip_family;
1239 options->chip_class = device->physical_device->rad_info.chip_class;
1240 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1241 options->dump_preoptir = options->dump_shader &&
1242 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1243 options->record_ir = keep_shader_info;
1244 options->record_stats = keep_statistic_info;
1245 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1246 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1247 options->address32_hi = device->physical_device->rad_info.address32_hi;
1248 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1249 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1250 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1251 options->debug.func = radv_compiler_debug;
1252 options->debug.private_data = &debug_data;
1253
1254 struct radv_shader_args args = {};
1255 args.options = options;
1256 args.shader_info = info;
1257 args.is_gs_copy_shader = gs_copy_shader;
1258 args.is_trap_handler_shader = trap_handler_shader;
1259
1260 radv_declare_shader_args(&args,
1261 gs_copy_shader ? MESA_SHADER_VERTEX
1262 : shaders[shader_count - 1]->info.stage,
1263 shader_count >= 2,
1264 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1265 : MESA_SHADER_VERTEX);
1266
1267 if (radv_use_llvm_for_stage(device, stage) ||
1268 options->dump_shader || options->record_ir)
1269 ac_init_llvm_once();
1270
1271 if (radv_use_llvm_for_stage(device, stage)) {
1272 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1273 } else {
1274 aco_compile_shader(shader_count, shaders, &binary, &args);
1275 }
1276
1277 binary->info = *info;
1278
1279 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1280 keep_shader_info);
1281 if (!variant) {
1282 free(binary);
1283 return NULL;
1284 }
1285
1286 if (options->dump_shader) {
1287 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1288 for (int i = 1; i < shader_count; ++i)
1289 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1290
1291 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1292 }
1293
1294
1295 if (keep_shader_info) {
1296 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1297 if (!gs_copy_shader && !trap_handler_shader && !module->nir) {
1298 variant->spirv = malloc(module->size);
1299 if (!variant->spirv) {
1300 free(variant);
1301 free(binary);
1302 return NULL;
1303 }
1304
1305 memcpy(variant->spirv, module->data, module->size);
1306 variant->spirv_size = module->size;
1307 }
1308 }
1309
1310 if (binary_out)
1311 *binary_out = binary;
1312 else
1313 free(binary);
1314
1315 return variant;
1316 }
1317
1318 struct radv_shader_variant *
1319 radv_shader_variant_compile(struct radv_device *device,
1320 struct radv_shader_module *module,
1321 struct nir_shader *const *shaders,
1322 int shader_count,
1323 struct radv_pipeline_layout *layout,
1324 const struct radv_shader_variant_key *key,
1325 struct radv_shader_info *info,
1326 bool keep_shader_info, bool keep_statistic_info,
1327 bool disable_optimizations,
1328 struct radv_shader_binary **binary_out)
1329 {
1330 gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
1331 struct radv_nir_compiler_options options = {0};
1332
1333 options.layout = layout;
1334 if (key)
1335 options.key = *key;
1336
1337 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1338 options.robust_buffer_access = device->robust_buffer_access;
1339 options.disable_optimizations = disable_optimizations;
1340
1341 return shader_variant_compile(device, module, shaders, shader_count, stage, info,
1342 &options, false, false,
1343 keep_shader_info, keep_statistic_info, binary_out);
1344 }
1345
1346 struct radv_shader_variant *
1347 radv_create_gs_copy_shader(struct radv_device *device,
1348 struct nir_shader *shader,
1349 struct radv_shader_info *info,
1350 struct radv_shader_binary **binary_out,
1351 bool keep_shader_info, bool keep_statistic_info,
1352 bool multiview, bool disable_optimizations)
1353 {
1354 struct radv_nir_compiler_options options = {0};
1355 gl_shader_stage stage = MESA_SHADER_VERTEX;
1356
1357 options.explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
1358 options.key.has_multiview_view_index = multiview;
1359 options.disable_optimizations = disable_optimizations;
1360
1361 return shader_variant_compile(device, NULL, &shader, 1, stage,
1362 info, &options, true, false,
1363 keep_shader_info, keep_statistic_info, binary_out);
1364 }
1365
1366 struct radv_shader_variant *
1367 radv_create_trap_handler_shader(struct radv_device *device)
1368 {
1369 struct radv_nir_compiler_options options = {0};
1370 struct radv_shader_variant *shader = NULL;
1371 struct radv_shader_binary *binary = NULL;
1372 struct radv_shader_info info = {0};
1373
1374 nir_builder b;
1375 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
1376 b.shader->info.name = ralloc_strdup(b.shader, "meta_trap_handler");
1377
1378 options.explicit_scratch_args = true;
1379 info.wave_size = 64;
1380
1381 shader = shader_variant_compile(device, NULL, &b.shader, 1,
1382 MESA_SHADER_COMPUTE, &info, &options,
1383 false, true, true, false, &binary);
1384
1385 ralloc_free(b.shader);
1386 free(binary);
1387
1388 return shader;
1389 }
1390
1391 void
1392 radv_shader_variant_destroy(struct radv_device *device,
1393 struct radv_shader_variant *variant)
1394 {
1395 if (!p_atomic_dec_zero(&variant->ref_count))
1396 return;
1397
1398 mtx_lock(&device->shader_slab_mutex);
1399 list_del(&variant->slab_list);
1400 mtx_unlock(&device->shader_slab_mutex);
1401
1402 free(variant->spirv);
1403 free(variant->nir_string);
1404 free(variant->disasm_string);
1405 free(variant->ir_string);
1406 free(variant->statistics);
1407 free(variant);
1408 }
1409
1410 const char *
1411 radv_get_shader_name(struct radv_shader_info *info,
1412 gl_shader_stage stage)
1413 {
1414 switch (stage) {
1415 case MESA_SHADER_VERTEX:
1416 if (info->vs.as_ls)
1417 return "Vertex Shader as LS";
1418 else if (info->vs.as_es)
1419 return "Vertex Shader as ES";
1420 else if (info->is_ngg)
1421 return "Vertex Shader as ESGS";
1422 else
1423 return "Vertex Shader as VS";
1424 case MESA_SHADER_TESS_CTRL:
1425 return "Tessellation Control Shader";
1426 case MESA_SHADER_TESS_EVAL:
1427 if (info->tes.as_es)
1428 return "Tessellation Evaluation Shader as ES";
1429 else if (info->is_ngg)
1430 return "Tessellation Evaluation Shader as ESGS";
1431 else
1432 return "Tessellation Evaluation Shader as VS";
1433 case MESA_SHADER_GEOMETRY:
1434 return "Geometry Shader";
1435 case MESA_SHADER_FRAGMENT:
1436 return "Pixel Shader";
1437 case MESA_SHADER_COMPUTE:
1438 return "Compute Shader";
1439 default:
1440 return "Unknown shader";
1441 };
1442 }
1443
1444 unsigned
1445 radv_get_max_workgroup_size(enum chip_class chip_class,
1446 gl_shader_stage stage,
1447 const unsigned *sizes)
1448 {
1449 switch (stage) {
1450 case MESA_SHADER_TESS_CTRL:
1451 return chip_class >= GFX7 ? 128 : 64;
1452 case MESA_SHADER_GEOMETRY:
1453 return chip_class >= GFX9 ? 128 : 64;
1454 case MESA_SHADER_COMPUTE:
1455 break;
1456 default:
1457 return 0;
1458 }
1459
1460 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1461 return max_workgroup_size;
1462 }
1463
1464 unsigned
1465 radv_get_max_waves(struct radv_device *device,
1466 struct radv_shader_variant *variant,
1467 gl_shader_stage stage)
1468 {
1469 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1470 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1471 uint8_t wave_size = variant->info.wave_size;
1472 struct ac_shader_config *conf = &variant->config;
1473 unsigned max_simd_waves;
1474 unsigned lds_per_wave = 0;
1475
1476 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1477
1478 if (stage == MESA_SHADER_FRAGMENT) {
1479 lds_per_wave = conf->lds_size * lds_increment +
1480 align(variant->info.ps.num_interp * 48,
1481 lds_increment);
1482 } else if (stage == MESA_SHADER_COMPUTE) {
1483 unsigned max_workgroup_size =
1484 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1485 lds_per_wave = (conf->lds_size * lds_increment) /
1486 DIV_ROUND_UP(max_workgroup_size, wave_size);
1487 }
1488
1489 if (conf->num_sgprs) {
1490 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1491 max_simd_waves =
1492 MIN2(max_simd_waves,
1493 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1494 sgprs);
1495 }
1496
1497 if (conf->num_vgprs) {
1498 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1499 max_simd_waves =
1500 MIN2(max_simd_waves,
1501 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1502 }
1503
1504 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1505 if (lds_per_wave)
1506 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1507
1508 return max_simd_waves;
1509 }
1510
1511 VkResult
1512 radv_GetShaderInfoAMD(VkDevice _device,
1513 VkPipeline _pipeline,
1514 VkShaderStageFlagBits shaderStage,
1515 VkShaderInfoTypeAMD infoType,
1516 size_t* pInfoSize,
1517 void* pInfo)
1518 {
1519 RADV_FROM_HANDLE(radv_device, device, _device);
1520 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1521 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1522 struct radv_shader_variant *variant = pipeline->shaders[stage];
1523 VkResult result = VK_SUCCESS;
1524
1525 /* Spec doesn't indicate what to do if the stage is invalid, so just
1526 * return no info for this. */
1527 if (!variant)
1528 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1529
1530 switch (infoType) {
1531 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1532 if (!pInfo) {
1533 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1534 } else {
1535 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1536 struct ac_shader_config *conf = &variant->config;
1537
1538 VkShaderStatisticsInfoAMD statistics = {};
1539 statistics.shaderStageMask = shaderStage;
1540 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1541 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1542 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1543
1544 if (stage == MESA_SHADER_COMPUTE) {
1545 unsigned *local_size = variant->info.cs.block_size;
1546 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1547
1548 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1549 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1550
1551 statistics.computeWorkGroupSize[0] = local_size[0];
1552 statistics.computeWorkGroupSize[1] = local_size[1];
1553 statistics.computeWorkGroupSize[2] = local_size[2];
1554 } else {
1555 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1556 }
1557
1558 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1559 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1560 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1561 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1562 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1563
1564 size_t size = *pInfoSize;
1565 *pInfoSize = sizeof(statistics);
1566
1567 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1568
1569 if (size < *pInfoSize)
1570 result = VK_INCOMPLETE;
1571 }
1572
1573 break;
1574 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD: {
1575 char *out;
1576 size_t outsize;
1577 FILE *memf = open_memstream(&out, &outsize);
1578
1579 fprintf(memf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1580 fprintf(memf, "%s\n\n", variant->ir_string);
1581 fprintf(memf, "%s\n\n", variant->disasm_string);
1582 radv_dump_shader_stats(device, pipeline, stage, memf);
1583 fclose(memf);
1584
1585 /* Need to include the null terminator. */
1586 size_t length = outsize + 1;
1587
1588 if (!pInfo) {
1589 *pInfoSize = length;
1590 } else {
1591 size_t size = *pInfoSize;
1592 *pInfoSize = length;
1593
1594 memcpy(pInfo, out, MIN2(size, length));
1595
1596 if (size < length)
1597 result = VK_INCOMPLETE;
1598 }
1599
1600 free(out);
1601 break;
1602 }
1603 default:
1604 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1605 result = VK_ERROR_FEATURE_NOT_PRESENT;
1606 break;
1607 }
1608
1609 return result;
1610 }
1611
1612 VkResult
1613 radv_dump_shader_stats(struct radv_device *device,
1614 struct radv_pipeline *pipeline,
1615 gl_shader_stage stage, FILE *output)
1616 {
1617 struct radv_shader_variant *shader = pipeline->shaders[stage];
1618 VkPipelineExecutablePropertiesKHR *props = NULL;
1619 uint32_t prop_count = 0;
1620 VkResult result;
1621
1622 VkPipelineInfoKHR pipeline_info = {};
1623 pipeline_info.sType = VK_STRUCTURE_TYPE_PIPELINE_INFO_KHR;
1624 pipeline_info.pipeline = radv_pipeline_to_handle(pipeline);
1625
1626 result = radv_GetPipelineExecutablePropertiesKHR(radv_device_to_handle(device),
1627 &pipeline_info,
1628 &prop_count, NULL);
1629 if (result != VK_SUCCESS)
1630 return result;
1631
1632 props = calloc(prop_count, sizeof(*props));
1633 if (!props)
1634 return VK_ERROR_OUT_OF_HOST_MEMORY;
1635
1636 result = radv_GetPipelineExecutablePropertiesKHR(radv_device_to_handle(device),
1637 &pipeline_info,
1638 &prop_count, props);
1639 if (result != VK_SUCCESS)
1640 goto fail;
1641
1642 for (unsigned i = 0; i < prop_count; i++) {
1643 if (!(props[i].stages & mesa_to_vk_shader_stage(stage)))
1644 continue;
1645
1646 VkPipelineExecutableStatisticKHR *stats = NULL;
1647 uint32_t stat_count = 0;
1648 VkResult result;
1649
1650 VkPipelineExecutableInfoKHR exec_info = {};
1651 exec_info.pipeline = radv_pipeline_to_handle(pipeline);
1652 exec_info.executableIndex = i;
1653
1654 result = radv_GetPipelineExecutableStatisticsKHR(radv_device_to_handle(device),
1655 &exec_info,
1656 &stat_count, NULL);
1657 if (result != VK_SUCCESS)
1658 goto fail;
1659
1660 stats = calloc(stat_count, sizeof(*stats));
1661 if (!stats) {
1662 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1663 goto fail;
1664 }
1665
1666 result = radv_GetPipelineExecutableStatisticsKHR(radv_device_to_handle(device),
1667 &exec_info,
1668 &stat_count, stats);
1669 if (result != VK_SUCCESS) {
1670 free(stats);
1671 goto fail;
1672 }
1673
1674 fprintf(output, "\n%s:\n",
1675 radv_get_shader_name(&shader->info, stage));
1676 fprintf(output, "*** SHADER STATS ***\n");
1677
1678 for (unsigned i = 0; i < stat_count; i++) {
1679 fprintf(output, "%s: ", stats[i].name);
1680 switch (stats[i].format) {
1681 case VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_BOOL32_KHR:
1682 fprintf(output, "%s", stats[i].value.b32 == VK_TRUE ? "true" : "false");
1683 break;
1684 case VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_INT64_KHR:
1685 fprintf(output, "%"PRIi64, stats[i].value.i64);
1686 break;
1687 case VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR:
1688 fprintf(output, "%"PRIu64, stats[i].value.u64);
1689 break;
1690 case VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_FLOAT64_KHR:
1691 fprintf(output, "%f", stats[i].value.f64);
1692 break;
1693 default:
1694 unreachable("Invalid pipeline statistic format");
1695 }
1696 fprintf(output, "\n");
1697 }
1698
1699 fprintf(output, "********************\n\n\n");
1700
1701 free(stats);
1702 }
1703
1704 fail:
1705 free(props);
1706 return result;
1707 }