2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
48 #include "aco_interface.h"
50 #include "util/string_buffer.h"
52 static const struct nir_shader_compiler_options nir_options_llvm
= {
53 .vertex_id_zero_based
= true,
58 .lower_device_index_to_zero
= true,
62 .lower_bitfield_insert_to_bitfield_select
= true,
63 .lower_bitfield_extract
= true,
65 .lower_pack_snorm_2x16
= true,
66 .lower_pack_snorm_4x8
= true,
67 .lower_pack_unorm_2x16
= true,
68 .lower_pack_unorm_4x8
= true,
69 .lower_unpack_snorm_2x16
= true,
70 .lower_unpack_snorm_4x8
= true,
71 .lower_unpack_unorm_2x16
= true,
72 .lower_unpack_unorm_4x8
= true,
73 .lower_extract_byte
= true,
74 .lower_extract_word
= true,
77 .lower_mul_2x32_64
= true,
79 .use_scoped_barrier
= true,
80 .max_unroll_iterations
= 32,
81 .use_interpolated_input_intrinsics
= true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options
= nir_lower_imul64
|
85 nir_lower_imul_high64
|
86 nir_lower_imul_2x32_64
|
90 .lower_doubles_options
= nir_lower_drcp
|
96 static const struct nir_shader_compiler_options nir_options_aco
= {
97 .vertex_id_zero_based
= true,
100 .lower_flrp32
= true,
101 .lower_flrp64
= true,
102 .lower_device_index_to_zero
= true,
105 .lower_bitfield_insert_to_bitfield_select
= true,
106 .lower_bitfield_extract
= true,
107 .lower_pack_snorm_2x16
= true,
108 .lower_pack_snorm_4x8
= true,
109 .lower_pack_unorm_2x16
= true,
110 .lower_pack_unorm_4x8
= true,
111 .lower_unpack_snorm_2x16
= true,
112 .lower_unpack_snorm_4x8
= true,
113 .lower_unpack_unorm_2x16
= true,
114 .lower_unpack_unorm_4x8
= true,
115 .lower_unpack_half_2x16
= true,
116 .lower_extract_byte
= true,
117 .lower_extract_word
= true,
120 .lower_mul_2x32_64
= true,
121 .lower_rotate
= true,
122 .use_scoped_barrier
= true,
123 .max_unroll_iterations
= 32,
124 .use_interpolated_input_intrinsics
= true,
125 .lower_int64_options
= nir_lower_imul64
|
126 nir_lower_imul_high64
|
127 nir_lower_imul_2x32_64
|
131 .lower_doubles_options
= nir_lower_drcp
|
138 radv_can_dump_shader(struct radv_device
*device
,
139 struct radv_shader_module
*module
,
140 bool is_gs_copy_shader
)
142 if (!(device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
))
145 return !module
->nir
||
146 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_META_SHADERS
);
148 return is_gs_copy_shader
;
152 radv_can_dump_shader_stats(struct radv_device
*device
,
153 struct radv_shader_module
*module
)
155 /* Only dump non-meta shader stats. */
156 return device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
&&
157 module
&& !module
->nir
;
160 VkResult
radv_CreateShaderModule(
162 const VkShaderModuleCreateInfo
* pCreateInfo
,
163 const VkAllocationCallbacks
* pAllocator
,
164 VkShaderModule
* pShaderModule
)
166 RADV_FROM_HANDLE(radv_device
, device
, _device
);
167 struct radv_shader_module
*module
;
169 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
170 assert(pCreateInfo
->flags
== 0);
172 module
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
173 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
176 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
178 vk_object_base_init(&device
->vk
, &module
->base
,
179 VK_OBJECT_TYPE_SHADER_MODULE
);
182 module
->size
= pCreateInfo
->codeSize
;
183 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
185 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
187 *pShaderModule
= radv_shader_module_to_handle(module
);
192 void radv_DestroyShaderModule(
194 VkShaderModule _module
,
195 const VkAllocationCallbacks
* pAllocator
)
197 RADV_FROM_HANDLE(radv_device
, device
, _device
);
198 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
203 vk_object_base_finish(&module
->base
);
204 vk_free2(&device
->vk
.alloc
, pAllocator
, module
);
208 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
212 unsigned lower_flrp
=
213 (shader
->options
->lower_flrp16
? 16 : 0) |
214 (shader
->options
->lower_flrp32
? 32 : 0) |
215 (shader
->options
->lower_flrp64
? 64 : 0);
220 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
221 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
223 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
224 NIR_PASS_V(shader
, nir_lower_pack
);
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
232 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
235 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
236 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
237 NIR_PASS(progress
, shader
, nir_remove_dead_variables
,
238 nir_var_function_temp
| nir_var_shader_in
| nir_var_shader_out
,
241 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
, NULL
);
242 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
244 NIR_PASS(progress
, shader
, nir_copy_prop
);
245 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
246 NIR_PASS(progress
, shader
, nir_opt_dce
);
247 if (nir_opt_trivial_continues(shader
)) {
249 NIR_PASS(progress
, shader
, nir_copy_prop
);
250 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
251 NIR_PASS(progress
, shader
, nir_opt_dce
);
253 NIR_PASS(progress
, shader
, nir_opt_if
, true);
254 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
255 NIR_PASS(progress
, shader
, nir_opt_cse
);
256 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
257 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
258 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
260 if (lower_flrp
!= 0) {
261 bool lower_flrp_progress
= false;
262 NIR_PASS(lower_flrp_progress
,
266 false /* always_precise */,
267 shader
->options
->lower_ffma
);
268 if (lower_flrp_progress
) {
269 NIR_PASS(progress
, shader
,
270 nir_opt_constant_folding
);
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
280 NIR_PASS(progress
, shader
, nir_opt_undef
);
281 if (shader
->options
->max_unroll_iterations
) {
282 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
284 } while (progress
&& !optimize_conservatively
);
286 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
287 NIR_PASS(progress
, shader
, nir_opt_shrink_vectors
);
288 NIR_PASS(progress
, shader
, nir_opt_move
, nir_move_load_ubo
);
292 shared_var_info(const struct glsl_type
*type
, unsigned *size
, unsigned *align
)
294 assert(glsl_type_is_vector_or_scalar(type
));
296 uint32_t comp_size
= glsl_type_is_boolean(type
) ? 4 : glsl_get_bit_size(type
) / 8;
297 unsigned length
= glsl_get_vector_elements(type
);
298 *size
= comp_size
* length
,
302 struct radv_spirv_debug_data
{
303 struct radv_device
*device
;
304 const struct radv_shader_module
*module
;
307 static void radv_spirv_nir_debug(void *private_data
,
308 enum nir_spirv_debug_level level
,
312 struct radv_spirv_debug_data
*debug_data
= private_data
;
313 struct radv_instance
*instance
= debug_data
->device
->instance
;
315 static const VkDebugReportFlagsEXT vk_flags
[] = {
316 [NIR_SPIRV_DEBUG_LEVEL_INFO
] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT
,
317 [NIR_SPIRV_DEBUG_LEVEL_WARNING
] = VK_DEBUG_REPORT_WARNING_BIT_EXT
,
318 [NIR_SPIRV_DEBUG_LEVEL_ERROR
] = VK_DEBUG_REPORT_ERROR_BIT_EXT
,
322 snprintf(buffer
, sizeof(buffer
), "SPIR-V offset %lu: %s",
323 (unsigned long)spirv_offset
, message
);
325 vk_debug_report(&instance
->debug_report_callbacks
,
327 VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT
,
328 (uint64_t)(uintptr_t)debug_data
->module
,
329 0, 0, "radv", buffer
);
333 radv_shader_compile_to_nir(struct radv_device
*device
,
334 struct radv_shader_module
*module
,
335 const char *entrypoint_name
,
336 gl_shader_stage stage
,
337 const VkSpecializationInfo
*spec_info
,
338 const VkPipelineCreateFlags flags
,
339 const struct radv_pipeline_layout
*layout
,
340 unsigned subgroup_size
, unsigned ballot_bit_size
)
343 const nir_shader_compiler_options
*nir_options
=
344 radv_use_llvm_for_stage(device
, stage
) ? &nir_options_llvm
: &nir_options_aco
;
347 /* Some things such as our meta clear/blit code will give us a NIR
348 * shader directly. In that case, we just ignore the SPIR-V entirely
349 * and just use the NIR shader */
351 nir
->options
= nir_options
;
352 nir_validate_shader(nir
, "in internal shader");
354 assert(exec_list_length(&nir
->functions
) == 1);
356 uint32_t *spirv
= (uint32_t *) module
->data
;
357 assert(module
->size
% 4 == 0);
359 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
360 radv_print_spirv(module
->data
, module
->size
, stderr
);
362 uint32_t num_spec_entries
= 0;
363 struct nir_spirv_specialization
*spec_entries
= NULL
;
364 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
365 num_spec_entries
= spec_info
->mapEntryCount
;
366 spec_entries
= calloc(num_spec_entries
, sizeof(*spec_entries
));
367 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
368 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
369 const void *data
= spec_info
->pData
+ entry
.offset
;
370 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
372 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
373 switch (entry
.size
) {
375 spec_entries
[i
].value
.u64
= *(const uint64_t *)data
;
378 spec_entries
[i
].value
.u32
= *(const uint32_t *)data
;
381 spec_entries
[i
].value
.u16
= *(const uint16_t *)data
;
384 spec_entries
[i
].value
.u8
= *(const uint8_t *)data
;
387 assert(!"Invalid spec constant size");
393 struct radv_spirv_debug_data spirv_debug_data
= {
397 const struct spirv_to_nir_options spirv_options
= {
398 .lower_ubo_ssbo_access_to_offsets
= true,
400 .amd_fragment_mask
= true,
401 .amd_gcn_shader
= true,
402 .amd_image_gather_bias_lod
= true,
403 .amd_image_read_write_lod
= true,
404 .amd_shader_ballot
= true,
405 .amd_shader_explicit_vertex_parameter
= true,
406 .amd_trinary_minmax
= true,
407 .demote_to_helper_invocation
= true,
408 .derivative_group
= true,
409 .descriptor_array_dynamic_indexing
= true,
410 .descriptor_array_non_uniform_indexing
= true,
411 .descriptor_indexing
= true,
412 .device_group
= true,
413 .draw_parameters
= true,
414 .float_controls
= true,
415 .float16
= device
->physical_device
->rad_info
.has_packed_math_16bit
,
416 .float32_atomic_add
= true,
418 .geometry_streams
= true,
419 .image_ms_array
= true,
420 .image_read_without_format
= true,
421 .image_write_without_format
= true,
425 .int64_atomics
= true,
428 .physical_storage_buffer_address
= true,
429 .post_depth_coverage
= true,
430 .runtime_descriptor_array
= true,
431 .shader_clock
= true,
432 .shader_viewport_index_layer
= true,
433 .stencil_export
= true,
434 .storage_8bit
= true,
435 .storage_16bit
= true,
436 .storage_image_ms
= true,
437 .subgroup_arithmetic
= true,
438 .subgroup_ballot
= true,
439 .subgroup_basic
= true,
440 .subgroup_quad
= true,
441 .subgroup_shuffle
= true,
442 .subgroup_vote
= true,
443 .tessellation
= true,
444 .transform_feedback
= true,
445 .variable_pointers
= true,
446 .vk_memory_model
= true,
447 .vk_memory_model_device_scope
= true,
449 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
450 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
451 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
452 .push_const_addr_format
= nir_address_format_logical
,
453 .shared_addr_format
= nir_address_format_32bit_offset
,
454 .frag_coord_is_sysval
= true,
456 .func
= radv_spirv_nir_debug
,
457 .private_data
= &spirv_debug_data
,
460 nir
= spirv_to_nir(spirv
, module
->size
/ 4,
461 spec_entries
, num_spec_entries
,
462 stage
, entrypoint_name
,
463 &spirv_options
, nir_options
);
464 assert(nir
->info
.stage
== stage
);
465 nir_validate_shader(nir
, "after spirv_to_nir");
469 /* We have to lower away local constant initializers right before we
470 * inline functions. That way they get properly initialized at the top
471 * of the function and not at the top of its caller.
473 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_function_temp
);
474 NIR_PASS_V(nir
, nir_lower_returns
);
475 NIR_PASS_V(nir
, nir_inline_functions
);
476 NIR_PASS_V(nir
, nir_copy_prop
);
477 NIR_PASS_V(nir
, nir_opt_deref
);
479 /* Pick off the single entrypoint that we want */
480 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
481 if (func
->is_entrypoint
)
482 func
->name
= ralloc_strdup(func
, "main");
484 exec_node_remove(&func
->node
);
486 assert(exec_list_length(&nir
->functions
) == 1);
488 /* Make sure we lower constant initializers on output variables so that
489 * nir_remove_dead_variables below sees the corresponding stores
491 NIR_PASS_V(nir
, nir_lower_variable_initializers
, nir_var_shader_out
);
493 /* Now that we've deleted all but the main function, we can go ahead and
494 * lower the rest of the constant initializers.
496 NIR_PASS_V(nir
, nir_lower_variable_initializers
, ~0);
498 /* Split member structs. We do this before lower_io_to_temporaries so that
499 * it doesn't lower system values to temporaries by accident.
501 NIR_PASS_V(nir
, nir_split_var_copies
);
502 NIR_PASS_V(nir
, nir_split_per_member_structs
);
504 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
505 !radv_use_llvm_for_stage(device
, nir
->info
.stage
))
506 NIR_PASS_V(nir
, nir_lower_io_to_vector
, nir_var_shader_out
);
507 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
508 NIR_PASS_V(nir
, nir_lower_input_attachments
,
509 &(nir_input_attachment_options
) {
510 .use_fragcoord_sysval
= true,
511 .use_layer_id_sysval
= true,
514 NIR_PASS_V(nir
, nir_remove_dead_variables
,
515 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
| nir_var_mem_shared
,
518 NIR_PASS_V(nir
, nir_propagate_invariant
);
520 NIR_PASS_V(nir
, nir_lower_system_values
);
521 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
523 if (device
->instance
->debug_flags
& RADV_DEBUG_DISCARD_TO_DEMOTE
)
524 NIR_PASS_V(nir
, nir_lower_discard_to_demote
);
526 nir_lower_doubles_options lower_doubles
=
527 nir
->options
->lower_doubles_options
;
529 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
530 /* GFX6 doesn't support v_floor_f64 and the precision
531 * of v_fract_f64 which is used to implement 64-bit
532 * floor is less than what Vulkan requires.
534 lower_doubles
|= nir_lower_dfloor
;
537 NIR_PASS_V(nir
, nir_lower_doubles
, NULL
, lower_doubles
);
540 /* Vulkan uses the separate-shader linking model */
541 nir
->info
.separate_shader
= true;
543 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
545 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
546 nir_lower_gs_intrinsics(nir
, true);
548 static const nir_lower_tex_options tex_options
= {
550 .lower_tg4_offsets
= true,
553 nir_lower_tex(nir
, &tex_options
);
555 nir_lower_vars_to_ssa(nir
);
557 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
558 nir
->info
.stage
== MESA_SHADER_GEOMETRY
||
559 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
560 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
561 nir_shader_get_entrypoint(nir
), true, true);
562 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
563 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
564 nir_shader_get_entrypoint(nir
), true, false);
567 nir_split_var_copies(nir
);
569 nir_lower_global_vars_to_local(nir
);
570 nir_remove_dead_variables(nir
, nir_var_function_temp
, NULL
);
571 bool gfx7minus
= device
->physical_device
->rad_info
.chip_class
<= GFX7
;
572 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
573 .subgroup_size
= subgroup_size
,
574 .ballot_bit_size
= ballot_bit_size
,
575 .lower_to_scalar
= 1,
576 .lower_subgroup_masks
= 1,
578 .lower_shuffle_to_32bit
= 1,
579 .lower_vote_eq_to_ballot
= 1,
580 .lower_quad_broadcast_dynamic
= 1,
581 .lower_quad_broadcast_dynamic_to_const
= gfx7minus
,
582 .lower_shuffle_to_swizzle_amd
= 1,
585 nir_lower_load_const_to_scalar(nir
);
587 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
588 radv_optimize_nir(nir
, false, true);
590 /* call radv_nir_lower_ycbcr_textures() late as there might still be
591 * tex with undef texture/sampler before first optimization */
592 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
594 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
595 * to remove any copies introduced by nir_opt_find_array_copies().
597 nir_lower_var_copies(nir
);
599 /* Lower deref operations for compute shared memory. */
600 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
601 NIR_PASS_V(nir
, nir_lower_vars_to_explicit_types
,
602 nir_var_mem_shared
, shared_var_info
);
603 NIR_PASS_V(nir
, nir_lower_explicit_io
,
604 nir_var_mem_shared
, nir_address_format_32bit_offset
);
607 /* Lower large variables that are always constant with load_constant
608 * intrinsics, which get turned into PC-relative loads from a data
609 * section next to the shader.
611 NIR_PASS_V(nir
, nir_opt_large_constants
,
612 glsl_get_natural_size_align_bytes
, 16);
614 /* Indirect lowering must be called after the radv_optimize_nir() loop
615 * has been called at least once. Otherwise indirect lowering can
616 * bloat the instruction count of the loop and cause it to be
617 * considered too large for unrolling.
619 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
620 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
626 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
628 return glsl_count_attribute_slots(type
, false);
631 static nir_variable
*
632 find_layer_in_var(nir_shader
*nir
)
635 nir_find_variable_with_location(nir
, nir_var_shader_in
, VARYING_SLOT_LAYER
);
639 var
= nir_variable_create(nir
, nir_var_shader_in
, glsl_int_type(), "layer id");
640 var
->data
.location
= VARYING_SLOT_LAYER
;
641 var
->data
.interpolation
= INTERP_MODE_FLAT
;
645 /* We use layered rendering to implement multiview, which means we need to map
646 * view_index to gl_Layer. The attachment lowering also uses needs to know the
647 * layer so that it can sample from the correct layer. The code generates a
648 * load from the layer_id sysval, but since we don't have a way to get at this
649 * information from the fragment shader, we also need to lower this to the
650 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
651 * slot, before lowering io, so that nir_assign_var_locations() will give the
652 * LAYER varying the correct driver_location.
656 lower_view_index(nir_shader
*nir
)
658 bool progress
= false;
659 nir_function_impl
*entry
= nir_shader_get_entrypoint(nir
);
661 nir_builder_init(&b
, entry
);
663 nir_variable
*layer
= NULL
;
664 nir_foreach_block(block
, entry
) {
665 nir_foreach_instr_safe(instr
, block
) {
666 if (instr
->type
!= nir_instr_type_intrinsic
)
669 nir_intrinsic_instr
*load
= nir_instr_as_intrinsic(instr
);
670 if (load
->intrinsic
!= nir_intrinsic_load_view_index
&&
671 load
->intrinsic
!= nir_intrinsic_load_layer_id
)
675 layer
= find_layer_in_var(nir
);
677 b
.cursor
= nir_before_instr(instr
);
678 nir_ssa_def
*def
= nir_load_var(&b
, layer
);
679 nir_ssa_def_rewrite_uses(&load
->dest
.ssa
,
680 nir_src_for_ssa(def
));
682 nir_instr_remove(instr
);
691 radv_lower_fs_io(nir_shader
*nir
)
693 NIR_PASS_V(nir
, lower_view_index
);
694 nir_assign_io_var_locations(nir
, nir_var_shader_in
, &nir
->num_inputs
,
695 MESA_SHADER_FRAGMENT
);
697 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
, type_size_vec4
, 0);
699 /* This pass needs actual constants */
700 nir_opt_constant_folding(nir
);
702 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_in
);
707 radv_alloc_shader_memory(struct radv_device
*device
,
708 struct radv_shader_variant
*shader
)
710 mtx_lock(&device
->shader_slab_mutex
);
711 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
713 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
714 if (s
->bo_offset
- offset
>= shader
->code_size
) {
715 shader
->bo
= slab
->bo
;
716 shader
->bo_offset
= offset
;
717 list_addtail(&shader
->slab_list
, &s
->slab_list
);
718 mtx_unlock(&device
->shader_slab_mutex
);
719 return slab
->ptr
+ offset
;
721 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
723 if (offset
<= slab
->size
&& slab
->size
- offset
>= shader
->code_size
) {
724 shader
->bo
= slab
->bo
;
725 shader
->bo_offset
= offset
;
726 list_addtail(&shader
->slab_list
, &slab
->shaders
);
727 mtx_unlock(&device
->shader_slab_mutex
);
728 return slab
->ptr
+ offset
;
732 mtx_unlock(&device
->shader_slab_mutex
);
733 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
735 slab
->size
= MAX2(256 * 1024, shader
->code_size
);
736 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
738 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
739 (device
->physical_device
->rad_info
.cpdma_prefetch_writes_memory
?
740 0 : RADEON_FLAG_READ_ONLY
),
741 RADV_BO_PRIORITY_SHADER
);
747 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
749 device
->ws
->buffer_destroy(slab
->bo
);
754 list_inithead(&slab
->shaders
);
756 mtx_lock(&device
->shader_slab_mutex
);
757 list_add(&slab
->slabs
, &device
->shader_slabs
);
759 shader
->bo
= slab
->bo
;
760 shader
->bo_offset
= 0;
761 list_add(&shader
->slab_list
, &slab
->shaders
);
762 mtx_unlock(&device
->shader_slab_mutex
);
767 radv_destroy_shader_slabs(struct radv_device
*device
)
769 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
770 device
->ws
->buffer_destroy(slab
->bo
);
773 mtx_destroy(&device
->shader_slab_mutex
);
776 /* For the UMR disassembler. */
777 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
778 #define DEBUGGER_NUM_MARKERS 5
781 radv_get_shader_binary_size(size_t code_size
)
783 return code_size
+ DEBUGGER_NUM_MARKERS
* 4;
786 static void radv_postprocess_config(const struct radv_physical_device
*pdevice
,
787 const struct ac_shader_config
*config_in
,
788 const struct radv_shader_info
*info
,
789 gl_shader_stage stage
,
790 struct ac_shader_config
*config_out
)
792 bool scratch_enabled
= config_in
->scratch_bytes_per_wave
> 0;
793 unsigned vgpr_comp_cnt
= 0;
794 unsigned num_input_vgprs
= info
->num_input_vgprs
;
796 if (stage
== MESA_SHADER_FRAGMENT
) {
797 num_input_vgprs
= ac_get_fs_input_vgpr_cnt(config_in
, NULL
, NULL
);
800 unsigned num_vgprs
= MAX2(config_in
->num_vgprs
, num_input_vgprs
);
801 /* +3 for scratch wave offset and VCC */
802 unsigned num_sgprs
= MAX2(config_in
->num_sgprs
, info
->num_input_sgprs
+ 3);
803 unsigned num_shared_vgprs
= config_in
->num_shared_vgprs
;
804 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
805 assert((pdevice
->rad_info
.chip_class
>= GFX10
&& num_shared_vgprs
% 8 == 0)
806 || (pdevice
->rad_info
.chip_class
< GFX10
&& num_shared_vgprs
== 0));
807 unsigned num_shared_vgpr_blocks
= num_shared_vgprs
/ 8;
809 *config_out
= *config_in
;
810 config_out
->num_vgprs
= num_vgprs
;
811 config_out
->num_sgprs
= num_sgprs
;
812 config_out
->num_shared_vgprs
= num_shared_vgprs
;
814 config_out
->rsrc2
= S_00B12C_USER_SGPR(info
->num_user_sgprs
) |
815 S_00B12C_SCRATCH_EN(scratch_enabled
);
817 if (!pdevice
->use_ngg_streamout
) {
818 config_out
->rsrc2
|= S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
819 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
820 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
821 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
822 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
825 config_out
->rsrc1
= S_00B848_VGPRS((num_vgprs
- 1) /
826 (info
->wave_size
== 32 ? 8 : 4)) |
827 S_00B848_DX10_CLAMP(1) |
828 S_00B848_FLOAT_MODE(config_out
->float_mode
);
830 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
831 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(info
->num_user_sgprs
>> 5);
833 config_out
->rsrc1
|= S_00B228_SGPRS((num_sgprs
- 1) / 8);
834 config_out
->rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(info
->num_user_sgprs
>> 5);
838 case MESA_SHADER_TESS_EVAL
:
840 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
841 config_out
->rsrc2
|= S_00B22C_OC_LDS_EN(1);
842 } else if (info
->tes
.as_es
) {
843 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
844 vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
846 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
848 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->uses_prim_id
;
849 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
851 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
852 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
854 config_out
->rsrc2
|= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
856 case MESA_SHADER_TESS_CTRL
:
857 if (pdevice
->rad_info
.chip_class
>= GFX9
) {
858 /* We need at least 2 components for LS.
859 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
860 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
862 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
863 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 3 : 1;
864 config_out
->rsrc2
|= S_00B42C_LDS_SIZE_GFX10(info
->tcs
.num_lds_blocks
);
866 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
867 config_out
->rsrc2
|= S_00B42C_LDS_SIZE_GFX9(info
->tcs
.num_lds_blocks
);
870 config_out
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
872 config_out
->rsrc1
|= S_00B428_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
873 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
874 config_out
->rsrc2
|= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
876 case MESA_SHADER_VERTEX
:
878 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
879 } else if (info
->vs
.as_ls
) {
880 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
881 /* We need at least 2 components for LS.
882 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
883 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
885 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 2 : 1;
886 } else if (info
->vs
.as_es
) {
887 assert(pdevice
->rad_info
.chip_class
<= GFX8
);
888 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
889 vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 1 : 0;
891 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
892 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
893 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
895 if (info
->vs
.needs_instance_id
&& pdevice
->rad_info
.chip_class
>= GFX10
) {
897 } else if (info
->vs
.export_prim_id
) {
899 } else if (info
->vs
.needs_instance_id
) {
905 config_out
->rsrc1
|= S_00B128_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
907 config_out
->rsrc2
|= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
909 case MESA_SHADER_FRAGMENT
:
910 config_out
->rsrc1
|= S_00B028_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
);
911 config_out
->rsrc2
|= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
913 case MESA_SHADER_GEOMETRY
:
914 config_out
->rsrc1
|= S_00B228_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
915 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
916 config_out
->rsrc2
|= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
918 case MESA_SHADER_COMPUTE
:
919 config_out
->rsrc1
|= S_00B848_MEM_ORDERED(pdevice
->rad_info
.chip_class
>= GFX10
) |
920 S_00B848_WGP_MODE(pdevice
->rad_info
.chip_class
>= GFX10
);
922 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
923 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
924 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
925 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
926 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
927 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
928 S_00B84C_LDS_SIZE(config_in
->lds_size
);
929 config_out
->rsrc3
|= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks
);
933 unreachable("unsupported shader type");
937 if (pdevice
->rad_info
.chip_class
>= GFX10
&& info
->is_ngg
&&
938 (stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_GEOMETRY
)) {
939 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
940 gl_shader_stage es_stage
= stage
;
941 if (stage
== MESA_SHADER_GEOMETRY
)
942 es_stage
= info
->gs
.es_type
;
944 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
945 if (es_stage
== MESA_SHADER_VERTEX
) {
946 es_vgpr_comp_cnt
= info
->vs
.needs_instance_id
? 3 : 0;
947 } else if (es_stage
== MESA_SHADER_TESS_EVAL
) {
948 bool enable_prim_id
= info
->tes
.export_prim_id
|| info
->uses_prim_id
;
949 es_vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
951 unreachable("Unexpected ES shader stage");
953 bool tes_triangles
= stage
== MESA_SHADER_TESS_EVAL
&&
954 info
->tes
.primitive_mode
>= 4; /* GL_TRIANGLES */
955 if (info
->uses_invocation_id
|| stage
== MESA_SHADER_VERTEX
) {
956 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
957 } else if (info
->uses_prim_id
) {
958 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
959 } else if (info
->gs
.vertices_in
>= 3 || tes_triangles
) {
960 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
962 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
965 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
) |
966 S_00B228_WGP_MODE(1);
967 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
968 S_00B22C_LDS_SIZE(config_in
->lds_size
) |
969 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
);
970 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
971 stage
== MESA_SHADER_GEOMETRY
) {
972 unsigned es_type
= info
->gs
.es_type
;
973 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
975 if (es_type
== MESA_SHADER_VERTEX
) {
976 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
977 if (info
->vs
.needs_instance_id
) {
978 es_vgpr_comp_cnt
= pdevice
->rad_info
.chip_class
>= GFX10
? 3 : 1;
980 es_vgpr_comp_cnt
= 0;
982 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
983 es_vgpr_comp_cnt
= info
->uses_prim_id
? 3 : 2;
985 unreachable("invalid shader ES type");
988 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
989 * VGPR[0:4] are always loaded.
991 if (info
->uses_invocation_id
) {
992 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
993 } else if (info
->uses_prim_id
) {
994 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
995 } else if (info
->gs
.vertices_in
>= 3) {
996 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
998 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1001 config_out
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
1002 config_out
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1003 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
1004 } else if (pdevice
->rad_info
.chip_class
>= GFX9
&&
1005 stage
== MESA_SHADER_TESS_CTRL
) {
1006 config_out
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
1008 config_out
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
1012 struct radv_shader_variant
*
1013 radv_shader_variant_create(struct radv_device
*device
,
1014 const struct radv_shader_binary
*binary
,
1015 bool keep_shader_info
)
1017 struct ac_shader_config config
= {0};
1018 struct ac_rtld_binary rtld_binary
= {0};
1019 struct radv_shader_variant
*variant
= calloc(1, sizeof(struct radv_shader_variant
));
1023 variant
->ref_count
= 1;
1025 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
1026 struct ac_rtld_symbol lds_symbols
[2];
1027 unsigned num_lds_symbols
= 0;
1028 const char *elf_data
= (const char *)((struct radv_shader_binary_rtld
*)binary
)->data
;
1029 size_t elf_size
= ((struct radv_shader_binary_rtld
*)binary
)->elf_size
;
1031 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1032 (binary
->stage
== MESA_SHADER_GEOMETRY
|| binary
->info
.is_ngg
) &&
1033 !binary
->is_gs_copy_shader
) {
1034 /* We add this symbol even on LLVM <= 8 to ensure that
1035 * shader->config.lds_size is set correctly below.
1037 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
1038 sym
->name
= "esgs_ring";
1039 sym
->size
= binary
->info
.ngg_info
.esgs_ring_size
;
1040 sym
->align
= 64 * 1024;
1043 if (binary
->info
.is_ngg
&&
1044 binary
->stage
== MESA_SHADER_GEOMETRY
) {
1045 struct ac_rtld_symbol
*sym
= &lds_symbols
[num_lds_symbols
++];
1046 sym
->name
= "ngg_emit";
1047 sym
->size
= binary
->info
.ngg_info
.ngg_emit_size
* 4;
1051 struct ac_rtld_open_info open_info
= {
1052 .info
= &device
->physical_device
->rad_info
,
1053 .shader_type
= binary
->stage
,
1054 .wave_size
= binary
->info
.wave_size
,
1056 .elf_ptrs
= &elf_data
,
1057 .elf_sizes
= &elf_size
,
1058 .num_shared_lds_symbols
= num_lds_symbols
,
1059 .shared_lds_symbols
= lds_symbols
,
1062 if (!ac_rtld_open(&rtld_binary
, open_info
)) {
1067 if (!ac_rtld_read_config(&device
->physical_device
->rad_info
,
1068 &rtld_binary
, &config
)) {
1069 ac_rtld_close(&rtld_binary
);
1074 if (rtld_binary
.lds_size
> 0) {
1075 unsigned alloc_granularity
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1076 config
.lds_size
= align(rtld_binary
.lds_size
, alloc_granularity
) / alloc_granularity
;
1079 variant
->code_size
= rtld_binary
.rx_size
;
1080 variant
->exec_size
= rtld_binary
.exec_size
;
1082 assert(binary
->type
== RADV_BINARY_TYPE_LEGACY
);
1083 config
= ((struct radv_shader_binary_legacy
*)binary
)->config
;
1084 variant
->code_size
= radv_get_shader_binary_size(((struct radv_shader_binary_legacy
*)binary
)->code_size
);
1085 variant
->exec_size
= ((struct radv_shader_binary_legacy
*)binary
)->exec_size
;
1088 variant
->info
= binary
->info
;
1089 radv_postprocess_config(device
->physical_device
, &config
, &binary
->info
,
1090 binary
->stage
, &variant
->config
);
1092 void *dest_ptr
= radv_alloc_shader_memory(device
, variant
);
1094 if (binary
->type
== RADV_BINARY_TYPE_RTLD
)
1095 ac_rtld_close(&rtld_binary
);
1100 if (binary
->type
== RADV_BINARY_TYPE_RTLD
) {
1101 struct radv_shader_binary_rtld
* bin
= (struct radv_shader_binary_rtld
*)binary
;
1102 struct ac_rtld_upload_info info
= {
1103 .binary
= &rtld_binary
,
1104 .rx_va
= radv_buffer_get_va(variant
->bo
) + variant
->bo_offset
,
1108 if (!ac_rtld_upload(&info
)) {
1109 radv_shader_variant_destroy(device
, variant
);
1110 ac_rtld_close(&rtld_binary
);
1114 if (keep_shader_info
||
1115 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
)) {
1116 const char *disasm_data
;
1118 if (!ac_rtld_get_section_by_name(&rtld_binary
, ".AMDGPU.disasm", &disasm_data
, &disasm_size
)) {
1119 radv_shader_variant_destroy(device
, variant
);
1120 ac_rtld_close(&rtld_binary
);
1124 variant
->ir_string
= bin
->llvm_ir_size
? strdup((const char*)(bin
->data
+ bin
->elf_size
)) : NULL
;
1125 variant
->disasm_string
= malloc(disasm_size
+ 1);
1126 memcpy(variant
->disasm_string
, disasm_data
, disasm_size
);
1127 variant
->disasm_string
[disasm_size
] = 0;
1130 ac_rtld_close(&rtld_binary
);
1132 struct radv_shader_binary_legacy
* bin
= (struct radv_shader_binary_legacy
*)binary
;
1133 memcpy(dest_ptr
, bin
->data
+ bin
->stats_size
, bin
->code_size
);
1135 /* Add end-of-code markers for the UMR disassembler. */
1136 uint32_t *ptr32
= (uint32_t *)dest_ptr
+ bin
->code_size
/ 4;
1137 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
1138 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
1140 variant
->ir_string
= bin
->ir_size
? strdup((const char*)(bin
->data
+ bin
->stats_size
+ bin
->code_size
)) : NULL
;
1141 variant
->disasm_string
= bin
->disasm_size
? strdup((const char*)(bin
->data
+ bin
->stats_size
+ bin
->code_size
+ bin
->ir_size
)) : NULL
;
1143 if (bin
->stats_size
) {
1144 variant
->statistics
= calloc(bin
->stats_size
, 1);
1145 memcpy(variant
->statistics
, bin
->data
, bin
->stats_size
);
1152 radv_dump_nir_shaders(struct nir_shader
* const *shaders
,
1158 FILE *f
= open_memstream(&data
, &size
);
1160 for (int i
= 0; i
< shader_count
; ++i
)
1161 nir_print_shader(shaders
[i
], f
);
1165 ret
= malloc(size
+ 1);
1167 memcpy(ret
, data
, size
);
1174 static struct radv_shader_variant
*
1175 shader_variant_compile(struct radv_device
*device
,
1176 struct radv_shader_module
*module
,
1177 struct nir_shader
* const *shaders
,
1179 gl_shader_stage stage
,
1180 struct radv_shader_info
*info
,
1181 struct radv_nir_compiler_options
*options
,
1182 bool gs_copy_shader
,
1183 bool keep_shader_info
,
1184 bool keep_statistic_info
,
1185 struct radv_shader_binary
**binary_out
)
1187 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
1188 struct radv_shader_binary
*binary
= NULL
;
1190 options
->family
= chip_family
;
1191 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
1192 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
1193 options
->dump_preoptir
= options
->dump_shader
&&
1194 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
1195 options
->record_ir
= keep_shader_info
;
1196 options
->record_stats
= keep_statistic_info
;
1197 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
1198 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
1199 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
1200 options
->has_ls_vgpr_init_bug
= device
->physical_device
->rad_info
.has_ls_vgpr_init_bug
;
1201 options
->use_ngg_streamout
= device
->physical_device
->use_ngg_streamout
;
1202 options
->enable_mrt_output_nan_fixup
= device
->instance
->enable_mrt_output_nan_fixup
;
1204 struct radv_shader_args args
= {};
1205 args
.options
= options
;
1206 args
.shader_info
= info
;
1207 args
.is_gs_copy_shader
= gs_copy_shader
;
1208 radv_declare_shader_args(&args
,
1209 gs_copy_shader
? MESA_SHADER_VERTEX
1210 : shaders
[shader_count
- 1]->info
.stage
,
1212 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
1213 : MESA_SHADER_VERTEX
);
1215 if (radv_use_llvm_for_stage(device
, stage
) ||
1216 options
->dump_shader
|| options
->record_ir
)
1217 ac_init_llvm_once();
1219 if (radv_use_llvm_for_stage(device
, stage
)) {
1220 llvm_compile_shader(device
, shader_count
, shaders
, &binary
, &args
);
1222 aco_compile_shader(shader_count
, shaders
, &binary
, &args
);
1225 binary
->info
= *info
;
1227 struct radv_shader_variant
*variant
= radv_shader_variant_create(device
, binary
,
1234 if (options
->dump_shader
) {
1235 fprintf(stderr
, "%s", radv_get_shader_name(info
, shaders
[0]->info
.stage
));
1236 for (int i
= 1; i
< shader_count
; ++i
)
1237 fprintf(stderr
, " + %s", radv_get_shader_name(info
, shaders
[i
]->info
.stage
));
1239 fprintf(stderr
, "\ndisasm:\n%s\n", variant
->disasm_string
);
1243 if (keep_shader_info
) {
1244 variant
->nir_string
= radv_dump_nir_shaders(shaders
, shader_count
);
1245 if (!gs_copy_shader
&& !module
->nir
) {
1246 variant
->spirv
= malloc(module
->size
);
1247 if (!variant
->spirv
) {
1253 memcpy(variant
->spirv
, module
->data
, module
->size
);
1254 variant
->spirv_size
= module
->size
;
1259 *binary_out
= binary
;
1266 struct radv_shader_variant
*
1267 radv_shader_variant_compile(struct radv_device
*device
,
1268 struct radv_shader_module
*module
,
1269 struct nir_shader
*const *shaders
,
1271 struct radv_pipeline_layout
*layout
,
1272 const struct radv_shader_variant_key
*key
,
1273 struct radv_shader_info
*info
,
1274 bool keep_shader_info
, bool keep_statistic_info
,
1275 struct radv_shader_binary
**binary_out
)
1277 gl_shader_stage stage
= shaders
[shader_count
- 1]->info
.stage
;
1278 struct radv_nir_compiler_options options
= {0};
1280 options
.layout
= layout
;
1284 options
.explicit_scratch_args
= !radv_use_llvm_for_stage(device
, stage
);
1285 options
.robust_buffer_access
= device
->robust_buffer_access
;
1287 return shader_variant_compile(device
, module
, shaders
, shader_count
, stage
, info
,
1288 &options
, false, keep_shader_info
, keep_statistic_info
, binary_out
);
1291 struct radv_shader_variant
*
1292 radv_create_gs_copy_shader(struct radv_device
*device
,
1293 struct nir_shader
*shader
,
1294 struct radv_shader_info
*info
,
1295 struct radv_shader_binary
**binary_out
,
1296 bool keep_shader_info
, bool keep_statistic_info
,
1299 struct radv_nir_compiler_options options
= {0};
1300 gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1302 options
.explicit_scratch_args
= !radv_use_llvm_for_stage(device
, stage
);
1303 options
.key
.has_multiview_view_index
= multiview
;
1305 return shader_variant_compile(device
, NULL
, &shader
, 1, stage
,
1306 info
, &options
, true, keep_shader_info
, keep_statistic_info
, binary_out
);
1310 radv_shader_variant_destroy(struct radv_device
*device
,
1311 struct radv_shader_variant
*variant
)
1313 if (!p_atomic_dec_zero(&variant
->ref_count
))
1316 mtx_lock(&device
->shader_slab_mutex
);
1317 list_del(&variant
->slab_list
);
1318 mtx_unlock(&device
->shader_slab_mutex
);
1320 free(variant
->spirv
);
1321 free(variant
->nir_string
);
1322 free(variant
->disasm_string
);
1323 free(variant
->ir_string
);
1324 free(variant
->statistics
);
1329 radv_get_shader_name(struct radv_shader_info
*info
,
1330 gl_shader_stage stage
)
1333 case MESA_SHADER_VERTEX
:
1335 return "Vertex Shader as LS";
1336 else if (info
->vs
.as_es
)
1337 return "Vertex Shader as ES";
1338 else if (info
->is_ngg
)
1339 return "Vertex Shader as ESGS";
1341 return "Vertex Shader as VS";
1342 case MESA_SHADER_TESS_CTRL
:
1343 return "Tessellation Control Shader";
1344 case MESA_SHADER_TESS_EVAL
:
1345 if (info
->tes
.as_es
)
1346 return "Tessellation Evaluation Shader as ES";
1347 else if (info
->is_ngg
)
1348 return "Tessellation Evaluation Shader as ESGS";
1350 return "Tessellation Evaluation Shader as VS";
1351 case MESA_SHADER_GEOMETRY
:
1352 return "Geometry Shader";
1353 case MESA_SHADER_FRAGMENT
:
1354 return "Pixel Shader";
1355 case MESA_SHADER_COMPUTE
:
1356 return "Compute Shader";
1358 return "Unknown shader";
1363 radv_get_max_workgroup_size(enum chip_class chip_class
,
1364 gl_shader_stage stage
,
1365 const unsigned *sizes
)
1368 case MESA_SHADER_TESS_CTRL
:
1369 return chip_class
>= GFX7
? 128 : 64;
1370 case MESA_SHADER_GEOMETRY
:
1371 return chip_class
>= GFX9
? 128 : 64;
1372 case MESA_SHADER_COMPUTE
:
1378 unsigned max_workgroup_size
= sizes
[0] * sizes
[1] * sizes
[2];
1379 return max_workgroup_size
;
1383 radv_get_max_waves(struct radv_device
*device
,
1384 struct radv_shader_variant
*variant
,
1385 gl_shader_stage stage
)
1387 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
1388 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
1389 uint8_t wave_size
= variant
->info
.wave_size
;
1390 struct ac_shader_config
*conf
= &variant
->config
;
1391 unsigned max_simd_waves
;
1392 unsigned lds_per_wave
= 0;
1394 max_simd_waves
= device
->physical_device
->rad_info
.max_wave64_per_simd
;
1396 if (stage
== MESA_SHADER_FRAGMENT
) {
1397 lds_per_wave
= conf
->lds_size
* lds_increment
+
1398 align(variant
->info
.ps
.num_interp
* 48,
1400 } else if (stage
== MESA_SHADER_COMPUTE
) {
1401 unsigned max_workgroup_size
=
1402 radv_get_max_workgroup_size(chip_class
, stage
, variant
->info
.cs
.block_size
);
1403 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
1404 DIV_ROUND_UP(max_workgroup_size
, wave_size
);
1407 if (conf
->num_sgprs
) {
1408 unsigned sgprs
= align(conf
->num_sgprs
, chip_class
>= GFX8
? 16 : 8);
1410 MIN2(max_simd_waves
,
1411 device
->physical_device
->rad_info
.num_physical_sgprs_per_simd
/
1415 if (conf
->num_vgprs
) {
1416 unsigned vgprs
= align(conf
->num_vgprs
, wave_size
== 32 ? 8 : 4);
1418 MIN2(max_simd_waves
,
1419 device
->physical_device
->rad_info
.num_physical_wave64_vgprs_per_simd
/ vgprs
);
1422 unsigned max_lds_per_simd
= device
->physical_device
->rad_info
.lds_size_per_workgroup
/ device
->physical_device
->rad_info
.num_simd_per_compute_unit
;
1424 max_simd_waves
= MIN2(max_simd_waves
, max_lds_per_simd
/ lds_per_wave
);
1426 return max_simd_waves
;
1430 generate_shader_stats(struct radv_device
*device
,
1431 struct radv_shader_variant
*variant
,
1432 gl_shader_stage stage
,
1433 struct _mesa_string_buffer
*buf
)
1435 struct ac_shader_config
*conf
= &variant
->config
;
1436 unsigned max_simd_waves
= radv_get_max_waves(device
, variant
, stage
);
1438 if (stage
== MESA_SHADER_FRAGMENT
) {
1439 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
1440 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1441 "SPI_PS_INPUT_ENA = 0x%04x\n",
1442 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
1445 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
1448 "Spilled SGPRs: %d\n"
1449 "Spilled VGPRs: %d\n"
1450 "PrivMem VGPRS: %d\n"
1451 "Code Size: %d bytes\n"
1453 "Scratch: %d bytes per wave\n"
1455 conf
->num_sgprs
, conf
->num_vgprs
,
1456 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
1457 variant
->info
.private_mem_vgprs
, variant
->exec_size
,
1458 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
1461 if (variant
->statistics
) {
1462 _mesa_string_buffer_printf(buf
, "*** COMPILER STATS ***\n");
1463 for (unsigned i
= 0; i
< variant
->statistics
->count
; i
++) {
1464 struct radv_compiler_statistic_info
*info
= &variant
->statistics
->infos
[i
];
1465 uint32_t value
= variant
->statistics
->values
[i
];
1466 _mesa_string_buffer_printf(buf
, "%s: %lu\n", info
->name
, value
);
1470 _mesa_string_buffer_printf(buf
, "********************\n\n\n");
1474 radv_shader_dump_stats(struct radv_device
*device
,
1475 struct radv_shader_variant
*variant
,
1476 gl_shader_stage stage
,
1479 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
1481 generate_shader_stats(device
, variant
, stage
, buf
);
1483 fprintf(file
, "\n%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1484 fprintf(file
, "%s", buf
->buf
);
1486 _mesa_string_buffer_destroy(buf
);
1490 radv_GetShaderInfoAMD(VkDevice _device
,
1491 VkPipeline _pipeline
,
1492 VkShaderStageFlagBits shaderStage
,
1493 VkShaderInfoTypeAMD infoType
,
1497 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1498 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
1499 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
1500 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
1501 struct _mesa_string_buffer
*buf
;
1502 VkResult result
= VK_SUCCESS
;
1504 /* Spec doesn't indicate what to do if the stage is invalid, so just
1505 * return no info for this. */
1507 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1510 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
1512 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
1514 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
1515 struct ac_shader_config
*conf
= &variant
->config
;
1517 VkShaderStatisticsInfoAMD statistics
= {};
1518 statistics
.shaderStageMask
= shaderStage
;
1519 statistics
.numPhysicalVgprs
= device
->physical_device
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1520 statistics
.numPhysicalSgprs
= device
->physical_device
->rad_info
.num_physical_sgprs_per_simd
;
1521 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
1523 if (stage
== MESA_SHADER_COMPUTE
) {
1524 unsigned *local_size
= variant
->info
.cs
.block_size
;
1525 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
1527 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
1528 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
1530 statistics
.computeWorkGroupSize
[0] = local_size
[0];
1531 statistics
.computeWorkGroupSize
[1] = local_size
[1];
1532 statistics
.computeWorkGroupSize
[2] = local_size
[2];
1534 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
1537 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
1538 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
1539 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
1540 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
1541 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
1543 size_t size
= *pInfoSize
;
1544 *pInfoSize
= sizeof(statistics
);
1546 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
1548 if (size
< *pInfoSize
)
1549 result
= VK_INCOMPLETE
;
1553 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
1554 buf
= _mesa_string_buffer_create(NULL
, 1024);
1556 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(&variant
->info
, stage
));
1557 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->ir_string
);
1558 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
1559 generate_shader_stats(device
, variant
, stage
, buf
);
1561 /* Need to include the null terminator. */
1562 size_t length
= buf
->length
+ 1;
1565 *pInfoSize
= length
;
1567 size_t size
= *pInfoSize
;
1568 *pInfoSize
= length
;
1570 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
1573 result
= VK_INCOMPLETE
;
1576 _mesa_string_buffer_destroy(buf
);
1579 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1580 result
= VK_ERROR_FEATURE_NOT_PRESENT
;