amd: Swap from nir_opt_shrink_load() to nir_opt_shrink_vectors().
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .use_scoped_barrier = true,
80 .max_unroll_iterations = 32,
81 .use_interpolated_input_intrinsics = true,
82 /* nir_lower_int64() isn't actually called for the LLVM backend, but
83 * this helps the loop unrolling heuristics. */
84 .lower_int64_options = nir_lower_imul64 |
85 nir_lower_imul_high64 |
86 nir_lower_imul_2x32_64 |
87 nir_lower_divmod64 |
88 nir_lower_minmax64 |
89 nir_lower_iabs64,
90 .lower_doubles_options = nir_lower_drcp |
91 nir_lower_dsqrt |
92 nir_lower_drsq |
93 nir_lower_ddiv,
94 };
95
96 static const struct nir_shader_compiler_options nir_options_aco = {
97 .vertex_id_zero_based = true,
98 .lower_scmp = true,
99 .lower_flrp16 = true,
100 .lower_flrp32 = true,
101 .lower_flrp64 = true,
102 .lower_device_index_to_zero = true,
103 .lower_fdiv = true,
104 .lower_fmod = true,
105 .lower_bitfield_insert_to_bitfield_select = true,
106 .lower_bitfield_extract = true,
107 .lower_pack_snorm_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_unorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_unpack_snorm_2x16 = true,
112 .lower_unpack_snorm_4x8 = true,
113 .lower_unpack_unorm_2x16 = true,
114 .lower_unpack_unorm_4x8 = true,
115 .lower_unpack_half_2x16 = true,
116 .lower_extract_byte = true,
117 .lower_extract_word = true,
118 .lower_ffma = true,
119 .lower_fpow = true,
120 .lower_mul_2x32_64 = true,
121 .lower_rotate = true,
122 .use_scoped_barrier = true,
123 .max_unroll_iterations = 32,
124 .use_interpolated_input_intrinsics = true,
125 .lower_int64_options = nir_lower_imul64 |
126 nir_lower_imul_high64 |
127 nir_lower_imul_2x32_64 |
128 nir_lower_divmod64 |
129 nir_lower_minmax64 |
130 nir_lower_iabs64,
131 .lower_doubles_options = nir_lower_drcp |
132 nir_lower_dsqrt |
133 nir_lower_drsq |
134 nir_lower_ddiv,
135 };
136
137 bool
138 radv_can_dump_shader(struct radv_device *device,
139 struct radv_shader_module *module,
140 bool is_gs_copy_shader)
141 {
142 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
143 return false;
144 if (module)
145 return !module->nir ||
146 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
147
148 return is_gs_copy_shader;
149 }
150
151 bool
152 radv_can_dump_shader_stats(struct radv_device *device,
153 struct radv_shader_module *module)
154 {
155 /* Only dump non-meta shader stats. */
156 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
157 module && !module->nir;
158 }
159
160 VkResult radv_CreateShaderModule(
161 VkDevice _device,
162 const VkShaderModuleCreateInfo* pCreateInfo,
163 const VkAllocationCallbacks* pAllocator,
164 VkShaderModule* pShaderModule)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 struct radv_shader_module *module;
168
169 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
170 assert(pCreateInfo->flags == 0);
171
172 module = vk_alloc2(&device->vk.alloc, pAllocator,
173 sizeof(*module) + pCreateInfo->codeSize, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (module == NULL)
176 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
177
178 vk_object_base_init(&device->vk, &module->base,
179 VK_OBJECT_TYPE_SHADER_MODULE);
180
181 module->nir = NULL;
182 module->size = pCreateInfo->codeSize;
183 memcpy(module->data, pCreateInfo->pCode, module->size);
184
185 _mesa_sha1_compute(module->data, module->size, module->sha1);
186
187 *pShaderModule = radv_shader_module_to_handle(module);
188
189 return VK_SUCCESS;
190 }
191
192 void radv_DestroyShaderModule(
193 VkDevice _device,
194 VkShaderModule _module,
195 const VkAllocationCallbacks* pAllocator)
196 {
197 RADV_FROM_HANDLE(radv_device, device, _device);
198 RADV_FROM_HANDLE(radv_shader_module, module, _module);
199
200 if (!module)
201 return;
202
203 vk_object_base_finish(&module->base);
204 vk_free2(&device->vk.alloc, pAllocator, module);
205 }
206
207 void
208 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
209 bool allow_copies)
210 {
211 bool progress;
212 unsigned lower_flrp =
213 (shader->options->lower_flrp16 ? 16 : 0) |
214 (shader->options->lower_flrp32 ? 32 : 0) |
215 (shader->options->lower_flrp64 ? 64 : 0);
216
217 do {
218 progress = false;
219
220 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
221 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
222
223 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
224 NIR_PASS_V(shader, nir_lower_pack);
225
226 if (allow_copies) {
227 /* Only run this pass in the first call to
228 * radv_optimize_nir. Later calls assume that we've
229 * lowered away any copy_deref instructions and we
230 * don't want to introduce any more.
231 */
232 NIR_PASS(progress, shader, nir_opt_find_array_copies);
233 }
234
235 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
236 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
237 NIR_PASS(progress, shader, nir_remove_dead_variables,
238 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out,
239 NULL);
240
241 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
242 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
243
244 NIR_PASS(progress, shader, nir_copy_prop);
245 NIR_PASS(progress, shader, nir_opt_remove_phis);
246 NIR_PASS(progress, shader, nir_opt_dce);
247 if (nir_opt_trivial_continues(shader)) {
248 progress = true;
249 NIR_PASS(progress, shader, nir_copy_prop);
250 NIR_PASS(progress, shader, nir_opt_remove_phis);
251 NIR_PASS(progress, shader, nir_opt_dce);
252 }
253 NIR_PASS(progress, shader, nir_opt_if, true);
254 NIR_PASS(progress, shader, nir_opt_dead_cf);
255 NIR_PASS(progress, shader, nir_opt_cse);
256 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
257 NIR_PASS(progress, shader, nir_opt_constant_folding);
258 NIR_PASS(progress, shader, nir_opt_algebraic);
259
260 if (lower_flrp != 0) {
261 bool lower_flrp_progress = false;
262 NIR_PASS(lower_flrp_progress,
263 shader,
264 nir_lower_flrp,
265 lower_flrp,
266 false /* always_precise */,
267 shader->options->lower_ffma);
268 if (lower_flrp_progress) {
269 NIR_PASS(progress, shader,
270 nir_opt_constant_folding);
271 progress = true;
272 }
273
274 /* Nothing should rematerialize any flrps, so we only
275 * need to do this lowering once.
276 */
277 lower_flrp = 0;
278 }
279
280 NIR_PASS(progress, shader, nir_opt_undef);
281 if (shader->options->max_unroll_iterations) {
282 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
283 }
284 } while (progress && !optimize_conservatively);
285
286 NIR_PASS(progress, shader, nir_opt_conditional_discard);
287 NIR_PASS(progress, shader, nir_opt_shrink_vectors);
288 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
289 }
290
291 static void
292 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
293 {
294 assert(glsl_type_is_vector_or_scalar(type));
295
296 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
297 unsigned length = glsl_get_vector_elements(type);
298 *size = comp_size * length,
299 *align = comp_size;
300 }
301
302 nir_shader *
303 radv_shader_compile_to_nir(struct radv_device *device,
304 struct radv_shader_module *module,
305 const char *entrypoint_name,
306 gl_shader_stage stage,
307 const VkSpecializationInfo *spec_info,
308 const VkPipelineCreateFlags flags,
309 const struct radv_pipeline_layout *layout,
310 unsigned subgroup_size, unsigned ballot_bit_size)
311 {
312 nir_shader *nir;
313 const nir_shader_compiler_options *nir_options =
314 device->physical_device->use_llvm ? &nir_options_llvm :
315 &nir_options_aco;
316
317 if (module->nir) {
318 /* Some things such as our meta clear/blit code will give us a NIR
319 * shader directly. In that case, we just ignore the SPIR-V entirely
320 * and just use the NIR shader */
321 nir = module->nir;
322 nir->options = nir_options;
323 nir_validate_shader(nir, "in internal shader");
324
325 assert(exec_list_length(&nir->functions) == 1);
326 } else {
327 uint32_t *spirv = (uint32_t *) module->data;
328 assert(module->size % 4 == 0);
329
330 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
331 radv_print_spirv(module->data, module->size, stderr);
332
333 uint32_t num_spec_entries = 0;
334 struct nir_spirv_specialization *spec_entries = NULL;
335 if (spec_info && spec_info->mapEntryCount > 0) {
336 num_spec_entries = spec_info->mapEntryCount;
337 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
338 for (uint32_t i = 0; i < num_spec_entries; i++) {
339 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
340 const void *data = spec_info->pData + entry.offset;
341 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
342
343 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
344 switch (entry.size) {
345 case 8:
346 spec_entries[i].value.u64 = *(const uint64_t *)data;
347 break;
348 case 4:
349 spec_entries[i].value.u32 = *(const uint32_t *)data;
350 break;
351 case 2:
352 spec_entries[i].value.u16 = *(const uint16_t *)data;
353 break;
354 case 1:
355 spec_entries[i].value.u8 = *(const uint8_t *)data;
356 break;
357 default:
358 assert(!"Invalid spec constant size");
359 break;
360 }
361 }
362 }
363 const struct spirv_to_nir_options spirv_options = {
364 .lower_ubo_ssbo_access_to_offsets = true,
365 .caps = {
366 .amd_fragment_mask = true,
367 .amd_gcn_shader = true,
368 .amd_image_gather_bias_lod = true,
369 .amd_image_read_write_lod = true,
370 .amd_shader_ballot = true,
371 .amd_shader_explicit_vertex_parameter = true,
372 .amd_trinary_minmax = true,
373 .demote_to_helper_invocation = true,
374 .derivative_group = true,
375 .descriptor_array_dynamic_indexing = true,
376 .descriptor_array_non_uniform_indexing = true,
377 .descriptor_indexing = true,
378 .device_group = true,
379 .draw_parameters = true,
380 .float_controls = true,
381 .float16 = device->physical_device->rad_info.has_packed_math_16bit,
382 .float32_atomic_add = true,
383 .float64 = true,
384 .geometry_streams = true,
385 .image_ms_array = true,
386 .image_read_without_format = true,
387 .image_write_without_format = true,
388 .int8 = true,
389 .int16 = true,
390 .int64 = true,
391 .int64_atomics = true,
392 .min_lod = true,
393 .multiview = true,
394 .physical_storage_buffer_address = true,
395 .post_depth_coverage = true,
396 .runtime_descriptor_array = true,
397 .shader_clock = true,
398 .shader_viewport_index_layer = true,
399 .stencil_export = true,
400 .storage_8bit = true,
401 .storage_16bit = true,
402 .storage_image_ms = true,
403 .subgroup_arithmetic = true,
404 .subgroup_ballot = true,
405 .subgroup_basic = true,
406 .subgroup_quad = true,
407 .subgroup_shuffle = true,
408 .subgroup_vote = true,
409 .tessellation = true,
410 .transform_feedback = true,
411 .variable_pointers = true,
412 },
413 .ubo_addr_format = nir_address_format_32bit_index_offset,
414 .ssbo_addr_format = nir_address_format_32bit_index_offset,
415 .phys_ssbo_addr_format = nir_address_format_64bit_global,
416 .push_const_addr_format = nir_address_format_logical,
417 .shared_addr_format = nir_address_format_32bit_offset,
418 .frag_coord_is_sysval = true,
419 };
420 nir = spirv_to_nir(spirv, module->size / 4,
421 spec_entries, num_spec_entries,
422 stage, entrypoint_name,
423 &spirv_options, nir_options);
424 assert(nir->info.stage == stage);
425 nir_validate_shader(nir, "after spirv_to_nir");
426
427 free(spec_entries);
428
429 /* We have to lower away local constant initializers right before we
430 * inline functions. That way they get properly initialized at the top
431 * of the function and not at the top of its caller.
432 */
433 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
434 NIR_PASS_V(nir, nir_lower_returns);
435 NIR_PASS_V(nir, nir_inline_functions);
436 NIR_PASS_V(nir, nir_copy_prop);
437 NIR_PASS_V(nir, nir_opt_deref);
438
439 /* Pick off the single entrypoint that we want */
440 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
441 if (func->is_entrypoint)
442 func->name = ralloc_strdup(func, "main");
443 else
444 exec_node_remove(&func->node);
445 }
446 assert(exec_list_length(&nir->functions) == 1);
447
448 /* Make sure we lower constant initializers on output variables so that
449 * nir_remove_dead_variables below sees the corresponding stores
450 */
451 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
452
453 /* Now that we've deleted all but the main function, we can go ahead and
454 * lower the rest of the constant initializers.
455 */
456 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
457
458 /* Split member structs. We do this before lower_io_to_temporaries so that
459 * it doesn't lower system values to temporaries by accident.
460 */
461 NIR_PASS_V(nir, nir_split_var_copies);
462 NIR_PASS_V(nir, nir_split_per_member_structs);
463
464 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
465 !device->physical_device->use_llvm)
466 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
467 if (nir->info.stage == MESA_SHADER_FRAGMENT)
468 NIR_PASS_V(nir, nir_lower_input_attachments, true);
469
470 NIR_PASS_V(nir, nir_remove_dead_variables,
471 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared,
472 NULL);
473
474 NIR_PASS_V(nir, nir_propagate_invariant);
475
476 NIR_PASS_V(nir, nir_lower_system_values);
477 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
478
479 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
480 NIR_PASS_V(nir, nir_lower_discard_to_demote);
481
482 nir_lower_doubles_options lower_doubles =
483 nir->options->lower_doubles_options;
484
485 if (device->physical_device->rad_info.chip_class == GFX6) {
486 /* GFX6 doesn't support v_floor_f64 and the precision
487 * of v_fract_f64 which is used to implement 64-bit
488 * floor is less than what Vulkan requires.
489 */
490 lower_doubles |= nir_lower_dfloor;
491 }
492
493 NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles);
494 }
495
496 /* Vulkan uses the separate-shader linking model */
497 nir->info.separate_shader = true;
498
499 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
500
501 if (nir->info.stage == MESA_SHADER_GEOMETRY)
502 nir_lower_gs_intrinsics(nir, true);
503
504 static const nir_lower_tex_options tex_options = {
505 .lower_txp = ~0,
506 .lower_tg4_offsets = true,
507 };
508
509 nir_lower_tex(nir, &tex_options);
510
511 nir_lower_vars_to_ssa(nir);
512
513 if (nir->info.stage == MESA_SHADER_VERTEX ||
514 nir->info.stage == MESA_SHADER_GEOMETRY ||
515 nir->info.stage == MESA_SHADER_FRAGMENT) {
516 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
517 nir_shader_get_entrypoint(nir), true, true);
518 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
519 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
520 nir_shader_get_entrypoint(nir), true, false);
521 }
522
523 nir_split_var_copies(nir);
524
525 nir_lower_global_vars_to_local(nir);
526 nir_remove_dead_variables(nir, nir_var_function_temp, NULL);
527 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
528 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
529 .subgroup_size = subgroup_size,
530 .ballot_bit_size = ballot_bit_size,
531 .lower_to_scalar = 1,
532 .lower_subgroup_masks = 1,
533 .lower_shuffle = 1,
534 .lower_shuffle_to_32bit = 1,
535 .lower_vote_eq_to_ballot = 1,
536 .lower_quad_broadcast_dynamic = 1,
537 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
538 .lower_shuffle_to_swizzle_amd = 1,
539 });
540
541 nir_lower_load_const_to_scalar(nir);
542
543 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
544 radv_optimize_nir(nir, false, true);
545
546 /* call radv_nir_lower_ycbcr_textures() late as there might still be
547 * tex with undef texture/sampler before first optimization */
548 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
549
550 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
551 * to remove any copies introduced by nir_opt_find_array_copies().
552 */
553 nir_lower_var_copies(nir);
554
555 /* Lower deref operations for compute shared memory. */
556 if (nir->info.stage == MESA_SHADER_COMPUTE) {
557 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
558 nir_var_mem_shared, shared_var_info);
559 NIR_PASS_V(nir, nir_lower_explicit_io,
560 nir_var_mem_shared, nir_address_format_32bit_offset);
561 }
562
563 /* Lower large variables that are always constant with load_constant
564 * intrinsics, which get turned into PC-relative loads from a data
565 * section next to the shader.
566 */
567 NIR_PASS_V(nir, nir_opt_large_constants,
568 glsl_get_natural_size_align_bytes, 16);
569
570 /* Indirect lowering must be called after the radv_optimize_nir() loop
571 * has been called at least once. Otherwise indirect lowering can
572 * bloat the instruction count of the loop and cause it to be
573 * considered too large for unrolling.
574 */
575 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
576 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
577
578 return nir;
579 }
580
581 static int
582 type_size_vec4(const struct glsl_type *type, bool bindless)
583 {
584 return glsl_count_attribute_slots(type, false);
585 }
586
587 static nir_variable *
588 find_layer_in_var(nir_shader *nir)
589 {
590 nir_variable *var =
591 nir_find_variable_with_location(nir, nir_var_shader_in, VARYING_SLOT_LAYER);
592 if (var != NULL)
593 return var;
594
595 var = nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
596 var->data.location = VARYING_SLOT_LAYER;
597 var->data.interpolation = INTERP_MODE_FLAT;
598 return var;
599 }
600
601 /* We use layered rendering to implement multiview, which means we need to map
602 * view_index to gl_Layer. The attachment lowering also uses needs to know the
603 * layer so that it can sample from the correct layer. The code generates a
604 * load from the layer_id sysval, but since we don't have a way to get at this
605 * information from the fragment shader, we also need to lower this to the
606 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
607 * slot, before lowering io, so that nir_assign_var_locations() will give the
608 * LAYER varying the correct driver_location.
609 */
610
611 static bool
612 lower_view_index(nir_shader *nir)
613 {
614 bool progress = false;
615 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
616 nir_builder b;
617 nir_builder_init(&b, entry);
618
619 nir_variable *layer = NULL;
620 nir_foreach_block(block, entry) {
621 nir_foreach_instr_safe(instr, block) {
622 if (instr->type != nir_instr_type_intrinsic)
623 continue;
624
625 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
626 if (load->intrinsic != nir_intrinsic_load_view_index &&
627 load->intrinsic != nir_intrinsic_load_layer_id)
628 continue;
629
630 if (!layer)
631 layer = find_layer_in_var(nir);
632
633 b.cursor = nir_before_instr(instr);
634 nir_ssa_def *def = nir_load_var(&b, layer);
635 nir_ssa_def_rewrite_uses(&load->dest.ssa,
636 nir_src_for_ssa(def));
637
638 nir_instr_remove(instr);
639 progress = true;
640 }
641 }
642
643 return progress;
644 }
645
646 void
647 radv_lower_fs_io(nir_shader *nir)
648 {
649 NIR_PASS_V(nir, lower_view_index);
650 nir_assign_io_var_locations(nir, nir_var_shader_in, &nir->num_inputs,
651 MESA_SHADER_FRAGMENT);
652
653 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
654
655 /* This pass needs actual constants */
656 nir_opt_constant_folding(nir);
657
658 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
659 }
660
661
662 static void *
663 radv_alloc_shader_memory(struct radv_device *device,
664 struct radv_shader_variant *shader)
665 {
666 mtx_lock(&device->shader_slab_mutex);
667 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
668 uint64_t offset = 0;
669 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
670 if (s->bo_offset - offset >= shader->code_size) {
671 shader->bo = slab->bo;
672 shader->bo_offset = offset;
673 list_addtail(&shader->slab_list, &s->slab_list);
674 mtx_unlock(&device->shader_slab_mutex);
675 return slab->ptr + offset;
676 }
677 offset = align_u64(s->bo_offset + s->code_size, 256);
678 }
679 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
680 shader->bo = slab->bo;
681 shader->bo_offset = offset;
682 list_addtail(&shader->slab_list, &slab->shaders);
683 mtx_unlock(&device->shader_slab_mutex);
684 return slab->ptr + offset;
685 }
686 }
687
688 mtx_unlock(&device->shader_slab_mutex);
689 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
690
691 slab->size = MAX2(256 * 1024, shader->code_size);
692 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
693 RADEON_DOMAIN_VRAM,
694 RADEON_FLAG_NO_INTERPROCESS_SHARING |
695 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
696 0 : RADEON_FLAG_READ_ONLY),
697 RADV_BO_PRIORITY_SHADER);
698 if (!slab->bo) {
699 free(slab);
700 return NULL;
701 }
702
703 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
704 if (!slab->ptr) {
705 device->ws->buffer_destroy(slab->bo);
706 free(slab);
707 return NULL;
708 }
709
710 list_inithead(&slab->shaders);
711
712 mtx_lock(&device->shader_slab_mutex);
713 list_add(&slab->slabs, &device->shader_slabs);
714
715 shader->bo = slab->bo;
716 shader->bo_offset = 0;
717 list_add(&shader->slab_list, &slab->shaders);
718 mtx_unlock(&device->shader_slab_mutex);
719 return slab->ptr;
720 }
721
722 void
723 radv_destroy_shader_slabs(struct radv_device *device)
724 {
725 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
726 device->ws->buffer_destroy(slab->bo);
727 free(slab);
728 }
729 mtx_destroy(&device->shader_slab_mutex);
730 }
731
732 /* For the UMR disassembler. */
733 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
734 #define DEBUGGER_NUM_MARKERS 5
735
736 static unsigned
737 radv_get_shader_binary_size(size_t code_size)
738 {
739 return code_size + DEBUGGER_NUM_MARKERS * 4;
740 }
741
742 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
743 const struct ac_shader_config *config_in,
744 const struct radv_shader_info *info,
745 gl_shader_stage stage,
746 struct ac_shader_config *config_out)
747 {
748 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
749 unsigned vgpr_comp_cnt = 0;
750 unsigned num_input_vgprs = info->num_input_vgprs;
751
752 if (stage == MESA_SHADER_FRAGMENT) {
753 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
754 }
755
756 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
757 /* +3 for scratch wave offset and VCC */
758 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
759 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
760 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
761 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
762 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
763 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
764
765 *config_out = *config_in;
766 config_out->num_vgprs = num_vgprs;
767 config_out->num_sgprs = num_sgprs;
768 config_out->num_shared_vgprs = num_shared_vgprs;
769
770 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
771 S_00B12C_SCRATCH_EN(scratch_enabled);
772
773 if (!pdevice->use_ngg_streamout) {
774 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
775 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
776 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
777 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
778 S_00B12C_SO_EN(!!info->so.num_outputs);
779 }
780
781 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
782 (info->wave_size == 32 ? 8 : 4)) |
783 S_00B848_DX10_CLAMP(1) |
784 S_00B848_FLOAT_MODE(config_out->float_mode);
785
786 if (pdevice->rad_info.chip_class >= GFX10) {
787 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
788 } else {
789 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
790 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
791 }
792
793 switch (stage) {
794 case MESA_SHADER_TESS_EVAL:
795 if (info->is_ngg) {
796 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
797 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
798 } else if (info->tes.as_es) {
799 assert(pdevice->rad_info.chip_class <= GFX8);
800 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
801
802 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
803 } else {
804 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
805 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
806
807 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
808 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
809 }
810 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
811 break;
812 case MESA_SHADER_TESS_CTRL:
813 if (pdevice->rad_info.chip_class >= GFX9) {
814 /* We need at least 2 components for LS.
815 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
816 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
817 */
818 if (pdevice->rad_info.chip_class >= GFX10) {
819 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
820 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX10(info->tcs.num_lds_blocks);
821 } else {
822 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
823 config_out->rsrc2 |= S_00B42C_LDS_SIZE_GFX9(info->tcs.num_lds_blocks);
824 }
825 } else {
826 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
827 }
828 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
829 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
830 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
831 break;
832 case MESA_SHADER_VERTEX:
833 if (info->is_ngg) {
834 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
835 } else if (info->vs.as_ls) {
836 assert(pdevice->rad_info.chip_class <= GFX8);
837 /* We need at least 2 components for LS.
838 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
839 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
840 */
841 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
842 } else if (info->vs.as_es) {
843 assert(pdevice->rad_info.chip_class <= GFX8);
844 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
845 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
846 } else {
847 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
848 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
849 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
850 */
851 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
852 vgpr_comp_cnt = 3;
853 } else if (info->vs.export_prim_id) {
854 vgpr_comp_cnt = 2;
855 } else if (info->vs.needs_instance_id) {
856 vgpr_comp_cnt = 1;
857 } else {
858 vgpr_comp_cnt = 0;
859 }
860
861 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
862 }
863 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
864 break;
865 case MESA_SHADER_FRAGMENT:
866 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
867 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
868 break;
869 case MESA_SHADER_GEOMETRY:
870 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
871 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
872 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
873 break;
874 case MESA_SHADER_COMPUTE:
875 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
876 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
877 config_out->rsrc2 |=
878 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
879 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
880 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
881 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
882 info->cs.uses_thread_id[1] ? 1 : 0) |
883 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
884 S_00B84C_LDS_SIZE(config_in->lds_size);
885 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
886
887 break;
888 default:
889 unreachable("unsupported shader type");
890 break;
891 }
892
893 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
894 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
895 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
896 gl_shader_stage es_stage = stage;
897 if (stage == MESA_SHADER_GEOMETRY)
898 es_stage = info->gs.es_type;
899
900 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
901 if (es_stage == MESA_SHADER_VERTEX) {
902 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
903 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
904 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
905 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
906 } else
907 unreachable("Unexpected ES shader stage");
908
909 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
910 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
911 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
912 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
913 } else if (info->uses_prim_id) {
914 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
915 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
916 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
917 } else {
918 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
919 }
920
921 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
922 S_00B228_WGP_MODE(1);
923 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
924 S_00B22C_LDS_SIZE(config_in->lds_size) |
925 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
926 } else if (pdevice->rad_info.chip_class >= GFX9 &&
927 stage == MESA_SHADER_GEOMETRY) {
928 unsigned es_type = info->gs.es_type;
929 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
930
931 if (es_type == MESA_SHADER_VERTEX) {
932 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
933 if (info->vs.needs_instance_id) {
934 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
935 } else {
936 es_vgpr_comp_cnt = 0;
937 }
938 } else if (es_type == MESA_SHADER_TESS_EVAL) {
939 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
940 } else {
941 unreachable("invalid shader ES type");
942 }
943
944 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
945 * VGPR[0:4] are always loaded.
946 */
947 if (info->uses_invocation_id) {
948 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
949 } else if (info->uses_prim_id) {
950 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
951 } else if (info->gs.vertices_in >= 3) {
952 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
953 } else {
954 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
955 }
956
957 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
958 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
959 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
960 } else if (pdevice->rad_info.chip_class >= GFX9 &&
961 stage == MESA_SHADER_TESS_CTRL) {
962 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
963 } else {
964 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
965 }
966 }
967
968 struct radv_shader_variant *
969 radv_shader_variant_create(struct radv_device *device,
970 const struct radv_shader_binary *binary,
971 bool keep_shader_info)
972 {
973 struct ac_shader_config config = {0};
974 struct ac_rtld_binary rtld_binary = {0};
975 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
976 if (!variant)
977 return NULL;
978
979 variant->ref_count = 1;
980
981 if (binary->type == RADV_BINARY_TYPE_RTLD) {
982 struct ac_rtld_symbol lds_symbols[2];
983 unsigned num_lds_symbols = 0;
984 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
985 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
986
987 if (device->physical_device->rad_info.chip_class >= GFX9 &&
988 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
989 !binary->is_gs_copy_shader) {
990 /* We add this symbol even on LLVM <= 8 to ensure that
991 * shader->config.lds_size is set correctly below.
992 */
993 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
994 sym->name = "esgs_ring";
995 sym->size = binary->info.ngg_info.esgs_ring_size;
996 sym->align = 64 * 1024;
997 }
998
999 if (binary->info.is_ngg &&
1000 binary->stage == MESA_SHADER_GEOMETRY) {
1001 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1002 sym->name = "ngg_emit";
1003 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
1004 sym->align = 4;
1005 }
1006
1007 struct ac_rtld_open_info open_info = {
1008 .info = &device->physical_device->rad_info,
1009 .shader_type = binary->stage,
1010 .wave_size = binary->info.wave_size,
1011 .num_parts = 1,
1012 .elf_ptrs = &elf_data,
1013 .elf_sizes = &elf_size,
1014 .num_shared_lds_symbols = num_lds_symbols,
1015 .shared_lds_symbols = lds_symbols,
1016 };
1017
1018 if (!ac_rtld_open(&rtld_binary, open_info)) {
1019 free(variant);
1020 return NULL;
1021 }
1022
1023 if (!ac_rtld_read_config(&device->physical_device->rad_info,
1024 &rtld_binary, &config)) {
1025 ac_rtld_close(&rtld_binary);
1026 free(variant);
1027 return NULL;
1028 }
1029
1030 if (rtld_binary.lds_size > 0) {
1031 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1032 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1033 }
1034
1035 variant->code_size = rtld_binary.rx_size;
1036 variant->exec_size = rtld_binary.exec_size;
1037 } else {
1038 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1039 config = ((struct radv_shader_binary_legacy *)binary)->config;
1040 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1041 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1042 }
1043
1044 variant->info = binary->info;
1045 radv_postprocess_config(device->physical_device, &config, &binary->info,
1046 binary->stage, &variant->config);
1047
1048 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1049 if (!dest_ptr) {
1050 if (binary->type == RADV_BINARY_TYPE_RTLD)
1051 ac_rtld_close(&rtld_binary);
1052 free(variant);
1053 return NULL;
1054 }
1055
1056 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1057 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1058 struct ac_rtld_upload_info info = {
1059 .binary = &rtld_binary,
1060 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1061 .rx_ptr = dest_ptr,
1062 };
1063
1064 if (!ac_rtld_upload(&info)) {
1065 radv_shader_variant_destroy(device, variant);
1066 ac_rtld_close(&rtld_binary);
1067 return NULL;
1068 }
1069
1070 if (keep_shader_info ||
1071 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1072 const char *disasm_data;
1073 size_t disasm_size;
1074 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1075 radv_shader_variant_destroy(device, variant);
1076 ac_rtld_close(&rtld_binary);
1077 return NULL;
1078 }
1079
1080 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1081 variant->disasm_string = malloc(disasm_size + 1);
1082 memcpy(variant->disasm_string, disasm_data, disasm_size);
1083 variant->disasm_string[disasm_size] = 0;
1084 }
1085
1086 ac_rtld_close(&rtld_binary);
1087 } else {
1088 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1089 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1090
1091 /* Add end-of-code markers for the UMR disassembler. */
1092 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1093 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1094 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1095
1096 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1097 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1098
1099 if (bin->stats_size) {
1100 variant->statistics = calloc(bin->stats_size, 1);
1101 memcpy(variant->statistics, bin->data, bin->stats_size);
1102 }
1103 }
1104 return variant;
1105 }
1106
1107 static char *
1108 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1109 int shader_count)
1110 {
1111 char *data = NULL;
1112 char *ret = NULL;
1113 size_t size = 0;
1114 FILE *f = open_memstream(&data, &size);
1115 if (f) {
1116 for (int i = 0; i < shader_count; ++i)
1117 nir_print_shader(shaders[i], f);
1118 fclose(f);
1119 }
1120
1121 ret = malloc(size + 1);
1122 if (ret) {
1123 memcpy(ret, data, size);
1124 ret[size] = 0;
1125 }
1126 free(data);
1127 return ret;
1128 }
1129
1130 static struct radv_shader_variant *
1131 shader_variant_compile(struct radv_device *device,
1132 struct radv_shader_module *module,
1133 struct nir_shader * const *shaders,
1134 int shader_count,
1135 gl_shader_stage stage,
1136 struct radv_shader_info *info,
1137 struct radv_nir_compiler_options *options,
1138 bool gs_copy_shader,
1139 bool keep_shader_info,
1140 bool keep_statistic_info,
1141 struct radv_shader_binary **binary_out)
1142 {
1143 enum radeon_family chip_family = device->physical_device->rad_info.family;
1144 struct radv_shader_binary *binary = NULL;
1145
1146 options->family = chip_family;
1147 options->chip_class = device->physical_device->rad_info.chip_class;
1148 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1149 options->dump_preoptir = options->dump_shader &&
1150 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1151 options->record_ir = keep_shader_info;
1152 options->record_stats = keep_statistic_info;
1153 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1154 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1155 options->address32_hi = device->physical_device->rad_info.address32_hi;
1156 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1157 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1158 options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup;
1159
1160 struct radv_shader_args args = {};
1161 args.options = options;
1162 args.shader_info = info;
1163 args.is_gs_copy_shader = gs_copy_shader;
1164 radv_declare_shader_args(&args,
1165 gs_copy_shader ? MESA_SHADER_VERTEX
1166 : shaders[shader_count - 1]->info.stage,
1167 shader_count >= 2,
1168 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1169 : MESA_SHADER_VERTEX);
1170
1171 if (device->physical_device->use_llvm ||
1172 options->dump_shader || options->record_ir)
1173 ac_init_llvm_once();
1174
1175 if (device->physical_device->use_llvm) {
1176 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1177 } else {
1178 aco_compile_shader(shader_count, shaders, &binary, &args);
1179 }
1180
1181 binary->info = *info;
1182
1183 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1184 keep_shader_info);
1185 if (!variant) {
1186 free(binary);
1187 return NULL;
1188 }
1189
1190 if (options->dump_shader) {
1191 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1192 for (int i = 1; i < shader_count; ++i)
1193 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1194
1195 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1196 }
1197
1198
1199 if (keep_shader_info) {
1200 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1201 if (!gs_copy_shader && !module->nir) {
1202 variant->spirv = malloc(module->size);
1203 if (!variant->spirv) {
1204 free(variant);
1205 free(binary);
1206 return NULL;
1207 }
1208
1209 memcpy(variant->spirv, module->data, module->size);
1210 variant->spirv_size = module->size;
1211 }
1212 }
1213
1214 if (binary_out)
1215 *binary_out = binary;
1216 else
1217 free(binary);
1218
1219 return variant;
1220 }
1221
1222 struct radv_shader_variant *
1223 radv_shader_variant_compile(struct radv_device *device,
1224 struct radv_shader_module *module,
1225 struct nir_shader *const *shaders,
1226 int shader_count,
1227 struct radv_pipeline_layout *layout,
1228 const struct radv_shader_variant_key *key,
1229 struct radv_shader_info *info,
1230 bool keep_shader_info, bool keep_statistic_info,
1231 struct radv_shader_binary **binary_out)
1232 {
1233 struct radv_nir_compiler_options options = {0};
1234
1235 options.layout = layout;
1236 if (key)
1237 options.key = *key;
1238
1239 options.explicit_scratch_args = !device->physical_device->use_llvm;
1240 options.robust_buffer_access = device->robust_buffer_access;
1241
1242 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1243 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1244 }
1245
1246 struct radv_shader_variant *
1247 radv_create_gs_copy_shader(struct radv_device *device,
1248 struct nir_shader *shader,
1249 struct radv_shader_info *info,
1250 struct radv_shader_binary **binary_out,
1251 bool keep_shader_info, bool keep_statistic_info,
1252 bool multiview)
1253 {
1254 struct radv_nir_compiler_options options = {0};
1255
1256 options.explicit_scratch_args = !device->physical_device->use_llvm;
1257 options.key.has_multiview_view_index = multiview;
1258
1259 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1260 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1261 }
1262
1263 void
1264 radv_shader_variant_destroy(struct radv_device *device,
1265 struct radv_shader_variant *variant)
1266 {
1267 if (!p_atomic_dec_zero(&variant->ref_count))
1268 return;
1269
1270 mtx_lock(&device->shader_slab_mutex);
1271 list_del(&variant->slab_list);
1272 mtx_unlock(&device->shader_slab_mutex);
1273
1274 free(variant->spirv);
1275 free(variant->nir_string);
1276 free(variant->disasm_string);
1277 free(variant->ir_string);
1278 free(variant->statistics);
1279 free(variant);
1280 }
1281
1282 const char *
1283 radv_get_shader_name(struct radv_shader_info *info,
1284 gl_shader_stage stage)
1285 {
1286 switch (stage) {
1287 case MESA_SHADER_VERTEX:
1288 if (info->vs.as_ls)
1289 return "Vertex Shader as LS";
1290 else if (info->vs.as_es)
1291 return "Vertex Shader as ES";
1292 else if (info->is_ngg)
1293 return "Vertex Shader as ESGS";
1294 else
1295 return "Vertex Shader as VS";
1296 case MESA_SHADER_TESS_CTRL:
1297 return "Tessellation Control Shader";
1298 case MESA_SHADER_TESS_EVAL:
1299 if (info->tes.as_es)
1300 return "Tessellation Evaluation Shader as ES";
1301 else if (info->is_ngg)
1302 return "Tessellation Evaluation Shader as ESGS";
1303 else
1304 return "Tessellation Evaluation Shader as VS";
1305 case MESA_SHADER_GEOMETRY:
1306 return "Geometry Shader";
1307 case MESA_SHADER_FRAGMENT:
1308 return "Pixel Shader";
1309 case MESA_SHADER_COMPUTE:
1310 return "Compute Shader";
1311 default:
1312 return "Unknown shader";
1313 };
1314 }
1315
1316 unsigned
1317 radv_get_max_workgroup_size(enum chip_class chip_class,
1318 gl_shader_stage stage,
1319 const unsigned *sizes)
1320 {
1321 switch (stage) {
1322 case MESA_SHADER_TESS_CTRL:
1323 return chip_class >= GFX7 ? 128 : 64;
1324 case MESA_SHADER_GEOMETRY:
1325 return chip_class >= GFX9 ? 128 : 64;
1326 case MESA_SHADER_COMPUTE:
1327 break;
1328 default:
1329 return 0;
1330 }
1331
1332 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1333 return max_workgroup_size;
1334 }
1335
1336 unsigned
1337 radv_get_max_waves(struct radv_device *device,
1338 struct radv_shader_variant *variant,
1339 gl_shader_stage stage)
1340 {
1341 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1342 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1343 uint8_t wave_size = variant->info.wave_size;
1344 struct ac_shader_config *conf = &variant->config;
1345 unsigned max_simd_waves;
1346 unsigned lds_per_wave = 0;
1347
1348 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1349
1350 if (stage == MESA_SHADER_FRAGMENT) {
1351 lds_per_wave = conf->lds_size * lds_increment +
1352 align(variant->info.ps.num_interp * 48,
1353 lds_increment);
1354 } else if (stage == MESA_SHADER_COMPUTE) {
1355 unsigned max_workgroup_size =
1356 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1357 lds_per_wave = (conf->lds_size * lds_increment) /
1358 DIV_ROUND_UP(max_workgroup_size, wave_size);
1359 }
1360
1361 if (conf->num_sgprs) {
1362 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1363 max_simd_waves =
1364 MIN2(max_simd_waves,
1365 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1366 sgprs);
1367 }
1368
1369 if (conf->num_vgprs) {
1370 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1371 max_simd_waves =
1372 MIN2(max_simd_waves,
1373 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1374 }
1375
1376 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1377 if (lds_per_wave)
1378 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1379
1380 return max_simd_waves;
1381 }
1382
1383 static void
1384 generate_shader_stats(struct radv_device *device,
1385 struct radv_shader_variant *variant,
1386 gl_shader_stage stage,
1387 struct _mesa_string_buffer *buf)
1388 {
1389 struct ac_shader_config *conf = &variant->config;
1390 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1391
1392 if (stage == MESA_SHADER_FRAGMENT) {
1393 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1394 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1395 "SPI_PS_INPUT_ENA = 0x%04x\n",
1396 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1397 }
1398
1399 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1400 "SGPRS: %d\n"
1401 "VGPRS: %d\n"
1402 "Spilled SGPRs: %d\n"
1403 "Spilled VGPRs: %d\n"
1404 "PrivMem VGPRS: %d\n"
1405 "Code Size: %d bytes\n"
1406 "LDS: %d blocks\n"
1407 "Scratch: %d bytes per wave\n"
1408 "Max Waves: %d\n",
1409 conf->num_sgprs, conf->num_vgprs,
1410 conf->spilled_sgprs, conf->spilled_vgprs,
1411 variant->info.private_mem_vgprs, variant->exec_size,
1412 conf->lds_size, conf->scratch_bytes_per_wave,
1413 max_simd_waves);
1414
1415 if (variant->statistics) {
1416 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1417 for (unsigned i = 0; i < variant->statistics->count; i++) {
1418 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1419 uint32_t value = variant->statistics->values[i];
1420 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1421 }
1422 }
1423
1424 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1425 }
1426
1427 void
1428 radv_shader_dump_stats(struct radv_device *device,
1429 struct radv_shader_variant *variant,
1430 gl_shader_stage stage,
1431 FILE *file)
1432 {
1433 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1434
1435 generate_shader_stats(device, variant, stage, buf);
1436
1437 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1438 fprintf(file, "%s", buf->buf);
1439
1440 _mesa_string_buffer_destroy(buf);
1441 }
1442
1443 VkResult
1444 radv_GetShaderInfoAMD(VkDevice _device,
1445 VkPipeline _pipeline,
1446 VkShaderStageFlagBits shaderStage,
1447 VkShaderInfoTypeAMD infoType,
1448 size_t* pInfoSize,
1449 void* pInfo)
1450 {
1451 RADV_FROM_HANDLE(radv_device, device, _device);
1452 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1453 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1454 struct radv_shader_variant *variant = pipeline->shaders[stage];
1455 struct _mesa_string_buffer *buf;
1456 VkResult result = VK_SUCCESS;
1457
1458 /* Spec doesn't indicate what to do if the stage is invalid, so just
1459 * return no info for this. */
1460 if (!variant)
1461 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1462
1463 switch (infoType) {
1464 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1465 if (!pInfo) {
1466 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1467 } else {
1468 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1469 struct ac_shader_config *conf = &variant->config;
1470
1471 VkShaderStatisticsInfoAMD statistics = {};
1472 statistics.shaderStageMask = shaderStage;
1473 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1474 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1475 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1476
1477 if (stage == MESA_SHADER_COMPUTE) {
1478 unsigned *local_size = variant->info.cs.block_size;
1479 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1480
1481 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1482 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1483
1484 statistics.computeWorkGroupSize[0] = local_size[0];
1485 statistics.computeWorkGroupSize[1] = local_size[1];
1486 statistics.computeWorkGroupSize[2] = local_size[2];
1487 } else {
1488 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1489 }
1490
1491 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1492 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1493 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1494 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1495 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1496
1497 size_t size = *pInfoSize;
1498 *pInfoSize = sizeof(statistics);
1499
1500 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1501
1502 if (size < *pInfoSize)
1503 result = VK_INCOMPLETE;
1504 }
1505
1506 break;
1507 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1508 buf = _mesa_string_buffer_create(NULL, 1024);
1509
1510 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1511 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1512 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1513 generate_shader_stats(device, variant, stage, buf);
1514
1515 /* Need to include the null terminator. */
1516 size_t length = buf->length + 1;
1517
1518 if (!pInfo) {
1519 *pInfoSize = length;
1520 } else {
1521 size_t size = *pInfoSize;
1522 *pInfoSize = length;
1523
1524 memcpy(pInfo, buf->buf, MIN2(size, length));
1525
1526 if (size < length)
1527 result = VK_INCOMPLETE;
1528 }
1529
1530 _mesa_string_buffer_destroy(buf);
1531 break;
1532 default:
1533 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1534 result = VK_ERROR_FEATURE_NOT_PRESENT;
1535 break;
1536 }
1537
1538 return result;
1539 }