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radv: Put wave size in shader options/info.
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "ac_rtld.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp16 = true,
57 .lower_flrp32 = true,
58 .lower_flrp64 = true,
59 .lower_device_index_to_zero = true,
60 .lower_fsat = true,
61 .lower_fdiv = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 };
82
83 bool
84 radv_can_dump_shader(struct radv_device *device,
85 struct radv_shader_module *module,
86 bool is_gs_copy_shader)
87 {
88 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
89 return false;
90
91 /* Only dump non-meta shaders, useful for debugging purposes. */
92 return (module && !module->nir) || is_gs_copy_shader;
93 }
94
95 bool
96 radv_can_dump_shader_stats(struct radv_device *device,
97 struct radv_shader_module *module)
98 {
99 /* Only dump non-meta shader stats. */
100 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
101 module && !module->nir;
102 }
103
104 unsigned shader_io_get_unique_index(gl_varying_slot slot)
105 {
106 /* handle patch indices separate */
107 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
108 return 0;
109 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
110 return 1;
111 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
112 return 2 + (slot - VARYING_SLOT_PATCH0);
113 if (slot == VARYING_SLOT_POS)
114 return 0;
115 if (slot == VARYING_SLOT_PSIZ)
116 return 1;
117 if (slot == VARYING_SLOT_CLIP_DIST0)
118 return 2;
119 if (slot == VARYING_SLOT_CLIP_DIST1)
120 return 3;
121 /* 3 is reserved for clip dist as well */
122 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
123 return 4 + (slot - VARYING_SLOT_VAR0);
124 unreachable("illegal slot in get unique index\n");
125 }
126
127 VkResult radv_CreateShaderModule(
128 VkDevice _device,
129 const VkShaderModuleCreateInfo* pCreateInfo,
130 const VkAllocationCallbacks* pAllocator,
131 VkShaderModule* pShaderModule)
132 {
133 RADV_FROM_HANDLE(radv_device, device, _device);
134 struct radv_shader_module *module;
135
136 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
137 assert(pCreateInfo->flags == 0);
138
139 module = vk_alloc2(&device->alloc, pAllocator,
140 sizeof(*module) + pCreateInfo->codeSize, 8,
141 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
142 if (module == NULL)
143 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
144
145 module->nir = NULL;
146 module->size = pCreateInfo->codeSize;
147 memcpy(module->data, pCreateInfo->pCode, module->size);
148
149 _mesa_sha1_compute(module->data, module->size, module->sha1);
150
151 *pShaderModule = radv_shader_module_to_handle(module);
152
153 return VK_SUCCESS;
154 }
155
156 void radv_DestroyShaderModule(
157 VkDevice _device,
158 VkShaderModule _module,
159 const VkAllocationCallbacks* pAllocator)
160 {
161 RADV_FROM_HANDLE(radv_device, device, _device);
162 RADV_FROM_HANDLE(radv_shader_module, module, _module);
163
164 if (!module)
165 return;
166
167 vk_free2(&device->alloc, pAllocator, module);
168 }
169
170 void
171 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
172 bool allow_copies)
173 {
174 bool progress;
175 unsigned lower_flrp =
176 (shader->options->lower_flrp16 ? 16 : 0) |
177 (shader->options->lower_flrp32 ? 32 : 0) |
178 (shader->options->lower_flrp64 ? 64 : 0);
179
180 do {
181 progress = false;
182
183 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
184 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
185
186 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
187 NIR_PASS_V(shader, nir_lower_pack);
188
189 if (allow_copies) {
190 /* Only run this pass in the first call to
191 * radv_optimize_nir. Later calls assume that we've
192 * lowered away any copy_deref instructions and we
193 * don't want to introduce any more.
194 */
195 NIR_PASS(progress, shader, nir_opt_find_array_copies);
196 }
197
198 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
199 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
200 NIR_PASS(progress, shader, nir_remove_dead_variables,
201 nir_var_function_temp);
202
203 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
204 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
205
206 NIR_PASS(progress, shader, nir_copy_prop);
207 NIR_PASS(progress, shader, nir_opt_remove_phis);
208 NIR_PASS(progress, shader, nir_opt_dce);
209 if (nir_opt_trivial_continues(shader)) {
210 progress = true;
211 NIR_PASS(progress, shader, nir_copy_prop);
212 NIR_PASS(progress, shader, nir_opt_remove_phis);
213 NIR_PASS(progress, shader, nir_opt_dce);
214 }
215 NIR_PASS(progress, shader, nir_opt_if, true);
216 NIR_PASS(progress, shader, nir_opt_dead_cf);
217 NIR_PASS(progress, shader, nir_opt_cse);
218 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
219 NIR_PASS(progress, shader, nir_opt_constant_folding);
220 NIR_PASS(progress, shader, nir_opt_algebraic);
221
222 if (lower_flrp != 0) {
223 bool lower_flrp_progress = false;
224 NIR_PASS(lower_flrp_progress,
225 shader,
226 nir_lower_flrp,
227 lower_flrp,
228 false /* always_precise */,
229 shader->options->lower_ffma);
230 if (lower_flrp_progress) {
231 NIR_PASS(progress, shader,
232 nir_opt_constant_folding);
233 progress = true;
234 }
235
236 /* Nothing should rematerialize any flrps, so we only
237 * need to do this lowering once.
238 */
239 lower_flrp = 0;
240 }
241
242 NIR_PASS(progress, shader, nir_opt_undef);
243 if (shader->options->max_unroll_iterations) {
244 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
245 }
246 } while (progress && !optimize_conservatively);
247
248 NIR_PASS(progress, shader, nir_opt_conditional_discard);
249 NIR_PASS(progress, shader, nir_opt_shrink_load);
250 NIR_PASS(progress, shader, nir_opt_move_load_ubo);
251 }
252
253 nir_shader *
254 radv_shader_compile_to_nir(struct radv_device *device,
255 struct radv_shader_module *module,
256 const char *entrypoint_name,
257 gl_shader_stage stage,
258 const VkSpecializationInfo *spec_info,
259 const VkPipelineCreateFlags flags,
260 const struct radv_pipeline_layout *layout)
261 {
262 nir_shader *nir;
263 if (module->nir) {
264 /* Some things such as our meta clear/blit code will give us a NIR
265 * shader directly. In that case, we just ignore the SPIR-V entirely
266 * and just use the NIR shader */
267 nir = module->nir;
268 nir->options = &nir_options;
269 nir_validate_shader(nir, "in internal shader");
270
271 assert(exec_list_length(&nir->functions) == 1);
272 } else {
273 uint32_t *spirv = (uint32_t *) module->data;
274 assert(module->size % 4 == 0);
275
276 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
277 radv_print_spirv(spirv, module->size, stderr);
278
279 uint32_t num_spec_entries = 0;
280 struct nir_spirv_specialization *spec_entries = NULL;
281 if (spec_info && spec_info->mapEntryCount > 0) {
282 num_spec_entries = spec_info->mapEntryCount;
283 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
284 for (uint32_t i = 0; i < num_spec_entries; i++) {
285 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
286 const void *data = spec_info->pData + entry.offset;
287 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
288
289 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
290 if (spec_info->dataSize == 8)
291 spec_entries[i].data64 = *(const uint64_t *)data;
292 else
293 spec_entries[i].data32 = *(const uint32_t *)data;
294 }
295 }
296 const struct spirv_to_nir_options spirv_options = {
297 .lower_ubo_ssbo_access_to_offsets = true,
298 .caps = {
299 .amd_gcn_shader = true,
300 .amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT,
301 .amd_trinary_minmax = true,
302 .derivative_group = true,
303 .descriptor_array_dynamic_indexing = true,
304 .descriptor_array_non_uniform_indexing = true,
305 .descriptor_indexing = true,
306 .device_group = true,
307 .draw_parameters = true,
308 .float16 = true,
309 .float64 = true,
310 .geometry_streams = true,
311 .image_read_without_format = true,
312 .image_write_without_format = true,
313 .int8 = true,
314 .int16 = true,
315 .int64 = true,
316 .int64_atomics = true,
317 .multiview = true,
318 .physical_storage_buffer_address = true,
319 .post_depth_coverage = true,
320 .runtime_descriptor_array = true,
321 .shader_viewport_index_layer = true,
322 .stencil_export = true,
323 .storage_8bit = true,
324 .storage_16bit = true,
325 .storage_image_ms = true,
326 .subgroup_arithmetic = true,
327 .subgroup_ballot = true,
328 .subgroup_basic = true,
329 .subgroup_quad = true,
330 .subgroup_shuffle = true,
331 .subgroup_vote = true,
332 .tessellation = true,
333 .transform_feedback = true,
334 .variable_pointers = true,
335 },
336 .ubo_addr_format = nir_address_format_32bit_index_offset,
337 .ssbo_addr_format = nir_address_format_32bit_index_offset,
338 .phys_ssbo_addr_format = nir_address_format_64bit_global,
339 .push_const_addr_format = nir_address_format_logical,
340 .shared_addr_format = nir_address_format_32bit_offset,
341 .frag_coord_is_sysval = true,
342 };
343 nir = spirv_to_nir(spirv, module->size / 4,
344 spec_entries, num_spec_entries,
345 stage, entrypoint_name,
346 &spirv_options, &nir_options);
347 assert(nir->info.stage == stage);
348 nir_validate_shader(nir, "after spirv_to_nir");
349
350 free(spec_entries);
351
352 /* We have to lower away local constant initializers right before we
353 * inline functions. That way they get properly initialized at the top
354 * of the function and not at the top of its caller.
355 */
356 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
357 NIR_PASS_V(nir, nir_lower_returns);
358 NIR_PASS_V(nir, nir_inline_functions);
359 NIR_PASS_V(nir, nir_opt_deref);
360
361 /* Pick off the single entrypoint that we want */
362 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
363 if (func->is_entrypoint)
364 func->name = ralloc_strdup(func, "main");
365 else
366 exec_node_remove(&func->node);
367 }
368 assert(exec_list_length(&nir->functions) == 1);
369
370 /* Make sure we lower constant initializers on output variables so that
371 * nir_remove_dead_variables below sees the corresponding stores
372 */
373 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
374
375 /* Now that we've deleted all but the main function, we can go ahead and
376 * lower the rest of the constant initializers.
377 */
378 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
379
380 /* Split member structs. We do this before lower_io_to_temporaries so that
381 * it doesn't lower system values to temporaries by accident.
382 */
383 NIR_PASS_V(nir, nir_split_var_copies);
384 NIR_PASS_V(nir, nir_split_per_member_structs);
385
386 if (nir->info.stage == MESA_SHADER_FRAGMENT)
387 NIR_PASS_V(nir, nir_lower_input_attachments, true);
388
389 NIR_PASS_V(nir, nir_remove_dead_variables,
390 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
391
392 NIR_PASS_V(nir, nir_lower_system_values);
393 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
394 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
395 }
396
397 /* Vulkan uses the separate-shader linking model */
398 nir->info.separate_shader = true;
399
400 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
401
402 static const nir_lower_tex_options tex_options = {
403 .lower_txp = ~0,
404 .lower_tg4_offsets = true,
405 };
406
407 nir_lower_tex(nir, &tex_options);
408
409 nir_lower_vars_to_ssa(nir);
410
411 if (nir->info.stage == MESA_SHADER_VERTEX ||
412 nir->info.stage == MESA_SHADER_GEOMETRY ||
413 nir->info.stage == MESA_SHADER_FRAGMENT) {
414 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
415 nir_shader_get_entrypoint(nir), true, true);
416 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
417 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
418 nir_shader_get_entrypoint(nir), true, false);
419 }
420
421 nir_split_var_copies(nir);
422
423 nir_lower_global_vars_to_local(nir);
424 nir_remove_dead_variables(nir, nir_var_function_temp);
425 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
426 .subgroup_size = 64,
427 .ballot_bit_size = 64,
428 .lower_to_scalar = 1,
429 .lower_subgroup_masks = 1,
430 .lower_shuffle = 1,
431 .lower_shuffle_to_32bit = 1,
432 .lower_vote_eq_to_ballot = 1,
433 });
434
435 nir_lower_load_const_to_scalar(nir);
436
437 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
438 radv_optimize_nir(nir, false, true);
439
440 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
441 * to remove any copies introduced by nir_opt_find_array_copies().
442 */
443 nir_lower_var_copies(nir);
444
445 /* Indirect lowering must be called after the radv_optimize_nir() loop
446 * has been called at least once. Otherwise indirect lowering can
447 * bloat the instruction count of the loop and cause it to be
448 * considered too large for unrolling.
449 */
450 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
451 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
452
453 return nir;
454 }
455
456 static void mark_16bit_fs_input(struct radv_shader_variant_info *shader_info,
457 const struct glsl_type *type,
458 int location)
459 {
460 if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
461 unsigned attrib_count = glsl_count_attribute_slots(type, false);
462 if (glsl_type_is_16bit(type)) {
463 shader_info->fs.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
464 }
465 } else if (glsl_type_is_array(type)) {
466 unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
467 for (unsigned i = 0; i < glsl_get_length(type); ++i) {
468 mark_16bit_fs_input(shader_info, glsl_get_array_element(type), location + i * stride);
469 }
470 } else {
471 assert(glsl_type_is_struct_or_ifc(type));
472 for (unsigned i = 0; i < glsl_get_length(type); i++) {
473 mark_16bit_fs_input(shader_info, glsl_get_struct_field(type, i), location);
474 location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
475 }
476 }
477 }
478
479 static void
480 handle_fs_input_decl(struct radv_shader_variant_info *shader_info,
481 struct nir_variable *variable)
482 {
483 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
484
485 if (variable->data.compact) {
486 unsigned component_count = variable->data.location_frac +
487 glsl_get_length(variable->type);
488 attrib_count = (component_count + 3) / 4;
489 } else {
490 mark_16bit_fs_input(shader_info, variable->type,
491 variable->data.driver_location);
492 }
493
494 uint64_t mask = ((1ull << attrib_count) - 1);
495
496 if (variable->data.interpolation == INTERP_MODE_FLAT)
497 shader_info->fs.flat_shaded_mask |= mask << variable->data.driver_location;
498
499 if (variable->data.location >= VARYING_SLOT_VAR0)
500 shader_info->fs.input_mask |= mask << (variable->data.location - VARYING_SLOT_VAR0);
501 }
502
503 static int
504 type_size_vec4(const struct glsl_type *type, bool bindless)
505 {
506 return glsl_count_attribute_slots(type, false);
507 }
508
509 static nir_variable *
510 find_layer_in_var(nir_shader *nir)
511 {
512 nir_foreach_variable(var, &nir->inputs) {
513 if (var->data.location == VARYING_SLOT_LAYER) {
514 return var;
515 }
516 }
517
518 nir_variable *var =
519 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
520 var->data.location = VARYING_SLOT_LAYER;
521 var->data.interpolation = INTERP_MODE_FLAT;
522 return var;
523 }
524
525 /* We use layered rendering to implement multiview, which means we need to map
526 * view_index to gl_Layer. The attachment lowering also uses needs to know the
527 * layer so that it can sample from the correct layer. The code generates a
528 * load from the layer_id sysval, but since we don't have a way to get at this
529 * information from the fragment shader, we also need to lower this to the
530 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
531 * slot, before lowering io, so that nir_assign_var_locations() will give the
532 * LAYER varying the correct driver_location.
533 */
534
535 static bool
536 lower_view_index(nir_shader *nir)
537 {
538 bool progress = false;
539 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
540 nir_builder b;
541 nir_builder_init(&b, entry);
542
543 nir_variable *layer = NULL;
544 nir_foreach_block(block, entry) {
545 nir_foreach_instr_safe(instr, block) {
546 if (instr->type != nir_instr_type_intrinsic)
547 continue;
548
549 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
550 if (load->intrinsic != nir_intrinsic_load_view_index &&
551 load->intrinsic != nir_intrinsic_load_layer_id)
552 continue;
553
554 if (!layer)
555 layer = find_layer_in_var(nir);
556
557 b.cursor = nir_before_instr(instr);
558 nir_ssa_def *def = nir_load_var(&b, layer);
559 nir_ssa_def_rewrite_uses(&load->dest.ssa,
560 nir_src_for_ssa(def));
561
562 nir_instr_remove(instr);
563 progress = true;
564 }
565 }
566
567 return progress;
568 }
569
570 /* Gather information needed to setup the vs<->ps linking registers in
571 * radv_pipeline_generate_ps_inputs().
572 */
573
574 static void
575 handle_fs_inputs(nir_shader *nir, struct radv_shader_variant_info *shader_info)
576 {
577 shader_info->fs.num_interp = nir->num_inputs;
578
579 nir_foreach_variable(variable, &nir->inputs)
580 handle_fs_input_decl(shader_info, variable);
581 }
582
583 static void
584 lower_fs_io(nir_shader *nir, struct radv_shader_variant_info *shader_info)
585 {
586 NIR_PASS_V(nir, lower_view_index);
587 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
588 MESA_SHADER_FRAGMENT);
589
590 handle_fs_inputs(nir, shader_info);
591
592 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
593
594 /* This pass needs actual constants */
595 nir_opt_constant_folding(nir);
596
597 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
598 }
599
600
601 void *
602 radv_alloc_shader_memory(struct radv_device *device,
603 struct radv_shader_variant *shader)
604 {
605 mtx_lock(&device->shader_slab_mutex);
606 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
607 uint64_t offset = 0;
608 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
609 if (s->bo_offset - offset >= shader->code_size) {
610 shader->bo = slab->bo;
611 shader->bo_offset = offset;
612 list_addtail(&shader->slab_list, &s->slab_list);
613 mtx_unlock(&device->shader_slab_mutex);
614 return slab->ptr + offset;
615 }
616 offset = align_u64(s->bo_offset + s->code_size, 256);
617 }
618 if (slab->size - offset >= shader->code_size) {
619 shader->bo = slab->bo;
620 shader->bo_offset = offset;
621 list_addtail(&shader->slab_list, &slab->shaders);
622 mtx_unlock(&device->shader_slab_mutex);
623 return slab->ptr + offset;
624 }
625 }
626
627 mtx_unlock(&device->shader_slab_mutex);
628 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
629
630 slab->size = 256 * 1024;
631 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
632 RADEON_DOMAIN_VRAM,
633 RADEON_FLAG_NO_INTERPROCESS_SHARING |
634 (device->physical_device->cpdma_prefetch_writes_memory ?
635 0 : RADEON_FLAG_READ_ONLY),
636 RADV_BO_PRIORITY_SHADER);
637 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
638 list_inithead(&slab->shaders);
639
640 mtx_lock(&device->shader_slab_mutex);
641 list_add(&slab->slabs, &device->shader_slabs);
642
643 shader->bo = slab->bo;
644 shader->bo_offset = 0;
645 list_add(&shader->slab_list, &slab->shaders);
646 mtx_unlock(&device->shader_slab_mutex);
647 return slab->ptr;
648 }
649
650 void
651 radv_destroy_shader_slabs(struct radv_device *device)
652 {
653 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
654 device->ws->buffer_destroy(slab->bo);
655 free(slab);
656 }
657 mtx_destroy(&device->shader_slab_mutex);
658 }
659
660 /* For the UMR disassembler. */
661 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
662 #define DEBUGGER_NUM_MARKERS 5
663
664 static unsigned
665 radv_get_shader_binary_size(size_t code_size)
666 {
667 return code_size + DEBUGGER_NUM_MARKERS * 4;
668 }
669
670 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
671 const struct ac_shader_config *config_in,
672 const struct radv_shader_variant_info *info,
673 gl_shader_stage stage,
674 struct ac_shader_config *config_out)
675 {
676 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
677 unsigned vgpr_comp_cnt = 0;
678 unsigned num_input_vgprs = info->num_input_vgprs;
679
680 if (stage == MESA_SHADER_FRAGMENT) {
681 num_input_vgprs = 0;
682 if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
683 num_input_vgprs += 2;
684 if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
685 num_input_vgprs += 2;
686 if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
687 num_input_vgprs += 2;
688 if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
689 num_input_vgprs += 3;
690 if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
691 num_input_vgprs += 2;
692 if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
693 num_input_vgprs += 2;
694 if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
695 num_input_vgprs += 2;
696 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
697 num_input_vgprs += 1;
698 if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
699 num_input_vgprs += 1;
700 if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
701 num_input_vgprs += 1;
702 if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
703 num_input_vgprs += 1;
704 if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
705 num_input_vgprs += 1;
706 if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
707 num_input_vgprs += 1;
708 if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
709 num_input_vgprs += 1;
710 if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
711 num_input_vgprs += 1;
712 if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
713 num_input_vgprs += 1;
714 }
715
716 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
717 /* +3 for scratch wave offset and VCC */
718 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
719
720 *config_out = *config_in;
721 config_out->num_vgprs = num_vgprs;
722 config_out->num_sgprs = num_sgprs;
723
724 /* Enable 64-bit and 16-bit denormals, because there is no performance
725 * cost.
726 *
727 * If denormals are enabled, all floating-point output modifiers are
728 * ignored.
729 *
730 * Don't enable denormals for 32-bit floats, because:
731 * - Floating-point output modifiers would be ignored by the hw.
732 * - Some opcodes don't support denormals, such as v_mad_f32. We would
733 * have to stop using those.
734 * - GFX6 & GFX7 would be very slow.
735 */
736 config_out->float_mode |= V_00B028_FP_64_DENORMS;
737
738 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
739 S_00B12C_SCRATCH_EN(scratch_enabled) |
740 S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
741 S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
742 S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
743 S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
744 S_00B12C_SO_EN(!!info->info.so.num_outputs);
745
746 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
747 (info->info.wave_size == 32 ? 8 : 4)) |
748 S_00B848_DX10_CLAMP(1) |
749 S_00B848_FLOAT_MODE(config_out->float_mode);
750
751 if (pdevice->rad_info.chip_class >= GFX10) {
752 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
753 } else {
754 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
755 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
756 }
757
758 switch (stage) {
759 case MESA_SHADER_TESS_EVAL:
760 if (info->is_ngg) {
761 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
762 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
763 } else if (info->tes.as_es) {
764 assert(pdevice->rad_info.chip_class <= GFX8);
765 vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
766
767 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
768 } else {
769 bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
770 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
771
772 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
773 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
774 }
775 break;
776 case MESA_SHADER_TESS_CTRL:
777 if (pdevice->rad_info.chip_class >= GFX9) {
778 /* We need at least 2 components for LS.
779 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
780 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
781 */
782 if (pdevice->rad_info.chip_class >= GFX10) {
783 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 1;
784 } else {
785 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
786 }
787 } else {
788 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
789 }
790 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
791 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
792 break;
793 case MESA_SHADER_VERTEX:
794 if (info->is_ngg) {
795 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
796 } else if (info->vs.as_ls) {
797 assert(pdevice->rad_info.chip_class <= GFX8);
798 /* We need at least 2 components for LS.
799 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
800 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
801 */
802 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
803 } else if (info->vs.as_es) {
804 assert(pdevice->rad_info.chip_class <= GFX8);
805 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
806 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
807 } else {
808 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
809 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
810 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
811 */
812 if (info->vs.export_prim_id) {
813 vgpr_comp_cnt = 2;
814 } else if (info->info.vs.needs_instance_id) {
815 vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
816 } else {
817 vgpr_comp_cnt = 0;
818 }
819
820 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
821 }
822 break;
823 case MESA_SHADER_FRAGMENT:
824 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
825 break;
826 case MESA_SHADER_GEOMETRY:
827 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
828 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
829 break;
830 case MESA_SHADER_COMPUTE:
831 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
832 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
833 config_out->rsrc2 |=
834 S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) |
835 S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) |
836 S_00B84C_TGID_Z_EN(info->info.cs.uses_block_id[2]) |
837 S_00B84C_TIDIG_COMP_CNT(info->info.cs.uses_thread_id[2] ? 2 :
838 info->info.cs.uses_thread_id[1] ? 1 : 0) |
839 S_00B84C_TG_SIZE_EN(info->info.cs.uses_local_invocation_idx) |
840 S_00B84C_LDS_SIZE(config_in->lds_size);
841 break;
842 default:
843 unreachable("unsupported shader type");
844 break;
845 }
846
847 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
848 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
849 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
850 gl_shader_stage es_stage = stage;
851 if (stage == MESA_SHADER_GEOMETRY)
852 es_stage = info->gs.es_type;
853
854 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
855 if (es_stage == MESA_SHADER_VERTEX) {
856 es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 0;
857 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
858 bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
859 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
860 } else
861 unreachable("Unexpected ES shader stage");
862
863 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
864 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
865 if (info->info.uses_invocation_id || stage == MESA_SHADER_VERTEX) {
866 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
867 } else if (info->info.uses_prim_id) {
868 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
869 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
870 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
871 } else {
872 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
873 }
874
875 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
876 S_00B228_WGP_MODE(1);
877 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
878 S_00B22C_LDS_SIZE(config_in->lds_size) |
879 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
880 } else if (pdevice->rad_info.chip_class >= GFX9 &&
881 stage == MESA_SHADER_GEOMETRY) {
882 unsigned es_type = info->gs.es_type;
883 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
884
885 if (es_type == MESA_SHADER_VERTEX) {
886 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
887 if (info->info.vs.needs_instance_id) {
888 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
889 } else {
890 es_vgpr_comp_cnt = 0;
891 }
892 } else if (es_type == MESA_SHADER_TESS_EVAL) {
893 es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
894 } else {
895 unreachable("invalid shader ES type");
896 }
897
898 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
899 * VGPR[0:4] are always loaded.
900 */
901 if (info->info.uses_invocation_id) {
902 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
903 } else if (info->info.uses_prim_id) {
904 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
905 } else if (info->gs.vertices_in >= 3) {
906 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
907 } else {
908 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
909 }
910
911 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
912 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
913 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
914 } else if (pdevice->rad_info.chip_class >= GFX9 &&
915 stage == MESA_SHADER_TESS_CTRL) {
916 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
917 } else {
918 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
919 }
920 }
921
922 static void radv_init_llvm_target()
923 {
924 LLVMInitializeAMDGPUTargetInfo();
925 LLVMInitializeAMDGPUTarget();
926 LLVMInitializeAMDGPUTargetMC();
927 LLVMInitializeAMDGPUAsmPrinter();
928
929 /* For inline assembly. */
930 LLVMInitializeAMDGPUAsmParser();
931
932 /* Workaround for bug in llvm 4.0 that causes image intrinsics
933 * to disappear.
934 * https://reviews.llvm.org/D26348
935 *
936 * Workaround for bug in llvm that causes the GPU to hang in presence
937 * of nested loops because there is an exec mask issue. The proper
938 * solution is to fix LLVM but this might require a bunch of work.
939 * https://bugs.llvm.org/show_bug.cgi?id=37744
940 *
941 * "mesa" is the prefix for error messages.
942 */
943 if (HAVE_LLVM >= 0x0800) {
944 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
945 LLVMParseCommandLineOptions(2, argv, NULL);
946
947 } else {
948 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
949 "-amdgpu-skip-threshold=1" };
950 LLVMParseCommandLineOptions(3, argv, NULL);
951 }
952 }
953
954 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
955
956 static void radv_init_llvm_once(void)
957 {
958 call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
959 }
960
961 struct radv_shader_variant *
962 radv_shader_variant_create(struct radv_device *device,
963 const struct radv_shader_binary *binary)
964 {
965 struct ac_shader_config config = {0};
966 struct ac_rtld_binary rtld_binary = {0};
967 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
968 if (!variant)
969 return NULL;
970
971 variant->ref_count = 1;
972
973 if (binary->type == RADV_BINARY_TYPE_RTLD) {
974 struct ac_rtld_symbol lds_symbols[1];
975 unsigned num_lds_symbols = 0;
976 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
977 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
978 unsigned esgs_ring_size = 0;
979
980 if (device->physical_device->rad_info.chip_class >= GFX9 &&
981 binary->stage == MESA_SHADER_GEOMETRY && !binary->is_gs_copy_shader) {
982 /* TODO: Do not hardcode this value */
983 esgs_ring_size = 32 * 1024;
984 }
985
986 if (binary->variant_info.is_ngg) {
987 /* GS stores Primitive IDs into LDS at the address
988 * corresponding to the ES thread of the provoking
989 * vertex. All ES threads load and export PrimitiveID
990 * for their thread.
991 */
992 if (binary->stage == MESA_SHADER_VERTEX &&
993 binary->variant_info.vs.export_prim_id) {
994 /* TODO: Do not harcode this value */
995 esgs_ring_size = 256 /* max_out_verts */ * 4;
996 }
997 }
998
999 if (esgs_ring_size) {
1000 /* We add this symbol even on LLVM <= 8 to ensure that
1001 * shader->config.lds_size is set correctly below.
1002 */
1003 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
1004 sym->name = "esgs_ring";
1005 sym->size = esgs_ring_size;
1006 sym->align = 64 * 1024;
1007
1008 /* Make sure to have LDS space for NGG scratch. */
1009 /* TODO: Compute this correctly somehow? */
1010 if (binary->variant_info.is_ngg)
1011 sym->size -= 32;
1012 }
1013
1014 struct ac_rtld_open_info open_info = {
1015 .info = &device->physical_device->rad_info,
1016 .shader_type = binary->stage,
1017 .wave_size = binary->variant_info.info.wave_size,
1018 .num_parts = 1,
1019 .elf_ptrs = &elf_data,
1020 .elf_sizes = &elf_size,
1021 .num_shared_lds_symbols = num_lds_symbols,
1022 .shared_lds_symbols = lds_symbols,
1023 };
1024
1025 if (!ac_rtld_open(&rtld_binary, open_info)) {
1026 free(variant);
1027 return NULL;
1028 }
1029
1030 if (!ac_rtld_read_config(&rtld_binary, &config)) {
1031 ac_rtld_close(&rtld_binary);
1032 free(variant);
1033 return NULL;
1034 }
1035
1036 if (rtld_binary.lds_size > 0) {
1037 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1038 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
1039 }
1040
1041 variant->code_size = rtld_binary.rx_size;
1042 } else {
1043 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1044 config = ((struct radv_shader_binary_legacy *)binary)->config;
1045 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1046 }
1047
1048 variant->info = binary->variant_info;
1049 radv_postprocess_config(device->physical_device, &config, &binary->variant_info,
1050 binary->stage, &variant->config);
1051
1052 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1053
1054 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1055 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1056 struct ac_rtld_upload_info info = {
1057 .binary = &rtld_binary,
1058 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1059 .rx_ptr = dest_ptr,
1060 };
1061
1062 if (!ac_rtld_upload(&info)) {
1063 radv_shader_variant_destroy(device, variant);
1064 ac_rtld_close(&rtld_binary);
1065 return NULL;
1066 }
1067
1068 if (device->keep_shader_info ||
1069 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1070 const char *disasm_data;
1071 size_t disasm_size;
1072 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1073 radv_shader_variant_destroy(device, variant);
1074 ac_rtld_close(&rtld_binary);
1075 return NULL;
1076 }
1077
1078 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1079 variant->disasm_string = malloc(disasm_size + 1);
1080 memcpy(variant->disasm_string, disasm_data, disasm_size);
1081 variant->disasm_string[disasm_size] = 0;
1082 }
1083
1084 ac_rtld_close(&rtld_binary);
1085 } else {
1086 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1087 memcpy(dest_ptr, bin->data, bin->code_size);
1088
1089 /* Add end-of-code markers for the UMR disassembler. */
1090 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1091 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1092 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1093
1094 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1095 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL;
1096 }
1097 return variant;
1098 }
1099
1100 static struct radv_shader_variant *
1101 shader_variant_compile(struct radv_device *device,
1102 struct radv_shader_module *module,
1103 struct nir_shader * const *shaders,
1104 int shader_count,
1105 gl_shader_stage stage,
1106 struct radv_nir_compiler_options *options,
1107 bool gs_copy_shader,
1108 struct radv_shader_binary **binary_out)
1109 {
1110 enum radeon_family chip_family = device->physical_device->rad_info.family;
1111 enum ac_target_machine_options tm_options = 0;
1112 struct ac_llvm_compiler ac_llvm;
1113 struct radv_shader_binary *binary = NULL;
1114 struct radv_shader_variant_info variant_info = {0};
1115 bool thread_compiler;
1116
1117 if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT)
1118 lower_fs_io(shaders[0], &variant_info);
1119
1120 options->family = chip_family;
1121 options->chip_class = device->physical_device->rad_info.chip_class;
1122 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1123 options->dump_preoptir = options->dump_shader &&
1124 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1125 options->record_llvm_ir = device->keep_shader_info;
1126 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1127 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1128 options->address32_hi = device->physical_device->rad_info.address32_hi;
1129
1130 if (stage == MESA_SHADER_COMPUTE)
1131 options->wave_size = device->physical_device->cs_wave_size;
1132 else if (stage == MESA_SHADER_FRAGMENT)
1133 options->wave_size = device->physical_device->ps_wave_size;
1134 else
1135 options->wave_size = device->physical_device->ge_wave_size;
1136
1137 if (options->supports_spill)
1138 tm_options |= AC_TM_SUPPORTS_SPILL;
1139 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1140 tm_options |= AC_TM_SISCHED;
1141 if (options->check_ir)
1142 tm_options |= AC_TM_CHECK_IR;
1143 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1144 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1145
1146 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1147 radv_init_llvm_once();
1148 radv_init_llvm_compiler(&ac_llvm,
1149 thread_compiler,
1150 chip_family, tm_options,
1151 options->wave_size);
1152 if (gs_copy_shader) {
1153 assert(shader_count == 1);
1154 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1155 &variant_info, options);
1156 } else {
1157 radv_compile_nir_shader(&ac_llvm, &binary, &variant_info,
1158 shaders, shader_count, options);
1159 }
1160 binary->variant_info = variant_info;
1161
1162 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1163
1164 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary);
1165 if (!variant) {
1166 free(binary);
1167 return NULL;
1168 }
1169
1170 if (options->dump_shader) {
1171 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1172 }
1173
1174
1175 if (device->keep_shader_info) {
1176 if (!gs_copy_shader && !module->nir) {
1177 variant->nir = *shaders;
1178 variant->spirv = (uint32_t *)module->data;
1179 variant->spirv_size = module->size;
1180 }
1181 }
1182
1183 if (binary_out)
1184 *binary_out = binary;
1185 else
1186 free(binary);
1187
1188 return variant;
1189 }
1190
1191 struct radv_shader_variant *
1192 radv_shader_variant_compile(struct radv_device *device,
1193 struct radv_shader_module *module,
1194 struct nir_shader *const *shaders,
1195 int shader_count,
1196 struct radv_pipeline_layout *layout,
1197 const struct radv_shader_variant_key *key,
1198 struct radv_shader_binary **binary_out)
1199 {
1200 struct radv_nir_compiler_options options = {0};
1201
1202 options.layout = layout;
1203 if (key)
1204 options.key = *key;
1205
1206 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
1207 options.supports_spill = true;
1208 options.robust_buffer_access = device->robust_buffer_access;
1209
1210 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
1211 &options, false, binary_out);
1212 }
1213
1214 struct radv_shader_variant *
1215 radv_create_gs_copy_shader(struct radv_device *device,
1216 struct nir_shader *shader,
1217 struct radv_shader_binary **binary_out,
1218 bool multiview)
1219 {
1220 struct radv_nir_compiler_options options = {0};
1221
1222 options.key.has_multiview_view_index = multiview;
1223
1224 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1225 &options, true, binary_out);
1226 }
1227
1228 void
1229 radv_shader_variant_destroy(struct radv_device *device,
1230 struct radv_shader_variant *variant)
1231 {
1232 if (!p_atomic_dec_zero(&variant->ref_count))
1233 return;
1234
1235 mtx_lock(&device->shader_slab_mutex);
1236 list_del(&variant->slab_list);
1237 mtx_unlock(&device->shader_slab_mutex);
1238
1239 ralloc_free(variant->nir);
1240 free(variant->disasm_string);
1241 free(variant->llvm_ir_string);
1242 free(variant);
1243 }
1244
1245 const char *
1246 radv_get_shader_name(struct radv_shader_variant_info *info,
1247 gl_shader_stage stage)
1248 {
1249 switch (stage) {
1250 case MESA_SHADER_VERTEX:
1251 if (info->vs.as_ls)
1252 return "Vertex Shader as LS";
1253 else if (info->vs.as_es)
1254 return "Vertex Shader as ES";
1255 else if (info->is_ngg)
1256 return "Vertex Shader as ESGS";
1257 else
1258 return "Vertex Shader as VS";
1259 case MESA_SHADER_TESS_CTRL:
1260 return "Tessellation Control Shader";
1261 case MESA_SHADER_TESS_EVAL:
1262 if (info->tes.as_es)
1263 return "Tessellation Evaluation Shader as ES";
1264 else if (info->is_ngg)
1265 return "Tessellation Evaluation Shader as ESGS";
1266 else
1267 return "Tessellation Evaluation Shader as VS";
1268 case MESA_SHADER_GEOMETRY:
1269 return "Geometry Shader";
1270 case MESA_SHADER_FRAGMENT:
1271 return "Pixel Shader";
1272 case MESA_SHADER_COMPUTE:
1273 return "Compute Shader";
1274 default:
1275 return "Unknown shader";
1276 };
1277 }
1278
1279 static void
1280 generate_shader_stats(struct radv_device *device,
1281 struct radv_shader_variant *variant,
1282 gl_shader_stage stage,
1283 struct _mesa_string_buffer *buf)
1284 {
1285 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1286 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1287 uint8_t wave_size = variant->info.info.wave_size;
1288 struct ac_shader_config *conf;
1289 unsigned max_simd_waves;
1290 unsigned lds_per_wave = 0;
1291
1292 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
1293
1294 conf = &variant->config;
1295
1296 if (stage == MESA_SHADER_FRAGMENT) {
1297 lds_per_wave = conf->lds_size * lds_increment +
1298 align(variant->info.fs.num_interp * 48,
1299 lds_increment);
1300 } else if (stage == MESA_SHADER_COMPUTE) {
1301 unsigned max_workgroup_size =
1302 radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir);
1303 lds_per_wave = (conf->lds_size * lds_increment) /
1304 DIV_ROUND_UP(max_workgroup_size, wave_size);
1305 }
1306
1307 if (conf->num_sgprs)
1308 max_simd_waves =
1309 MIN2(max_simd_waves,
1310 ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
1311
1312 if (conf->num_vgprs)
1313 max_simd_waves =
1314 MIN2(max_simd_waves,
1315 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
1316
1317 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1318 * that PS can use.
1319 */
1320 if (lds_per_wave)
1321 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1322
1323 if (stage == MESA_SHADER_FRAGMENT) {
1324 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1325 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1326 "SPI_PS_INPUT_ENA = 0x%04x\n",
1327 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1328 }
1329
1330 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1331 "SGPRS: %d\n"
1332 "VGPRS: %d\n"
1333 "Spilled SGPRs: %d\n"
1334 "Spilled VGPRs: %d\n"
1335 "PrivMem VGPRS: %d\n"
1336 "Code Size: %d bytes\n"
1337 "LDS: %d blocks\n"
1338 "Scratch: %d bytes per wave\n"
1339 "Max Waves: %d\n"
1340 "********************\n\n\n",
1341 conf->num_sgprs, conf->num_vgprs,
1342 conf->spilled_sgprs, conf->spilled_vgprs,
1343 variant->info.private_mem_vgprs, variant->code_size,
1344 conf->lds_size, conf->scratch_bytes_per_wave,
1345 max_simd_waves);
1346 }
1347
1348 void
1349 radv_shader_dump_stats(struct radv_device *device,
1350 struct radv_shader_variant *variant,
1351 gl_shader_stage stage,
1352 FILE *file)
1353 {
1354 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1355
1356 generate_shader_stats(device, variant, stage, buf);
1357
1358 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1359 fprintf(file, "%s", buf->buf);
1360
1361 _mesa_string_buffer_destroy(buf);
1362 }
1363
1364 VkResult
1365 radv_GetShaderInfoAMD(VkDevice _device,
1366 VkPipeline _pipeline,
1367 VkShaderStageFlagBits shaderStage,
1368 VkShaderInfoTypeAMD infoType,
1369 size_t* pInfoSize,
1370 void* pInfo)
1371 {
1372 RADV_FROM_HANDLE(radv_device, device, _device);
1373 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1374 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1375 struct radv_shader_variant *variant = pipeline->shaders[stage];
1376 struct _mesa_string_buffer *buf;
1377 VkResult result = VK_SUCCESS;
1378
1379 /* Spec doesn't indicate what to do if the stage is invalid, so just
1380 * return no info for this. */
1381 if (!variant)
1382 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1383
1384 switch (infoType) {
1385 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1386 if (!pInfo) {
1387 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1388 } else {
1389 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1390 struct ac_shader_config *conf = &variant->config;
1391
1392 VkShaderStatisticsInfoAMD statistics = {};
1393 statistics.shaderStageMask = shaderStage;
1394 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1395 statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
1396 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1397
1398 if (stage == MESA_SHADER_COMPUTE) {
1399 unsigned *local_size = variant->nir->info.cs.local_size;
1400 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1401
1402 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1403 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1404
1405 statistics.computeWorkGroupSize[0] = local_size[0];
1406 statistics.computeWorkGroupSize[1] = local_size[1];
1407 statistics.computeWorkGroupSize[2] = local_size[2];
1408 } else {
1409 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1410 }
1411
1412 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1413 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1414 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1415 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1416 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1417
1418 size_t size = *pInfoSize;
1419 *pInfoSize = sizeof(statistics);
1420
1421 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1422
1423 if (size < *pInfoSize)
1424 result = VK_INCOMPLETE;
1425 }
1426
1427 break;
1428 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1429 buf = _mesa_string_buffer_create(NULL, 1024);
1430
1431 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1432 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
1433 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1434 generate_shader_stats(device, variant, stage, buf);
1435
1436 /* Need to include the null terminator. */
1437 size_t length = buf->length + 1;
1438
1439 if (!pInfo) {
1440 *pInfoSize = length;
1441 } else {
1442 size_t size = *pInfoSize;
1443 *pInfoSize = length;
1444
1445 memcpy(pInfo, buf->buf, MIN2(size, length));
1446
1447 if (size < length)
1448 result = VK_INCOMPLETE;
1449 }
1450
1451 _mesa_string_buffer_destroy(buf);
1452 break;
1453 default:
1454 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1455 result = VK_ERROR_FEATURE_NOT_PRESENT;
1456 break;
1457 }
1458
1459 return result;
1460 }