src/amd/vulkan/radv_shader.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "util/mesa-sha1.h"
  29 #include "util/u_atomic.h"
  30 #include "radv_debug.h"
  31 #include "radv_private.h"
  32 #include "radv_shader.h"
  33 #include "radv_shader_helper.h"
  34 #include "nir/nir.h"
  35 #include "nir/nir_builder.h"
  36 #include "spirv/nir_spirv.h"
  37
  38 #include <llvm-c/Core.h>
  39 #include <llvm-c/TargetMachine.h>
  40 #include <llvm-c/Support.h>
  41
  42 #include "sid.h"
  43 #include "gfx9d.h"
  44 #include "ac_binary.h"
  45 #include "ac_llvm_util.h"
  46 #include "ac_nir_to_llvm.h"
  47 #include "vk_format.h"
  48 #include "util/debug.h"
  49 #include "ac_exp_param.h"
  50
  51 #include "util/string_buffer.h"
  52
  53 static const struct nir_shader_compiler_options nir_options = {
  54         .vertex_id_zero_based = true,
  55         .lower_scmp = true,
  56         .lower_flrp32 = true,
  57         .lower_flrp64 = true,
  58         .lower_device_index_to_zero = true,
  59         .lower_fsat = true,
  60         .lower_fdiv = true,
  61         .lower_sub = true,
  62         .lower_pack_snorm_2x16 = true,
  63         .lower_pack_snorm_4x8 = true,
  64         .lower_pack_unorm_2x16 = true,
  65         .lower_pack_unorm_4x8 = true,
  66         .lower_unpack_snorm_2x16 = true,
  67         .lower_unpack_snorm_4x8 = true,
  68         .lower_unpack_unorm_2x16 = true,
  69         .lower_unpack_unorm_4x8 = true,
  70         .lower_extract_byte = true,
  71         .lower_extract_word = true,
  72         .lower_ffma = true,
  73         .lower_fpow = true,
  74         .lower_mul_2x32_64 = true,
  75         .max_unroll_iterations = 32
  76 };
  77
  78 VkResult radv_CreateShaderModule(
  79         VkDevice                                    _device,
  80         const VkShaderModuleCreateInfo*             pCreateInfo,
  81         const VkAllocationCallbacks*                pAllocator,
  82         VkShaderModule*                             pShaderModule)
  83 {
  84         RADV_FROM_HANDLE(radv_device, device, _device);
  85         struct radv_shader_module *module;
  86
  87         assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
  88         assert(pCreateInfo->flags == 0);
  89
  90         module = vk_alloc2(&device->alloc, pAllocator,
  91                              sizeof(*module) + pCreateInfo->codeSize, 8,
  92                              VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
  93         if (module == NULL)
  94                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
  95
  96         module->nir = NULL;
  97         module->size = pCreateInfo->codeSize;
  98         memcpy(module->data, pCreateInfo->pCode, module->size);
  99
 100         _mesa_sha1_compute(module->data, module->size, module->sha1);
 101
 102         *pShaderModule = radv_shader_module_to_handle(module);
 103
 104         return VK_SUCCESS;
 105 }
 106
 107 void radv_DestroyShaderModule(
 108         VkDevice                                    _device,
 109         VkShaderModule                              _module,
 110         const VkAllocationCallbacks*                pAllocator)
 111 {
 112         RADV_FROM_HANDLE(radv_device, device, _device);
 113         RADV_FROM_HANDLE(radv_shader_module, module, _module);
 114
 115         if (!module)
 116                 return;
 117
 118         vk_free2(&device->alloc, pAllocator, module);
 119 }
 120
 121 void
 122 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 123                   bool allow_copies)
 124 {
 125         bool progress;
 126
 127         do {
 128                 progress = false;
 129
 130                 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
 131                 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
 132
 133                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 134                 NIR_PASS_V(shader, nir_lower_pack);
 135
 136                 if (allow_copies) {
 137                         /* Only run this pass in the first call to
 138                          * radv_optimize_nir.  Later calls assume that we've
 139                          * lowered away any copy_deref instructions and we
 140                          *  don't want to introduce any more.
 141                         */
 142                         NIR_PASS(progress, shader, nir_opt_find_array_copies);
 143                 }
 144
 145                 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
 146                 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 147
 148                 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
 149                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 150
 151                 NIR_PASS(progress, shader, nir_copy_prop);
 152                 NIR_PASS(progress, shader, nir_opt_remove_phis);
 153                 NIR_PASS(progress, shader, nir_opt_dce);
 154                 if (nir_opt_trivial_continues(shader)) {
 155                         progress = true;
 156                         NIR_PASS(progress, shader, nir_copy_prop);
 157                         NIR_PASS(progress, shader, nir_opt_remove_phis);
 158                         NIR_PASS(progress, shader, nir_opt_dce);
 159                 }
 160                 NIR_PASS(progress, shader, nir_opt_if);
 161                 NIR_PASS(progress, shader, nir_opt_dead_cf);
 162                 NIR_PASS(progress, shader, nir_opt_cse);
 163                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
 164                 NIR_PASS(progress, shader, nir_opt_algebraic);
 165                 NIR_PASS(progress, shader, nir_opt_constant_folding);
 166                 NIR_PASS(progress, shader, nir_opt_undef);
 167                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
 168                 if (shader->options->max_unroll_iterations) {
 169                         NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
 170                 }
 171         } while (progress && !optimize_conservatively);
 172
 173         NIR_PASS(progress, shader, nir_opt_shrink_load);
 174         NIR_PASS(progress, shader, nir_opt_move_load_ubo);
 175 }
 176
 177 nir_shader *
 178 radv_shader_compile_to_nir(struct radv_device *device,
 179                            struct radv_shader_module *module,
 180                            const char *entrypoint_name,
 181                            gl_shader_stage stage,
 182                            const VkSpecializationInfo *spec_info,
 183                            const VkPipelineCreateFlags flags)
 184 {
 185         nir_shader *nir;
 186         nir_function *entry_point;
 187         if (module->nir) {
 188                 /* Some things such as our meta clear/blit code will give us a NIR
 189                  * shader directly.  In that case, we just ignore the SPIR-V entirely
 190                  * and just use the NIR shader */
 191                 nir = module->nir;
 192                 nir->options = &nir_options;
 193                 nir_validate_shader(nir, "in internal shader");
 194
 195                 assert(exec_list_length(&nir->functions) == 1);
 196                 struct exec_node *node = exec_list_get_head(&nir->functions);
 197                 entry_point = exec_node_data(nir_function, node, node);
 198         } else {
 199                 uint32_t *spirv = (uint32_t *) module->data;
 200                 assert(module->size % 4 == 0);
 201
 202                 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
 203                         radv_print_spirv(spirv, module->size, stderr);
 204
 205                 uint32_t num_spec_entries = 0;
 206                 struct nir_spirv_specialization *spec_entries = NULL;
 207                 if (spec_info && spec_info->mapEntryCount > 0) {
 208                         num_spec_entries = spec_info->mapEntryCount;
 209                         spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
 210                         for (uint32_t i = 0; i < num_spec_entries; i++) {
 211                                 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
 212                                 const void *data = spec_info->pData + entry.offset;
 213                                 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
 214
 215                                 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
 216                                 if (spec_info->dataSize == 8)
 217                                         spec_entries[i].data64 = *(const uint64_t *)data;
 218                                 else
 219                                         spec_entries[i].data32 = *(const uint32_t *)data;
 220                         }
 221                 }
 222                 const struct spirv_to_nir_options spirv_options = {
 223                         .lower_ubo_ssbo_access_to_offsets = true,
 224                         .caps = {
 225                                 .descriptor_array_dynamic_indexing = true,
 226                                 .device_group = true,
 227                                 .draw_parameters = true,
 228                                 .float64 = true,
 229                                 .gcn_shader = true,
 230                                 .geometry_streams = true,
 231                                 .image_read_without_format = true,
 232                                 .image_write_without_format = true,
 233                                 .int16 = true,
 234                                 .int64 = true,
 235                                 .multiview = true,
 236                                 .physical_storage_buffer_address = true,
 237                                 .runtime_descriptor_array = true,
 238                                 .shader_viewport_index_layer = true,
 239                                 .stencil_export = true,
 240                                 .storage_16bit = true,
 241                                 .storage_image_ms = true,
 242                                 .subgroup_arithmetic = true,
 243                                 .subgroup_ballot = true,
 244                                 .subgroup_basic = true,
 245                                 .subgroup_quad = true,
 246                                 .subgroup_shuffle = true,
 247                                 .subgroup_vote = true,
 248                                 .tessellation = true,
 249                                 .transform_feedback = true,
 250                                 .trinary_minmax = true,
 251                                 .variable_pointers = true,
 252                                 .storage_8bit = true,
 253                         },
 254                         .ubo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
 255                         .ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT, 2),
 256                         .phys_ssbo_ptr_type = glsl_vector_type(GLSL_TYPE_UINT64, 1),
 257                         .push_const_ptr_type = glsl_uint_type(),
 258                         .shared_ptr_type = glsl_uint_type(),
 259                 };
 260                 entry_point = spirv_to_nir(spirv, module->size / 4,
 261                                            spec_entries, num_spec_entries,
 262                                            stage, entrypoint_name,
 263                                            &spirv_options, &nir_options);
 264                 nir = entry_point->shader;
 265                 assert(nir->info.stage == stage);
 266                 nir_validate_shader(nir, "after spirv_to_nir");
 267
 268                 free(spec_entries);
 269
 270                 /* We have to lower away local constant initializers right before we
 271                  * inline functions.  That way they get properly initialized at the top
 272                  * of the function and not at the top of its caller.
 273                  */
 274                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
 275                 NIR_PASS_V(nir, nir_lower_returns);
 276                 NIR_PASS_V(nir, nir_inline_functions);
 277                 NIR_PASS_V(nir, nir_opt_deref);
 278
 279                 /* Pick off the single entrypoint that we want */
 280                 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
 281                         if (func != entry_point)
 282                                 exec_node_remove(&func->node);
 283                 }
 284                 assert(exec_list_length(&nir->functions) == 1);
 285                 entry_point->name = ralloc_strdup(entry_point, "main");
 286
 287                 /* Make sure we lower constant initializers on output variables so that
 288                  * nir_remove_dead_variables below sees the corresponding stores
 289                  */
 290                 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
 291
 292                 /* Now that we've deleted all but the main function, we can go ahead and
 293                  * lower the rest of the constant initializers.
 294                  */
 295                 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
 296
 297                 /* Split member structs.  We do this before lower_io_to_temporaries so that
 298                  * it doesn't lower system values to temporaries by accident.
 299                  */
 300                 NIR_PASS_V(nir, nir_split_var_copies);
 301                 NIR_PASS_V(nir, nir_split_per_member_structs);
 302
 303                 NIR_PASS_V(nir, nir_remove_dead_variables,
 304                            nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 305
 306                 NIR_PASS_V(nir, nir_lower_system_values);
 307                 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 308                 NIR_PASS_V(nir, nir_lower_frexp);
 309         }
 310
 311         /* Vulkan uses the separate-shader linking model */
 312         nir->info.separate_shader = true;
 313
 314         nir_shader_gather_info(nir, entry_point->impl);
 315
 316         static const nir_lower_tex_options tex_options = {
 317           .lower_txp = ~0,
 318           .lower_tg4_offsets = true,
 319         };
 320
 321         nir_lower_tex(nir, &tex_options);
 322
 323         nir_lower_vars_to_ssa(nir);
 324
 325         if (nir->info.stage == MESA_SHADER_VERTEX ||
 326             nir->info.stage == MESA_SHADER_GEOMETRY) {
 327                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 328                            nir_shader_get_entrypoint(nir), true, true);
 329         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
 330                    nir->info.stage == MESA_SHADER_FRAGMENT) {
 331                 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 332                            nir_shader_get_entrypoint(nir), true, false);
 333         }
 334
 335         nir_split_var_copies(nir);
 336
 337         nir_lower_global_vars_to_local(nir);
 338         nir_remove_dead_variables(nir, nir_var_function_temp);
 339         nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 340                         .subgroup_size = 64,
 341                         .ballot_bit_size = 64,
 342                         .lower_to_scalar = 1,
 343                         .lower_subgroup_masks = 1,
 344                         .lower_shuffle = 1,
 345                         .lower_shuffle_to_32bit = 1,
 346                         .lower_vote_eq_to_ballot = 1,
 347                 });
 348
 349         nir_lower_load_const_to_scalar(nir);
 350
 351         if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
 352                 radv_optimize_nir(nir, false, true);
 353
 354         /* We call nir_lower_var_copies() after the first radv_optimize_nir()
 355          * to remove any copies introduced by nir_opt_find_array_copies().
 356          */
 357         nir_lower_var_copies(nir);
 358
 359         /* Indirect lowering must be called after the radv_optimize_nir() loop
 360          * has been called at least once. Otherwise indirect lowering can
 361          * bloat the instruction count of the loop and cause it to be
 362          * considered too large for unrolling.
 363          */
 364         ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
 365         radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
 366
 367         return nir;
 368 }
 369
 370 void *
 371 radv_alloc_shader_memory(struct radv_device *device,
 372                          struct radv_shader_variant *shader)
 373 {
 374         mtx_lock(&device->shader_slab_mutex);
 375         list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 376                 uint64_t offset = 0;
 377                 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
 378                         if (s->bo_offset - offset >= shader->code_size) {
 379                                 shader->bo = slab->bo;
 380                                 shader->bo_offset = offset;
 381                                 list_addtail(&shader->slab_list, &s->slab_list);
 382                                 mtx_unlock(&device->shader_slab_mutex);
 383                                 return slab->ptr + offset;
 384                         }
 385                         offset = align_u64(s->bo_offset + s->code_size, 256);
 386                 }
 387                 if (slab->size - offset >= shader->code_size) {
 388                         shader->bo = slab->bo;
 389                         shader->bo_offset = offset;
 390                         list_addtail(&shader->slab_list, &slab->shaders);
 391                         mtx_unlock(&device->shader_slab_mutex);
 392                         return slab->ptr + offset;
 393                 }
 394         }
 395
 396         mtx_unlock(&device->shader_slab_mutex);
 397         struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
 398
 399         slab->size = 256 * 1024;
 400         slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
 401                                              RADEON_DOMAIN_VRAM,
 402                                              RADEON_FLAG_NO_INTERPROCESS_SHARING |
 403                                              (device->physical_device->cpdma_prefetch_writes_memory ?
 404                                                      0 : RADEON_FLAG_READ_ONLY),
 405                                              RADV_BO_PRIORITY_SHADER);
 406         slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 407         list_inithead(&slab->shaders);
 408
 409         mtx_lock(&device->shader_slab_mutex);
 410         list_add(&slab->slabs, &device->shader_slabs);
 411
 412         shader->bo = slab->bo;
 413         shader->bo_offset = 0;
 414         list_add(&shader->slab_list, &slab->shaders);
 415         mtx_unlock(&device->shader_slab_mutex);
 416         return slab->ptr;
 417 }
 418
 419 void
 420 radv_destroy_shader_slabs(struct radv_device *device)
 421 {
 422         list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
 423                 device->ws->buffer_destroy(slab->bo);
 424                 free(slab);
 425         }
 426         mtx_destroy(&device->shader_slab_mutex);
 427 }
 428
 429 /* For the UMR disassembler. */
 430 #define DEBUGGER_END_OF_CODE_MARKER    0xbf9f0000 /* invalid instruction */
 431 #define DEBUGGER_NUM_MARKERS           5
 432
 433 static unsigned
 434 radv_get_shader_binary_size(struct ac_shader_binary *binary)
 435 {
 436         return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
 437 }
 438
 439 static void
 440 radv_fill_shader_variant(struct radv_device *device,
 441                          struct radv_shader_variant *variant,
 442                          struct ac_shader_binary *binary,
 443                          gl_shader_stage stage)
 444 {
 445         bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
 446         struct radv_shader_info *info = &variant->info.info;
 447         unsigned vgpr_comp_cnt = 0;
 448
 449         variant->code_size = radv_get_shader_binary_size(binary);
 450         variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 451                          S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
 452                          S_00B12C_SCRATCH_EN(scratch_enabled) |
 453                          S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
 454                          S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
 455                          S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
 456                          S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
 457                          S_00B12C_SO_EN(!!info->so.num_outputs);
 458
 459         variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
 460                 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
 461                 S_00B848_DX10_CLAMP(1) |
 462                 S_00B848_FLOAT_MODE(variant->config.float_mode);
 463
 464         switch (stage) {
 465         case MESA_SHADER_TESS_EVAL:
 466                 vgpr_comp_cnt = 3;
 467                 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 468                 break;
 469         case MESA_SHADER_TESS_CTRL:
 470                 if (device->physical_device->rad_info.chip_class >= GFX9) {
 471                         vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 472                 } else {
 473                         variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 474                 }
 475                 break;
 476         case MESA_SHADER_VERTEX:
 477         case MESA_SHADER_GEOMETRY:
 478                 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 479                 break;
 480         case MESA_SHADER_FRAGMENT:
 481                 break;
 482         case MESA_SHADER_COMPUTE:
 483                 variant->rsrc2 |=
 484                         S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
 485                         S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
 486                         S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
 487                         S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
 488                                                 info->cs.uses_thread_id[1] ? 1 : 0) |
 489                         S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
 490                         S_00B84C_LDS_SIZE(variant->config.lds_size);
 491                 break;
 492         default:
 493                 unreachable("unsupported shader type");
 494                 break;
 495         }
 496
 497         if (device->physical_device->rad_info.chip_class >= GFX9 &&
 498             stage == MESA_SHADER_GEOMETRY) {
 499                 unsigned es_type = variant->info.gs.es_type;
 500                 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 501
 502                 if (es_type == MESA_SHADER_VERTEX) {
 503                         es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
 504                 } else if (es_type == MESA_SHADER_TESS_EVAL) {
 505                         es_vgpr_comp_cnt = 3;
 506                 } else {
 507                         unreachable("invalid shader ES type");
 508                 }
 509
 510                 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 511                  * VGPR[0:4] are always loaded.
 512                  */
 513                 if (info->uses_invocation_id) {
 514                         gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
 515                 } else if (info->uses_prim_id) {
 516                         gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
 517                 } else if (variant->info.gs.vertices_in >= 3) {
 518                         gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 519                 } else {
 520                         gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 521                 }
 522
 523                 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
 524                 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
 525                                   S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
 526         } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
 527                    stage == MESA_SHADER_TESS_CTRL) {
 528                 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 529         } else {
 530                 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 531         }
 532
 533         void *ptr = radv_alloc_shader_memory(device, variant);
 534         memcpy(ptr, binary->code, binary->code_size);
 535
 536         /* Add end-of-code markers for the UMR disassembler. */
 537        uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
 538        for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
 539                 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 540
 541 }
 542
 543 static void radv_init_llvm_target()
 544 {
 545         LLVMInitializeAMDGPUTargetInfo();
 546         LLVMInitializeAMDGPUTarget();
 547         LLVMInitializeAMDGPUTargetMC();
 548         LLVMInitializeAMDGPUAsmPrinter();
 549
 550         /* For inline assembly. */
 551         LLVMInitializeAMDGPUAsmParser();
 552
 553         /* Workaround for bug in llvm 4.0 that causes image intrinsics
 554          * to disappear.
 555          * https://reviews.llvm.org/D26348
 556          *
 557          * Workaround for bug in llvm that causes the GPU to hang in presence
 558          * of nested loops because there is an exec mask issue. The proper
 559          * solution is to fix LLVM but this might require a bunch of work.
 560          * https://bugs.llvm.org/show_bug.cgi?id=37744
 561          *
 562          * "mesa" is the prefix for error messages.
 563          */
 564         if (HAVE_LLVM >= 0x0800) {
 565                 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
 566                 LLVMParseCommandLineOptions(2, argv, NULL);
 567
 568         } else {
 569                 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
 570                                         "-amdgpu-skip-threshold=1" };
 571                 LLVMParseCommandLineOptions(3, argv, NULL);
 572         }
 573 }
 574
 575 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
 576
 577 static void radv_init_llvm_once(void)
 578 {
 579         call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 580 }
 581
 582 static struct radv_shader_variant *
 583 shader_variant_create(struct radv_device *device,
 584                       struct radv_shader_module *module,
 585                       struct nir_shader * const *shaders,
 586                       int shader_count,
 587                       gl_shader_stage stage,
 588                       struct radv_nir_compiler_options *options,
 589                       bool gs_copy_shader,
 590                       void **code_out,
 591                       unsigned *code_size_out)
 592 {
 593         enum radeon_family chip_family = device->physical_device->rad_info.family;
 594         enum ac_target_machine_options tm_options = 0;
 595         struct radv_shader_variant *variant;
 596         struct ac_shader_binary binary;
 597         struct ac_llvm_compiler ac_llvm;
 598         bool thread_compiler;
 599         variant = calloc(1, sizeof(struct radv_shader_variant));
 600         if (!variant)
 601                 return NULL;
 602
 603         options->family = chip_family;
 604         options->chip_class = device->physical_device->rad_info.chip_class;
 605         options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
 606         options->dump_preoptir = options->dump_shader &&
 607                                  device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
 608         options->record_llvm_ir = device->keep_shader_info;
 609         options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
 610         options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
 611         options->address32_hi = device->physical_device->rad_info.address32_hi;
 612
 613         if (options->supports_spill)
 614                 tm_options |= AC_TM_SUPPORTS_SPILL;
 615         if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
 616                 tm_options |= AC_TM_SISCHED;
 617         if (options->check_ir)
 618                 tm_options |= AC_TM_CHECK_IR;
 619
 620         thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 621         radv_init_llvm_once();
 622         radv_init_llvm_compiler(&ac_llvm,
 623                                 thread_compiler,
 624                                 chip_family, tm_options);
 625         if (gs_copy_shader) {
 626                 assert(shader_count == 1);
 627                 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
 628                                             &variant->config, &variant->info,
 629                                             options);
 630         } else {
 631                 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
 632                                         &variant->info, shaders, shader_count,
 633                                         options);
 634         }
 635
 636         radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 637
 638         radv_fill_shader_variant(device, variant, &binary, stage);
 639
 640         if (code_out) {
 641                 *code_out = binary.code;
 642                 *code_size_out = binary.code_size;
 643         } else
 644                 free(binary.code);
 645         free(binary.config);
 646         free(binary.rodata);
 647         free(binary.global_symbol_offsets);
 648         free(binary.relocs);
 649         variant->ref_count = 1;
 650
 651         if (device->keep_shader_info) {
 652                 variant->disasm_string = binary.disasm_string;
 653                 variant->llvm_ir_string = binary.llvm_ir_string;
 654                 if (!gs_copy_shader && !module->nir) {
 655                         variant->nir = *shaders;
 656                         variant->spirv = (uint32_t *)module->data;
 657                         variant->spirv_size = module->size;
 658                 }
 659         } else {
 660                 free(binary.disasm_string);
 661         }
 662
 663         return variant;
 664 }
 665
 666 struct radv_shader_variant *
 667 radv_shader_variant_create(struct radv_device *device,
 668                            struct radv_shader_module *module,
 669                            struct nir_shader *const *shaders,
 670                            int shader_count,
 671                            struct radv_pipeline_layout *layout,
 672                            const struct radv_shader_variant_key *key,
 673                            void **code_out,
 674                            unsigned *code_size_out)
 675 {
 676         struct radv_nir_compiler_options options = {0};
 677
 678         options.layout = layout;
 679         if (key)
 680                 options.key = *key;
 681
 682         options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 683         options.supports_spill = true;
 684
 685         return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
 686                                      &options, false, code_out, code_size_out);
 687 }
 688
 689 struct radv_shader_variant *
 690 radv_create_gs_copy_shader(struct radv_device *device,
 691                            struct nir_shader *shader,
 692                            void **code_out,
 693                            unsigned *code_size_out,
 694                            bool multiview)
 695 {
 696         struct radv_nir_compiler_options options = {0};
 697
 698         options.key.has_multiview_view_index = multiview;
 699
 700         return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
 701                                      &options, true, code_out, code_size_out);
 702 }
 703
 704 void
 705 radv_shader_variant_destroy(struct radv_device *device,
 706                             struct radv_shader_variant *variant)
 707 {
 708         if (!p_atomic_dec_zero(&variant->ref_count))
 709                 return;
 710
 711         mtx_lock(&device->shader_slab_mutex);
 712         list_del(&variant->slab_list);
 713         mtx_unlock(&device->shader_slab_mutex);
 714
 715         ralloc_free(variant->nir);
 716         free(variant->disasm_string);
 717         free(variant->llvm_ir_string);
 718         free(variant);
 719 }
 720
 721 const char *
 722 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
 723 {
 724         switch (stage) {
 725         case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
 726         case MESA_SHADER_GEOMETRY: return "Geometry Shader";
 727         case MESA_SHADER_FRAGMENT: return "Pixel Shader";
 728         case MESA_SHADER_COMPUTE: return "Compute Shader";
 729         case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
 730         case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
 731         default:
 732                 return "Unknown shader";
 733         };
 734 }
 735
 736 static void
 737 generate_shader_stats(struct radv_device *device,
 738                       struct radv_shader_variant *variant,
 739                       gl_shader_stage stage,
 740                       struct _mesa_string_buffer *buf)
 741 {
 742         enum chip_class chip_class = device->physical_device->rad_info.chip_class;
 743         unsigned lds_increment = chip_class >= CIK ? 512 : 256;
 744         struct ac_shader_config *conf;
 745         unsigned max_simd_waves;
 746         unsigned lds_per_wave = 0;
 747
 748         max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
 749
 750         conf = &variant->config;
 751
 752         if (stage == MESA_SHADER_FRAGMENT) {
 753                 lds_per_wave = conf->lds_size * lds_increment +
 754                                align(variant->info.fs.num_interp * 48,
 755                                      lds_increment);
 756         } else if (stage == MESA_SHADER_COMPUTE) {
 757                 unsigned max_workgroup_size =
 758                                 radv_nir_get_max_workgroup_size(chip_class, variant->nir);
 759                 lds_per_wave = (conf->lds_size * lds_increment) /
 760                                DIV_ROUND_UP(max_workgroup_size, 64);
 761         }
 762
 763         if (conf->num_sgprs)
 764                 max_simd_waves =
 765                         MIN2(max_simd_waves,
 766                              ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
 767
 768         if (conf->num_vgprs)
 769                 max_simd_waves =
 770                         MIN2(max_simd_waves,
 771                              RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
 772
 773         /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
 774          * that PS can use.
 775          */
 776         if (lds_per_wave)
 777                 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
 778
 779         if (stage == MESA_SHADER_FRAGMENT) {
 780                 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
 781                                            "SPI_PS_INPUT_ADDR = 0x%04x\n"
 782                                            "SPI_PS_INPUT_ENA  = 0x%04x\n",
 783                                            conf->spi_ps_input_addr, conf->spi_ps_input_ena);
 784         }
 785
 786         _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
 787                                    "SGPRS: %d\n"
 788                                    "VGPRS: %d\n"
 789                                    "Spilled SGPRs: %d\n"
 790                                    "Spilled VGPRs: %d\n"
 791                                    "PrivMem VGPRS: %d\n"
 792                                    "Code Size: %d bytes\n"
 793                                    "LDS: %d blocks\n"
 794                                    "Scratch: %d bytes per wave\n"
 795                                    "Max Waves: %d\n"
 796                                    "********************\n\n\n",
 797                                    conf->num_sgprs, conf->num_vgprs,
 798                                    conf->spilled_sgprs, conf->spilled_vgprs,
 799                                    variant->info.private_mem_vgprs, variant->code_size,
 800                                    conf->lds_size, conf->scratch_bytes_per_wave,
 801                                    max_simd_waves);
 802 }
 803
 804 void
 805 radv_shader_dump_stats(struct radv_device *device,
 806                        struct radv_shader_variant *variant,
 807                        gl_shader_stage stage,
 808                        FILE *file)
 809 {
 810         struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
 811
 812         generate_shader_stats(device, variant, stage, buf);
 813
 814         fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
 815         fprintf(file, "%s", buf->buf);
 816
 817         _mesa_string_buffer_destroy(buf);
 818 }
 819
 820 VkResult
 821 radv_GetShaderInfoAMD(VkDevice _device,
 822                       VkPipeline _pipeline,
 823                       VkShaderStageFlagBits shaderStage,
 824                       VkShaderInfoTypeAMD infoType,
 825                       size_t* pInfoSize,
 826                       void* pInfo)
 827 {
 828         RADV_FROM_HANDLE(radv_device, device, _device);
 829         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
 830         gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
 831         struct radv_shader_variant *variant = pipeline->shaders[stage];
 832         struct _mesa_string_buffer *buf;
 833         VkResult result = VK_SUCCESS;
 834
 835         /* Spec doesn't indicate what to do if the stage is invalid, so just
 836          * return no info for this. */
 837         if (!variant)
 838                 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
 839
 840         switch (infoType) {
 841         case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
 842                 if (!pInfo) {
 843                         *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 844                 } else {
 845                         unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
 846                         struct ac_shader_config *conf = &variant->config;
 847
 848                         VkShaderStatisticsInfoAMD statistics = {};
 849                         statistics.shaderStageMask = shaderStage;
 850                         statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
 851                         statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
 852                         statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 853
 854                         if (stage == MESA_SHADER_COMPUTE) {
 855                                 unsigned *local_size = variant->nir->info.cs.local_size;
 856                                 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
 857
 858                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
 859                                                                ceil((double)workgroup_size / statistics.numPhysicalVgprs);
 860
 861                                 statistics.computeWorkGroupSize[0] = local_size[0];
 862                                 statistics.computeWorkGroupSize[1] = local_size[1];
 863                                 statistics.computeWorkGroupSize[2] = local_size[2];
 864                         } else {
 865                                 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
 866                         }
 867
 868                         statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
 869                         statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
 870                         statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
 871                         statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
 872                         statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
 873
 874                         size_t size = *pInfoSize;
 875                         *pInfoSize = sizeof(statistics);
 876
 877                         memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
 878
 879                         if (size < *pInfoSize)
 880                                 result = VK_INCOMPLETE;
 881                 }
 882
 883                 break;
 884         case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 885                 buf = _mesa_string_buffer_create(NULL, 1024);
 886
 887                 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
 888                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
 889                 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 890                 generate_shader_stats(device, variant, stage, buf);
 891
 892                 /* Need to include the null terminator. */
 893                 size_t length = buf->length + 1;
 894
 895                 if (!pInfo) {
 896                         *pInfoSize = length;
 897                 } else {
 898                         size_t size = *pInfoSize;
 899                         *pInfoSize = length;
 900
 901                         memcpy(pInfo, buf->buf, MIN2(size, length));
 902
 903                         if (size < length)
 904                                 result = VK_INCOMPLETE;
 905                 }
 906
 907                 _mesa_string_buffer_destroy(buf);
 908                 break;
 909         default:
 910                 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
 911                 result = VK_ERROR_FEATURE_NOT_PRESENT;
 912                 break;
 913         }
 914
 915         return result;
 916 }